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[deliverable/linux.git] / drivers / pci / quirks.c
1 /*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/acpi.h>
24 #include <linux/kallsyms.h>
25 #include "pci.h"
26
27 /* The Mellanox Tavor device gives false positive parity errors
28 * Mark this device with a broken_parity_status, to allow
29 * PCI scanning code to "skip" this now blacklisted device.
30 */
31 static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
32 {
33 dev->broken_parity_status = 1; /* This device gives false positives */
34 }
35 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
36 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
37
38 /* Deal with broken BIOS'es that neglect to enable passive release,
39 which can cause problems in combination with the 82441FX/PPro MTRRs */
40 static void quirk_passive_release(struct pci_dev *dev)
41 {
42 struct pci_dev *d = NULL;
43 unsigned char dlc;
44
45 /* We have to make sure a particular bit is set in the PIIX3
46 ISA bridge, so we have to go out and find it. */
47 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
48 pci_read_config_byte(d, 0x82, &dlc);
49 if (!(dlc & 1<<1)) {
50 dev_err(&d->dev, "PIIX3: Enabling Passive Release\n");
51 dlc |= 1<<1;
52 pci_write_config_byte(d, 0x82, dlc);
53 }
54 }
55 }
56 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
57 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
58
59 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
60 but VIA don't answer queries. If you happen to have good contacts at VIA
61 ask them for me please -- Alan
62
63 This appears to be BIOS not version dependent. So presumably there is a
64 chipset level fix */
65 int isa_dma_bridge_buggy;
66 EXPORT_SYMBOL(isa_dma_bridge_buggy);
67
68 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
69 {
70 if (!isa_dma_bridge_buggy) {
71 isa_dma_bridge_buggy=1;
72 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
73 }
74 }
75 /*
76 * Its not totally clear which chipsets are the problematic ones
77 * We know 82C586 and 82C596 variants are affected.
78 */
79 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
80 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
81 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
82 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
83 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
84 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
85 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
86
87 int pci_pci_problems;
88 EXPORT_SYMBOL(pci_pci_problems);
89
90 /*
91 * Chipsets where PCI->PCI transfers vanish or hang
92 */
93 static void __devinit quirk_nopcipci(struct pci_dev *dev)
94 {
95 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
96 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
97 pci_pci_problems |= PCIPCI_FAIL;
98 }
99 }
100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
101 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
102
103 static void __devinit quirk_nopciamd(struct pci_dev *dev)
104 {
105 u8 rev;
106 pci_read_config_byte(dev, 0x08, &rev);
107 if (rev == 0x13) {
108 /* Erratum 24 */
109 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
110 pci_pci_problems |= PCIAGP_FAIL;
111 }
112 }
113 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
114
115 /*
116 * Triton requires workarounds to be used by the drivers
117 */
118 static void __devinit quirk_triton(struct pci_dev *dev)
119 {
120 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
121 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
122 pci_pci_problems |= PCIPCI_TRITON;
123 }
124 }
125 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
126 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
127 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
128 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
129
130 /*
131 * VIA Apollo KT133 needs PCI latency patch
132 * Made according to a windows driver based patch by George E. Breese
133 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
134 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
135 * the info on which Mr Breese based his work.
136 *
137 * Updated based on further information from the site and also on
138 * information provided by VIA
139 */
140 static void quirk_vialatency(struct pci_dev *dev)
141 {
142 struct pci_dev *p;
143 u8 busarb;
144 /* Ok we have a potential problem chipset here. Now see if we have
145 a buggy southbridge */
146
147 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
148 if (p!=NULL) {
149 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
150 /* Check for buggy part revisions */
151 if (p->revision < 0x40 || p->revision > 0x42)
152 goto exit;
153 } else {
154 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
155 if (p==NULL) /* No problem parts */
156 goto exit;
157 /* Check for buggy part revisions */
158 if (p->revision < 0x10 || p->revision > 0x12)
159 goto exit;
160 }
161
162 /*
163 * Ok we have the problem. Now set the PCI master grant to
164 * occur every master grant. The apparent bug is that under high
165 * PCI load (quite common in Linux of course) you can get data
166 * loss when the CPU is held off the bus for 3 bus master requests
167 * This happens to include the IDE controllers....
168 *
169 * VIA only apply this fix when an SB Live! is present but under
170 * both Linux and Windows this isnt enough, and we have seen
171 * corruption without SB Live! but with things like 3 UDMA IDE
172 * controllers. So we ignore that bit of the VIA recommendation..
173 */
174
175 pci_read_config_byte(dev, 0x76, &busarb);
176 /* Set bit 4 and bi 5 of byte 76 to 0x01
177 "Master priority rotation on every PCI master grant */
178 busarb &= ~(1<<5);
179 busarb |= (1<<4);
180 pci_write_config_byte(dev, 0x76, busarb);
181 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
182 exit:
183 pci_dev_put(p);
184 }
185 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
186 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
187 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
188 /* Must restore this on a resume from RAM */
189 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
190 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
191 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
192
193 /*
194 * VIA Apollo VP3 needs ETBF on BT848/878
195 */
196 static void __devinit quirk_viaetbf(struct pci_dev *dev)
197 {
198 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
199 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
200 pci_pci_problems |= PCIPCI_VIAETBF;
201 }
202 }
203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
204
205 static void __devinit quirk_vsfx(struct pci_dev *dev)
206 {
207 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
208 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
209 pci_pci_problems |= PCIPCI_VSFX;
210 }
211 }
212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
213
214 /*
215 * Ali Magik requires workarounds to be used by the drivers
216 * that DMA to AGP space. Latency must be set to 0xA and triton
217 * workaround applied too
218 * [Info kindly provided by ALi]
219 */
220 static void __init quirk_alimagik(struct pci_dev *dev)
221 {
222 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
223 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
224 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
225 }
226 }
227 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
229
230 /*
231 * Natoma has some interesting boundary conditions with Zoran stuff
232 * at least
233 */
234 static void __devinit quirk_natoma(struct pci_dev *dev)
235 {
236 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
237 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
238 pci_pci_problems |= PCIPCI_NATOMA;
239 }
240 }
241 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
242 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
243 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
245 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
246 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
247
248 /*
249 * This chip can cause PCI parity errors if config register 0xA0 is read
250 * while DMAs are occurring.
251 */
252 static void __devinit quirk_citrine(struct pci_dev *dev)
253 {
254 dev->cfg_size = 0xA0;
255 }
256 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
257
258 /*
259 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
260 * If it's needed, re-allocate the region.
261 */
262 static void __devinit quirk_s3_64M(struct pci_dev *dev)
263 {
264 struct resource *r = &dev->resource[0];
265
266 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
267 r->start = 0;
268 r->end = 0x3ffffff;
269 }
270 }
271 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
272 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
273
274 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
275 unsigned size, int nr, const char *name)
276 {
277 region &= ~(size-1);
278 if (region) {
279 struct pci_bus_region bus_region;
280 struct resource *res = dev->resource + nr;
281
282 res->name = pci_name(dev);
283 res->start = region;
284 res->end = region + size - 1;
285 res->flags = IORESOURCE_IO;
286
287 /* Convert from PCI bus to resource space. */
288 bus_region.start = res->start;
289 bus_region.end = res->end;
290 pcibios_bus_to_resource(dev, res, &bus_region);
291
292 pci_claim_resource(dev, nr);
293 dev_info(&dev->dev, "quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
294 }
295 }
296
297 /*
298 * ATI Northbridge setups MCE the processor if you even
299 * read somewhere between 0x3b0->0x3bb or read 0x3d3
300 */
301 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
302 {
303 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
304 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
305 request_region(0x3b0, 0x0C, "RadeonIGP");
306 request_region(0x3d3, 0x01, "RadeonIGP");
307 }
308 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
309
310 /*
311 * Let's make the southbridge information explicit instead
312 * of having to worry about people probing the ACPI areas,
313 * for example.. (Yes, it happens, and if you read the wrong
314 * ACPI register it will put the machine to sleep with no
315 * way of waking it up again. Bummer).
316 *
317 * ALI M7101: Two IO regions pointed to by words at
318 * 0xE0 (64 bytes of ACPI registers)
319 * 0xE2 (32 bytes of SMB registers)
320 */
321 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
322 {
323 u16 region;
324
325 pci_read_config_word(dev, 0xE0, &region);
326 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
327 pci_read_config_word(dev, 0xE2, &region);
328 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
329 }
330 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
331
332 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
333 {
334 u32 devres;
335 u32 mask, size, base;
336
337 pci_read_config_dword(dev, port, &devres);
338 if ((devres & enable) != enable)
339 return;
340 mask = (devres >> 16) & 15;
341 base = devres & 0xffff;
342 size = 16;
343 for (;;) {
344 unsigned bit = size >> 1;
345 if ((bit & mask) == bit)
346 break;
347 size = bit;
348 }
349 /*
350 * For now we only print it out. Eventually we'll want to
351 * reserve it (at least if it's in the 0x1000+ range), but
352 * let's get enough confirmation reports first.
353 */
354 base &= -size;
355 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
356 }
357
358 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
359 {
360 u32 devres;
361 u32 mask, size, base;
362
363 pci_read_config_dword(dev, port, &devres);
364 if ((devres & enable) != enable)
365 return;
366 base = devres & 0xffff0000;
367 mask = (devres & 0x3f) << 16;
368 size = 128 << 16;
369 for (;;) {
370 unsigned bit = size >> 1;
371 if ((bit & mask) == bit)
372 break;
373 size = bit;
374 }
375 /*
376 * For now we only print it out. Eventually we'll want to
377 * reserve it, but let's get enough confirmation reports first.
378 */
379 base &= -size;
380 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
381 }
382
383 /*
384 * PIIX4 ACPI: Two IO regions pointed to by longwords at
385 * 0x40 (64 bytes of ACPI registers)
386 * 0x90 (16 bytes of SMB registers)
387 * and a few strange programmable PIIX4 device resources.
388 */
389 static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
390 {
391 u32 region, res_a;
392
393 pci_read_config_dword(dev, 0x40, &region);
394 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
395 pci_read_config_dword(dev, 0x90, &region);
396 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
397
398 /* Device resource A has enables for some of the other ones */
399 pci_read_config_dword(dev, 0x5c, &res_a);
400
401 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
402 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
403
404 /* Device resource D is just bitfields for static resources */
405
406 /* Device 12 enabled? */
407 if (res_a & (1 << 29)) {
408 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
409 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
410 }
411 /* Device 13 enabled? */
412 if (res_a & (1 << 30)) {
413 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
414 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
415 }
416 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
417 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
418 }
419 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
420 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
421
422 /*
423 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
424 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
425 * 0x58 (64 bytes of GPIO I/O space)
426 */
427 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
428 {
429 u32 region;
430
431 pci_read_config_dword(dev, 0x40, &region);
432 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
433
434 pci_read_config_dword(dev, 0x58, &region);
435 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
436 }
437 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
438 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
439 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
440 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
441 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
442 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
443 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
444 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
445 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
446 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
447
448 static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
449 {
450 u32 region;
451
452 pci_read_config_dword(dev, 0x40, &region);
453 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
454
455 pci_read_config_dword(dev, 0x48, &region);
456 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
457 }
458 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi);
459 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi);
460 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich6_lpc_acpi);
461 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich6_lpc_acpi);
462 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich6_lpc_acpi);
463 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich6_lpc_acpi);
464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich6_lpc_acpi);
465 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich6_lpc_acpi);
466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich6_lpc_acpi);
467 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich6_lpc_acpi);
468 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich6_lpc_acpi);
469 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich6_lpc_acpi);
470 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich6_lpc_acpi);
471 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich6_lpc_acpi);
472
473 /*
474 * VIA ACPI: One IO region pointed to by longword at
475 * 0x48 or 0x20 (256 bytes of ACPI registers)
476 */
477 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
478 {
479 u32 region;
480
481 if (dev->revision & 0x10) {
482 pci_read_config_dword(dev, 0x48, &region);
483 region &= PCI_BASE_ADDRESS_IO_MASK;
484 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
485 }
486 }
487 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
488
489 /*
490 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
491 * 0x48 (256 bytes of ACPI registers)
492 * 0x70 (128 bytes of hardware monitoring register)
493 * 0x90 (16 bytes of SMB registers)
494 */
495 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
496 {
497 u16 hm;
498 u32 smb;
499
500 quirk_vt82c586_acpi(dev);
501
502 pci_read_config_word(dev, 0x70, &hm);
503 hm &= PCI_BASE_ADDRESS_IO_MASK;
504 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
505
506 pci_read_config_dword(dev, 0x90, &smb);
507 smb &= PCI_BASE_ADDRESS_IO_MASK;
508 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
509 }
510 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
511
512 /*
513 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
514 * 0x88 (128 bytes of power management registers)
515 * 0xd0 (16 bytes of SMB registers)
516 */
517 static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
518 {
519 u16 pm, smb;
520
521 pci_read_config_word(dev, 0x88, &pm);
522 pm &= PCI_BASE_ADDRESS_IO_MASK;
523 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
524
525 pci_read_config_word(dev, 0xd0, &smb);
526 smb &= PCI_BASE_ADDRESS_IO_MASK;
527 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
528 }
529 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
530
531
532 #ifdef CONFIG_X86_IO_APIC
533
534 #include <asm/io_apic.h>
535
536 /*
537 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
538 * devices to the external APIC.
539 *
540 * TODO: When we have device-specific interrupt routers,
541 * this code will go away from quirks.
542 */
543 static void quirk_via_ioapic(struct pci_dev *dev)
544 {
545 u8 tmp;
546
547 if (nr_ioapics < 1)
548 tmp = 0; /* nothing routed to external APIC */
549 else
550 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
551
552 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
553 tmp == 0 ? "Disa" : "Ena");
554
555 /* Offset 0x58: External APIC IRQ output control */
556 pci_write_config_byte (dev, 0x58, tmp);
557 }
558 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
559 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
560
561 /*
562 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
563 * This leads to doubled level interrupt rates.
564 * Set this bit to get rid of cycle wastage.
565 * Otherwise uncritical.
566 */
567 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
568 {
569 u8 misc_control2;
570 #define BYPASS_APIC_DEASSERT 8
571
572 pci_read_config_byte(dev, 0x5B, &misc_control2);
573 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
574 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
575 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
576 }
577 }
578 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
579 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
580
581 /*
582 * The AMD io apic can hang the box when an apic irq is masked.
583 * We check all revs >= B0 (yet not in the pre production!) as the bug
584 * is currently marked NoFix
585 *
586 * We have multiple reports of hangs with this chipset that went away with
587 * noapic specified. For the moment we assume it's the erratum. We may be wrong
588 * of course. However the advice is demonstrably good even if so..
589 */
590 static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
591 {
592 if (dev->revision >= 0x02) {
593 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
594 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
595 }
596 }
597 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
598
599 static void __init quirk_ioapic_rmw(struct pci_dev *dev)
600 {
601 if (dev->devfn == 0 && dev->bus->number == 0)
602 sis_apic_bug = 1;
603 }
604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
605 #endif /* CONFIG_X86_IO_APIC */
606
607 /*
608 * Some settings of MMRBC can lead to data corruption so block changes.
609 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
610 */
611 static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
612 {
613 if (dev->subordinate && dev->revision <= 0x12) {
614 dev_info(&dev->dev, "AMD8131 rev %x detected; "
615 "disabling PCI-X MMRBC\n", dev->revision);
616 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
617 }
618 }
619 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
620
621 /*
622 * FIXME: it is questionable that quirk_via_acpi
623 * is needed. It shows up as an ISA bridge, and does not
624 * support the PCI_INTERRUPT_LINE register at all. Therefore
625 * it seems like setting the pci_dev's 'irq' to the
626 * value of the ACPI SCI interrupt is only done for convenience.
627 * -jgarzik
628 */
629 static void __devinit quirk_via_acpi(struct pci_dev *d)
630 {
631 /*
632 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
633 */
634 u8 irq;
635 pci_read_config_byte(d, 0x42, &irq);
636 irq &= 0xf;
637 if (irq && (irq != 2))
638 d->irq = irq;
639 }
640 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
641 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
642
643
644 /*
645 * VIA bridges which have VLink
646 */
647
648 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
649
650 static void quirk_via_bridge(struct pci_dev *dev)
651 {
652 /* See what bridge we have and find the device ranges */
653 switch (dev->device) {
654 case PCI_DEVICE_ID_VIA_82C686:
655 /* The VT82C686 is special, it attaches to PCI and can have
656 any device number. All its subdevices are functions of
657 that single device. */
658 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
659 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
660 break;
661 case PCI_DEVICE_ID_VIA_8237:
662 case PCI_DEVICE_ID_VIA_8237A:
663 via_vlink_dev_lo = 15;
664 break;
665 case PCI_DEVICE_ID_VIA_8235:
666 via_vlink_dev_lo = 16;
667 break;
668 case PCI_DEVICE_ID_VIA_8231:
669 case PCI_DEVICE_ID_VIA_8233_0:
670 case PCI_DEVICE_ID_VIA_8233A:
671 case PCI_DEVICE_ID_VIA_8233C_0:
672 via_vlink_dev_lo = 17;
673 break;
674 }
675 }
676 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
677 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
678 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
679 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
680 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
681 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
682 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
683 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
684
685 /**
686 * quirk_via_vlink - VIA VLink IRQ number update
687 * @dev: PCI device
688 *
689 * If the device we are dealing with is on a PIC IRQ we need to
690 * ensure that the IRQ line register which usually is not relevant
691 * for PCI cards, is actually written so that interrupts get sent
692 * to the right place.
693 * We only do this on systems where a VIA south bridge was detected,
694 * and only for VIA devices on the motherboard (see quirk_via_bridge
695 * above).
696 */
697
698 static void quirk_via_vlink(struct pci_dev *dev)
699 {
700 u8 irq, new_irq;
701
702 /* Check if we have VLink at all */
703 if (via_vlink_dev_lo == -1)
704 return;
705
706 new_irq = dev->irq;
707
708 /* Don't quirk interrupts outside the legacy IRQ range */
709 if (!new_irq || new_irq > 15)
710 return;
711
712 /* Internal device ? */
713 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
714 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
715 return;
716
717 /* This is an internal VLink device on a PIC interrupt. The BIOS
718 ought to have set this but may not have, so we redo it */
719
720 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
721 if (new_irq != irq) {
722 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
723 irq, new_irq);
724 udelay(15); /* unknown if delay really needed */
725 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
726 }
727 }
728 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
729
730 /*
731 * VIA VT82C598 has its device ID settable and many BIOSes
732 * set it to the ID of VT82C597 for backward compatibility.
733 * We need to switch it off to be able to recognize the real
734 * type of the chip.
735 */
736 static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
737 {
738 pci_write_config_byte(dev, 0xfc, 0);
739 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
740 }
741 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
742
743 /*
744 * CardBus controllers have a legacy base address that enables them
745 * to respond as i82365 pcmcia controllers. We don't want them to
746 * do this even if the Linux CardBus driver is not loaded, because
747 * the Linux i82365 driver does not (and should not) handle CardBus.
748 */
749 static void quirk_cardbus_legacy(struct pci_dev *dev)
750 {
751 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
752 return;
753 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
754 }
755 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
756 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
757
758 /*
759 * Following the PCI ordering rules is optional on the AMD762. I'm not
760 * sure what the designers were smoking but let's not inhale...
761 *
762 * To be fair to AMD, it follows the spec by default, its BIOS people
763 * who turn it off!
764 */
765 static void quirk_amd_ordering(struct pci_dev *dev)
766 {
767 u32 pcic;
768 pci_read_config_dword(dev, 0x4C, &pcic);
769 if ((pcic&6)!=6) {
770 pcic |= 6;
771 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
772 pci_write_config_dword(dev, 0x4C, pcic);
773 pci_read_config_dword(dev, 0x84, &pcic);
774 pcic |= (1<<23); /* Required in this mode */
775 pci_write_config_dword(dev, 0x84, pcic);
776 }
777 }
778 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
779 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
780
781 /*
782 * DreamWorks provided workaround for Dunord I-3000 problem
783 *
784 * This card decodes and responds to addresses not apparently
785 * assigned to it. We force a larger allocation to ensure that
786 * nothing gets put too close to it.
787 */
788 static void __devinit quirk_dunord ( struct pci_dev * dev )
789 {
790 struct resource *r = &dev->resource [1];
791 r->start = 0;
792 r->end = 0xffffff;
793 }
794 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
795
796 /*
797 * i82380FB mobile docking controller: its PCI-to-PCI bridge
798 * is subtractive decoding (transparent), and does indicate this
799 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
800 * instead of 0x01.
801 */
802 static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
803 {
804 dev->transparent = 1;
805 }
806 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
807 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
808
809 /*
810 * Common misconfiguration of the MediaGX/Geode PCI master that will
811 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
812 * datasheets found at http://www.national.com/ds/GX for info on what
813 * these bits do. <christer@weinigel.se>
814 */
815 static void quirk_mediagx_master(struct pci_dev *dev)
816 {
817 u8 reg;
818 pci_read_config_byte(dev, 0x41, &reg);
819 if (reg & 2) {
820 reg &= ~2;
821 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
822 pci_write_config_byte(dev, 0x41, reg);
823 }
824 }
825 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
826 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
827
828 /*
829 * Ensure C0 rev restreaming is off. This is normally done by
830 * the BIOS but in the odd case it is not the results are corruption
831 * hence the presence of a Linux check
832 */
833 static void quirk_disable_pxb(struct pci_dev *pdev)
834 {
835 u16 config;
836
837 if (pdev->revision != 0x04) /* Only C0 requires this */
838 return;
839 pci_read_config_word(pdev, 0x40, &config);
840 if (config & (1<<6)) {
841 config &= ~(1<<6);
842 pci_write_config_word(pdev, 0x40, config);
843 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
844 }
845 }
846 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
847 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
848
849 static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
850 {
851 /* set sb600/sb700/sb800 sata to ahci mode */
852 u8 tmp;
853
854 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
855 if (tmp == 0x01) {
856 pci_read_config_byte(pdev, 0x40, &tmp);
857 pci_write_config_byte(pdev, 0x40, tmp|1);
858 pci_write_config_byte(pdev, 0x9, 1);
859 pci_write_config_byte(pdev, 0xa, 6);
860 pci_write_config_byte(pdev, 0x40, tmp);
861
862 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
863 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
864 }
865 }
866 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
867 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
868 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
869 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
870
871 /*
872 * Serverworks CSB5 IDE does not fully support native mode
873 */
874 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
875 {
876 u8 prog;
877 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
878 if (prog & 5) {
879 prog &= ~5;
880 pdev->class &= ~5;
881 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
882 /* PCI layer will sort out resources */
883 }
884 }
885 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
886
887 /*
888 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
889 */
890 static void __init quirk_ide_samemode(struct pci_dev *pdev)
891 {
892 u8 prog;
893
894 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
895
896 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
897 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
898 prog &= ~5;
899 pdev->class &= ~5;
900 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
901 }
902 }
903 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
904
905 /* This was originally an Alpha specific thing, but it really fits here.
906 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
907 */
908 static void __init quirk_eisa_bridge(struct pci_dev *dev)
909 {
910 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
911 }
912 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
913
914
915 /*
916 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
917 * is not activated. The myth is that Asus said that they do not want the
918 * users to be irritated by just another PCI Device in the Win98 device
919 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
920 * package 2.7.0 for details)
921 *
922 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
923 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
924 * becomes necessary to do this tweak in two steps -- the chosen trigger
925 * is either the Host bridge (preferred) or on-board VGA controller.
926 *
927 * Note that we used to unhide the SMBus that way on Toshiba laptops
928 * (Satellite A40 and Tecra M2) but then found that the thermal management
929 * was done by SMM code, which could cause unsynchronized concurrent
930 * accesses to the SMBus registers, with potentially bad effects. Thus you
931 * should be very careful when adding new entries: if SMM is accessing the
932 * Intel SMBus, this is a very good reason to leave it hidden.
933 *
934 * Likewise, many recent laptops use ACPI for thermal management. If the
935 * ACPI DSDT code accesses the SMBus, then Linux should not access it
936 * natively, and keeping the SMBus hidden is the right thing to do. If you
937 * are about to add an entry in the table below, please first disassemble
938 * the DSDT and double-check that there is no code accessing the SMBus.
939 */
940 static int asus_hides_smbus;
941
942 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
943 {
944 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
945 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
946 switch(dev->subsystem_device) {
947 case 0x8025: /* P4B-LX */
948 case 0x8070: /* P4B */
949 case 0x8088: /* P4B533 */
950 case 0x1626: /* L3C notebook */
951 asus_hides_smbus = 1;
952 }
953 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
954 switch(dev->subsystem_device) {
955 case 0x80b1: /* P4GE-V */
956 case 0x80b2: /* P4PE */
957 case 0x8093: /* P4B533-V */
958 asus_hides_smbus = 1;
959 }
960 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
961 switch(dev->subsystem_device) {
962 case 0x8030: /* P4T533 */
963 asus_hides_smbus = 1;
964 }
965 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
966 switch (dev->subsystem_device) {
967 case 0x8070: /* P4G8X Deluxe */
968 asus_hides_smbus = 1;
969 }
970 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
971 switch (dev->subsystem_device) {
972 case 0x80c9: /* PU-DLS */
973 asus_hides_smbus = 1;
974 }
975 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
976 switch (dev->subsystem_device) {
977 case 0x1751: /* M2N notebook */
978 case 0x1821: /* M5N notebook */
979 asus_hides_smbus = 1;
980 }
981 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
982 switch (dev->subsystem_device) {
983 case 0x184b: /* W1N notebook */
984 case 0x186a: /* M6Ne notebook */
985 asus_hides_smbus = 1;
986 }
987 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
988 switch (dev->subsystem_device) {
989 case 0x80f2: /* P4P800-X */
990 asus_hides_smbus = 1;
991 }
992 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
993 switch (dev->subsystem_device) {
994 case 0x1882: /* M6V notebook */
995 case 0x1977: /* A6VA notebook */
996 asus_hides_smbus = 1;
997 }
998 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
999 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1000 switch(dev->subsystem_device) {
1001 case 0x088C: /* HP Compaq nc8000 */
1002 case 0x0890: /* HP Compaq nc6000 */
1003 asus_hides_smbus = 1;
1004 }
1005 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1006 switch (dev->subsystem_device) {
1007 case 0x12bc: /* HP D330L */
1008 case 0x12bd: /* HP D530 */
1009 asus_hides_smbus = 1;
1010 }
1011 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1012 switch (dev->subsystem_device) {
1013 case 0x12bf: /* HP xw4100 */
1014 asus_hides_smbus = 1;
1015 }
1016 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1017 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1018 switch(dev->subsystem_device) {
1019 case 0xC00C: /* Samsung P35 notebook */
1020 asus_hides_smbus = 1;
1021 }
1022 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1023 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1024 switch(dev->subsystem_device) {
1025 case 0x0058: /* Compaq Evo N620c */
1026 asus_hides_smbus = 1;
1027 }
1028 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1029 switch(dev->subsystem_device) {
1030 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1031 /* Motherboard doesn't have Host bridge
1032 * subvendor/subdevice IDs, therefore checking
1033 * its on-board VGA controller */
1034 asus_hides_smbus = 1;
1035 }
1036 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_IG)
1037 switch(dev->subsystem_device) {
1038 case 0x00b8: /* Compaq Evo D510 CMT */
1039 case 0x00b9: /* Compaq Evo D510 SFF */
1040 asus_hides_smbus = 1;
1041 }
1042 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1043 switch (dev->subsystem_device) {
1044 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1045 /* Motherboard doesn't have host bridge
1046 * subvendor/subdevice IDs, therefore checking
1047 * its on-board VGA controller */
1048 asus_hides_smbus = 1;
1049 }
1050 }
1051 }
1052 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1053 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1054 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1055 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1056 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1057 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1058 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1059 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1060 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1061 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1062
1063 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1064 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_IG, asus_hides_smbus_hostbridge);
1065 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1066
1067 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1068 {
1069 u16 val;
1070
1071 if (likely(!asus_hides_smbus))
1072 return;
1073
1074 pci_read_config_word(dev, 0xF2, &val);
1075 if (val & 0x8) {
1076 pci_write_config_word(dev, 0xF2, val & (~0x8));
1077 pci_read_config_word(dev, 0xF2, &val);
1078 if (val & 0x8)
1079 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1080 else
1081 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1082 }
1083 }
1084 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1085 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1086 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1087 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1088 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1089 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1090 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1091 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1092 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1093 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1094 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1095 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1096 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1097 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1098
1099 /* It appears we just have one such device. If not, we have a warning */
1100 static void __iomem *asus_rcba_base;
1101 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1102 {
1103 u32 rcba;
1104
1105 if (likely(!asus_hides_smbus))
1106 return;
1107 WARN_ON(asus_rcba_base);
1108
1109 pci_read_config_dword(dev, 0xF0, &rcba);
1110 /* use bits 31:14, 16 kB aligned */
1111 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1112 if (asus_rcba_base == NULL)
1113 return;
1114 }
1115
1116 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1117 {
1118 u32 val;
1119
1120 if (likely(!asus_hides_smbus || !asus_rcba_base))
1121 return;
1122 /* read the Function Disable register, dword mode only */
1123 val = readl(asus_rcba_base + 0x3418);
1124 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1125 }
1126
1127 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1128 {
1129 if (likely(!asus_hides_smbus || !asus_rcba_base))
1130 return;
1131 iounmap(asus_rcba_base);
1132 asus_rcba_base = NULL;
1133 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1134 }
1135
1136 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1137 {
1138 asus_hides_smbus_lpc_ich6_suspend(dev);
1139 asus_hides_smbus_lpc_ich6_resume_early(dev);
1140 asus_hides_smbus_lpc_ich6_resume(dev);
1141 }
1142 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1143 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1144 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1145 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1146
1147 /*
1148 * SiS 96x south bridge: BIOS typically hides SMBus device...
1149 */
1150 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1151 {
1152 u8 val = 0;
1153 pci_read_config_byte(dev, 0x77, &val);
1154 if (val & 0x10) {
1155 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1156 pci_write_config_byte(dev, 0x77, val & ~0x10);
1157 }
1158 }
1159 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1160 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1161 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1162 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1163 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1164 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1165 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1166 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1167
1168 /*
1169 * ... This is further complicated by the fact that some SiS96x south
1170 * bridges pretend to be 85C503/5513 instead. In that case see if we
1171 * spotted a compatible north bridge to make sure.
1172 * (pci_find_device doesn't work yet)
1173 *
1174 * We can also enable the sis96x bit in the discovery register..
1175 */
1176 #define SIS_DETECT_REGISTER 0x40
1177
1178 static void quirk_sis_503(struct pci_dev *dev)
1179 {
1180 u8 reg;
1181 u16 devid;
1182
1183 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1184 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1185 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1186 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1187 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1188 return;
1189 }
1190
1191 /*
1192 * Ok, it now shows up as a 96x.. run the 96x quirk by
1193 * hand in case it has already been processed.
1194 * (depends on link order, which is apparently not guaranteed)
1195 */
1196 dev->device = devid;
1197 quirk_sis_96x_smbus(dev);
1198 }
1199 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1200 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1201
1202
1203 /*
1204 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1205 * and MC97 modem controller are disabled when a second PCI soundcard is
1206 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1207 * -- bjd
1208 */
1209 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1210 {
1211 u8 val;
1212 int asus_hides_ac97 = 0;
1213
1214 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1215 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1216 asus_hides_ac97 = 1;
1217 }
1218
1219 if (!asus_hides_ac97)
1220 return;
1221
1222 pci_read_config_byte(dev, 0x50, &val);
1223 if (val & 0xc0) {
1224 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1225 pci_read_config_byte(dev, 0x50, &val);
1226 if (val & 0xc0)
1227 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1228 else
1229 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1230 }
1231 }
1232 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1233 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1234
1235 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1236
1237 /*
1238 * If we are using libata we can drive this chip properly but must
1239 * do this early on to make the additional device appear during
1240 * the PCI scanning.
1241 */
1242 static void quirk_jmicron_ata(struct pci_dev *pdev)
1243 {
1244 u32 conf1, conf5, class;
1245 u8 hdr;
1246
1247 /* Only poke fn 0 */
1248 if (PCI_FUNC(pdev->devfn))
1249 return;
1250
1251 pci_read_config_dword(pdev, 0x40, &conf1);
1252 pci_read_config_dword(pdev, 0x80, &conf5);
1253
1254 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1255 conf5 &= ~(1 << 24); /* Clear bit 24 */
1256
1257 switch (pdev->device) {
1258 case PCI_DEVICE_ID_JMICRON_JMB360:
1259 /* The controller should be in single function ahci mode */
1260 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1261 break;
1262
1263 case PCI_DEVICE_ID_JMICRON_JMB365:
1264 case PCI_DEVICE_ID_JMICRON_JMB366:
1265 /* Redirect IDE second PATA port to the right spot */
1266 conf5 |= (1 << 24);
1267 /* Fall through */
1268 case PCI_DEVICE_ID_JMICRON_JMB361:
1269 case PCI_DEVICE_ID_JMICRON_JMB363:
1270 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1271 /* Set the class codes correctly and then direct IDE 0 */
1272 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1273 break;
1274
1275 case PCI_DEVICE_ID_JMICRON_JMB368:
1276 /* The controller should be in single function IDE mode */
1277 conf1 |= 0x00C00000; /* Set 22, 23 */
1278 break;
1279 }
1280
1281 pci_write_config_dword(pdev, 0x40, conf1);
1282 pci_write_config_dword(pdev, 0x80, conf5);
1283
1284 /* Update pdev accordingly */
1285 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1286 pdev->hdr_type = hdr & 0x7f;
1287 pdev->multifunction = !!(hdr & 0x80);
1288
1289 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1290 pdev->class = class >> 8;
1291 }
1292 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1293 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1294 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1295 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1296 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1297 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1298 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1299 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1300 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1301 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1302 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1303 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1304
1305 #endif
1306
1307 #ifdef CONFIG_X86_IO_APIC
1308 static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1309 {
1310 int i;
1311
1312 if ((pdev->class >> 8) != 0xff00)
1313 return;
1314
1315 /* the first BAR is the location of the IO APIC...we must
1316 * not touch this (and it's already covered by the fixmap), so
1317 * forcibly insert it into the resource tree */
1318 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1319 insert_resource(&iomem_resource, &pdev->resource[0]);
1320
1321 /* The next five BARs all seem to be rubbish, so just clean
1322 * them out */
1323 for (i=1; i < 6; i++) {
1324 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1325 }
1326
1327 }
1328 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1329 #endif
1330
1331 int pcie_mch_quirk;
1332 EXPORT_SYMBOL(pcie_mch_quirk);
1333
1334 static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1335 {
1336 pcie_mch_quirk = 1;
1337 }
1338 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1339 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1340 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1341
1342
1343 /*
1344 * It's possible for the MSI to get corrupted if shpc and acpi
1345 * are used together on certain PXH-based systems.
1346 */
1347 static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1348 {
1349 pci_msi_off(dev);
1350 dev->no_msi = 1;
1351 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1352 }
1353 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1354 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1355 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1356 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1357 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1358
1359 /*
1360 * Some Intel PCI Express chipsets have trouble with downstream
1361 * device power management.
1362 */
1363 static void quirk_intel_pcie_pm(struct pci_dev * dev)
1364 {
1365 pci_pm_d3_delay = 120;
1366 dev->no_d1d2 = 1;
1367 }
1368
1369 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1370 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1371 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1372 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1373 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1374 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1375 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1376 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1377 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1378 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1379 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1380 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1381 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1382 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1383 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1384 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1385 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1386 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1387 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1388 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1389 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1390
1391 #ifdef CONFIG_X86_IO_APIC
1392 /*
1393 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1394 * remap the original interrupt in the linux kernel to the boot interrupt, so
1395 * that a PCI device's interrupt handler is installed on the boot interrupt
1396 * line instead.
1397 */
1398 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1399 {
1400 if (noioapicquirk || noioapicreroute)
1401 return;
1402
1403 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1404
1405 printk(KERN_INFO "PCI quirk: reroute interrupts for 0x%04x:0x%04x\n",
1406 dev->vendor, dev->device);
1407 return;
1408 }
1409 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1410 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1411 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1412 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1413 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1414 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1415 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1416 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1417 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1418 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1419 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1420 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1421 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1422 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1423 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1424 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1425
1426 /*
1427 * On some chipsets we can disable the generation of legacy INTx boot
1428 * interrupts.
1429 */
1430
1431 /*
1432 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1433 * 300641-004US, section 5.7.3.
1434 */
1435 #define INTEL_6300_IOAPIC_ABAR 0x40
1436 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1437
1438 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1439 {
1440 u16 pci_config_word;
1441
1442 if (noioapicquirk)
1443 return;
1444
1445 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1446 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1447 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1448
1449 printk(KERN_INFO "disabled boot interrupt on device 0x%04x:0x%04x\n",
1450 dev->vendor, dev->device);
1451 }
1452 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1453 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1454
1455 /*
1456 * disable boot interrupts on HT-1000
1457 */
1458 #define BC_HT1000_FEATURE_REG 0x64
1459 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1460 #define BC_HT1000_MAP_IDX 0xC00
1461 #define BC_HT1000_MAP_DATA 0xC01
1462
1463 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1464 {
1465 u32 pci_config_dword;
1466 u8 irq;
1467
1468 if (noioapicquirk)
1469 return;
1470
1471 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1472 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1473 BC_HT1000_PIC_REGS_ENABLE);
1474
1475 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1476 outb(irq, BC_HT1000_MAP_IDX);
1477 outb(0x00, BC_HT1000_MAP_DATA);
1478 }
1479
1480 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1481
1482 printk(KERN_INFO "disabled boot interrupts on PCI device"
1483 "0x%04x:0x%04x\n", dev->vendor, dev->device);
1484 }
1485 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1486 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1487
1488 /*
1489 * disable boot interrupts on AMD and ATI chipsets
1490 */
1491 /*
1492 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1493 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1494 * (due to an erratum).
1495 */
1496 #define AMD_813X_MISC 0x40
1497 #define AMD_813X_NOIOAMODE (1<<0)
1498
1499 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1500 {
1501 u32 pci_config_dword;
1502
1503 if (noioapicquirk)
1504 return;
1505
1506 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1507 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1508 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1509
1510 printk(KERN_INFO "disabled boot interrupts on PCI device "
1511 "0x%04x:0x%04x\n", dev->vendor, dev->device);
1512 }
1513 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1514 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1515
1516 #define AMD_8111_PCI_IRQ_ROUTING 0x56
1517
1518 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1519 {
1520 u16 pci_config_word;
1521
1522 if (noioapicquirk)
1523 return;
1524
1525 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1526 if (!pci_config_word) {
1527 printk(KERN_INFO "boot interrupts on PCI device 0x%04x:0x%04x "
1528 "already disabled\n",
1529 dev->vendor, dev->device);
1530 return;
1531 }
1532 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1533 printk(KERN_INFO "disabled boot interrupts on PCI device "
1534 "0x%04x:0x%04x\n", dev->vendor, dev->device);
1535 }
1536 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1537 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1538 #endif /* CONFIG_X86_IO_APIC */
1539
1540 /*
1541 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1542 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1543 * Re-allocate the region if needed...
1544 */
1545 static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1546 {
1547 struct resource *r = &dev->resource[0];
1548
1549 if (r->start & 0x8) {
1550 r->start = 0;
1551 r->end = 0xf;
1552 }
1553 }
1554 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1555 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1556 quirk_tc86c001_ide);
1557
1558 static void __devinit quirk_netmos(struct pci_dev *dev)
1559 {
1560 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1561 unsigned int num_serial = dev->subsystem_device & 0xf;
1562
1563 /*
1564 * These Netmos parts are multiport serial devices with optional
1565 * parallel ports. Even when parallel ports are present, they
1566 * are identified as class SERIAL, which means the serial driver
1567 * will claim them. To prevent this, mark them as class OTHER.
1568 * These combo devices should be claimed by parport_serial.
1569 *
1570 * The subdevice ID is of the form 0x00PS, where <P> is the number
1571 * of parallel ports and <S> is the number of serial ports.
1572 */
1573 switch (dev->device) {
1574 case PCI_DEVICE_ID_NETMOS_9735:
1575 case PCI_DEVICE_ID_NETMOS_9745:
1576 case PCI_DEVICE_ID_NETMOS_9835:
1577 case PCI_DEVICE_ID_NETMOS_9845:
1578 case PCI_DEVICE_ID_NETMOS_9855:
1579 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1580 num_parallel) {
1581 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1582 "%u serial); changing class SERIAL to OTHER "
1583 "(use parport_serial)\n",
1584 dev->device, num_parallel, num_serial);
1585 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1586 (dev->class & 0xff);
1587 }
1588 }
1589 }
1590 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1591
1592 static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1593 {
1594 u16 command, pmcsr;
1595 u8 __iomem *csr;
1596 u8 cmd_hi;
1597 int pm;
1598
1599 switch (dev->device) {
1600 /* PCI IDs taken from drivers/net/e100.c */
1601 case 0x1029:
1602 case 0x1030 ... 0x1034:
1603 case 0x1038 ... 0x103E:
1604 case 0x1050 ... 0x1057:
1605 case 0x1059:
1606 case 0x1064 ... 0x106B:
1607 case 0x1091 ... 0x1095:
1608 case 0x1209:
1609 case 0x1229:
1610 case 0x2449:
1611 case 0x2459:
1612 case 0x245D:
1613 case 0x27DC:
1614 break;
1615 default:
1616 return;
1617 }
1618
1619 /*
1620 * Some firmware hands off the e100 with interrupts enabled,
1621 * which can cause a flood of interrupts if packets are
1622 * received before the driver attaches to the device. So
1623 * disable all e100 interrupts here. The driver will
1624 * re-enable them when it's ready.
1625 */
1626 pci_read_config_word(dev, PCI_COMMAND, &command);
1627
1628 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1629 return;
1630
1631 /*
1632 * Check that the device is in the D0 power state. If it's not,
1633 * there is no point to look any further.
1634 */
1635 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1636 if (pm) {
1637 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1638 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1639 return;
1640 }
1641
1642 /* Convert from PCI bus to resource space. */
1643 csr = ioremap(pci_resource_start(dev, 0), 8);
1644 if (!csr) {
1645 dev_warn(&dev->dev, "Can't map e100 registers\n");
1646 return;
1647 }
1648
1649 cmd_hi = readb(csr + 3);
1650 if (cmd_hi == 0) {
1651 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1652 "disabling\n");
1653 writeb(1, csr + 3);
1654 }
1655
1656 iounmap(csr);
1657 }
1658 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
1659
1660 static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1661 {
1662 /* rev 1 ncr53c810 chips don't set the class at all which means
1663 * they don't get their resources remapped. Fix that here.
1664 */
1665
1666 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1667 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
1668 dev->class = PCI_CLASS_STORAGE_SCSI;
1669 }
1670 }
1671 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1672
1673 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1674 {
1675 while (f < end) {
1676 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1677 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1678 #ifdef DEBUG
1679 dev_dbg(&dev->dev, "calling ");
1680 print_fn_descriptor_symbol("%s\n", f->hook);
1681 #endif
1682 f->hook(dev);
1683 }
1684 f++;
1685 }
1686 }
1687
1688 extern struct pci_fixup __start_pci_fixups_early[];
1689 extern struct pci_fixup __end_pci_fixups_early[];
1690 extern struct pci_fixup __start_pci_fixups_header[];
1691 extern struct pci_fixup __end_pci_fixups_header[];
1692 extern struct pci_fixup __start_pci_fixups_final[];
1693 extern struct pci_fixup __end_pci_fixups_final[];
1694 extern struct pci_fixup __start_pci_fixups_enable[];
1695 extern struct pci_fixup __end_pci_fixups_enable[];
1696 extern struct pci_fixup __start_pci_fixups_resume[];
1697 extern struct pci_fixup __end_pci_fixups_resume[];
1698 extern struct pci_fixup __start_pci_fixups_resume_early[];
1699 extern struct pci_fixup __end_pci_fixups_resume_early[];
1700 extern struct pci_fixup __start_pci_fixups_suspend[];
1701 extern struct pci_fixup __end_pci_fixups_suspend[];
1702
1703
1704 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1705 {
1706 struct pci_fixup *start, *end;
1707
1708 switch(pass) {
1709 case pci_fixup_early:
1710 start = __start_pci_fixups_early;
1711 end = __end_pci_fixups_early;
1712 break;
1713
1714 case pci_fixup_header:
1715 start = __start_pci_fixups_header;
1716 end = __end_pci_fixups_header;
1717 break;
1718
1719 case pci_fixup_final:
1720 start = __start_pci_fixups_final;
1721 end = __end_pci_fixups_final;
1722 break;
1723
1724 case pci_fixup_enable:
1725 start = __start_pci_fixups_enable;
1726 end = __end_pci_fixups_enable;
1727 break;
1728
1729 case pci_fixup_resume:
1730 start = __start_pci_fixups_resume;
1731 end = __end_pci_fixups_resume;
1732 break;
1733
1734 case pci_fixup_resume_early:
1735 start = __start_pci_fixups_resume_early;
1736 end = __end_pci_fixups_resume_early;
1737 break;
1738
1739 case pci_fixup_suspend:
1740 start = __start_pci_fixups_suspend;
1741 end = __end_pci_fixups_suspend;
1742 break;
1743
1744 default:
1745 /* stupid compiler warning, you would think with an enum... */
1746 return;
1747 }
1748 pci_do_fixups(dev, start, end);
1749 }
1750 EXPORT_SYMBOL(pci_fixup_device);
1751
1752 /* Enable 1k I/O space granularity on the Intel P64H2 */
1753 static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1754 {
1755 u16 en1k;
1756 u8 io_base_lo, io_limit_lo;
1757 unsigned long base, limit;
1758 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1759
1760 pci_read_config_word(dev, 0x40, &en1k);
1761
1762 if (en1k & 0x200) {
1763 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
1764
1765 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1766 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1767 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1768 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1769
1770 if (base <= limit) {
1771 res->start = base;
1772 res->end = limit + 0x3ff;
1773 }
1774 }
1775 }
1776 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1777
1778 /* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1779 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1780 * in drivers/pci/setup-bus.c
1781 */
1782 static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1783 {
1784 u16 en1k, iobl_adr, iobl_adr_1k;
1785 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1786
1787 pci_read_config_word(dev, 0x40, &en1k);
1788
1789 if (en1k & 0x200) {
1790 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1791
1792 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1793
1794 if (iobl_adr != iobl_adr_1k) {
1795 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
1796 iobl_adr,iobl_adr_1k);
1797 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1798 }
1799 }
1800 }
1801 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1802
1803 /* Under some circumstances, AER is not linked with extended capabilities.
1804 * Force it to be linked by setting the corresponding control bit in the
1805 * config space.
1806 */
1807 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1808 {
1809 uint8_t b;
1810 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1811 if (!(b & 0x20)) {
1812 pci_write_config_byte(dev, 0xf41, b | 0x20);
1813 dev_info(&dev->dev,
1814 "Linking AER extended capability\n");
1815 }
1816 }
1817 }
1818 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1819 quirk_nvidia_ck804_pcie_aer_ext_cap);
1820 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1821 quirk_nvidia_ck804_pcie_aer_ext_cap);
1822
1823 static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1824 {
1825 /*
1826 * Disable PCI Bus Parking and PCI Master read caching on CX700
1827 * which causes unspecified timing errors with a VT6212L on the PCI
1828 * bus leading to USB2.0 packet loss. The defaults are that these
1829 * features are turned off but some BIOSes turn them on.
1830 */
1831
1832 uint8_t b;
1833 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
1834 if (b & 0x40) {
1835 /* Turn off PCI Bus Parking */
1836 pci_write_config_byte(dev, 0x76, b ^ 0x40);
1837
1838 dev_info(&dev->dev,
1839 "Disabling VIA CX700 PCI parking\n");
1840 }
1841 }
1842
1843 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
1844 if (b != 0) {
1845 /* Turn off PCI Master read caching */
1846 pci_write_config_byte(dev, 0x72, 0x0);
1847
1848 /* Set PCI Master Bus time-out to "1x16 PCLK" */
1849 pci_write_config_byte(dev, 0x75, 0x1);
1850
1851 /* Disable "Read FIFO Timer" */
1852 pci_write_config_byte(dev, 0x77, 0x0);
1853
1854 dev_info(&dev->dev,
1855 "Disabling VIA CX700 PCI caching\n");
1856 }
1857 }
1858 }
1859 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
1860
1861 /*
1862 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
1863 * VPD end tag will hang the device. This problem was initially
1864 * observed when a vpd entry was created in sysfs
1865 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
1866 * will dump 32k of data. Reading a full 32k will cause an access
1867 * beyond the VPD end tag causing the device to hang. Once the device
1868 * is hung, the bnx2 driver will not be able to reset the device.
1869 * We believe that it is legal to read beyond the end tag and
1870 * therefore the solution is to limit the read/write length.
1871 */
1872 static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
1873 {
1874 /* Only disable the VPD capability for 5706, 5708, and 5709 rev. A */
1875 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
1876 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
1877 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
1878 (dev->revision & 0xf0) == 0x0)) {
1879 if (dev->vpd)
1880 dev->vpd->len = 0x80;
1881 }
1882 }
1883
1884 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM,
1885 PCI_DEVICE_ID_NX2_5706,
1886 quirk_brcm_570x_limit_vpd);
1887 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM,
1888 PCI_DEVICE_ID_NX2_5706S,
1889 quirk_brcm_570x_limit_vpd);
1890 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM,
1891 PCI_DEVICE_ID_NX2_5708,
1892 quirk_brcm_570x_limit_vpd);
1893 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM,
1894 PCI_DEVICE_ID_NX2_5708S,
1895 quirk_brcm_570x_limit_vpd);
1896 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM,
1897 PCI_DEVICE_ID_NX2_5709,
1898 quirk_brcm_570x_limit_vpd);
1899 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM,
1900 PCI_DEVICE_ID_NX2_5709S,
1901 quirk_brcm_570x_limit_vpd);
1902
1903 #ifdef CONFIG_PCI_MSI
1904 /* Some chipsets do not support MSI. We cannot easily rely on setting
1905 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
1906 * some other busses controlled by the chipset even if Linux is not
1907 * aware of it. Instead of setting the flag on all busses in the
1908 * machine, simply disable MSI globally.
1909 */
1910 static void __init quirk_disable_all_msi(struct pci_dev *dev)
1911 {
1912 pci_no_msi();
1913 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
1914 }
1915 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
1916 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
1917 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
1918 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
1919 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
1920
1921 /* Disable MSI on chipsets that are known to not support it */
1922 static void __devinit quirk_disable_msi(struct pci_dev *dev)
1923 {
1924 if (dev->subordinate) {
1925 dev_warn(&dev->dev, "MSI quirk detected; "
1926 "subordinate MSI disabled\n");
1927 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1928 }
1929 }
1930 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
1931
1932 /* Go through the list of Hypertransport capabilities and
1933 * return 1 if a HT MSI capability is found and enabled */
1934 static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
1935 {
1936 int pos, ttl = 48;
1937
1938 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1939 while (pos && ttl--) {
1940 u8 flags;
1941
1942 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1943 &flags) == 0)
1944 {
1945 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
1946 flags & HT_MSI_FLAGS_ENABLE ?
1947 "enabled" : "disabled");
1948 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
1949 }
1950
1951 pos = pci_find_next_ht_capability(dev, pos,
1952 HT_CAPTYPE_MSI_MAPPING);
1953 }
1954 return 0;
1955 }
1956
1957 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
1958 static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
1959 {
1960 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
1961 dev_warn(&dev->dev, "MSI quirk detected; "
1962 "subordinate MSI disabled\n");
1963 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1964 }
1965 }
1966 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
1967 quirk_msi_ht_cap);
1968
1969
1970 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
1971 * MSI are supported if the MSI capability set in any of these mappings.
1972 */
1973 static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
1974 {
1975 struct pci_dev *pdev;
1976
1977 if (!dev->subordinate)
1978 return;
1979
1980 /* check HT MSI cap on this chipset and the root one.
1981 * a single one having MSI is enough to be sure that MSI are supported.
1982 */
1983 pdev = pci_get_slot(dev->bus, 0);
1984 if (!pdev)
1985 return;
1986 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
1987 dev_warn(&dev->dev, "MSI quirk detected; "
1988 "subordinate MSI disabled\n");
1989 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1990 }
1991 pci_dev_put(pdev);
1992 }
1993 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1994 quirk_nvidia_ck804_msi_ht_cap);
1995
1996 /* Force enable MSI mapping capability on HT bridges */
1997 static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
1998 {
1999 int pos, ttl = 48;
2000
2001 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2002 while (pos && ttl--) {
2003 u8 flags;
2004
2005 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2006 &flags) == 0) {
2007 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2008
2009 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2010 flags | HT_MSI_FLAGS_ENABLE);
2011 }
2012 pos = pci_find_next_ht_capability(dev, pos,
2013 HT_CAPTYPE_MSI_MAPPING);
2014 }
2015 }
2016 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2017 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2018 ht_enable_msi_mapping);
2019
2020 static void __devinit nv_msi_ht_cap_quirk(struct pci_dev *dev)
2021 {
2022 struct pci_dev *host_bridge;
2023 int pos, ttl = 48;
2024
2025 /*
2026 * HT MSI mapping should be disabled on devices that are below
2027 * a non-Hypertransport host bridge. Locate the host bridge...
2028 */
2029 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2030 if (host_bridge == NULL) {
2031 dev_warn(&dev->dev,
2032 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2033 return;
2034 }
2035
2036 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2037 if (pos != 0) {
2038 /* Host bridge is to HT */
2039 ht_enable_msi_mapping(dev);
2040 return;
2041 }
2042
2043 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2044 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2045 while (pos && ttl--) {
2046 u8 flags;
2047
2048 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2049 &flags) == 0) {
2050 dev_info(&dev->dev, "Disabling HT MSI mapping");
2051 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2052 flags & ~HT_MSI_FLAGS_ENABLE);
2053 }
2054 pos = pci_find_next_ht_capability(dev, pos,
2055 HT_CAPTYPE_MSI_MAPPING);
2056 }
2057 }
2058 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk);
2059 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk);
2060
2061 static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
2062 {
2063 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2064 }
2065 static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2066 {
2067 struct pci_dev *p;
2068
2069 /* SB700 MSI issue will be fixed at HW level from revision A21,
2070 * we need check PCI REVISION ID of SMBus controller to get SB700
2071 * revision.
2072 */
2073 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2074 NULL);
2075 if (!p)
2076 return;
2077
2078 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2079 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2080 pci_dev_put(p);
2081 }
2082 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2083 PCI_DEVICE_ID_TIGON3_5780,
2084 quirk_msi_intx_disable_bug);
2085 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2086 PCI_DEVICE_ID_TIGON3_5780S,
2087 quirk_msi_intx_disable_bug);
2088 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2089 PCI_DEVICE_ID_TIGON3_5714,
2090 quirk_msi_intx_disable_bug);
2091 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2092 PCI_DEVICE_ID_TIGON3_5714S,
2093 quirk_msi_intx_disable_bug);
2094 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2095 PCI_DEVICE_ID_TIGON3_5715,
2096 quirk_msi_intx_disable_bug);
2097 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2098 PCI_DEVICE_ID_TIGON3_5715S,
2099 quirk_msi_intx_disable_bug);
2100
2101 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2102 quirk_msi_intx_disable_ati_bug);
2103 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2104 quirk_msi_intx_disable_ati_bug);
2105 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2106 quirk_msi_intx_disable_ati_bug);
2107 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2108 quirk_msi_intx_disable_ati_bug);
2109 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2110 quirk_msi_intx_disable_ati_bug);
2111
2112 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2113 quirk_msi_intx_disable_bug);
2114 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2115 quirk_msi_intx_disable_bug);
2116 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2117 quirk_msi_intx_disable_bug);
2118
2119 #endif /* CONFIG_PCI_MSI */
Linux kernel - Deliverables
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