projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Update broken web addresses in the kernel.
[deliverable/linux.git] / drivers / pci / quirks.c
1 /*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/acpi.h>
24 #include <linux/kallsyms.h>
25 #include <linux/dmi.h>
26 #include <linux/pci-aspm.h>
27 #include <linux/ioport.h>
28 #include <asm/dma.h> /* isa_dma_bridge_buggy */
29 #include "pci.h"
30
31 /*
32 * This quirk function disables memory decoding and releases memory resources
33 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
34 * It also rounds up size to specified alignment.
35 * Later on, the kernel will assign page-aligned memory resource back
36 * to the device.
37 */
38 static void __devinit quirk_resource_alignment(struct pci_dev *dev)
39 {
40 int i;
41 struct resource *r;
42 resource_size_t align, size;
43 u16 command;
44
45 if (!pci_is_reassigndev(dev))
46 return;
47
48 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
49 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
50 dev_warn(&dev->dev,
51 "Can't reassign resources to host bridge.\n");
52 return;
53 }
54
55 dev_info(&dev->dev,
56 "Disabling memory decoding and releasing memory resources.\n");
57 pci_read_config_word(dev, PCI_COMMAND, &command);
58 command &= ~PCI_COMMAND_MEMORY;
59 pci_write_config_word(dev, PCI_COMMAND, command);
60
61 align = pci_specified_resource_alignment(dev);
62 for (i=0; i < PCI_BRIDGE_RESOURCES; i++) {
63 r = &dev->resource[i];
64 if (!(r->flags & IORESOURCE_MEM))
65 continue;
66 size = resource_size(r);
67 if (size < align) {
68 size = align;
69 dev_info(&dev->dev,
70 "Rounding up size of resource #%d to %#llx.\n",
71 i, (unsigned long long)size);
72 }
73 r->end = size - 1;
74 r->start = 0;
75 }
76 /* Need to disable bridge's resource window,
77 * to enable the kernel to reassign new resource
78 * window later on.
79 */
80 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
81 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
82 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
83 r = &dev->resource[i];
84 if (!(r->flags & IORESOURCE_MEM))
85 continue;
86 r->end = resource_size(r) - 1;
87 r->start = 0;
88 }
89 pci_disable_bridge_window(dev);
90 }
91 }
92 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment);
93
94 /*
95 * Decoding should be disabled for a PCI device during BAR sizing to avoid
96 * conflict. But doing so may cause problems on host bridge and perhaps other
97 * key system devices. For devices that need to have mmio decoding always-on,
98 * we need to set the dev->mmio_always_on bit.
99 */
100 static void __devinit quirk_mmio_always_on(struct pci_dev *dev)
101 {
102 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
103 dev->mmio_always_on = 1;
104 }
105 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_mmio_always_on);
106
107 /* The Mellanox Tavor device gives false positive parity errors
108 * Mark this device with a broken_parity_status, to allow
109 * PCI scanning code to "skip" this now blacklisted device.
110 */
111 static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
112 {
113 dev->broken_parity_status = 1; /* This device gives false positives */
114 }
115 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
116 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
117
118 /* Deal with broken BIOS'es that neglect to enable passive release,
119 which can cause problems in combination with the 82441FX/PPro MTRRs */
120 static void quirk_passive_release(struct pci_dev *dev)
121 {
122 struct pci_dev *d = NULL;
123 unsigned char dlc;
124
125 /* We have to make sure a particular bit is set in the PIIX3
126 ISA bridge, so we have to go out and find it. */
127 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
128 pci_read_config_byte(d, 0x82, &dlc);
129 if (!(dlc & 1<<1)) {
130 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
131 dlc |= 1<<1;
132 pci_write_config_byte(d, 0x82, dlc);
133 }
134 }
135 }
136 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
137 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
138
139 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
140 but VIA don't answer queries. If you happen to have good contacts at VIA
141 ask them for me please -- Alan
142
143 This appears to be BIOS not version dependent. So presumably there is a
144 chipset level fix */
145
146 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
147 {
148 if (!isa_dma_bridge_buggy) {
149 isa_dma_bridge_buggy=1;
150 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
151 }
152 }
153 /*
154 * Its not totally clear which chipsets are the problematic ones
155 * We know 82C586 and 82C596 variants are affected.
156 */
157 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
162 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
163 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
164
165 /*
166 * Chipsets where PCI->PCI transfers vanish or hang
167 */
168 static void __devinit quirk_nopcipci(struct pci_dev *dev)
169 {
170 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
171 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
172 pci_pci_problems |= PCIPCI_FAIL;
173 }
174 }
175 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
176 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
177
178 static void __devinit quirk_nopciamd(struct pci_dev *dev)
179 {
180 u8 rev;
181 pci_read_config_byte(dev, 0x08, &rev);
182 if (rev == 0x13) {
183 /* Erratum 24 */
184 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
185 pci_pci_problems |= PCIAGP_FAIL;
186 }
187 }
188 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
189
190 /*
191 * Triton requires workarounds to be used by the drivers
192 */
193 static void __devinit quirk_triton(struct pci_dev *dev)
194 {
195 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
196 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
197 pci_pci_problems |= PCIPCI_TRITON;
198 }
199 }
200 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
204
205 /*
206 * VIA Apollo KT133 needs PCI latency patch
207 * Made according to a windows driver based patch by George E. Breese
208 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
209 * and http://www.georgebreese.com/net/software/#PCI
210 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
211 * the info on which Mr Breese based his work.
212 *
213 * Updated based on further information from the site and also on
214 * information provided by VIA
215 */
216 static void quirk_vialatency(struct pci_dev *dev)
217 {
218 struct pci_dev *p;
219 u8 busarb;
220 /* Ok we have a potential problem chipset here. Now see if we have
221 a buggy southbridge */
222
223 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
224 if (p!=NULL) {
225 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
226 /* Check for buggy part revisions */
227 if (p->revision < 0x40 || p->revision > 0x42)
228 goto exit;
229 } else {
230 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
231 if (p==NULL) /* No problem parts */
232 goto exit;
233 /* Check for buggy part revisions */
234 if (p->revision < 0x10 || p->revision > 0x12)
235 goto exit;
236 }
237
238 /*
239 * Ok we have the problem. Now set the PCI master grant to
240 * occur every master grant. The apparent bug is that under high
241 * PCI load (quite common in Linux of course) you can get data
242 * loss when the CPU is held off the bus for 3 bus master requests
243 * This happens to include the IDE controllers....
244 *
245 * VIA only apply this fix when an SB Live! is present but under
246 * both Linux and Windows this isnt enough, and we have seen
247 * corruption without SB Live! but with things like 3 UDMA IDE
248 * controllers. So we ignore that bit of the VIA recommendation..
249 */
250
251 pci_read_config_byte(dev, 0x76, &busarb);
252 /* Set bit 4 and bi 5 of byte 76 to 0x01
253 "Master priority rotation on every PCI master grant */
254 busarb &= ~(1<<5);
255 busarb |= (1<<4);
256 pci_write_config_byte(dev, 0x76, busarb);
257 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
258 exit:
259 pci_dev_put(p);
260 }
261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
262 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
263 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
264 /* Must restore this on a resume from RAM */
265 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
266 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
267 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
268
269 /*
270 * VIA Apollo VP3 needs ETBF on BT848/878
271 */
272 static void __devinit quirk_viaetbf(struct pci_dev *dev)
273 {
274 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
275 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
276 pci_pci_problems |= PCIPCI_VIAETBF;
277 }
278 }
279 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
280
281 static void __devinit quirk_vsfx(struct pci_dev *dev)
282 {
283 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
284 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
285 pci_pci_problems |= PCIPCI_VSFX;
286 }
287 }
288 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
289
290 /*
291 * Ali Magik requires workarounds to be used by the drivers
292 * that DMA to AGP space. Latency must be set to 0xA and triton
293 * workaround applied too
294 * [Info kindly provided by ALi]
295 */
296 static void __init quirk_alimagik(struct pci_dev *dev)
297 {
298 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
299 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
300 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
301 }
302 }
303 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
304 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
305
306 /*
307 * Natoma has some interesting boundary conditions with Zoran stuff
308 * at least
309 */
310 static void __devinit quirk_natoma(struct pci_dev *dev)
311 {
312 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
313 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
314 pci_pci_problems |= PCIPCI_NATOMA;
315 }
316 }
317 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
318 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
319 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
320 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
321 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
322 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
323
324 /*
325 * This chip can cause PCI parity errors if config register 0xA0 is read
326 * while DMAs are occurring.
327 */
328 static void __devinit quirk_citrine(struct pci_dev *dev)
329 {
330 dev->cfg_size = 0xA0;
331 }
332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
333
334 /*
335 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
336 * If it's needed, re-allocate the region.
337 */
338 static void __devinit quirk_s3_64M(struct pci_dev *dev)
339 {
340 struct resource *r = &dev->resource[0];
341
342 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
343 r->start = 0;
344 r->end = 0x3ffffff;
345 }
346 }
347 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
348 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
349
350 /*
351 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
352 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
353 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
354 * (which conflicts w/ BAR1's memory range).
355 */
356 static void __devinit quirk_cs5536_vsa(struct pci_dev *dev)
357 {
358 if (pci_resource_len(dev, 0) != 8) {
359 struct resource *res = &dev->resource[0];
360 res->end = res->start + 8 - 1;
361 dev_info(&dev->dev, "CS5536 ISA bridge bug detected "
362 "(incorrect header); workaround applied.\n");
363 }
364 }
365 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
366
367 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
368 unsigned size, int nr, const char *name)
369 {
370 region &= ~(size-1);
371 if (region) {
372 struct pci_bus_region bus_region;
373 struct resource *res = dev->resource + nr;
374
375 res->name = pci_name(dev);
376 res->start = region;
377 res->end = region + size - 1;
378 res->flags = IORESOURCE_IO;
379
380 /* Convert from PCI bus to resource space. */
381 bus_region.start = res->start;
382 bus_region.end = res->end;
383 pcibios_bus_to_resource(dev, res, &bus_region);
384
385 if (pci_claim_resource(dev, nr) == 0)
386 dev_info(&dev->dev, "quirk: %pR claimed by %s\n",
387 res, name);
388 }
389 }
390
391 /*
392 * ATI Northbridge setups MCE the processor if you even
393 * read somewhere between 0x3b0->0x3bb or read 0x3d3
394 */
395 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
396 {
397 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
398 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
399 request_region(0x3b0, 0x0C, "RadeonIGP");
400 request_region(0x3d3, 0x01, "RadeonIGP");
401 }
402 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
403
404 /*
405 * Let's make the southbridge information explicit instead
406 * of having to worry about people probing the ACPI areas,
407 * for example.. (Yes, it happens, and if you read the wrong
408 * ACPI register it will put the machine to sleep with no
409 * way of waking it up again. Bummer).
410 *
411 * ALI M7101: Two IO regions pointed to by words at
412 * 0xE0 (64 bytes of ACPI registers)
413 * 0xE2 (32 bytes of SMB registers)
414 */
415 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
416 {
417 u16 region;
418
419 pci_read_config_word(dev, 0xE0, &region);
420 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
421 pci_read_config_word(dev, 0xE2, &region);
422 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
423 }
424 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
425
426 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
427 {
428 u32 devres;
429 u32 mask, size, base;
430
431 pci_read_config_dword(dev, port, &devres);
432 if ((devres & enable) != enable)
433 return;
434 mask = (devres >> 16) & 15;
435 base = devres & 0xffff;
436 size = 16;
437 for (;;) {
438 unsigned bit = size >> 1;
439 if ((bit & mask) == bit)
440 break;
441 size = bit;
442 }
443 /*
444 * For now we only print it out. Eventually we'll want to
445 * reserve it (at least if it's in the 0x1000+ range), but
446 * let's get enough confirmation reports first.
447 */
448 base &= -size;
449 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
450 }
451
452 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
453 {
454 u32 devres;
455 u32 mask, size, base;
456
457 pci_read_config_dword(dev, port, &devres);
458 if ((devres & enable) != enable)
459 return;
460 base = devres & 0xffff0000;
461 mask = (devres & 0x3f) << 16;
462 size = 128 << 16;
463 for (;;) {
464 unsigned bit = size >> 1;
465 if ((bit & mask) == bit)
466 break;
467 size = bit;
468 }
469 /*
470 * For now we only print it out. Eventually we'll want to
471 * reserve it, but let's get enough confirmation reports first.
472 */
473 base &= -size;
474 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
475 }
476
477 /*
478 * PIIX4 ACPI: Two IO regions pointed to by longwords at
479 * 0x40 (64 bytes of ACPI registers)
480 * 0x90 (16 bytes of SMB registers)
481 * and a few strange programmable PIIX4 device resources.
482 */
483 static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
484 {
485 u32 region, res_a;
486
487 pci_read_config_dword(dev, 0x40, &region);
488 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
489 pci_read_config_dword(dev, 0x90, &region);
490 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
491
492 /* Device resource A has enables for some of the other ones */
493 pci_read_config_dword(dev, 0x5c, &res_a);
494
495 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
496 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
497
498 /* Device resource D is just bitfields for static resources */
499
500 /* Device 12 enabled? */
501 if (res_a & (1 << 29)) {
502 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
503 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
504 }
505 /* Device 13 enabled? */
506 if (res_a & (1 << 30)) {
507 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
508 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
509 }
510 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
511 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
512 }
513 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
514 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
515
516 /*
517 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
518 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
519 * 0x58 (64 bytes of GPIO I/O space)
520 */
521 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
522 {
523 u32 region;
524
525 pci_read_config_dword(dev, 0x40, &region);
526 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
527
528 pci_read_config_dword(dev, 0x58, &region);
529 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
530 }
531 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
532 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
533 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
534 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
535 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
536 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
537 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
538 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
539 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
540 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
541
542 static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
543 {
544 u32 region;
545
546 pci_read_config_dword(dev, 0x40, &region);
547 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
548
549 pci_read_config_dword(dev, 0x48, &region);
550 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
551 }
552
553 static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
554 {
555 u32 val;
556 u32 size, base;
557
558 pci_read_config_dword(dev, reg, &val);
559
560 /* Enabled? */
561 if (!(val & 1))
562 return;
563 base = val & 0xfffc;
564 if (dynsize) {
565 /*
566 * This is not correct. It is 16, 32 or 64 bytes depending on
567 * register D31:F0:ADh bits 5:4.
568 *
569 * But this gets us at least _part_ of it.
570 */
571 size = 16;
572 } else {
573 size = 128;
574 }
575 base &= ~(size-1);
576
577 /* Just print it out for now. We should reserve it after more debugging */
578 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
579 }
580
581 static void __devinit quirk_ich6_lpc(struct pci_dev *dev)
582 {
583 /* Shared ACPI/GPIO decode with all ICH6+ */
584 ich6_lpc_acpi_gpio(dev);
585
586 /* ICH6-specific generic IO decode */
587 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
588 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
589 }
590 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
591 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
592
593 static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
594 {
595 u32 val;
596 u32 mask, base;
597
598 pci_read_config_dword(dev, reg, &val);
599
600 /* Enabled? */
601 if (!(val & 1))
602 return;
603
604 /*
605 * IO base in bits 15:2, mask in bits 23:18, both
606 * are dword-based
607 */
608 base = val & 0xfffc;
609 mask = (val >> 16) & 0xfc;
610 mask |= 3;
611
612 /* Just print it out for now. We should reserve it after more debugging */
613 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
614 }
615
616 /* ICH7-10 has the same common LPC generic IO decode registers */
617 static void __devinit quirk_ich7_lpc(struct pci_dev *dev)
618 {
619 /* We share the common ACPI/DPIO decode with ICH6 */
620 ich6_lpc_acpi_gpio(dev);
621
622 /* And have 4 ICH7+ generic decodes */
623 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
624 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
625 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
626 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
627 }
628 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
629 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
630 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
631 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
632 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
633 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
634 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
635 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
636 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
637 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
638 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
639 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
640 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
641
642 /*
643 * VIA ACPI: One IO region pointed to by longword at
644 * 0x48 or 0x20 (256 bytes of ACPI registers)
645 */
646 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
647 {
648 u32 region;
649
650 if (dev->revision & 0x10) {
651 pci_read_config_dword(dev, 0x48, &region);
652 region &= PCI_BASE_ADDRESS_IO_MASK;
653 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
654 }
655 }
656 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
657
658 /*
659 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
660 * 0x48 (256 bytes of ACPI registers)
661 * 0x70 (128 bytes of hardware monitoring register)
662 * 0x90 (16 bytes of SMB registers)
663 */
664 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
665 {
666 u16 hm;
667 u32 smb;
668
669 quirk_vt82c586_acpi(dev);
670
671 pci_read_config_word(dev, 0x70, &hm);
672 hm &= PCI_BASE_ADDRESS_IO_MASK;
673 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
674
675 pci_read_config_dword(dev, 0x90, &smb);
676 smb &= PCI_BASE_ADDRESS_IO_MASK;
677 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
678 }
679 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
680
681 /*
682 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
683 * 0x88 (128 bytes of power management registers)
684 * 0xd0 (16 bytes of SMB registers)
685 */
686 static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
687 {
688 u16 pm, smb;
689
690 pci_read_config_word(dev, 0x88, &pm);
691 pm &= PCI_BASE_ADDRESS_IO_MASK;
692 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
693
694 pci_read_config_word(dev, 0xd0, &smb);
695 smb &= PCI_BASE_ADDRESS_IO_MASK;
696 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
697 }
698 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
699
700 /*
701 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
702 * Disable fast back-to-back on the secondary bus segment
703 */
704 static void __devinit quirk_xio2000a(struct pci_dev *dev)
705 {
706 struct pci_dev *pdev;
707 u16 command;
708
709 dev_warn(&dev->dev, "TI XIO2000a quirk detected; "
710 "secondary bus fast back-to-back transfers disabled\n");
711 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
712 pci_read_config_word(pdev, PCI_COMMAND, &command);
713 if (command & PCI_COMMAND_FAST_BACK)
714 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
715 }
716 }
717 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
718 quirk_xio2000a);
719
720 #ifdef CONFIG_X86_IO_APIC
721
722 #include <asm/io_apic.h>
723
724 /*
725 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
726 * devices to the external APIC.
727 *
728 * TODO: When we have device-specific interrupt routers,
729 * this code will go away from quirks.
730 */
731 static void quirk_via_ioapic(struct pci_dev *dev)
732 {
733 u8 tmp;
734
735 if (nr_ioapics < 1)
736 tmp = 0; /* nothing routed to external APIC */
737 else
738 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
739
740 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
741 tmp == 0 ? "Disa" : "Ena");
742
743 /* Offset 0x58: External APIC IRQ output control */
744 pci_write_config_byte (dev, 0x58, tmp);
745 }
746 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
747 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
748
749 /*
750 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
751 * This leads to doubled level interrupt rates.
752 * Set this bit to get rid of cycle wastage.
753 * Otherwise uncritical.
754 */
755 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
756 {
757 u8 misc_control2;
758 #define BYPASS_APIC_DEASSERT 8
759
760 pci_read_config_byte(dev, 0x5B, &misc_control2);
761 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
762 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
763 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
764 }
765 }
766 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
767 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
768
769 /*
770 * The AMD io apic can hang the box when an apic irq is masked.
771 * We check all revs >= B0 (yet not in the pre production!) as the bug
772 * is currently marked NoFix
773 *
774 * We have multiple reports of hangs with this chipset that went away with
775 * noapic specified. For the moment we assume it's the erratum. We may be wrong
776 * of course. However the advice is demonstrably good even if so..
777 */
778 static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
779 {
780 if (dev->revision >= 0x02) {
781 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
782 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
783 }
784 }
785 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
786
787 static void __init quirk_ioapic_rmw(struct pci_dev *dev)
788 {
789 if (dev->devfn == 0 && dev->bus->number == 0)
790 sis_apic_bug = 1;
791 }
792 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
793 #endif /* CONFIG_X86_IO_APIC */
794
795 /*
796 * Some settings of MMRBC can lead to data corruption so block changes.
797 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
798 */
799 static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
800 {
801 if (dev->subordinate && dev->revision <= 0x12) {
802 dev_info(&dev->dev, "AMD8131 rev %x detected; "
803 "disabling PCI-X MMRBC\n", dev->revision);
804 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
805 }
806 }
807 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
808
809 /*
810 * FIXME: it is questionable that quirk_via_acpi
811 * is needed. It shows up as an ISA bridge, and does not
812 * support the PCI_INTERRUPT_LINE register at all. Therefore
813 * it seems like setting the pci_dev's 'irq' to the
814 * value of the ACPI SCI interrupt is only done for convenience.
815 * -jgarzik
816 */
817 static void __devinit quirk_via_acpi(struct pci_dev *d)
818 {
819 /*
820 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
821 */
822 u8 irq;
823 pci_read_config_byte(d, 0x42, &irq);
824 irq &= 0xf;
825 if (irq && (irq != 2))
826 d->irq = irq;
827 }
828 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
829 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
830
831
832 /*
833 * VIA bridges which have VLink
834 */
835
836 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
837
838 static void quirk_via_bridge(struct pci_dev *dev)
839 {
840 /* See what bridge we have and find the device ranges */
841 switch (dev->device) {
842 case PCI_DEVICE_ID_VIA_82C686:
843 /* The VT82C686 is special, it attaches to PCI and can have
844 any device number. All its subdevices are functions of
845 that single device. */
846 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
847 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
848 break;
849 case PCI_DEVICE_ID_VIA_8237:
850 case PCI_DEVICE_ID_VIA_8237A:
851 via_vlink_dev_lo = 15;
852 break;
853 case PCI_DEVICE_ID_VIA_8235:
854 via_vlink_dev_lo = 16;
855 break;
856 case PCI_DEVICE_ID_VIA_8231:
857 case PCI_DEVICE_ID_VIA_8233_0:
858 case PCI_DEVICE_ID_VIA_8233A:
859 case PCI_DEVICE_ID_VIA_8233C_0:
860 via_vlink_dev_lo = 17;
861 break;
862 }
863 }
864 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
865 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
866 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
867 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
868 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
869 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
870 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
871 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
872
873 /**
874 * quirk_via_vlink - VIA VLink IRQ number update
875 * @dev: PCI device
876 *
877 * If the device we are dealing with is on a PIC IRQ we need to
878 * ensure that the IRQ line register which usually is not relevant
879 * for PCI cards, is actually written so that interrupts get sent
880 * to the right place.
881 * We only do this on systems where a VIA south bridge was detected,
882 * and only for VIA devices on the motherboard (see quirk_via_bridge
883 * above).
884 */
885
886 static void quirk_via_vlink(struct pci_dev *dev)
887 {
888 u8 irq, new_irq;
889
890 /* Check if we have VLink at all */
891 if (via_vlink_dev_lo == -1)
892 return;
893
894 new_irq = dev->irq;
895
896 /* Don't quirk interrupts outside the legacy IRQ range */
897 if (!new_irq || new_irq > 15)
898 return;
899
900 /* Internal device ? */
901 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
902 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
903 return;
904
905 /* This is an internal VLink device on a PIC interrupt. The BIOS
906 ought to have set this but may not have, so we redo it */
907
908 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
909 if (new_irq != irq) {
910 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
911 irq, new_irq);
912 udelay(15); /* unknown if delay really needed */
913 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
914 }
915 }
916 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
917
918 /*
919 * VIA VT82C598 has its device ID settable and many BIOSes
920 * set it to the ID of VT82C597 for backward compatibility.
921 * We need to switch it off to be able to recognize the real
922 * type of the chip.
923 */
924 static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
925 {
926 pci_write_config_byte(dev, 0xfc, 0);
927 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
928 }
929 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
930
931 /*
932 * CardBus controllers have a legacy base address that enables them
933 * to respond as i82365 pcmcia controllers. We don't want them to
934 * do this even if the Linux CardBus driver is not loaded, because
935 * the Linux i82365 driver does not (and should not) handle CardBus.
936 */
937 static void quirk_cardbus_legacy(struct pci_dev *dev)
938 {
939 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
940 return;
941 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
942 }
943 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
944 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
945
946 /*
947 * Following the PCI ordering rules is optional on the AMD762. I'm not
948 * sure what the designers were smoking but let's not inhale...
949 *
950 * To be fair to AMD, it follows the spec by default, its BIOS people
951 * who turn it off!
952 */
953 static void quirk_amd_ordering(struct pci_dev *dev)
954 {
955 u32 pcic;
956 pci_read_config_dword(dev, 0x4C, &pcic);
957 if ((pcic&6)!=6) {
958 pcic |= 6;
959 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
960 pci_write_config_dword(dev, 0x4C, pcic);
961 pci_read_config_dword(dev, 0x84, &pcic);
962 pcic |= (1<<23); /* Required in this mode */
963 pci_write_config_dword(dev, 0x84, pcic);
964 }
965 }
966 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
967 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
968
969 /*
970 * DreamWorks provided workaround for Dunord I-3000 problem
971 *
972 * This card decodes and responds to addresses not apparently
973 * assigned to it. We force a larger allocation to ensure that
974 * nothing gets put too close to it.
975 */
976 static void __devinit quirk_dunord ( struct pci_dev * dev )
977 {
978 struct resource *r = &dev->resource [1];
979 r->start = 0;
980 r->end = 0xffffff;
981 }
982 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
983
984 /*
985 * i82380FB mobile docking controller: its PCI-to-PCI bridge
986 * is subtractive decoding (transparent), and does indicate this
987 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
988 * instead of 0x01.
989 */
990 static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
991 {
992 dev->transparent = 1;
993 }
994 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
995 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
996
997 /*
998 * Common misconfiguration of the MediaGX/Geode PCI master that will
999 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
1000 * datasheets found at http://www.national.com/analog for info on what
1001 * these bits do. <christer@weinigel.se>
1002 */
1003 static void quirk_mediagx_master(struct pci_dev *dev)
1004 {
1005 u8 reg;
1006 pci_read_config_byte(dev, 0x41, &reg);
1007 if (reg & 2) {
1008 reg &= ~2;
1009 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
1010 pci_write_config_byte(dev, 0x41, reg);
1011 }
1012 }
1013 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1014 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1015
1016 /*
1017 * Ensure C0 rev restreaming is off. This is normally done by
1018 * the BIOS but in the odd case it is not the results are corruption
1019 * hence the presence of a Linux check
1020 */
1021 static void quirk_disable_pxb(struct pci_dev *pdev)
1022 {
1023 u16 config;
1024
1025 if (pdev->revision != 0x04) /* Only C0 requires this */
1026 return;
1027 pci_read_config_word(pdev, 0x40, &config);
1028 if (config & (1<<6)) {
1029 config &= ~(1<<6);
1030 pci_write_config_word(pdev, 0x40, config);
1031 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1032 }
1033 }
1034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1035 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1036
1037 static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
1038 {
1039 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1040 u8 tmp;
1041
1042 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1043 if (tmp == 0x01) {
1044 pci_read_config_byte(pdev, 0x40, &tmp);
1045 pci_write_config_byte(pdev, 0x40, tmp|1);
1046 pci_write_config_byte(pdev, 0x9, 1);
1047 pci_write_config_byte(pdev, 0xa, 6);
1048 pci_write_config_byte(pdev, 0x40, tmp);
1049
1050 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1051 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1052 }
1053 }
1054 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1055 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1056 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1057 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1058 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1059 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1060
1061 /*
1062 * Serverworks CSB5 IDE does not fully support native mode
1063 */
1064 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
1065 {
1066 u8 prog;
1067 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1068 if (prog & 5) {
1069 prog &= ~5;
1070 pdev->class &= ~5;
1071 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1072 /* PCI layer will sort out resources */
1073 }
1074 }
1075 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1076
1077 /*
1078 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1079 */
1080 static void __init quirk_ide_samemode(struct pci_dev *pdev)
1081 {
1082 u8 prog;
1083
1084 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1085
1086 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1087 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1088 prog &= ~5;
1089 pdev->class &= ~5;
1090 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1091 }
1092 }
1093 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1094
1095 /*
1096 * Some ATA devices break if put into D3
1097 */
1098
1099 static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
1100 {
1101 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1102 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE)
1103 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1104 }
1105 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3);
1106 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3);
1107 /* ALi loses some register settings that we cannot then restore */
1108 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, quirk_no_ata_d3);
1109 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1110 occur when mode detecting */
1111 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_no_ata_d3);
1112
1113 /* This was originally an Alpha specific thing, but it really fits here.
1114 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1115 */
1116 static void __init quirk_eisa_bridge(struct pci_dev *dev)
1117 {
1118 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1119 }
1120 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1121
1122
1123 /*
1124 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1125 * is not activated. The myth is that Asus said that they do not want the
1126 * users to be irritated by just another PCI Device in the Win98 device
1127 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1128 * package 2.7.0 for details)
1129 *
1130 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1131 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1132 * becomes necessary to do this tweak in two steps -- the chosen trigger
1133 * is either the Host bridge (preferred) or on-board VGA controller.
1134 *
1135 * Note that we used to unhide the SMBus that way on Toshiba laptops
1136 * (Satellite A40 and Tecra M2) but then found that the thermal management
1137 * was done by SMM code, which could cause unsynchronized concurrent
1138 * accesses to the SMBus registers, with potentially bad effects. Thus you
1139 * should be very careful when adding new entries: if SMM is accessing the
1140 * Intel SMBus, this is a very good reason to leave it hidden.
1141 *
1142 * Likewise, many recent laptops use ACPI for thermal management. If the
1143 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1144 * natively, and keeping the SMBus hidden is the right thing to do. If you
1145 * are about to add an entry in the table below, please first disassemble
1146 * the DSDT and double-check that there is no code accessing the SMBus.
1147 */
1148 static int asus_hides_smbus;
1149
1150 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1151 {
1152 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1153 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1154 switch(dev->subsystem_device) {
1155 case 0x8025: /* P4B-LX */
1156 case 0x8070: /* P4B */
1157 case 0x8088: /* P4B533 */
1158 case 0x1626: /* L3C notebook */
1159 asus_hides_smbus = 1;
1160 }
1161 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1162 switch(dev->subsystem_device) {
1163 case 0x80b1: /* P4GE-V */
1164 case 0x80b2: /* P4PE */
1165 case 0x8093: /* P4B533-V */
1166 asus_hides_smbus = 1;
1167 }
1168 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1169 switch(dev->subsystem_device) {
1170 case 0x8030: /* P4T533 */
1171 asus_hides_smbus = 1;
1172 }
1173 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1174 switch (dev->subsystem_device) {
1175 case 0x8070: /* P4G8X Deluxe */
1176 asus_hides_smbus = 1;
1177 }
1178 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1179 switch (dev->subsystem_device) {
1180 case 0x80c9: /* PU-DLS */
1181 asus_hides_smbus = 1;
1182 }
1183 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1184 switch (dev->subsystem_device) {
1185 case 0x1751: /* M2N notebook */
1186 case 0x1821: /* M5N notebook */
1187 case 0x1897: /* A6L notebook */
1188 asus_hides_smbus = 1;
1189 }
1190 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1191 switch (dev->subsystem_device) {
1192 case 0x184b: /* W1N notebook */
1193 case 0x186a: /* M6Ne notebook */
1194 asus_hides_smbus = 1;
1195 }
1196 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1197 switch (dev->subsystem_device) {
1198 case 0x80f2: /* P4P800-X */
1199 asus_hides_smbus = 1;
1200 }
1201 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1202 switch (dev->subsystem_device) {
1203 case 0x1882: /* M6V notebook */
1204 case 0x1977: /* A6VA notebook */
1205 asus_hides_smbus = 1;
1206 }
1207 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1208 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1209 switch(dev->subsystem_device) {
1210 case 0x088C: /* HP Compaq nc8000 */
1211 case 0x0890: /* HP Compaq nc6000 */
1212 asus_hides_smbus = 1;
1213 }
1214 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1215 switch (dev->subsystem_device) {
1216 case 0x12bc: /* HP D330L */
1217 case 0x12bd: /* HP D530 */
1218 case 0x006a: /* HP Compaq nx9500 */
1219 asus_hides_smbus = 1;
1220 }
1221 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1222 switch (dev->subsystem_device) {
1223 case 0x12bf: /* HP xw4100 */
1224 asus_hides_smbus = 1;
1225 }
1226 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1227 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1228 switch(dev->subsystem_device) {
1229 case 0xC00C: /* Samsung P35 notebook */
1230 asus_hides_smbus = 1;
1231 }
1232 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1233 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1234 switch(dev->subsystem_device) {
1235 case 0x0058: /* Compaq Evo N620c */
1236 asus_hides_smbus = 1;
1237 }
1238 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1239 switch(dev->subsystem_device) {
1240 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1241 /* Motherboard doesn't have Host bridge
1242 * subvendor/subdevice IDs, therefore checking
1243 * its on-board VGA controller */
1244 asus_hides_smbus = 1;
1245 }
1246 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1247 switch(dev->subsystem_device) {
1248 case 0x00b8: /* Compaq Evo D510 CMT */
1249 case 0x00b9: /* Compaq Evo D510 SFF */
1250 case 0x00ba: /* Compaq Evo D510 USDT */
1251 /* Motherboard doesn't have Host bridge
1252 * subvendor/subdevice IDs and on-board VGA
1253 * controller is disabled if an AGP card is
1254 * inserted, therefore checking USB UHCI
1255 * Controller #1 */
1256 asus_hides_smbus = 1;
1257 }
1258 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1259 switch (dev->subsystem_device) {
1260 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1261 /* Motherboard doesn't have host bridge
1262 * subvendor/subdevice IDs, therefore checking
1263 * its on-board VGA controller */
1264 asus_hides_smbus = 1;
1265 }
1266 }
1267 }
1268 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1269 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1270 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1271 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1272 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1273 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1274 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1275 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1276 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1277 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1278
1279 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1280 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1281 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1282
1283 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1284 {
1285 u16 val;
1286
1287 if (likely(!asus_hides_smbus))
1288 return;
1289
1290 pci_read_config_word(dev, 0xF2, &val);
1291 if (val & 0x8) {
1292 pci_write_config_word(dev, 0xF2, val & (~0x8));
1293 pci_read_config_word(dev, 0xF2, &val);
1294 if (val & 0x8)
1295 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1296 else
1297 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1298 }
1299 }
1300 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1301 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1302 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1303 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1304 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1305 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1306 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1307 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1308 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1309 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1310 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1311 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1312 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1313 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1314
1315 /* It appears we just have one such device. If not, we have a warning */
1316 static void __iomem *asus_rcba_base;
1317 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1318 {
1319 u32 rcba;
1320
1321 if (likely(!asus_hides_smbus))
1322 return;
1323 WARN_ON(asus_rcba_base);
1324
1325 pci_read_config_dword(dev, 0xF0, &rcba);
1326 /* use bits 31:14, 16 kB aligned */
1327 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1328 if (asus_rcba_base == NULL)
1329 return;
1330 }
1331
1332 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1333 {
1334 u32 val;
1335
1336 if (likely(!asus_hides_smbus || !asus_rcba_base))
1337 return;
1338 /* read the Function Disable register, dword mode only */
1339 val = readl(asus_rcba_base + 0x3418);
1340 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1341 }
1342
1343 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1344 {
1345 if (likely(!asus_hides_smbus || !asus_rcba_base))
1346 return;
1347 iounmap(asus_rcba_base);
1348 asus_rcba_base = NULL;
1349 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1350 }
1351
1352 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1353 {
1354 asus_hides_smbus_lpc_ich6_suspend(dev);
1355 asus_hides_smbus_lpc_ich6_resume_early(dev);
1356 asus_hides_smbus_lpc_ich6_resume(dev);
1357 }
1358 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1359 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1360 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1361 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1362
1363 /*
1364 * SiS 96x south bridge: BIOS typically hides SMBus device...
1365 */
1366 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1367 {
1368 u8 val = 0;
1369 pci_read_config_byte(dev, 0x77, &val);
1370 if (val & 0x10) {
1371 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1372 pci_write_config_byte(dev, 0x77, val & ~0x10);
1373 }
1374 }
1375 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1376 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1377 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1378 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1379 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1380 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1381 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1382 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1383
1384 /*
1385 * ... This is further complicated by the fact that some SiS96x south
1386 * bridges pretend to be 85C503/5513 instead. In that case see if we
1387 * spotted a compatible north bridge to make sure.
1388 * (pci_find_device doesn't work yet)
1389 *
1390 * We can also enable the sis96x bit in the discovery register..
1391 */
1392 #define SIS_DETECT_REGISTER 0x40
1393
1394 static void quirk_sis_503(struct pci_dev *dev)
1395 {
1396 u8 reg;
1397 u16 devid;
1398
1399 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1400 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1401 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1402 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1403 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1404 return;
1405 }
1406
1407 /*
1408 * Ok, it now shows up as a 96x.. run the 96x quirk by
1409 * hand in case it has already been processed.
1410 * (depends on link order, which is apparently not guaranteed)
1411 */
1412 dev->device = devid;
1413 quirk_sis_96x_smbus(dev);
1414 }
1415 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1416 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1417
1418
1419 /*
1420 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1421 * and MC97 modem controller are disabled when a second PCI soundcard is
1422 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1423 * -- bjd
1424 */
1425 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1426 {
1427 u8 val;
1428 int asus_hides_ac97 = 0;
1429
1430 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1431 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1432 asus_hides_ac97 = 1;
1433 }
1434
1435 if (!asus_hides_ac97)
1436 return;
1437
1438 pci_read_config_byte(dev, 0x50, &val);
1439 if (val & 0xc0) {
1440 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1441 pci_read_config_byte(dev, 0x50, &val);
1442 if (val & 0xc0)
1443 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1444 else
1445 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1446 }
1447 }
1448 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1449 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1450
1451 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1452
1453 /*
1454 * If we are using libata we can drive this chip properly but must
1455 * do this early on to make the additional device appear during
1456 * the PCI scanning.
1457 */
1458 static void quirk_jmicron_ata(struct pci_dev *pdev)
1459 {
1460 u32 conf1, conf5, class;
1461 u8 hdr;
1462
1463 /* Only poke fn 0 */
1464 if (PCI_FUNC(pdev->devfn))
1465 return;
1466
1467 pci_read_config_dword(pdev, 0x40, &conf1);
1468 pci_read_config_dword(pdev, 0x80, &conf5);
1469
1470 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1471 conf5 &= ~(1 << 24); /* Clear bit 24 */
1472
1473 switch (pdev->device) {
1474 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1475 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1476 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1477 /* The controller should be in single function ahci mode */
1478 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1479 break;
1480
1481 case PCI_DEVICE_ID_JMICRON_JMB365:
1482 case PCI_DEVICE_ID_JMICRON_JMB366:
1483 /* Redirect IDE second PATA port to the right spot */
1484 conf5 |= (1 << 24);
1485 /* Fall through */
1486 case PCI_DEVICE_ID_JMICRON_JMB361:
1487 case PCI_DEVICE_ID_JMICRON_JMB363:
1488 case PCI_DEVICE_ID_JMICRON_JMB369:
1489 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1490 /* Set the class codes correctly and then direct IDE 0 */
1491 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1492 break;
1493
1494 case PCI_DEVICE_ID_JMICRON_JMB368:
1495 /* The controller should be in single function IDE mode */
1496 conf1 |= 0x00C00000; /* Set 22, 23 */
1497 break;
1498 }
1499
1500 pci_write_config_dword(pdev, 0x40, conf1);
1501 pci_write_config_dword(pdev, 0x80, conf5);
1502
1503 /* Update pdev accordingly */
1504 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1505 pdev->hdr_type = hdr & 0x7f;
1506 pdev->multifunction = !!(hdr & 0x80);
1507
1508 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1509 pdev->class = class >> 8;
1510 }
1511 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1512 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1513 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1514 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1515 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1516 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1517 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1518 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1519 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1520 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1521 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1522 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1523 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1524 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1525 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1526 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1527 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1528 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1529
1530 #endif
1531
1532 #ifdef CONFIG_X86_IO_APIC
1533 static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1534 {
1535 int i;
1536
1537 if ((pdev->class >> 8) != 0xff00)
1538 return;
1539
1540 /* the first BAR is the location of the IO APIC...we must
1541 * not touch this (and it's already covered by the fixmap), so
1542 * forcibly insert it into the resource tree */
1543 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1544 insert_resource(&iomem_resource, &pdev->resource[0]);
1545
1546 /* The next five BARs all seem to be rubbish, so just clean
1547 * them out */
1548 for (i=1; i < 6; i++) {
1549 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1550 }
1551
1552 }
1553 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1554 #endif
1555
1556 static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1557 {
1558 pci_msi_off(pdev);
1559 pdev->no_msi = 1;
1560 }
1561 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1562 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1563 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1564
1565
1566 /*
1567 * It's possible for the MSI to get corrupted if shpc and acpi
1568 * are used together on certain PXH-based systems.
1569 */
1570 static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1571 {
1572 pci_msi_off(dev);
1573 dev->no_msi = 1;
1574 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1575 }
1576 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1577 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1578 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1579 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1580 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1581
1582 /*
1583 * Some Intel PCI Express chipsets have trouble with downstream
1584 * device power management.
1585 */
1586 static void quirk_intel_pcie_pm(struct pci_dev * dev)
1587 {
1588 pci_pm_d3_delay = 120;
1589 dev->no_d1d2 = 1;
1590 }
1591
1592 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1593 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1594 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1595 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1596 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1597 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1598 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1599 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1600 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1601 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1602 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1603 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1608 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1609 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1610 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1611 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1612 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1613
1614 #ifdef CONFIG_X86_IO_APIC
1615 /*
1616 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1617 * remap the original interrupt in the linux kernel to the boot interrupt, so
1618 * that a PCI device's interrupt handler is installed on the boot interrupt
1619 * line instead.
1620 */
1621 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1622 {
1623 if (noioapicquirk || noioapicreroute)
1624 return;
1625
1626 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1627 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1628 dev->vendor, dev->device);
1629 }
1630 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1631 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1632 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1633 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1634 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1635 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1636 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1637 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1638 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1639 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1640 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1641 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1642 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1643 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1644 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1645 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1646
1647 /*
1648 * On some chipsets we can disable the generation of legacy INTx boot
1649 * interrupts.
1650 */
1651
1652 /*
1653 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1654 * 300641-004US, section 5.7.3.
1655 */
1656 #define INTEL_6300_IOAPIC_ABAR 0x40
1657 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1658
1659 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1660 {
1661 u16 pci_config_word;
1662
1663 if (noioapicquirk)
1664 return;
1665
1666 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1667 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1668 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1669
1670 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1671 dev->vendor, dev->device);
1672 }
1673 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1674 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1675
1676 /*
1677 * disable boot interrupts on HT-1000
1678 */
1679 #define BC_HT1000_FEATURE_REG 0x64
1680 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1681 #define BC_HT1000_MAP_IDX 0xC00
1682 #define BC_HT1000_MAP_DATA 0xC01
1683
1684 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1685 {
1686 u32 pci_config_dword;
1687 u8 irq;
1688
1689 if (noioapicquirk)
1690 return;
1691
1692 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1693 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1694 BC_HT1000_PIC_REGS_ENABLE);
1695
1696 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1697 outb(irq, BC_HT1000_MAP_IDX);
1698 outb(0x00, BC_HT1000_MAP_DATA);
1699 }
1700
1701 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1702
1703 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1704 dev->vendor, dev->device);
1705 }
1706 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1707 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1708
1709 /*
1710 * disable boot interrupts on AMD and ATI chipsets
1711 */
1712 /*
1713 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1714 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1715 * (due to an erratum).
1716 */
1717 #define AMD_813X_MISC 0x40
1718 #define AMD_813X_NOIOAMODE (1<<0)
1719 #define AMD_813X_REV_B1 0x12
1720 #define AMD_813X_REV_B2 0x13
1721
1722 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1723 {
1724 u32 pci_config_dword;
1725
1726 if (noioapicquirk)
1727 return;
1728 if ((dev->revision == AMD_813X_REV_B1) ||
1729 (dev->revision == AMD_813X_REV_B2))
1730 return;
1731
1732 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1733 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1734 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1735
1736 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1737 dev->vendor, dev->device);
1738 }
1739 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1740 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1741 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1742 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1743
1744 #define AMD_8111_PCI_IRQ_ROUTING 0x56
1745
1746 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1747 {
1748 u16 pci_config_word;
1749
1750 if (noioapicquirk)
1751 return;
1752
1753 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1754 if (!pci_config_word) {
1755 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] "
1756 "already disabled\n", dev->vendor, dev->device);
1757 return;
1758 }
1759 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1760 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1761 dev->vendor, dev->device);
1762 }
1763 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1764 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1765 #endif /* CONFIG_X86_IO_APIC */
1766
1767 /*
1768 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1769 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1770 * Re-allocate the region if needed...
1771 */
1772 static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1773 {
1774 struct resource *r = &dev->resource[0];
1775
1776 if (r->start & 0x8) {
1777 r->start = 0;
1778 r->end = 0xf;
1779 }
1780 }
1781 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1782 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1783 quirk_tc86c001_ide);
1784
1785 static void __devinit quirk_netmos(struct pci_dev *dev)
1786 {
1787 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1788 unsigned int num_serial = dev->subsystem_device & 0xf;
1789
1790 /*
1791 * These Netmos parts are multiport serial devices with optional
1792 * parallel ports. Even when parallel ports are present, they
1793 * are identified as class SERIAL, which means the serial driver
1794 * will claim them. To prevent this, mark them as class OTHER.
1795 * These combo devices should be claimed by parport_serial.
1796 *
1797 * The subdevice ID is of the form 0x00PS, where <P> is the number
1798 * of parallel ports and <S> is the number of serial ports.
1799 */
1800 switch (dev->device) {
1801 case PCI_DEVICE_ID_NETMOS_9835:
1802 /* Well, this rule doesn't hold for the following 9835 device */
1803 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1804 dev->subsystem_device == 0x0299)
1805 return;
1806 case PCI_DEVICE_ID_NETMOS_9735:
1807 case PCI_DEVICE_ID_NETMOS_9745:
1808 case PCI_DEVICE_ID_NETMOS_9845:
1809 case PCI_DEVICE_ID_NETMOS_9855:
1810 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1811 num_parallel) {
1812 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1813 "%u serial); changing class SERIAL to OTHER "
1814 "(use parport_serial)\n",
1815 dev->device, num_parallel, num_serial);
1816 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1817 (dev->class & 0xff);
1818 }
1819 }
1820 }
1821 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1822
1823 static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1824 {
1825 u16 command, pmcsr;
1826 u8 __iomem *csr;
1827 u8 cmd_hi;
1828 int pm;
1829
1830 switch (dev->device) {
1831 /* PCI IDs taken from drivers/net/e100.c */
1832 case 0x1029:
1833 case 0x1030 ... 0x1034:
1834 case 0x1038 ... 0x103E:
1835 case 0x1050 ... 0x1057:
1836 case 0x1059:
1837 case 0x1064 ... 0x106B:
1838 case 0x1091 ... 0x1095:
1839 case 0x1209:
1840 case 0x1229:
1841 case 0x2449:
1842 case 0x2459:
1843 case 0x245D:
1844 case 0x27DC:
1845 break;
1846 default:
1847 return;
1848 }
1849
1850 /*
1851 * Some firmware hands off the e100 with interrupts enabled,
1852 * which can cause a flood of interrupts if packets are
1853 * received before the driver attaches to the device. So
1854 * disable all e100 interrupts here. The driver will
1855 * re-enable them when it's ready.
1856 */
1857 pci_read_config_word(dev, PCI_COMMAND, &command);
1858
1859 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1860 return;
1861
1862 /*
1863 * Check that the device is in the D0 power state. If it's not,
1864 * there is no point to look any further.
1865 */
1866 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1867 if (pm) {
1868 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1869 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1870 return;
1871 }
1872
1873 /* Convert from PCI bus to resource space. */
1874 csr = ioremap(pci_resource_start(dev, 0), 8);
1875 if (!csr) {
1876 dev_warn(&dev->dev, "Can't map e100 registers\n");
1877 return;
1878 }
1879
1880 cmd_hi = readb(csr + 3);
1881 if (cmd_hi == 0) {
1882 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1883 "disabling\n");
1884 writeb(1, csr + 3);
1885 }
1886
1887 iounmap(csr);
1888 }
1889 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
1890
1891 /*
1892 * The 82575 and 82598 may experience data corruption issues when transitioning
1893 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1894 */
1895 static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev)
1896 {
1897 dev_info(&dev->dev, "Disabling L0s\n");
1898 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1899 }
1900 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1901 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1902 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1903 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1904 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1905 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1906 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1907 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1908 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1909 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1910 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1911 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1912 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1913 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1914
1915 static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1916 {
1917 /* rev 1 ncr53c810 chips don't set the class at all which means
1918 * they don't get their resources remapped. Fix that here.
1919 */
1920
1921 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1922 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
1923 dev->class = PCI_CLASS_STORAGE_SCSI;
1924 }
1925 }
1926 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1927
1928 /* Enable 1k I/O space granularity on the Intel P64H2 */
1929 static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1930 {
1931 u16 en1k;
1932 u8 io_base_lo, io_limit_lo;
1933 unsigned long base, limit;
1934 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1935
1936 pci_read_config_word(dev, 0x40, &en1k);
1937
1938 if (en1k & 0x200) {
1939 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
1940
1941 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1942 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1943 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1944 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1945
1946 if (base <= limit) {
1947 res->start = base;
1948 res->end = limit + 0x3ff;
1949 }
1950 }
1951 }
1952 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1953
1954 /* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1955 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1956 * in drivers/pci/setup-bus.c
1957 */
1958 static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1959 {
1960 u16 en1k, iobl_adr, iobl_adr_1k;
1961 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1962
1963 pci_read_config_word(dev, 0x40, &en1k);
1964
1965 if (en1k & 0x200) {
1966 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1967
1968 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1969
1970 if (iobl_adr != iobl_adr_1k) {
1971 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
1972 iobl_adr,iobl_adr_1k);
1973 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1974 }
1975 }
1976 }
1977 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1978
1979 /* Under some circumstances, AER is not linked with extended capabilities.
1980 * Force it to be linked by setting the corresponding control bit in the
1981 * config space.
1982 */
1983 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1984 {
1985 uint8_t b;
1986 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1987 if (!(b & 0x20)) {
1988 pci_write_config_byte(dev, 0xf41, b | 0x20);
1989 dev_info(&dev->dev,
1990 "Linking AER extended capability\n");
1991 }
1992 }
1993 }
1994 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1995 quirk_nvidia_ck804_pcie_aer_ext_cap);
1996 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1997 quirk_nvidia_ck804_pcie_aer_ext_cap);
1998
1999 static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2000 {
2001 /*
2002 * Disable PCI Bus Parking and PCI Master read caching on CX700
2003 * which causes unspecified timing errors with a VT6212L on the PCI
2004 * bus leading to USB2.0 packet loss.
2005 *
2006 * This quirk is only enabled if a second (on the external PCI bus)
2007 * VT6212L is found -- the CX700 core itself also contains a USB
2008 * host controller with the same PCI ID as the VT6212L.
2009 */
2010
2011 /* Count VT6212L instances */
2012 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2013 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2014 uint8_t b;
2015
2016 /* p should contain the first (internal) VT6212L -- see if we have
2017 an external one by searching again */
2018 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2019 if (!p)
2020 return;
2021 pci_dev_put(p);
2022
2023 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2024 if (b & 0x40) {
2025 /* Turn off PCI Bus Parking */
2026 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2027
2028 dev_info(&dev->dev,
2029 "Disabling VIA CX700 PCI parking\n");
2030 }
2031 }
2032
2033 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2034 if (b != 0) {
2035 /* Turn off PCI Master read caching */
2036 pci_write_config_byte(dev, 0x72, 0x0);
2037
2038 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2039 pci_write_config_byte(dev, 0x75, 0x1);
2040
2041 /* Disable "Read FIFO Timer" */
2042 pci_write_config_byte(dev, 0x77, 0x0);
2043
2044 dev_info(&dev->dev,
2045 "Disabling VIA CX700 PCI caching\n");
2046 }
2047 }
2048 }
2049 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2050
2051 /*
2052 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2053 * VPD end tag will hang the device. This problem was initially
2054 * observed when a vpd entry was created in sysfs
2055 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2056 * will dump 32k of data. Reading a full 32k will cause an access
2057 * beyond the VPD end tag causing the device to hang. Once the device
2058 * is hung, the bnx2 driver will not be able to reset the device.
2059 * We believe that it is legal to read beyond the end tag and
2060 * therefore the solution is to limit the read/write length.
2061 */
2062 static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2063 {
2064 /*
2065 * Only disable the VPD capability for 5706, 5706S, 5708,
2066 * 5708S and 5709 rev. A
2067 */
2068 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2069 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2070 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2071 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2072 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2073 (dev->revision & 0xf0) == 0x0)) {
2074 if (dev->vpd)
2075 dev->vpd->len = 0x80;
2076 }
2077 }
2078
2079 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2080 PCI_DEVICE_ID_NX2_5706,
2081 quirk_brcm_570x_limit_vpd);
2082 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2083 PCI_DEVICE_ID_NX2_5706S,
2084 quirk_brcm_570x_limit_vpd);
2085 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2086 PCI_DEVICE_ID_NX2_5708,
2087 quirk_brcm_570x_limit_vpd);
2088 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2089 PCI_DEVICE_ID_NX2_5708S,
2090 quirk_brcm_570x_limit_vpd);
2091 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2092 PCI_DEVICE_ID_NX2_5709,
2093 quirk_brcm_570x_limit_vpd);
2094 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2095 PCI_DEVICE_ID_NX2_5709S,
2096 quirk_brcm_570x_limit_vpd);
2097
2098 /* Originally in EDAC sources for i82875P:
2099 * Intel tells BIOS developers to hide device 6 which
2100 * configures the overflow device access containing
2101 * the DRBs - this is where we expose device 6.
2102 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2103 */
2104 static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev)
2105 {
2106 u8 reg;
2107
2108 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2109 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2110 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2111 }
2112 }
2113
2114 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2115 quirk_unhide_mch_dev6);
2116 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2117 quirk_unhide_mch_dev6);
2118
2119
2120 #ifdef CONFIG_PCI_MSI
2121 /* Some chipsets do not support MSI. We cannot easily rely on setting
2122 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2123 * some other busses controlled by the chipset even if Linux is not
2124 * aware of it. Instead of setting the flag on all busses in the
2125 * machine, simply disable MSI globally.
2126 */
2127 static void __init quirk_disable_all_msi(struct pci_dev *dev)
2128 {
2129 pci_no_msi();
2130 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2131 }
2132 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2133 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2134 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2135 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2136 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2137 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2138 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2139
2140 /* Disable MSI on chipsets that are known to not support it */
2141 static void __devinit quirk_disable_msi(struct pci_dev *dev)
2142 {
2143 if (dev->subordinate) {
2144 dev_warn(&dev->dev, "MSI quirk detected; "
2145 "subordinate MSI disabled\n");
2146 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2147 }
2148 }
2149 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2150 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2151 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2152
2153 /*
2154 * The APC bridge device in AMD 780 family northbridges has some random
2155 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2156 * we use the possible vendor/device IDs of the host bridge for the
2157 * declared quirk, and search for the APC bridge by slot number.
2158 */
2159 static void __devinit quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2160 {
2161 struct pci_dev *apc_bridge;
2162
2163 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2164 if (apc_bridge) {
2165 if (apc_bridge->device == 0x9602)
2166 quirk_disable_msi(apc_bridge);
2167 pci_dev_put(apc_bridge);
2168 }
2169 }
2170 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2171 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2172
2173 /* Go through the list of Hypertransport capabilities and
2174 * return 1 if a HT MSI capability is found and enabled */
2175 static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
2176 {
2177 int pos, ttl = 48;
2178
2179 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2180 while (pos && ttl--) {
2181 u8 flags;
2182
2183 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2184 &flags) == 0)
2185 {
2186 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2187 flags & HT_MSI_FLAGS_ENABLE ?
2188 "enabled" : "disabled");
2189 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2190 }
2191
2192 pos = pci_find_next_ht_capability(dev, pos,
2193 HT_CAPTYPE_MSI_MAPPING);
2194 }
2195 return 0;
2196 }
2197
2198 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2199 static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
2200 {
2201 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2202 dev_warn(&dev->dev, "MSI quirk detected; "
2203 "subordinate MSI disabled\n");
2204 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2205 }
2206 }
2207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2208 quirk_msi_ht_cap);
2209
2210 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
2211 * MSI are supported if the MSI capability set in any of these mappings.
2212 */
2213 static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2214 {
2215 struct pci_dev *pdev;
2216
2217 if (!dev->subordinate)
2218 return;
2219
2220 /* check HT MSI cap on this chipset and the root one.
2221 * a single one having MSI is enough to be sure that MSI are supported.
2222 */
2223 pdev = pci_get_slot(dev->bus, 0);
2224 if (!pdev)
2225 return;
2226 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2227 dev_warn(&dev->dev, "MSI quirk detected; "
2228 "subordinate MSI disabled\n");
2229 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2230 }
2231 pci_dev_put(pdev);
2232 }
2233 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2234 quirk_nvidia_ck804_msi_ht_cap);
2235
2236 /* Force enable MSI mapping capability on HT bridges */
2237 static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
2238 {
2239 int pos, ttl = 48;
2240
2241 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2242 while (pos && ttl--) {
2243 u8 flags;
2244
2245 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2246 &flags) == 0) {
2247 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2248
2249 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2250 flags | HT_MSI_FLAGS_ENABLE);
2251 }
2252 pos = pci_find_next_ht_capability(dev, pos,
2253 HT_CAPTYPE_MSI_MAPPING);
2254 }
2255 }
2256 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2257 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2258 ht_enable_msi_mapping);
2259
2260 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2261 ht_enable_msi_mapping);
2262
2263 /* The P5N32-SLI motherboards from Asus have a problem with msi
2264 * for the MCP55 NIC. It is not yet determined whether the msi problem
2265 * also affects other devices. As for now, turn off msi for this device.
2266 */
2267 static void __devinit nvenet_msi_disable(struct pci_dev *dev)
2268 {
2269 if (dmi_name_in_vendors("P5N32-SLI PREMIUM") ||
2270 dmi_name_in_vendors("P5N32-E SLI")) {
2271 dev_info(&dev->dev,
2272 "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2273 dev->no_msi = 1;
2274 }
2275 }
2276 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2277 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2278 nvenet_msi_disable);
2279
2280 static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
2281 {
2282 int pos, ttl = 48;
2283 int found = 0;
2284
2285 /* check if there is HT MSI cap or enabled on this device */
2286 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2287 while (pos && ttl--) {
2288 u8 flags;
2289
2290 if (found < 1)
2291 found = 1;
2292 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2293 &flags) == 0) {
2294 if (flags & HT_MSI_FLAGS_ENABLE) {
2295 if (found < 2) {
2296 found = 2;
2297 break;
2298 }
2299 }
2300 }
2301 pos = pci_find_next_ht_capability(dev, pos,
2302 HT_CAPTYPE_MSI_MAPPING);
2303 }
2304
2305 return found;
2306 }
2307
2308 static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
2309 {
2310 struct pci_dev *dev;
2311 int pos;
2312 int i, dev_no;
2313 int found = 0;
2314
2315 dev_no = host_bridge->devfn >> 3;
2316 for (i = dev_no + 1; i < 0x20; i++) {
2317 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2318 if (!dev)
2319 continue;
2320
2321 /* found next host bridge ?*/
2322 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2323 if (pos != 0) {
2324 pci_dev_put(dev);
2325 break;
2326 }
2327
2328 if (ht_check_msi_mapping(dev)) {
2329 found = 1;
2330 pci_dev_put(dev);
2331 break;
2332 }
2333 pci_dev_put(dev);
2334 }
2335
2336 return found;
2337 }
2338
2339 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2340 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2341
2342 static int __devinit is_end_of_ht_chain(struct pci_dev *dev)
2343 {
2344 int pos, ctrl_off;
2345 int end = 0;
2346 u16 flags, ctrl;
2347
2348 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2349
2350 if (!pos)
2351 goto out;
2352
2353 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2354
2355 ctrl_off = ((flags >> 10) & 1) ?
2356 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2357 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2358
2359 if (ctrl & (1 << 6))
2360 end = 1;
2361
2362 out:
2363 return end;
2364 }
2365
2366 static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
2367 {
2368 struct pci_dev *host_bridge;
2369 int pos;
2370 int i, dev_no;
2371 int found = 0;
2372
2373 dev_no = dev->devfn >> 3;
2374 for (i = dev_no; i >= 0; i--) {
2375 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2376 if (!host_bridge)
2377 continue;
2378
2379 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2380 if (pos != 0) {
2381 found = 1;
2382 break;
2383 }
2384 pci_dev_put(host_bridge);
2385 }
2386
2387 if (!found)
2388 return;
2389
2390 /* don't enable end_device/host_bridge with leaf directly here */
2391 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2392 host_bridge_with_leaf(host_bridge))
2393 goto out;
2394
2395 /* root did that ! */
2396 if (msi_ht_cap_enabled(host_bridge))
2397 goto out;
2398
2399 ht_enable_msi_mapping(dev);
2400
2401 out:
2402 pci_dev_put(host_bridge);
2403 }
2404
2405 static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
2406 {
2407 int pos, ttl = 48;
2408
2409 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2410 while (pos && ttl--) {
2411 u8 flags;
2412
2413 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2414 &flags) == 0) {
2415 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2416
2417 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2418 flags & ~HT_MSI_FLAGS_ENABLE);
2419 }
2420 pos = pci_find_next_ht_capability(dev, pos,
2421 HT_CAPTYPE_MSI_MAPPING);
2422 }
2423 }
2424
2425 static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2426 {
2427 struct pci_dev *host_bridge;
2428 int pos;
2429 int found;
2430
2431 if (!pci_msi_enabled())
2432 return;
2433
2434 /* check if there is HT MSI cap or enabled on this device */
2435 found = ht_check_msi_mapping(dev);
2436
2437 /* no HT MSI CAP */
2438 if (found == 0)
2439 return;
2440
2441 /*
2442 * HT MSI mapping should be disabled on devices that are below
2443 * a non-Hypertransport host bridge. Locate the host bridge...
2444 */
2445 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2446 if (host_bridge == NULL) {
2447 dev_warn(&dev->dev,
2448 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2449 return;
2450 }
2451
2452 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2453 if (pos != 0) {
2454 /* Host bridge is to HT */
2455 if (found == 1) {
2456 /* it is not enabled, try to enable it */
2457 if (all)
2458 ht_enable_msi_mapping(dev);
2459 else
2460 nv_ht_enable_msi_mapping(dev);
2461 }
2462 return;
2463 }
2464
2465 /* HT MSI is not enabled */
2466 if (found == 1)
2467 return;
2468
2469 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2470 ht_disable_msi_mapping(dev);
2471 }
2472
2473 static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2474 {
2475 return __nv_msi_ht_cap_quirk(dev, 1);
2476 }
2477
2478 static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2479 {
2480 return __nv_msi_ht_cap_quirk(dev, 0);
2481 }
2482
2483 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2484 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2485
2486 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2487 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2488
2489 static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
2490 {
2491 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2492 }
2493 static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2494 {
2495 struct pci_dev *p;
2496
2497 /* SB700 MSI issue will be fixed at HW level from revision A21,
2498 * we need check PCI REVISION ID of SMBus controller to get SB700
2499 * revision.
2500 */
2501 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2502 NULL);
2503 if (!p)
2504 return;
2505
2506 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2507 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2508 pci_dev_put(p);
2509 }
2510 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2511 PCI_DEVICE_ID_TIGON3_5780,
2512 quirk_msi_intx_disable_bug);
2513 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2514 PCI_DEVICE_ID_TIGON3_5780S,
2515 quirk_msi_intx_disable_bug);
2516 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2517 PCI_DEVICE_ID_TIGON3_5714,
2518 quirk_msi_intx_disable_bug);
2519 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2520 PCI_DEVICE_ID_TIGON3_5714S,
2521 quirk_msi_intx_disable_bug);
2522 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2523 PCI_DEVICE_ID_TIGON3_5715,
2524 quirk_msi_intx_disable_bug);
2525 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2526 PCI_DEVICE_ID_TIGON3_5715S,
2527 quirk_msi_intx_disable_bug);
2528
2529 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2530 quirk_msi_intx_disable_ati_bug);
2531 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2532 quirk_msi_intx_disable_ati_bug);
2533 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2534 quirk_msi_intx_disable_ati_bug);
2535 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2536 quirk_msi_intx_disable_ati_bug);
2537 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2538 quirk_msi_intx_disable_ati_bug);
2539
2540 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2541 quirk_msi_intx_disable_bug);
2542 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2543 quirk_msi_intx_disable_bug);
2544 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2545 quirk_msi_intx_disable_bug);
2546
2547 #endif /* CONFIG_PCI_MSI */
2548
2549 #ifdef CONFIG_PCI_IOV
2550
2551 /*
2552 * For Intel 82576 SR-IOV NIC, if BIOS doesn't allocate resources for the
2553 * SR-IOV BARs, zero the Flash BAR and program the SR-IOV BARs to use the
2554 * old Flash Memory Space.
2555 */
2556 static void __devinit quirk_i82576_sriov(struct pci_dev *dev)
2557 {
2558 int pos, flags;
2559 u32 bar, start, size;
2560
2561 if (PAGE_SIZE > 0x10000)
2562 return;
2563
2564 flags = pci_resource_flags(dev, 0);
2565 if ((flags & PCI_BASE_ADDRESS_SPACE) !=
2566 PCI_BASE_ADDRESS_SPACE_MEMORY ||
2567 (flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) !=
2568 PCI_BASE_ADDRESS_MEM_TYPE_32)
2569 return;
2570
2571 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
2572 if (!pos)
2573 return;
2574
2575 pci_read_config_dword(dev, pos + PCI_SRIOV_BAR, &bar);
2576 if (bar & PCI_BASE_ADDRESS_MEM_MASK)
2577 return;
2578
2579 start = pci_resource_start(dev, 1);
2580 size = pci_resource_len(dev, 1);
2581 if (!start || size != 0x400000 || start & (size - 1))
2582 return;
2583
2584 pci_resource_flags(dev, 1) = 0;
2585 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
2586 pci_write_config_dword(dev, pos + PCI_SRIOV_BAR, start);
2587 pci_write_config_dword(dev, pos + PCI_SRIOV_BAR + 12, start + size / 2);
2588
2589 dev_info(&dev->dev, "use Flash Memory Space for SR-IOV BARs\n");
2590 }
2591 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c9, quirk_i82576_sriov);
2592 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e6, quirk_i82576_sriov);
2593 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e7, quirk_i82576_sriov);
2594 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e8, quirk_i82576_sriov);
2595 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150a, quirk_i82576_sriov);
2596 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150d, quirk_i82576_sriov);
2597 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1518, quirk_i82576_sriov);
2598
2599 #endif /* CONFIG_PCI_IOV */
2600
2601 /* Allow manual resource allocation for PCI hotplug bridges
2602 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2603 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2604 * kernel fails to allocate resources when hotplug device is
2605 * inserted and PCI bus is rescanned.
2606 */
2607 static void __devinit quirk_hotplug_bridge(struct pci_dev *dev)
2608 {
2609 dev->is_hotplug_bridge = 1;
2610 }
2611
2612 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2613
2614 /*
2615 * This is a quirk for the Ricoh MMC controller found as a part of
2616 * some mulifunction chips.
2617
2618 * This is very similiar and based on the ricoh_mmc driver written by
2619 * Philip Langdale. Thank you for these magic sequences.
2620 *
2621 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2622 * and one or both of cardbus or firewire.
2623 *
2624 * It happens that they implement SD and MMC
2625 * support as separate controllers (and PCI functions). The linux SDHCI
2626 * driver supports MMC cards but the chip detects MMC cards in hardware
2627 * and directs them to the MMC controller - so the SDHCI driver never sees
2628 * them.
2629 *
2630 * To get around this, we must disable the useless MMC controller.
2631 * At that point, the SDHCI controller will start seeing them
2632 * It seems to be the case that the relevant PCI registers to deactivate the
2633 * MMC controller live on PCI function 0, which might be the cardbus controller
2634 * or the firewire controller, depending on the particular chip in question
2635 *
2636 * This has to be done early, because as soon as we disable the MMC controller
2637 * other pci functions shift up one level, e.g. function #2 becomes function
2638 * #1, and this will confuse the pci core.
2639 */
2640
2641 #ifdef CONFIG_MMC_RICOH_MMC
2642 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2643 {
2644 /* disable via cardbus interface */
2645 u8 write_enable;
2646 u8 write_target;
2647 u8 disable;
2648
2649 /* disable must be done via function #0 */
2650 if (PCI_FUNC(dev->devfn))
2651 return;
2652
2653 pci_read_config_byte(dev, 0xB7, &disable);
2654 if (disable & 0x02)
2655 return;
2656
2657 pci_read_config_byte(dev, 0x8E, &write_enable);
2658 pci_write_config_byte(dev, 0x8E, 0xAA);
2659 pci_read_config_byte(dev, 0x8D, &write_target);
2660 pci_write_config_byte(dev, 0x8D, 0xB7);
2661 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2662 pci_write_config_byte(dev, 0x8E, write_enable);
2663 pci_write_config_byte(dev, 0x8D, write_target);
2664
2665 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2666 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2667 }
2668 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2669 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2670
2671 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2672 {
2673 /* disable via firewire interface */
2674 u8 write_enable;
2675 u8 disable;
2676
2677 /* disable must be done via function #0 */
2678 if (PCI_FUNC(dev->devfn))
2679 return;
2680
2681 pci_read_config_byte(dev, 0xCB, &disable);
2682
2683 if (disable & 0x02)
2684 return;
2685
2686 pci_read_config_byte(dev, 0xCA, &write_enable);
2687 pci_write_config_byte(dev, 0xCA, 0x57);
2688 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2689 pci_write_config_byte(dev, 0xCA, write_enable);
2690
2691 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2692 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2693 }
2694 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2695 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2696 #endif /*CONFIG_MMC_RICOH_MMC*/
2697
2698
2699 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2700 struct pci_fixup *end)
2701 {
2702 while (f < end) {
2703 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
2704 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
2705 dev_dbg(&dev->dev, "calling %pF\n", f->hook);
2706 f->hook(dev);
2707 }
2708 f++;
2709 }
2710 }
2711
2712 extern struct pci_fixup __start_pci_fixups_early[];
2713 extern struct pci_fixup __end_pci_fixups_early[];
2714 extern struct pci_fixup __start_pci_fixups_header[];
2715 extern struct pci_fixup __end_pci_fixups_header[];
2716 extern struct pci_fixup __start_pci_fixups_final[];
2717 extern struct pci_fixup __end_pci_fixups_final[];
2718 extern struct pci_fixup __start_pci_fixups_enable[];
2719 extern struct pci_fixup __end_pci_fixups_enable[];
2720 extern struct pci_fixup __start_pci_fixups_resume[];
2721 extern struct pci_fixup __end_pci_fixups_resume[];
2722 extern struct pci_fixup __start_pci_fixups_resume_early[];
2723 extern struct pci_fixup __end_pci_fixups_resume_early[];
2724 extern struct pci_fixup __start_pci_fixups_suspend[];
2725 extern struct pci_fixup __end_pci_fixups_suspend[];
2726
2727
2728 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2729 {
2730 struct pci_fixup *start, *end;
2731
2732 switch(pass) {
2733 case pci_fixup_early:
2734 start = __start_pci_fixups_early;
2735 end = __end_pci_fixups_early;
2736 break;
2737
2738 case pci_fixup_header:
2739 start = __start_pci_fixups_header;
2740 end = __end_pci_fixups_header;
2741 break;
2742
2743 case pci_fixup_final:
2744 start = __start_pci_fixups_final;
2745 end = __end_pci_fixups_final;
2746 break;
2747
2748 case pci_fixup_enable:
2749 start = __start_pci_fixups_enable;
2750 end = __end_pci_fixups_enable;
2751 break;
2752
2753 case pci_fixup_resume:
2754 start = __start_pci_fixups_resume;
2755 end = __end_pci_fixups_resume;
2756 break;
2757
2758 case pci_fixup_resume_early:
2759 start = __start_pci_fixups_resume_early;
2760 end = __end_pci_fixups_resume_early;
2761 break;
2762
2763 case pci_fixup_suspend:
2764 start = __start_pci_fixups_suspend;
2765 end = __end_pci_fixups_suspend;
2766 break;
2767
2768 default:
2769 /* stupid compiler warning, you would think with an enum... */
2770 return;
2771 }
2772 pci_do_fixups(dev, start, end);
2773 }
2774 EXPORT_SYMBOL(pci_fixup_device);
2775
2776 static int __init pci_apply_final_quirks(void)
2777 {
2778 struct pci_dev *dev = NULL;
2779 u8 cls = 0;
2780 u8 tmp;
2781
2782 if (pci_cache_line_size)
2783 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
2784 pci_cache_line_size << 2);
2785
2786 for_each_pci_dev(dev) {
2787 pci_fixup_device(pci_fixup_final, dev);
2788 /*
2789 * If arch hasn't set it explicitly yet, use the CLS
2790 * value shared by all PCI devices. If there's a
2791 * mismatch, fall back to the default value.
2792 */
2793 if (!pci_cache_line_size) {
2794 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
2795 if (!cls)
2796 cls = tmp;
2797 if (!tmp || cls == tmp)
2798 continue;
2799
2800 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), "
2801 "using %u bytes\n", cls << 2, tmp << 2,
2802 pci_dfl_cache_line_size << 2);
2803 pci_cache_line_size = pci_dfl_cache_line_size;
2804 }
2805 }
2806 if (!pci_cache_line_size) {
2807 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
2808 cls << 2, pci_dfl_cache_line_size << 2);
2809 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
2810 }
2811
2812 return 0;
2813 }
2814
2815 fs_initcall_sync(pci_apply_final_quirks);
2816
2817 /*
2818 * Followings are device-specific reset methods which can be used to
2819 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
2820 * not available.
2821 */
2822 static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
2823 {
2824 int pos;
2825
2826 /* only implement PCI_CLASS_SERIAL_USB at present */
2827 if (dev->class == PCI_CLASS_SERIAL_USB) {
2828 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
2829 if (!pos)
2830 return -ENOTTY;
2831
2832 if (probe)
2833 return 0;
2834
2835 pci_write_config_byte(dev, pos + 0x4, 1);
2836 msleep(100);
2837
2838 return 0;
2839 } else {
2840 return -ENOTTY;
2841 }
2842 }
2843
2844 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
2845 {
2846 int pos;
2847
2848 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
2849 if (!pos)
2850 return -ENOTTY;
2851
2852 if (probe)
2853 return 0;
2854
2855 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
2856 PCI_EXP_DEVCTL_BCR_FLR);
2857 msleep(100);
2858
2859 return 0;
2860 }
2861
2862 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
2863
2864 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
2865 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
2866 reset_intel_82599_sfp_virtfn },
2867 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2868 reset_intel_generic_dev },
2869 { 0 }
2870 };
2871
2872 int pci_dev_specific_reset(struct pci_dev *dev, int probe)
2873 {
2874 const struct pci_dev_reset_methods *i;
2875
2876 for (i = pci_dev_reset_methods; i->reset; i++) {
2877 if ((i->vendor == dev->vendor ||
2878 i->vendor == (u16)PCI_ANY_ID) &&
2879 (i->device == dev->device ||
2880 i->device == (u16)PCI_ANY_ID))
2881 return i->reset(dev, probe);
2882 }
2883
2884 return -ENOTTY;
2885 }
Linux kernel - Deliverables
This page took 0.152774 seconds and 5 git commands to generate.