projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
x86/PCI: irq and pci_ids patch for additional Intel Cougar Point DeviceIDs
[deliverable/linux.git] / drivers / pci / quirks.c
1 /*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/acpi.h>
24 #include <linux/kallsyms.h>
25 #include <linux/dmi.h>
26 #include <linux/pci-aspm.h>
27 #include <linux/ioport.h>
28 #include <asm/dma.h> /* isa_dma_bridge_buggy */
29 #include "pci.h"
30
31 /*
32 * This quirk function disables memory decoding and releases memory resources
33 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
34 * It also rounds up size to specified alignment.
35 * Later on, the kernel will assign page-aligned memory resource back
36 * to the device.
37 */
38 static void __devinit quirk_resource_alignment(struct pci_dev *dev)
39 {
40 int i;
41 struct resource *r;
42 resource_size_t align, size;
43 u16 command;
44
45 if (!pci_is_reassigndev(dev))
46 return;
47
48 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
49 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
50 dev_warn(&dev->dev,
51 "Can't reassign resources to host bridge.\n");
52 return;
53 }
54
55 dev_info(&dev->dev,
56 "Disabling memory decoding and releasing memory resources.\n");
57 pci_read_config_word(dev, PCI_COMMAND, &command);
58 command &= ~PCI_COMMAND_MEMORY;
59 pci_write_config_word(dev, PCI_COMMAND, command);
60
61 align = pci_specified_resource_alignment(dev);
62 for (i=0; i < PCI_BRIDGE_RESOURCES; i++) {
63 r = &dev->resource[i];
64 if (!(r->flags & IORESOURCE_MEM))
65 continue;
66 size = resource_size(r);
67 if (size < align) {
68 size = align;
69 dev_info(&dev->dev,
70 "Rounding up size of resource #%d to %#llx.\n",
71 i, (unsigned long long)size);
72 }
73 r->end = size - 1;
74 r->start = 0;
75 }
76 /* Need to disable bridge's resource window,
77 * to enable the kernel to reassign new resource
78 * window later on.
79 */
80 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
81 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
82 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
83 r = &dev->resource[i];
84 if (!(r->flags & IORESOURCE_MEM))
85 continue;
86 r->end = resource_size(r) - 1;
87 r->start = 0;
88 }
89 pci_disable_bridge_window(dev);
90 }
91 }
92 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment);
93
94 /* The Mellanox Tavor device gives false positive parity errors
95 * Mark this device with a broken_parity_status, to allow
96 * PCI scanning code to "skip" this now blacklisted device.
97 */
98 static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
99 {
100 dev->broken_parity_status = 1; /* This device gives false positives */
101 }
102 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
103 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
104
105 /* Deal with broken BIOS'es that neglect to enable passive release,
106 which can cause problems in combination with the 82441FX/PPro MTRRs */
107 static void quirk_passive_release(struct pci_dev *dev)
108 {
109 struct pci_dev *d = NULL;
110 unsigned char dlc;
111
112 /* We have to make sure a particular bit is set in the PIIX3
113 ISA bridge, so we have to go out and find it. */
114 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
115 pci_read_config_byte(d, 0x82, &dlc);
116 if (!(dlc & 1<<1)) {
117 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
118 dlc |= 1<<1;
119 pci_write_config_byte(d, 0x82, dlc);
120 }
121 }
122 }
123 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
124 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
125
126 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
127 but VIA don't answer queries. If you happen to have good contacts at VIA
128 ask them for me please -- Alan
129
130 This appears to be BIOS not version dependent. So presumably there is a
131 chipset level fix */
132
133 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
134 {
135 if (!isa_dma_bridge_buggy) {
136 isa_dma_bridge_buggy=1;
137 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
138 }
139 }
140 /*
141 * Its not totally clear which chipsets are the problematic ones
142 * We know 82C586 and 82C596 variants are affected.
143 */
144 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
145 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
146 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
147 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
148 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
149 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
150 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
151
152 /*
153 * Chipsets where PCI->PCI transfers vanish or hang
154 */
155 static void __devinit quirk_nopcipci(struct pci_dev *dev)
156 {
157 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
158 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
159 pci_pci_problems |= PCIPCI_FAIL;
160 }
161 }
162 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
163 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
164
165 static void __devinit quirk_nopciamd(struct pci_dev *dev)
166 {
167 u8 rev;
168 pci_read_config_byte(dev, 0x08, &rev);
169 if (rev == 0x13) {
170 /* Erratum 24 */
171 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
172 pci_pci_problems |= PCIAGP_FAIL;
173 }
174 }
175 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
176
177 /*
178 * Triton requires workarounds to be used by the drivers
179 */
180 static void __devinit quirk_triton(struct pci_dev *dev)
181 {
182 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
183 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
184 pci_pci_problems |= PCIPCI_TRITON;
185 }
186 }
187 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
188 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
189 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
190 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
191
192 /*
193 * VIA Apollo KT133 needs PCI latency patch
194 * Made according to a windows driver based patch by George E. Breese
195 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
196 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
197 * the info on which Mr Breese based his work.
198 *
199 * Updated based on further information from the site and also on
200 * information provided by VIA
201 */
202 static void quirk_vialatency(struct pci_dev *dev)
203 {
204 struct pci_dev *p;
205 u8 busarb;
206 /* Ok we have a potential problem chipset here. Now see if we have
207 a buggy southbridge */
208
209 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
210 if (p!=NULL) {
211 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
212 /* Check for buggy part revisions */
213 if (p->revision < 0x40 || p->revision > 0x42)
214 goto exit;
215 } else {
216 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
217 if (p==NULL) /* No problem parts */
218 goto exit;
219 /* Check for buggy part revisions */
220 if (p->revision < 0x10 || p->revision > 0x12)
221 goto exit;
222 }
223
224 /*
225 * Ok we have the problem. Now set the PCI master grant to
226 * occur every master grant. The apparent bug is that under high
227 * PCI load (quite common in Linux of course) you can get data
228 * loss when the CPU is held off the bus for 3 bus master requests
229 * This happens to include the IDE controllers....
230 *
231 * VIA only apply this fix when an SB Live! is present but under
232 * both Linux and Windows this isnt enough, and we have seen
233 * corruption without SB Live! but with things like 3 UDMA IDE
234 * controllers. So we ignore that bit of the VIA recommendation..
235 */
236
237 pci_read_config_byte(dev, 0x76, &busarb);
238 /* Set bit 4 and bi 5 of byte 76 to 0x01
239 "Master priority rotation on every PCI master grant */
240 busarb &= ~(1<<5);
241 busarb |= (1<<4);
242 pci_write_config_byte(dev, 0x76, busarb);
243 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
244 exit:
245 pci_dev_put(p);
246 }
247 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
248 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
249 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
250 /* Must restore this on a resume from RAM */
251 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
252 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
253 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
254
255 /*
256 * VIA Apollo VP3 needs ETBF on BT848/878
257 */
258 static void __devinit quirk_viaetbf(struct pci_dev *dev)
259 {
260 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
261 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
262 pci_pci_problems |= PCIPCI_VIAETBF;
263 }
264 }
265 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
266
267 static void __devinit quirk_vsfx(struct pci_dev *dev)
268 {
269 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
270 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
271 pci_pci_problems |= PCIPCI_VSFX;
272 }
273 }
274 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
275
276 /*
277 * Ali Magik requires workarounds to be used by the drivers
278 * that DMA to AGP space. Latency must be set to 0xA and triton
279 * workaround applied too
280 * [Info kindly provided by ALi]
281 */
282 static void __init quirk_alimagik(struct pci_dev *dev)
283 {
284 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
285 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
286 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
287 }
288 }
289 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
290 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
291
292 /*
293 * Natoma has some interesting boundary conditions with Zoran stuff
294 * at least
295 */
296 static void __devinit quirk_natoma(struct pci_dev *dev)
297 {
298 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
299 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
300 pci_pci_problems |= PCIPCI_NATOMA;
301 }
302 }
303 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
304 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
305 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
306 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
307 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
308 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
309
310 /*
311 * This chip can cause PCI parity errors if config register 0xA0 is read
312 * while DMAs are occurring.
313 */
314 static void __devinit quirk_citrine(struct pci_dev *dev)
315 {
316 dev->cfg_size = 0xA0;
317 }
318 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
319
320 /*
321 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
322 * If it's needed, re-allocate the region.
323 */
324 static void __devinit quirk_s3_64M(struct pci_dev *dev)
325 {
326 struct resource *r = &dev->resource[0];
327
328 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
329 r->start = 0;
330 r->end = 0x3ffffff;
331 }
332 }
333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
335
336 /*
337 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
338 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
339 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
340 * (which conflicts w/ BAR1's memory range).
341 */
342 static void __devinit quirk_cs5536_vsa(struct pci_dev *dev)
343 {
344 if (pci_resource_len(dev, 0) != 8) {
345 struct resource *res = &dev->resource[0];
346 res->end = res->start + 8 - 1;
347 dev_info(&dev->dev, "CS5536 ISA bridge bug detected "
348 "(incorrect header); workaround applied.\n");
349 }
350 }
351 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
352
353 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
354 unsigned size, int nr, const char *name)
355 {
356 region &= ~(size-1);
357 if (region) {
358 struct pci_bus_region bus_region;
359 struct resource *res = dev->resource + nr;
360
361 res->name = pci_name(dev);
362 res->start = region;
363 res->end = region + size - 1;
364 res->flags = IORESOURCE_IO;
365
366 /* Convert from PCI bus to resource space. */
367 bus_region.start = res->start;
368 bus_region.end = res->end;
369 pcibios_bus_to_resource(dev, res, &bus_region);
370
371 if (pci_claim_resource(dev, nr) == 0)
372 dev_info(&dev->dev, "quirk: %pR claimed by %s\n",
373 res, name);
374 }
375 }
376
377 /*
378 * ATI Northbridge setups MCE the processor if you even
379 * read somewhere between 0x3b0->0x3bb or read 0x3d3
380 */
381 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
382 {
383 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
384 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
385 request_region(0x3b0, 0x0C, "RadeonIGP");
386 request_region(0x3d3, 0x01, "RadeonIGP");
387 }
388 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
389
390 /*
391 * Let's make the southbridge information explicit instead
392 * of having to worry about people probing the ACPI areas,
393 * for example.. (Yes, it happens, and if you read the wrong
394 * ACPI register it will put the machine to sleep with no
395 * way of waking it up again. Bummer).
396 *
397 * ALI M7101: Two IO regions pointed to by words at
398 * 0xE0 (64 bytes of ACPI registers)
399 * 0xE2 (32 bytes of SMB registers)
400 */
401 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
402 {
403 u16 region;
404
405 pci_read_config_word(dev, 0xE0, &region);
406 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
407 pci_read_config_word(dev, 0xE2, &region);
408 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
409 }
410 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
411
412 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
413 {
414 u32 devres;
415 u32 mask, size, base;
416
417 pci_read_config_dword(dev, port, &devres);
418 if ((devres & enable) != enable)
419 return;
420 mask = (devres >> 16) & 15;
421 base = devres & 0xffff;
422 size = 16;
423 for (;;) {
424 unsigned bit = size >> 1;
425 if ((bit & mask) == bit)
426 break;
427 size = bit;
428 }
429 /*
430 * For now we only print it out. Eventually we'll want to
431 * reserve it (at least if it's in the 0x1000+ range), but
432 * let's get enough confirmation reports first.
433 */
434 base &= -size;
435 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
436 }
437
438 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
439 {
440 u32 devres;
441 u32 mask, size, base;
442
443 pci_read_config_dword(dev, port, &devres);
444 if ((devres & enable) != enable)
445 return;
446 base = devres & 0xffff0000;
447 mask = (devres & 0x3f) << 16;
448 size = 128 << 16;
449 for (;;) {
450 unsigned bit = size >> 1;
451 if ((bit & mask) == bit)
452 break;
453 size = bit;
454 }
455 /*
456 * For now we only print it out. Eventually we'll want to
457 * reserve it, but let's get enough confirmation reports first.
458 */
459 base &= -size;
460 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
461 }
462
463 /*
464 * PIIX4 ACPI: Two IO regions pointed to by longwords at
465 * 0x40 (64 bytes of ACPI registers)
466 * 0x90 (16 bytes of SMB registers)
467 * and a few strange programmable PIIX4 device resources.
468 */
469 static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
470 {
471 u32 region, res_a;
472
473 pci_read_config_dword(dev, 0x40, &region);
474 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
475 pci_read_config_dword(dev, 0x90, &region);
476 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
477
478 /* Device resource A has enables for some of the other ones */
479 pci_read_config_dword(dev, 0x5c, &res_a);
480
481 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
482 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
483
484 /* Device resource D is just bitfields for static resources */
485
486 /* Device 12 enabled? */
487 if (res_a & (1 << 29)) {
488 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
489 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
490 }
491 /* Device 13 enabled? */
492 if (res_a & (1 << 30)) {
493 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
494 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
495 }
496 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
497 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
498 }
499 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
500 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
501
502 /*
503 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
504 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
505 * 0x58 (64 bytes of GPIO I/O space)
506 */
507 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
508 {
509 u32 region;
510
511 pci_read_config_dword(dev, 0x40, &region);
512 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
513
514 pci_read_config_dword(dev, 0x58, &region);
515 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
516 }
517 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
518 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
519 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
520 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
521 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
522 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
523 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
524 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
525 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
526 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
527
528 static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
529 {
530 u32 region;
531
532 pci_read_config_dword(dev, 0x40, &region);
533 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
534
535 pci_read_config_dword(dev, 0x48, &region);
536 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
537 }
538
539 static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
540 {
541 u32 val;
542 u32 size, base;
543
544 pci_read_config_dword(dev, reg, &val);
545
546 /* Enabled? */
547 if (!(val & 1))
548 return;
549 base = val & 0xfffc;
550 if (dynsize) {
551 /*
552 * This is not correct. It is 16, 32 or 64 bytes depending on
553 * register D31:F0:ADh bits 5:4.
554 *
555 * But this gets us at least _part_ of it.
556 */
557 size = 16;
558 } else {
559 size = 128;
560 }
561 base &= ~(size-1);
562
563 /* Just print it out for now. We should reserve it after more debugging */
564 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
565 }
566
567 static void __devinit quirk_ich6_lpc(struct pci_dev *dev)
568 {
569 /* Shared ACPI/GPIO decode with all ICH6+ */
570 ich6_lpc_acpi_gpio(dev);
571
572 /* ICH6-specific generic IO decode */
573 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
574 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
575 }
576 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
577 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
578
579 static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
580 {
581 u32 val;
582 u32 mask, base;
583
584 pci_read_config_dword(dev, reg, &val);
585
586 /* Enabled? */
587 if (!(val & 1))
588 return;
589
590 /*
591 * IO base in bits 15:2, mask in bits 23:18, both
592 * are dword-based
593 */
594 base = val & 0xfffc;
595 mask = (val >> 16) & 0xfc;
596 mask |= 3;
597
598 /* Just print it out for now. We should reserve it after more debugging */
599 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
600 }
601
602 /* ICH7-10 has the same common LPC generic IO decode registers */
603 static void __devinit quirk_ich7_lpc(struct pci_dev *dev)
604 {
605 /* We share the common ACPI/DPIO decode with ICH6 */
606 ich6_lpc_acpi_gpio(dev);
607
608 /* And have 4 ICH7+ generic decodes */
609 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
610 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
611 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
612 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
613 }
614 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
615 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
616 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
617 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
618 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
619 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
620 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
621 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
622 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
623 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
624 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
625 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
626 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
627
628 /*
629 * VIA ACPI: One IO region pointed to by longword at
630 * 0x48 or 0x20 (256 bytes of ACPI registers)
631 */
632 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
633 {
634 u32 region;
635
636 if (dev->revision & 0x10) {
637 pci_read_config_dword(dev, 0x48, &region);
638 region &= PCI_BASE_ADDRESS_IO_MASK;
639 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
640 }
641 }
642 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
643
644 /*
645 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
646 * 0x48 (256 bytes of ACPI registers)
647 * 0x70 (128 bytes of hardware monitoring register)
648 * 0x90 (16 bytes of SMB registers)
649 */
650 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
651 {
652 u16 hm;
653 u32 smb;
654
655 quirk_vt82c586_acpi(dev);
656
657 pci_read_config_word(dev, 0x70, &hm);
658 hm &= PCI_BASE_ADDRESS_IO_MASK;
659 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
660
661 pci_read_config_dword(dev, 0x90, &smb);
662 smb &= PCI_BASE_ADDRESS_IO_MASK;
663 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
664 }
665 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
666
667 /*
668 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
669 * 0x88 (128 bytes of power management registers)
670 * 0xd0 (16 bytes of SMB registers)
671 */
672 static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
673 {
674 u16 pm, smb;
675
676 pci_read_config_word(dev, 0x88, &pm);
677 pm &= PCI_BASE_ADDRESS_IO_MASK;
678 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
679
680 pci_read_config_word(dev, 0xd0, &smb);
681 smb &= PCI_BASE_ADDRESS_IO_MASK;
682 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
683 }
684 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
685
686 /*
687 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
688 * Disable fast back-to-back on the secondary bus segment
689 */
690 static void __devinit quirk_xio2000a(struct pci_dev *dev)
691 {
692 struct pci_dev *pdev;
693 u16 command;
694
695 dev_warn(&dev->dev, "TI XIO2000a quirk detected; "
696 "secondary bus fast back-to-back transfers disabled\n");
697 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
698 pci_read_config_word(pdev, PCI_COMMAND, &command);
699 if (command & PCI_COMMAND_FAST_BACK)
700 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
701 }
702 }
703 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
704 quirk_xio2000a);
705
706 #ifdef CONFIG_X86_IO_APIC
707
708 #include <asm/io_apic.h>
709
710 /*
711 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
712 * devices to the external APIC.
713 *
714 * TODO: When we have device-specific interrupt routers,
715 * this code will go away from quirks.
716 */
717 static void quirk_via_ioapic(struct pci_dev *dev)
718 {
719 u8 tmp;
720
721 if (nr_ioapics < 1)
722 tmp = 0; /* nothing routed to external APIC */
723 else
724 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
725
726 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
727 tmp == 0 ? "Disa" : "Ena");
728
729 /* Offset 0x58: External APIC IRQ output control */
730 pci_write_config_byte (dev, 0x58, tmp);
731 }
732 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
733 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
734
735 /*
736 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
737 * This leads to doubled level interrupt rates.
738 * Set this bit to get rid of cycle wastage.
739 * Otherwise uncritical.
740 */
741 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
742 {
743 u8 misc_control2;
744 #define BYPASS_APIC_DEASSERT 8
745
746 pci_read_config_byte(dev, 0x5B, &misc_control2);
747 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
748 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
749 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
750 }
751 }
752 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
753 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
754
755 /*
756 * The AMD io apic can hang the box when an apic irq is masked.
757 * We check all revs >= B0 (yet not in the pre production!) as the bug
758 * is currently marked NoFix
759 *
760 * We have multiple reports of hangs with this chipset that went away with
761 * noapic specified. For the moment we assume it's the erratum. We may be wrong
762 * of course. However the advice is demonstrably good even if so..
763 */
764 static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
765 {
766 if (dev->revision >= 0x02) {
767 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
768 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
769 }
770 }
771 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
772
773 static void __init quirk_ioapic_rmw(struct pci_dev *dev)
774 {
775 if (dev->devfn == 0 && dev->bus->number == 0)
776 sis_apic_bug = 1;
777 }
778 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
779 #endif /* CONFIG_X86_IO_APIC */
780
781 /*
782 * Some settings of MMRBC can lead to data corruption so block changes.
783 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
784 */
785 static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
786 {
787 if (dev->subordinate && dev->revision <= 0x12) {
788 dev_info(&dev->dev, "AMD8131 rev %x detected; "
789 "disabling PCI-X MMRBC\n", dev->revision);
790 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
791 }
792 }
793 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
794
795 /*
796 * FIXME: it is questionable that quirk_via_acpi
797 * is needed. It shows up as an ISA bridge, and does not
798 * support the PCI_INTERRUPT_LINE register at all. Therefore
799 * it seems like setting the pci_dev's 'irq' to the
800 * value of the ACPI SCI interrupt is only done for convenience.
801 * -jgarzik
802 */
803 static void __devinit quirk_via_acpi(struct pci_dev *d)
804 {
805 /*
806 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
807 */
808 u8 irq;
809 pci_read_config_byte(d, 0x42, &irq);
810 irq &= 0xf;
811 if (irq && (irq != 2))
812 d->irq = irq;
813 }
814 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
815 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
816
817
818 /*
819 * VIA bridges which have VLink
820 */
821
822 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
823
824 static void quirk_via_bridge(struct pci_dev *dev)
825 {
826 /* See what bridge we have and find the device ranges */
827 switch (dev->device) {
828 case PCI_DEVICE_ID_VIA_82C686:
829 /* The VT82C686 is special, it attaches to PCI and can have
830 any device number. All its subdevices are functions of
831 that single device. */
832 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
833 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
834 break;
835 case PCI_DEVICE_ID_VIA_8237:
836 case PCI_DEVICE_ID_VIA_8237A:
837 via_vlink_dev_lo = 15;
838 break;
839 case PCI_DEVICE_ID_VIA_8235:
840 via_vlink_dev_lo = 16;
841 break;
842 case PCI_DEVICE_ID_VIA_8231:
843 case PCI_DEVICE_ID_VIA_8233_0:
844 case PCI_DEVICE_ID_VIA_8233A:
845 case PCI_DEVICE_ID_VIA_8233C_0:
846 via_vlink_dev_lo = 17;
847 break;
848 }
849 }
850 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
851 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
852 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
853 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
854 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
855 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
856 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
857 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
858
859 /**
860 * quirk_via_vlink - VIA VLink IRQ number update
861 * @dev: PCI device
862 *
863 * If the device we are dealing with is on a PIC IRQ we need to
864 * ensure that the IRQ line register which usually is not relevant
865 * for PCI cards, is actually written so that interrupts get sent
866 * to the right place.
867 * We only do this on systems where a VIA south bridge was detected,
868 * and only for VIA devices on the motherboard (see quirk_via_bridge
869 * above).
870 */
871
872 static void quirk_via_vlink(struct pci_dev *dev)
873 {
874 u8 irq, new_irq;
875
876 /* Check if we have VLink at all */
877 if (via_vlink_dev_lo == -1)
878 return;
879
880 new_irq = dev->irq;
881
882 /* Don't quirk interrupts outside the legacy IRQ range */
883 if (!new_irq || new_irq > 15)
884 return;
885
886 /* Internal device ? */
887 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
888 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
889 return;
890
891 /* This is an internal VLink device on a PIC interrupt. The BIOS
892 ought to have set this but may not have, so we redo it */
893
894 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
895 if (new_irq != irq) {
896 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
897 irq, new_irq);
898 udelay(15); /* unknown if delay really needed */
899 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
900 }
901 }
902 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
903
904 /*
905 * VIA VT82C598 has its device ID settable and many BIOSes
906 * set it to the ID of VT82C597 for backward compatibility.
907 * We need to switch it off to be able to recognize the real
908 * type of the chip.
909 */
910 static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
911 {
912 pci_write_config_byte(dev, 0xfc, 0);
913 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
914 }
915 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
916
917 /*
918 * CardBus controllers have a legacy base address that enables them
919 * to respond as i82365 pcmcia controllers. We don't want them to
920 * do this even if the Linux CardBus driver is not loaded, because
921 * the Linux i82365 driver does not (and should not) handle CardBus.
922 */
923 static void quirk_cardbus_legacy(struct pci_dev *dev)
924 {
925 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
926 return;
927 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
928 }
929 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
930 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
931
932 /*
933 * Following the PCI ordering rules is optional on the AMD762. I'm not
934 * sure what the designers were smoking but let's not inhale...
935 *
936 * To be fair to AMD, it follows the spec by default, its BIOS people
937 * who turn it off!
938 */
939 static void quirk_amd_ordering(struct pci_dev *dev)
940 {
941 u32 pcic;
942 pci_read_config_dword(dev, 0x4C, &pcic);
943 if ((pcic&6)!=6) {
944 pcic |= 6;
945 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
946 pci_write_config_dword(dev, 0x4C, pcic);
947 pci_read_config_dword(dev, 0x84, &pcic);
948 pcic |= (1<<23); /* Required in this mode */
949 pci_write_config_dword(dev, 0x84, pcic);
950 }
951 }
952 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
953 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
954
955 /*
956 * DreamWorks provided workaround for Dunord I-3000 problem
957 *
958 * This card decodes and responds to addresses not apparently
959 * assigned to it. We force a larger allocation to ensure that
960 * nothing gets put too close to it.
961 */
962 static void __devinit quirk_dunord ( struct pci_dev * dev )
963 {
964 struct resource *r = &dev->resource [1];
965 r->start = 0;
966 r->end = 0xffffff;
967 }
968 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
969
970 /*
971 * i82380FB mobile docking controller: its PCI-to-PCI bridge
972 * is subtractive decoding (transparent), and does indicate this
973 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
974 * instead of 0x01.
975 */
976 static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
977 {
978 dev->transparent = 1;
979 }
980 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
981 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
982
983 /*
984 * Common misconfiguration of the MediaGX/Geode PCI master that will
985 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
986 * datasheets found at http://www.national.com/ds/GX for info on what
987 * these bits do. <christer@weinigel.se>
988 */
989 static void quirk_mediagx_master(struct pci_dev *dev)
990 {
991 u8 reg;
992 pci_read_config_byte(dev, 0x41, &reg);
993 if (reg & 2) {
994 reg &= ~2;
995 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
996 pci_write_config_byte(dev, 0x41, reg);
997 }
998 }
999 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1000 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1001
1002 /*
1003 * Ensure C0 rev restreaming is off. This is normally done by
1004 * the BIOS but in the odd case it is not the results are corruption
1005 * hence the presence of a Linux check
1006 */
1007 static void quirk_disable_pxb(struct pci_dev *pdev)
1008 {
1009 u16 config;
1010
1011 if (pdev->revision != 0x04) /* Only C0 requires this */
1012 return;
1013 pci_read_config_word(pdev, 0x40, &config);
1014 if (config & (1<<6)) {
1015 config &= ~(1<<6);
1016 pci_write_config_word(pdev, 0x40, config);
1017 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1018 }
1019 }
1020 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1021 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1022
1023 static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
1024 {
1025 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1026 u8 tmp;
1027
1028 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1029 if (tmp == 0x01) {
1030 pci_read_config_byte(pdev, 0x40, &tmp);
1031 pci_write_config_byte(pdev, 0x40, tmp|1);
1032 pci_write_config_byte(pdev, 0x9, 1);
1033 pci_write_config_byte(pdev, 0xa, 6);
1034 pci_write_config_byte(pdev, 0x40, tmp);
1035
1036 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1037 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1038 }
1039 }
1040 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1041 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1042 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1043 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1044 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1045 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1046
1047 /*
1048 * Serverworks CSB5 IDE does not fully support native mode
1049 */
1050 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
1051 {
1052 u8 prog;
1053 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1054 if (prog & 5) {
1055 prog &= ~5;
1056 pdev->class &= ~5;
1057 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1058 /* PCI layer will sort out resources */
1059 }
1060 }
1061 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1062
1063 /*
1064 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1065 */
1066 static void __init quirk_ide_samemode(struct pci_dev *pdev)
1067 {
1068 u8 prog;
1069
1070 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1071
1072 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1073 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1074 prog &= ~5;
1075 pdev->class &= ~5;
1076 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1077 }
1078 }
1079 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1080
1081 /*
1082 * Some ATA devices break if put into D3
1083 */
1084
1085 static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
1086 {
1087 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1088 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE)
1089 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1090 }
1091 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3);
1092 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3);
1093 /* ALi loses some register settings that we cannot then restore */
1094 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, quirk_no_ata_d3);
1095 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1096 occur when mode detecting */
1097 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_no_ata_d3);
1098
1099 /* This was originally an Alpha specific thing, but it really fits here.
1100 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1101 */
1102 static void __init quirk_eisa_bridge(struct pci_dev *dev)
1103 {
1104 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1105 }
1106 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1107
1108
1109 /*
1110 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1111 * is not activated. The myth is that Asus said that they do not want the
1112 * users to be irritated by just another PCI Device in the Win98 device
1113 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1114 * package 2.7.0 for details)
1115 *
1116 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1117 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1118 * becomes necessary to do this tweak in two steps -- the chosen trigger
1119 * is either the Host bridge (preferred) or on-board VGA controller.
1120 *
1121 * Note that we used to unhide the SMBus that way on Toshiba laptops
1122 * (Satellite A40 and Tecra M2) but then found that the thermal management
1123 * was done by SMM code, which could cause unsynchronized concurrent
1124 * accesses to the SMBus registers, with potentially bad effects. Thus you
1125 * should be very careful when adding new entries: if SMM is accessing the
1126 * Intel SMBus, this is a very good reason to leave it hidden.
1127 *
1128 * Likewise, many recent laptops use ACPI for thermal management. If the
1129 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1130 * natively, and keeping the SMBus hidden is the right thing to do. If you
1131 * are about to add an entry in the table below, please first disassemble
1132 * the DSDT and double-check that there is no code accessing the SMBus.
1133 */
1134 static int asus_hides_smbus;
1135
1136 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1137 {
1138 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1139 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1140 switch(dev->subsystem_device) {
1141 case 0x8025: /* P4B-LX */
1142 case 0x8070: /* P4B */
1143 case 0x8088: /* P4B533 */
1144 case 0x1626: /* L3C notebook */
1145 asus_hides_smbus = 1;
1146 }
1147 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1148 switch(dev->subsystem_device) {
1149 case 0x80b1: /* P4GE-V */
1150 case 0x80b2: /* P4PE */
1151 case 0x8093: /* P4B533-V */
1152 asus_hides_smbus = 1;
1153 }
1154 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1155 switch(dev->subsystem_device) {
1156 case 0x8030: /* P4T533 */
1157 asus_hides_smbus = 1;
1158 }
1159 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1160 switch (dev->subsystem_device) {
1161 case 0x8070: /* P4G8X Deluxe */
1162 asus_hides_smbus = 1;
1163 }
1164 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1165 switch (dev->subsystem_device) {
1166 case 0x80c9: /* PU-DLS */
1167 asus_hides_smbus = 1;
1168 }
1169 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1170 switch (dev->subsystem_device) {
1171 case 0x1751: /* M2N notebook */
1172 case 0x1821: /* M5N notebook */
1173 case 0x1897: /* A6L notebook */
1174 asus_hides_smbus = 1;
1175 }
1176 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1177 switch (dev->subsystem_device) {
1178 case 0x184b: /* W1N notebook */
1179 case 0x186a: /* M6Ne notebook */
1180 asus_hides_smbus = 1;
1181 }
1182 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1183 switch (dev->subsystem_device) {
1184 case 0x80f2: /* P4P800-X */
1185 asus_hides_smbus = 1;
1186 }
1187 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1188 switch (dev->subsystem_device) {
1189 case 0x1882: /* M6V notebook */
1190 case 0x1977: /* A6VA notebook */
1191 asus_hides_smbus = 1;
1192 }
1193 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1194 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1195 switch(dev->subsystem_device) {
1196 case 0x088C: /* HP Compaq nc8000 */
1197 case 0x0890: /* HP Compaq nc6000 */
1198 asus_hides_smbus = 1;
1199 }
1200 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1201 switch (dev->subsystem_device) {
1202 case 0x12bc: /* HP D330L */
1203 case 0x12bd: /* HP D530 */
1204 case 0x006a: /* HP Compaq nx9500 */
1205 asus_hides_smbus = 1;
1206 }
1207 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1208 switch (dev->subsystem_device) {
1209 case 0x12bf: /* HP xw4100 */
1210 asus_hides_smbus = 1;
1211 }
1212 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1213 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1214 switch(dev->subsystem_device) {
1215 case 0xC00C: /* Samsung P35 notebook */
1216 asus_hides_smbus = 1;
1217 }
1218 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1219 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1220 switch(dev->subsystem_device) {
1221 case 0x0058: /* Compaq Evo N620c */
1222 asus_hides_smbus = 1;
1223 }
1224 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1225 switch(dev->subsystem_device) {
1226 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1227 /* Motherboard doesn't have Host bridge
1228 * subvendor/subdevice IDs, therefore checking
1229 * its on-board VGA controller */
1230 asus_hides_smbus = 1;
1231 }
1232 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1233 switch(dev->subsystem_device) {
1234 case 0x00b8: /* Compaq Evo D510 CMT */
1235 case 0x00b9: /* Compaq Evo D510 SFF */
1236 case 0x00ba: /* Compaq Evo D510 USDT */
1237 /* Motherboard doesn't have Host bridge
1238 * subvendor/subdevice IDs and on-board VGA
1239 * controller is disabled if an AGP card is
1240 * inserted, therefore checking USB UHCI
1241 * Controller #1 */
1242 asus_hides_smbus = 1;
1243 }
1244 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1245 switch (dev->subsystem_device) {
1246 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1247 /* Motherboard doesn't have host bridge
1248 * subvendor/subdevice IDs, therefore checking
1249 * its on-board VGA controller */
1250 asus_hides_smbus = 1;
1251 }
1252 }
1253 }
1254 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1255 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1256 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1257 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1258 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1259 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1260 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1261 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1262 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1263 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1264
1265 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1266 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1267 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1268
1269 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1270 {
1271 u16 val;
1272
1273 if (likely(!asus_hides_smbus))
1274 return;
1275
1276 pci_read_config_word(dev, 0xF2, &val);
1277 if (val & 0x8) {
1278 pci_write_config_word(dev, 0xF2, val & (~0x8));
1279 pci_read_config_word(dev, 0xF2, &val);
1280 if (val & 0x8)
1281 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1282 else
1283 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1284 }
1285 }
1286 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1287 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1288 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1289 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1290 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1291 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1292 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1293 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1294 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1295 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1296 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1297 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1298 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1299 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1300
1301 /* It appears we just have one such device. If not, we have a warning */
1302 static void __iomem *asus_rcba_base;
1303 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1304 {
1305 u32 rcba;
1306
1307 if (likely(!asus_hides_smbus))
1308 return;
1309 WARN_ON(asus_rcba_base);
1310
1311 pci_read_config_dword(dev, 0xF0, &rcba);
1312 /* use bits 31:14, 16 kB aligned */
1313 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1314 if (asus_rcba_base == NULL)
1315 return;
1316 }
1317
1318 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1319 {
1320 u32 val;
1321
1322 if (likely(!asus_hides_smbus || !asus_rcba_base))
1323 return;
1324 /* read the Function Disable register, dword mode only */
1325 val = readl(asus_rcba_base + 0x3418);
1326 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1327 }
1328
1329 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1330 {
1331 if (likely(!asus_hides_smbus || !asus_rcba_base))
1332 return;
1333 iounmap(asus_rcba_base);
1334 asus_rcba_base = NULL;
1335 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1336 }
1337
1338 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1339 {
1340 asus_hides_smbus_lpc_ich6_suspend(dev);
1341 asus_hides_smbus_lpc_ich6_resume_early(dev);
1342 asus_hides_smbus_lpc_ich6_resume(dev);
1343 }
1344 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1345 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1346 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1347 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1348
1349 /*
1350 * SiS 96x south bridge: BIOS typically hides SMBus device...
1351 */
1352 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1353 {
1354 u8 val = 0;
1355 pci_read_config_byte(dev, 0x77, &val);
1356 if (val & 0x10) {
1357 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1358 pci_write_config_byte(dev, 0x77, val & ~0x10);
1359 }
1360 }
1361 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1362 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1363 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1364 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1365 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1366 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1367 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1368 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1369
1370 /*
1371 * ... This is further complicated by the fact that some SiS96x south
1372 * bridges pretend to be 85C503/5513 instead. In that case see if we
1373 * spotted a compatible north bridge to make sure.
1374 * (pci_find_device doesn't work yet)
1375 *
1376 * We can also enable the sis96x bit in the discovery register..
1377 */
1378 #define SIS_DETECT_REGISTER 0x40
1379
1380 static void quirk_sis_503(struct pci_dev *dev)
1381 {
1382 u8 reg;
1383 u16 devid;
1384
1385 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1386 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1387 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1388 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1389 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1390 return;
1391 }
1392
1393 /*
1394 * Ok, it now shows up as a 96x.. run the 96x quirk by
1395 * hand in case it has already been processed.
1396 * (depends on link order, which is apparently not guaranteed)
1397 */
1398 dev->device = devid;
1399 quirk_sis_96x_smbus(dev);
1400 }
1401 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1402 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1403
1404
1405 /*
1406 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1407 * and MC97 modem controller are disabled when a second PCI soundcard is
1408 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1409 * -- bjd
1410 */
1411 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1412 {
1413 u8 val;
1414 int asus_hides_ac97 = 0;
1415
1416 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1417 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1418 asus_hides_ac97 = 1;
1419 }
1420
1421 if (!asus_hides_ac97)
1422 return;
1423
1424 pci_read_config_byte(dev, 0x50, &val);
1425 if (val & 0xc0) {
1426 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1427 pci_read_config_byte(dev, 0x50, &val);
1428 if (val & 0xc0)
1429 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1430 else
1431 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1432 }
1433 }
1434 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1435 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1436
1437 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1438
1439 /*
1440 * If we are using libata we can drive this chip properly but must
1441 * do this early on to make the additional device appear during
1442 * the PCI scanning.
1443 */
1444 static void quirk_jmicron_ata(struct pci_dev *pdev)
1445 {
1446 u32 conf1, conf5, class;
1447 u8 hdr;
1448
1449 /* Only poke fn 0 */
1450 if (PCI_FUNC(pdev->devfn))
1451 return;
1452
1453 pci_read_config_dword(pdev, 0x40, &conf1);
1454 pci_read_config_dword(pdev, 0x80, &conf5);
1455
1456 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1457 conf5 &= ~(1 << 24); /* Clear bit 24 */
1458
1459 switch (pdev->device) {
1460 case PCI_DEVICE_ID_JMICRON_JMB360:
1461 /* The controller should be in single function ahci mode */
1462 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1463 break;
1464
1465 case PCI_DEVICE_ID_JMICRON_JMB365:
1466 case PCI_DEVICE_ID_JMICRON_JMB366:
1467 /* Redirect IDE second PATA port to the right spot */
1468 conf5 |= (1 << 24);
1469 /* Fall through */
1470 case PCI_DEVICE_ID_JMICRON_JMB361:
1471 case PCI_DEVICE_ID_JMICRON_JMB363:
1472 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1473 /* Set the class codes correctly and then direct IDE 0 */
1474 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1475 break;
1476
1477 case PCI_DEVICE_ID_JMICRON_JMB368:
1478 /* The controller should be in single function IDE mode */
1479 conf1 |= 0x00C00000; /* Set 22, 23 */
1480 break;
1481 }
1482
1483 pci_write_config_dword(pdev, 0x40, conf1);
1484 pci_write_config_dword(pdev, 0x80, conf5);
1485
1486 /* Update pdev accordingly */
1487 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1488 pdev->hdr_type = hdr & 0x7f;
1489 pdev->multifunction = !!(hdr & 0x80);
1490
1491 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1492 pdev->class = class >> 8;
1493 }
1494 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1495 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1496 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1497 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1498 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1499 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1500 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1501 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1502 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1503 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1504 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1505 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1506
1507 #endif
1508
1509 #ifdef CONFIG_X86_IO_APIC
1510 static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1511 {
1512 int i;
1513
1514 if ((pdev->class >> 8) != 0xff00)
1515 return;
1516
1517 /* the first BAR is the location of the IO APIC...we must
1518 * not touch this (and it's already covered by the fixmap), so
1519 * forcibly insert it into the resource tree */
1520 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1521 insert_resource(&iomem_resource, &pdev->resource[0]);
1522
1523 /* The next five BARs all seem to be rubbish, so just clean
1524 * them out */
1525 for (i=1; i < 6; i++) {
1526 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1527 }
1528
1529 }
1530 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1531 #endif
1532
1533 static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1534 {
1535 pci_msi_off(pdev);
1536 pdev->no_msi = 1;
1537 }
1538 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1539 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1540 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1541
1542
1543 /*
1544 * It's possible for the MSI to get corrupted if shpc and acpi
1545 * are used together on certain PXH-based systems.
1546 */
1547 static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1548 {
1549 pci_msi_off(dev);
1550 dev->no_msi = 1;
1551 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1552 }
1553 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1554 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1555 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1556 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1557 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1558
1559 /*
1560 * Some Intel PCI Express chipsets have trouble with downstream
1561 * device power management.
1562 */
1563 static void quirk_intel_pcie_pm(struct pci_dev * dev)
1564 {
1565 pci_pm_d3_delay = 120;
1566 dev->no_d1d2 = 1;
1567 }
1568
1569 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1570 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1571 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1572 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1573 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1574 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1575 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1576 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1577 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1578 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1579 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1580 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1581 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1582 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1583 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1584 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1585 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1586 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1587 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1588 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1589 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1590
1591 #ifdef CONFIG_X86_IO_APIC
1592 /*
1593 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1594 * remap the original interrupt in the linux kernel to the boot interrupt, so
1595 * that a PCI device's interrupt handler is installed on the boot interrupt
1596 * line instead.
1597 */
1598 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1599 {
1600 if (noioapicquirk || noioapicreroute)
1601 return;
1602
1603 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1604 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1605 dev->vendor, dev->device);
1606 }
1607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1608 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1609 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1610 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1611 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1612 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1613 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1614 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1615 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1616 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1617 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1618 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1619 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1620 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1621 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1622 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1623
1624 /*
1625 * On some chipsets we can disable the generation of legacy INTx boot
1626 * interrupts.
1627 */
1628
1629 /*
1630 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1631 * 300641-004US, section 5.7.3.
1632 */
1633 #define INTEL_6300_IOAPIC_ABAR 0x40
1634 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1635
1636 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1637 {
1638 u16 pci_config_word;
1639
1640 if (noioapicquirk)
1641 return;
1642
1643 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1644 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1645 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1646
1647 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1648 dev->vendor, dev->device);
1649 }
1650 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1651 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1652
1653 /*
1654 * disable boot interrupts on HT-1000
1655 */
1656 #define BC_HT1000_FEATURE_REG 0x64
1657 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1658 #define BC_HT1000_MAP_IDX 0xC00
1659 #define BC_HT1000_MAP_DATA 0xC01
1660
1661 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1662 {
1663 u32 pci_config_dword;
1664 u8 irq;
1665
1666 if (noioapicquirk)
1667 return;
1668
1669 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1670 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1671 BC_HT1000_PIC_REGS_ENABLE);
1672
1673 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1674 outb(irq, BC_HT1000_MAP_IDX);
1675 outb(0x00, BC_HT1000_MAP_DATA);
1676 }
1677
1678 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1679
1680 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1681 dev->vendor, dev->device);
1682 }
1683 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1684 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1685
1686 /*
1687 * disable boot interrupts on AMD and ATI chipsets
1688 */
1689 /*
1690 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1691 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1692 * (due to an erratum).
1693 */
1694 #define AMD_813X_MISC 0x40
1695 #define AMD_813X_NOIOAMODE (1<<0)
1696 #define AMD_813X_REV_B1 0x12
1697 #define AMD_813X_REV_B2 0x13
1698
1699 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1700 {
1701 u32 pci_config_dword;
1702
1703 if (noioapicquirk)
1704 return;
1705 if ((dev->revision == AMD_813X_REV_B1) ||
1706 (dev->revision == AMD_813X_REV_B2))
1707 return;
1708
1709 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1710 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1711 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1712
1713 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1714 dev->vendor, dev->device);
1715 }
1716 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1717 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1718 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1719 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1720
1721 #define AMD_8111_PCI_IRQ_ROUTING 0x56
1722
1723 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1724 {
1725 u16 pci_config_word;
1726
1727 if (noioapicquirk)
1728 return;
1729
1730 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1731 if (!pci_config_word) {
1732 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] "
1733 "already disabled\n", dev->vendor, dev->device);
1734 return;
1735 }
1736 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1737 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1738 dev->vendor, dev->device);
1739 }
1740 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1741 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1742 #endif /* CONFIG_X86_IO_APIC */
1743
1744 /*
1745 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1746 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1747 * Re-allocate the region if needed...
1748 */
1749 static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1750 {
1751 struct resource *r = &dev->resource[0];
1752
1753 if (r->start & 0x8) {
1754 r->start = 0;
1755 r->end = 0xf;
1756 }
1757 }
1758 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1759 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1760 quirk_tc86c001_ide);
1761
1762 static void __devinit quirk_netmos(struct pci_dev *dev)
1763 {
1764 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1765 unsigned int num_serial = dev->subsystem_device & 0xf;
1766
1767 /*
1768 * These Netmos parts are multiport serial devices with optional
1769 * parallel ports. Even when parallel ports are present, they
1770 * are identified as class SERIAL, which means the serial driver
1771 * will claim them. To prevent this, mark them as class OTHER.
1772 * These combo devices should be claimed by parport_serial.
1773 *
1774 * The subdevice ID is of the form 0x00PS, where <P> is the number
1775 * of parallel ports and <S> is the number of serial ports.
1776 */
1777 switch (dev->device) {
1778 case PCI_DEVICE_ID_NETMOS_9835:
1779 /* Well, this rule doesn't hold for the following 9835 device */
1780 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1781 dev->subsystem_device == 0x0299)
1782 return;
1783 case PCI_DEVICE_ID_NETMOS_9735:
1784 case PCI_DEVICE_ID_NETMOS_9745:
1785 case PCI_DEVICE_ID_NETMOS_9845:
1786 case PCI_DEVICE_ID_NETMOS_9855:
1787 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1788 num_parallel) {
1789 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1790 "%u serial); changing class SERIAL to OTHER "
1791 "(use parport_serial)\n",
1792 dev->device, num_parallel, num_serial);
1793 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1794 (dev->class & 0xff);
1795 }
1796 }
1797 }
1798 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1799
1800 static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1801 {
1802 u16 command, pmcsr;
1803 u8 __iomem *csr;
1804 u8 cmd_hi;
1805 int pm;
1806
1807 switch (dev->device) {
1808 /* PCI IDs taken from drivers/net/e100.c */
1809 case 0x1029:
1810 case 0x1030 ... 0x1034:
1811 case 0x1038 ... 0x103E:
1812 case 0x1050 ... 0x1057:
1813 case 0x1059:
1814 case 0x1064 ... 0x106B:
1815 case 0x1091 ... 0x1095:
1816 case 0x1209:
1817 case 0x1229:
1818 case 0x2449:
1819 case 0x2459:
1820 case 0x245D:
1821 case 0x27DC:
1822 break;
1823 default:
1824 return;
1825 }
1826
1827 /*
1828 * Some firmware hands off the e100 with interrupts enabled,
1829 * which can cause a flood of interrupts if packets are
1830 * received before the driver attaches to the device. So
1831 * disable all e100 interrupts here. The driver will
1832 * re-enable them when it's ready.
1833 */
1834 pci_read_config_word(dev, PCI_COMMAND, &command);
1835
1836 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1837 return;
1838
1839 /*
1840 * Check that the device is in the D0 power state. If it's not,
1841 * there is no point to look any further.
1842 */
1843 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1844 if (pm) {
1845 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1846 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1847 return;
1848 }
1849
1850 /* Convert from PCI bus to resource space. */
1851 csr = ioremap(pci_resource_start(dev, 0), 8);
1852 if (!csr) {
1853 dev_warn(&dev->dev, "Can't map e100 registers\n");
1854 return;
1855 }
1856
1857 cmd_hi = readb(csr + 3);
1858 if (cmd_hi == 0) {
1859 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1860 "disabling\n");
1861 writeb(1, csr + 3);
1862 }
1863
1864 iounmap(csr);
1865 }
1866 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
1867
1868 /*
1869 * The 82575 and 82598 may experience data corruption issues when transitioning
1870 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1871 */
1872 static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev)
1873 {
1874 dev_info(&dev->dev, "Disabling L0s\n");
1875 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1876 }
1877 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1878 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1879 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1880 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1881 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1882 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1883 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1884 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1885 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1886 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1887 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1888 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1889 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1890 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1891
1892 static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1893 {
1894 /* rev 1 ncr53c810 chips don't set the class at all which means
1895 * they don't get their resources remapped. Fix that here.
1896 */
1897
1898 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1899 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
1900 dev->class = PCI_CLASS_STORAGE_SCSI;
1901 }
1902 }
1903 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1904
1905 /* Enable 1k I/O space granularity on the Intel P64H2 */
1906 static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1907 {
1908 u16 en1k;
1909 u8 io_base_lo, io_limit_lo;
1910 unsigned long base, limit;
1911 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1912
1913 pci_read_config_word(dev, 0x40, &en1k);
1914
1915 if (en1k & 0x200) {
1916 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
1917
1918 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1919 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1920 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1921 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1922
1923 if (base <= limit) {
1924 res->start = base;
1925 res->end = limit + 0x3ff;
1926 }
1927 }
1928 }
1929 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1930
1931 /* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1932 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1933 * in drivers/pci/setup-bus.c
1934 */
1935 static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1936 {
1937 u16 en1k, iobl_adr, iobl_adr_1k;
1938 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1939
1940 pci_read_config_word(dev, 0x40, &en1k);
1941
1942 if (en1k & 0x200) {
1943 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1944
1945 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1946
1947 if (iobl_adr != iobl_adr_1k) {
1948 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
1949 iobl_adr,iobl_adr_1k);
1950 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1951 }
1952 }
1953 }
1954 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1955
1956 /* Under some circumstances, AER is not linked with extended capabilities.
1957 * Force it to be linked by setting the corresponding control bit in the
1958 * config space.
1959 */
1960 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1961 {
1962 uint8_t b;
1963 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1964 if (!(b & 0x20)) {
1965 pci_write_config_byte(dev, 0xf41, b | 0x20);
1966 dev_info(&dev->dev,
1967 "Linking AER extended capability\n");
1968 }
1969 }
1970 }
1971 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1972 quirk_nvidia_ck804_pcie_aer_ext_cap);
1973 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1974 quirk_nvidia_ck804_pcie_aer_ext_cap);
1975
1976 static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1977 {
1978 /*
1979 * Disable PCI Bus Parking and PCI Master read caching on CX700
1980 * which causes unspecified timing errors with a VT6212L on the PCI
1981 * bus leading to USB2.0 packet loss.
1982 *
1983 * This quirk is only enabled if a second (on the external PCI bus)
1984 * VT6212L is found -- the CX700 core itself also contains a USB
1985 * host controller with the same PCI ID as the VT6212L.
1986 */
1987
1988 /* Count VT6212L instances */
1989 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
1990 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
1991 uint8_t b;
1992
1993 /* p should contain the first (internal) VT6212L -- see if we have
1994 an external one by searching again */
1995 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
1996 if (!p)
1997 return;
1998 pci_dev_put(p);
1999
2000 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2001 if (b & 0x40) {
2002 /* Turn off PCI Bus Parking */
2003 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2004
2005 dev_info(&dev->dev,
2006 "Disabling VIA CX700 PCI parking\n");
2007 }
2008 }
2009
2010 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2011 if (b != 0) {
2012 /* Turn off PCI Master read caching */
2013 pci_write_config_byte(dev, 0x72, 0x0);
2014
2015 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2016 pci_write_config_byte(dev, 0x75, 0x1);
2017
2018 /* Disable "Read FIFO Timer" */
2019 pci_write_config_byte(dev, 0x77, 0x0);
2020
2021 dev_info(&dev->dev,
2022 "Disabling VIA CX700 PCI caching\n");
2023 }
2024 }
2025 }
2026 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2027
2028 /*
2029 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2030 * VPD end tag will hang the device. This problem was initially
2031 * observed when a vpd entry was created in sysfs
2032 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2033 * will dump 32k of data. Reading a full 32k will cause an access
2034 * beyond the VPD end tag causing the device to hang. Once the device
2035 * is hung, the bnx2 driver will not be able to reset the device.
2036 * We believe that it is legal to read beyond the end tag and
2037 * therefore the solution is to limit the read/write length.
2038 */
2039 static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2040 {
2041 /*
2042 * Only disable the VPD capability for 5706, 5706S, 5708,
2043 * 5708S and 5709 rev. A
2044 */
2045 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2046 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2047 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2048 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2049 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2050 (dev->revision & 0xf0) == 0x0)) {
2051 if (dev->vpd)
2052 dev->vpd->len = 0x80;
2053 }
2054 }
2055
2056 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2057 PCI_DEVICE_ID_NX2_5706,
2058 quirk_brcm_570x_limit_vpd);
2059 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2060 PCI_DEVICE_ID_NX2_5706S,
2061 quirk_brcm_570x_limit_vpd);
2062 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2063 PCI_DEVICE_ID_NX2_5708,
2064 quirk_brcm_570x_limit_vpd);
2065 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2066 PCI_DEVICE_ID_NX2_5708S,
2067 quirk_brcm_570x_limit_vpd);
2068 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2069 PCI_DEVICE_ID_NX2_5709,
2070 quirk_brcm_570x_limit_vpd);
2071 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2072 PCI_DEVICE_ID_NX2_5709S,
2073 quirk_brcm_570x_limit_vpd);
2074
2075 /* Originally in EDAC sources for i82875P:
2076 * Intel tells BIOS developers to hide device 6 which
2077 * configures the overflow device access containing
2078 * the DRBs - this is where we expose device 6.
2079 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2080 */
2081 static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev)
2082 {
2083 u8 reg;
2084
2085 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2086 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2087 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2088 }
2089 }
2090
2091 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2092 quirk_unhide_mch_dev6);
2093 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2094 quirk_unhide_mch_dev6);
2095
2096
2097 #ifdef CONFIG_PCI_MSI
2098 /* Some chipsets do not support MSI. We cannot easily rely on setting
2099 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2100 * some other busses controlled by the chipset even if Linux is not
2101 * aware of it. Instead of setting the flag on all busses in the
2102 * machine, simply disable MSI globally.
2103 */
2104 static void __init quirk_disable_all_msi(struct pci_dev *dev)
2105 {
2106 pci_no_msi();
2107 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2108 }
2109 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2110 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2111 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2112 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2113 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2114 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2115
2116 /* Disable MSI on chipsets that are known to not support it */
2117 static void __devinit quirk_disable_msi(struct pci_dev *dev)
2118 {
2119 if (dev->subordinate) {
2120 dev_warn(&dev->dev, "MSI quirk detected; "
2121 "subordinate MSI disabled\n");
2122 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2123 }
2124 }
2125 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2126 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9602, quirk_disable_msi);
2127 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASUSTEK, 0x9602, quirk_disable_msi);
2128 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AI, 0x9602, quirk_disable_msi);
2129 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2130
2131 /* Go through the list of Hypertransport capabilities and
2132 * return 1 if a HT MSI capability is found and enabled */
2133 static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
2134 {
2135 int pos, ttl = 48;
2136
2137 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2138 while (pos && ttl--) {
2139 u8 flags;
2140
2141 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2142 &flags) == 0)
2143 {
2144 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2145 flags & HT_MSI_FLAGS_ENABLE ?
2146 "enabled" : "disabled");
2147 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2148 }
2149
2150 pos = pci_find_next_ht_capability(dev, pos,
2151 HT_CAPTYPE_MSI_MAPPING);
2152 }
2153 return 0;
2154 }
2155
2156 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2157 static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
2158 {
2159 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2160 dev_warn(&dev->dev, "MSI quirk detected; "
2161 "subordinate MSI disabled\n");
2162 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2163 }
2164 }
2165 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2166 quirk_msi_ht_cap);
2167
2168 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
2169 * MSI are supported if the MSI capability set in any of these mappings.
2170 */
2171 static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2172 {
2173 struct pci_dev *pdev;
2174
2175 if (!dev->subordinate)
2176 return;
2177
2178 /* check HT MSI cap on this chipset and the root one.
2179 * a single one having MSI is enough to be sure that MSI are supported.
2180 */
2181 pdev = pci_get_slot(dev->bus, 0);
2182 if (!pdev)
2183 return;
2184 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2185 dev_warn(&dev->dev, "MSI quirk detected; "
2186 "subordinate MSI disabled\n");
2187 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2188 }
2189 pci_dev_put(pdev);
2190 }
2191 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2192 quirk_nvidia_ck804_msi_ht_cap);
2193
2194 /* Force enable MSI mapping capability on HT bridges */
2195 static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
2196 {
2197 int pos, ttl = 48;
2198
2199 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2200 while (pos && ttl--) {
2201 u8 flags;
2202
2203 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2204 &flags) == 0) {
2205 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2206
2207 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2208 flags | HT_MSI_FLAGS_ENABLE);
2209 }
2210 pos = pci_find_next_ht_capability(dev, pos,
2211 HT_CAPTYPE_MSI_MAPPING);
2212 }
2213 }
2214 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2215 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2216 ht_enable_msi_mapping);
2217
2218 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2219 ht_enable_msi_mapping);
2220
2221 /* The P5N32-SLI Premium motherboard from Asus has a problem with msi
2222 * for the MCP55 NIC. It is not yet determined whether the msi problem
2223 * also affects other devices. As for now, turn off msi for this device.
2224 */
2225 static void __devinit nvenet_msi_disable(struct pci_dev *dev)
2226 {
2227 if (dmi_name_in_vendors("P5N32-SLI PREMIUM")) {
2228 dev_info(&dev->dev,
2229 "Disabling msi for MCP55 NIC on P5N32-SLI Premium\n");
2230 dev->no_msi = 1;
2231 }
2232 }
2233 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2234 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2235 nvenet_msi_disable);
2236
2237 static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
2238 {
2239 int pos, ttl = 48;
2240 int found = 0;
2241
2242 /* check if there is HT MSI cap or enabled on this device */
2243 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2244 while (pos && ttl--) {
2245 u8 flags;
2246
2247 if (found < 1)
2248 found = 1;
2249 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2250 &flags) == 0) {
2251 if (flags & HT_MSI_FLAGS_ENABLE) {
2252 if (found < 2) {
2253 found = 2;
2254 break;
2255 }
2256 }
2257 }
2258 pos = pci_find_next_ht_capability(dev, pos,
2259 HT_CAPTYPE_MSI_MAPPING);
2260 }
2261
2262 return found;
2263 }
2264
2265 static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
2266 {
2267 struct pci_dev *dev;
2268 int pos;
2269 int i, dev_no;
2270 int found = 0;
2271
2272 dev_no = host_bridge->devfn >> 3;
2273 for (i = dev_no + 1; i < 0x20; i++) {
2274 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2275 if (!dev)
2276 continue;
2277
2278 /* found next host bridge ?*/
2279 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2280 if (pos != 0) {
2281 pci_dev_put(dev);
2282 break;
2283 }
2284
2285 if (ht_check_msi_mapping(dev)) {
2286 found = 1;
2287 pci_dev_put(dev);
2288 break;
2289 }
2290 pci_dev_put(dev);
2291 }
2292
2293 return found;
2294 }
2295
2296 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2297 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2298
2299 static int __devinit is_end_of_ht_chain(struct pci_dev *dev)
2300 {
2301 int pos, ctrl_off;
2302 int end = 0;
2303 u16 flags, ctrl;
2304
2305 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2306
2307 if (!pos)
2308 goto out;
2309
2310 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2311
2312 ctrl_off = ((flags >> 10) & 1) ?
2313 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2314 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2315
2316 if (ctrl & (1 << 6))
2317 end = 1;
2318
2319 out:
2320 return end;
2321 }
2322
2323 static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
2324 {
2325 struct pci_dev *host_bridge;
2326 int pos;
2327 int i, dev_no;
2328 int found = 0;
2329
2330 dev_no = dev->devfn >> 3;
2331 for (i = dev_no; i >= 0; i--) {
2332 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2333 if (!host_bridge)
2334 continue;
2335
2336 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2337 if (pos != 0) {
2338 found = 1;
2339 break;
2340 }
2341 pci_dev_put(host_bridge);
2342 }
2343
2344 if (!found)
2345 return;
2346
2347 /* don't enable end_device/host_bridge with leaf directly here */
2348 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2349 host_bridge_with_leaf(host_bridge))
2350 goto out;
2351
2352 /* root did that ! */
2353 if (msi_ht_cap_enabled(host_bridge))
2354 goto out;
2355
2356 ht_enable_msi_mapping(dev);
2357
2358 out:
2359 pci_dev_put(host_bridge);
2360 }
2361
2362 static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
2363 {
2364 int pos, ttl = 48;
2365
2366 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2367 while (pos && ttl--) {
2368 u8 flags;
2369
2370 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2371 &flags) == 0) {
2372 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2373
2374 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2375 flags & ~HT_MSI_FLAGS_ENABLE);
2376 }
2377 pos = pci_find_next_ht_capability(dev, pos,
2378 HT_CAPTYPE_MSI_MAPPING);
2379 }
2380 }
2381
2382 static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2383 {
2384 struct pci_dev *host_bridge;
2385 int pos;
2386 int found;
2387
2388 /* check if there is HT MSI cap or enabled on this device */
2389 found = ht_check_msi_mapping(dev);
2390
2391 /* no HT MSI CAP */
2392 if (found == 0)
2393 return;
2394
2395 /*
2396 * HT MSI mapping should be disabled on devices that are below
2397 * a non-Hypertransport host bridge. Locate the host bridge...
2398 */
2399 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2400 if (host_bridge == NULL) {
2401 dev_warn(&dev->dev,
2402 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2403 return;
2404 }
2405
2406 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2407 if (pos != 0) {
2408 /* Host bridge is to HT */
2409 if (found == 1) {
2410 /* it is not enabled, try to enable it */
2411 if (all)
2412 ht_enable_msi_mapping(dev);
2413 else
2414 nv_ht_enable_msi_mapping(dev);
2415 }
2416 return;
2417 }
2418
2419 /* HT MSI is not enabled */
2420 if (found == 1)
2421 return;
2422
2423 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2424 ht_disable_msi_mapping(dev);
2425 }
2426
2427 static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2428 {
2429 return __nv_msi_ht_cap_quirk(dev, 1);
2430 }
2431
2432 static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2433 {
2434 return __nv_msi_ht_cap_quirk(dev, 0);
2435 }
2436
2437 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2438 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2439
2440 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2441 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2442
2443 static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
2444 {
2445 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2446 }
2447 static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2448 {
2449 struct pci_dev *p;
2450
2451 /* SB700 MSI issue will be fixed at HW level from revision A21,
2452 * we need check PCI REVISION ID of SMBus controller to get SB700
2453 * revision.
2454 */
2455 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2456 NULL);
2457 if (!p)
2458 return;
2459
2460 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2461 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2462 pci_dev_put(p);
2463 }
2464 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2465 PCI_DEVICE_ID_TIGON3_5780,
2466 quirk_msi_intx_disable_bug);
2467 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2468 PCI_DEVICE_ID_TIGON3_5780S,
2469 quirk_msi_intx_disable_bug);
2470 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2471 PCI_DEVICE_ID_TIGON3_5714,
2472 quirk_msi_intx_disable_bug);
2473 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2474 PCI_DEVICE_ID_TIGON3_5714S,
2475 quirk_msi_intx_disable_bug);
2476 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2477 PCI_DEVICE_ID_TIGON3_5715,
2478 quirk_msi_intx_disable_bug);
2479 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2480 PCI_DEVICE_ID_TIGON3_5715S,
2481 quirk_msi_intx_disable_bug);
2482
2483 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2484 quirk_msi_intx_disable_ati_bug);
2485 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2486 quirk_msi_intx_disable_ati_bug);
2487 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2488 quirk_msi_intx_disable_ati_bug);
2489 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2490 quirk_msi_intx_disable_ati_bug);
2491 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2492 quirk_msi_intx_disable_ati_bug);
2493
2494 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2495 quirk_msi_intx_disable_bug);
2496 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2497 quirk_msi_intx_disable_bug);
2498 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2499 quirk_msi_intx_disable_bug);
2500
2501 #endif /* CONFIG_PCI_MSI */
2502
2503 #ifdef CONFIG_PCI_IOV
2504
2505 /*
2506 * For Intel 82576 SR-IOV NIC, if BIOS doesn't allocate resources for the
2507 * SR-IOV BARs, zero the Flash BAR and program the SR-IOV BARs to use the
2508 * old Flash Memory Space.
2509 */
2510 static void __devinit quirk_i82576_sriov(struct pci_dev *dev)
2511 {
2512 int pos, flags;
2513 u32 bar, start, size;
2514
2515 if (PAGE_SIZE > 0x10000)
2516 return;
2517
2518 flags = pci_resource_flags(dev, 0);
2519 if ((flags & PCI_BASE_ADDRESS_SPACE) !=
2520 PCI_BASE_ADDRESS_SPACE_MEMORY ||
2521 (flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) !=
2522 PCI_BASE_ADDRESS_MEM_TYPE_32)
2523 return;
2524
2525 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
2526 if (!pos)
2527 return;
2528
2529 pci_read_config_dword(dev, pos + PCI_SRIOV_BAR, &bar);
2530 if (bar & PCI_BASE_ADDRESS_MEM_MASK)
2531 return;
2532
2533 start = pci_resource_start(dev, 1);
2534 size = pci_resource_len(dev, 1);
2535 if (!start || size != 0x400000 || start & (size - 1))
2536 return;
2537
2538 pci_resource_flags(dev, 1) = 0;
2539 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
2540 pci_write_config_dword(dev, pos + PCI_SRIOV_BAR, start);
2541 pci_write_config_dword(dev, pos + PCI_SRIOV_BAR + 12, start + size / 2);
2542
2543 dev_info(&dev->dev, "use Flash Memory Space for SR-IOV BARs\n");
2544 }
2545 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c9, quirk_i82576_sriov);
2546 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e6, quirk_i82576_sriov);
2547 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e7, quirk_i82576_sriov);
2548 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e8, quirk_i82576_sriov);
2549 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150a, quirk_i82576_sriov);
2550 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150d, quirk_i82576_sriov);
2551 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1518, quirk_i82576_sriov);
2552
2553 #endif /* CONFIG_PCI_IOV */
2554
2555 /*
2556 * This is a quirk for the Ricoh MMC controller found as a part of
2557 * some mulifunction chips.
2558
2559 * This is very similiar and based on the ricoh_mmc driver written by
2560 * Philip Langdale. Thank you for these magic sequences.
2561 *
2562 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2563 * and one or both of cardbus or firewire.
2564 *
2565 * It happens that they implement SD and MMC
2566 * support as separate controllers (and PCI functions). The linux SDHCI
2567 * driver supports MMC cards but the chip detects MMC cards in hardware
2568 * and directs them to the MMC controller - so the SDHCI driver never sees
2569 * them.
2570 *
2571 * To get around this, we must disable the useless MMC controller.
2572 * At that point, the SDHCI controller will start seeing them
2573 * It seems to be the case that the relevant PCI registers to deactivate the
2574 * MMC controller live on PCI function 0, which might be the cardbus controller
2575 * or the firewire controller, depending on the particular chip in question
2576 *
2577 * This has to be done early, because as soon as we disable the MMC controller
2578 * other pci functions shift up one level, e.g. function #2 becomes function
2579 * #1, and this will confuse the pci core.
2580 */
2581
2582 #ifdef CONFIG_MMC_RICOH_MMC
2583 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2584 {
2585 /* disable via cardbus interface */
2586 u8 write_enable;
2587 u8 write_target;
2588 u8 disable;
2589
2590 /* disable must be done via function #0 */
2591 if (PCI_FUNC(dev->devfn))
2592 return;
2593
2594 pci_read_config_byte(dev, 0xB7, &disable);
2595 if (disable & 0x02)
2596 return;
2597
2598 pci_read_config_byte(dev, 0x8E, &write_enable);
2599 pci_write_config_byte(dev, 0x8E, 0xAA);
2600 pci_read_config_byte(dev, 0x8D, &write_target);
2601 pci_write_config_byte(dev, 0x8D, 0xB7);
2602 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2603 pci_write_config_byte(dev, 0x8E, write_enable);
2604 pci_write_config_byte(dev, 0x8D, write_target);
2605
2606 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2607 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2608 }
2609 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2610 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2611
2612 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2613 {
2614 /* disable via firewire interface */
2615 u8 write_enable;
2616 u8 disable;
2617
2618 /* disable must be done via function #0 */
2619 if (PCI_FUNC(dev->devfn))
2620 return;
2621
2622 pci_read_config_byte(dev, 0xCB, &disable);
2623
2624 if (disable & 0x02)
2625 return;
2626
2627 pci_read_config_byte(dev, 0xCA, &write_enable);
2628 pci_write_config_byte(dev, 0xCA, 0x57);
2629 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2630 pci_write_config_byte(dev, 0xCA, write_enable);
2631
2632 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2633 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2634 }
2635 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2636 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2637 #endif /*CONFIG_MMC_RICOH_MMC*/
2638
2639
2640 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2641 struct pci_fixup *end)
2642 {
2643 while (f < end) {
2644 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
2645 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
2646 dev_dbg(&dev->dev, "calling %pF\n", f->hook);
2647 f->hook(dev);
2648 }
2649 f++;
2650 }
2651 }
2652
2653 extern struct pci_fixup __start_pci_fixups_early[];
2654 extern struct pci_fixup __end_pci_fixups_early[];
2655 extern struct pci_fixup __start_pci_fixups_header[];
2656 extern struct pci_fixup __end_pci_fixups_header[];
2657 extern struct pci_fixup __start_pci_fixups_final[];
2658 extern struct pci_fixup __end_pci_fixups_final[];
2659 extern struct pci_fixup __start_pci_fixups_enable[];
2660 extern struct pci_fixup __end_pci_fixups_enable[];
2661 extern struct pci_fixup __start_pci_fixups_resume[];
2662 extern struct pci_fixup __end_pci_fixups_resume[];
2663 extern struct pci_fixup __start_pci_fixups_resume_early[];
2664 extern struct pci_fixup __end_pci_fixups_resume_early[];
2665 extern struct pci_fixup __start_pci_fixups_suspend[];
2666 extern struct pci_fixup __end_pci_fixups_suspend[];
2667
2668
2669 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2670 {
2671 struct pci_fixup *start, *end;
2672
2673 switch(pass) {
2674 case pci_fixup_early:
2675 start = __start_pci_fixups_early;
2676 end = __end_pci_fixups_early;
2677 break;
2678
2679 case pci_fixup_header:
2680 start = __start_pci_fixups_header;
2681 end = __end_pci_fixups_header;
2682 break;
2683
2684 case pci_fixup_final:
2685 start = __start_pci_fixups_final;
2686 end = __end_pci_fixups_final;
2687 break;
2688
2689 case pci_fixup_enable:
2690 start = __start_pci_fixups_enable;
2691 end = __end_pci_fixups_enable;
2692 break;
2693
2694 case pci_fixup_resume:
2695 start = __start_pci_fixups_resume;
2696 end = __end_pci_fixups_resume;
2697 break;
2698
2699 case pci_fixup_resume_early:
2700 start = __start_pci_fixups_resume_early;
2701 end = __end_pci_fixups_resume_early;
2702 break;
2703
2704 case pci_fixup_suspend:
2705 start = __start_pci_fixups_suspend;
2706 end = __end_pci_fixups_suspend;
2707 break;
2708
2709 default:
2710 /* stupid compiler warning, you would think with an enum... */
2711 return;
2712 }
2713 pci_do_fixups(dev, start, end);
2714 }
2715 EXPORT_SYMBOL(pci_fixup_device);
2716
2717 static int __init pci_apply_final_quirks(void)
2718 {
2719 struct pci_dev *dev = NULL;
2720 u8 cls = 0;
2721 u8 tmp;
2722
2723 if (pci_cache_line_size)
2724 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
2725 pci_cache_line_size << 2);
2726
2727 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2728 pci_fixup_device(pci_fixup_final, dev);
2729 /*
2730 * If arch hasn't set it explicitly yet, use the CLS
2731 * value shared by all PCI devices. If there's a
2732 * mismatch, fall back to the default value.
2733 */
2734 if (!pci_cache_line_size) {
2735 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
2736 if (!cls)
2737 cls = tmp;
2738 if (!tmp || cls == tmp)
2739 continue;
2740
2741 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), "
2742 "using %u bytes\n", cls << 2, tmp << 2,
2743 pci_dfl_cache_line_size << 2);
2744 pci_cache_line_size = pci_dfl_cache_line_size;
2745 }
2746 }
2747 if (!pci_cache_line_size) {
2748 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
2749 cls << 2, pci_dfl_cache_line_size << 2);
2750 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
2751 }
2752
2753 return 0;
2754 }
2755
2756 fs_initcall_sync(pci_apply_final_quirks);
2757
2758 /*
2759 * Followings are device-specific reset methods which can be used to
2760 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
2761 * not available.
2762 */
2763 static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
2764 {
2765 int pos;
2766
2767 /* only implement PCI_CLASS_SERIAL_USB at present */
2768 if (dev->class == PCI_CLASS_SERIAL_USB) {
2769 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
2770 if (!pos)
2771 return -ENOTTY;
2772
2773 if (probe)
2774 return 0;
2775
2776 pci_write_config_byte(dev, pos + 0x4, 1);
2777 msleep(100);
2778
2779 return 0;
2780 } else {
2781 return -ENOTTY;
2782 }
2783 }
2784
2785 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
2786 {
2787 int pos;
2788
2789 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
2790 if (!pos)
2791 return -ENOTTY;
2792
2793 if (probe)
2794 return 0;
2795
2796 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
2797 PCI_EXP_DEVCTL_BCR_FLR);
2798 msleep(100);
2799
2800 return 0;
2801 }
2802
2803 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
2804
2805 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
2806 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
2807 reset_intel_82599_sfp_virtfn },
2808 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2809 reset_intel_generic_dev },
2810 { 0 }
2811 };
2812
2813 int pci_dev_specific_reset(struct pci_dev *dev, int probe)
2814 {
2815 const struct pci_dev_reset_methods *i;
2816
2817 for (i = pci_dev_reset_methods; i->reset; i++) {
2818 if ((i->vendor == dev->vendor ||
2819 i->vendor == (u16)PCI_ANY_ID) &&
2820 (i->device == dev->device ||
2821 i->device == (u16)PCI_ANY_ID))
2822 return i->reset(dev, probe);
2823 }
2824
2825 return -ENOTTY;
2826 }
Linux kernel - Deliverables
This page took 0.089185 seconds and 6 git commands to generate.