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Merge branches 'pci/hotplug' and 'pci/resource' into next
[deliverable/linux.git] / drivers / pci / quirks.c
1 /*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 */
13
14 #include <linux/types.h>
15 #include <linux/kernel.h>
16 #include <linux/export.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/acpi.h>
21 #include <linux/kallsyms.h>
22 #include <linux/dmi.h>
23 #include <linux/pci-aspm.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/ktime.h>
27 #include <linux/mm.h>
28 #include <asm/dma.h> /* isa_dma_bridge_buggy */
29 #include "pci.h"
30
31 /*
32 * Decoding should be disabled for a PCI device during BAR sizing to avoid
33 * conflict. But doing so may cause problems on host bridge and perhaps other
34 * key system devices. For devices that need to have mmio decoding always-on,
35 * we need to set the dev->mmio_always_on bit.
36 */
37 static void quirk_mmio_always_on(struct pci_dev *dev)
38 {
39 dev->mmio_always_on = 1;
40 }
41 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
42 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
43
44 /* The Mellanox Tavor device gives false positive parity errors
45 * Mark this device with a broken_parity_status, to allow
46 * PCI scanning code to "skip" this now blacklisted device.
47 */
48 static void quirk_mellanox_tavor(struct pci_dev *dev)
49 {
50 dev->broken_parity_status = 1; /* This device gives false positives */
51 }
52 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
53 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
54
55 /* Deal with broken BIOSes that neglect to enable passive release,
56 which can cause problems in combination with the 82441FX/PPro MTRRs */
57 static void quirk_passive_release(struct pci_dev *dev)
58 {
59 struct pci_dev *d = NULL;
60 unsigned char dlc;
61
62 /* We have to make sure a particular bit is set in the PIIX3
63 ISA bridge, so we have to go out and find it. */
64 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
65 pci_read_config_byte(d, 0x82, &dlc);
66 if (!(dlc & 1<<1)) {
67 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
68 dlc |= 1<<1;
69 pci_write_config_byte(d, 0x82, dlc);
70 }
71 }
72 }
73 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
74 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
75
76 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
77 but VIA don't answer queries. If you happen to have good contacts at VIA
78 ask them for me please -- Alan
79
80 This appears to be BIOS not version dependent. So presumably there is a
81 chipset level fix */
82
83 static void quirk_isa_dma_hangs(struct pci_dev *dev)
84 {
85 if (!isa_dma_bridge_buggy) {
86 isa_dma_bridge_buggy = 1;
87 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
88 }
89 }
90 /*
91 * Its not totally clear which chipsets are the problematic ones
92 * We know 82C586 and 82C596 variants are affected.
93 */
94 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
95 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
101
102 /*
103 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
104 * for some HT machines to use C4 w/o hanging.
105 */
106 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
107 {
108 u32 pmbase;
109 u16 pm1a;
110
111 pci_read_config_dword(dev, 0x40, &pmbase);
112 pmbase = pmbase & 0xff80;
113 pm1a = inw(pmbase);
114
115 if (pm1a & 0x10) {
116 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
117 outw(0x10, pmbase);
118 }
119 }
120 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
121
122 /*
123 * Chipsets where PCI->PCI transfers vanish or hang
124 */
125 static void quirk_nopcipci(struct pci_dev *dev)
126 {
127 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
128 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
129 pci_pci_problems |= PCIPCI_FAIL;
130 }
131 }
132 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
133 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
134
135 static void quirk_nopciamd(struct pci_dev *dev)
136 {
137 u8 rev;
138 pci_read_config_byte(dev, 0x08, &rev);
139 if (rev == 0x13) {
140 /* Erratum 24 */
141 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
142 pci_pci_problems |= PCIAGP_FAIL;
143 }
144 }
145 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
146
147 /*
148 * Triton requires workarounds to be used by the drivers
149 */
150 static void quirk_triton(struct pci_dev *dev)
151 {
152 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
153 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
154 pci_pci_problems |= PCIPCI_TRITON;
155 }
156 }
157 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
161
162 /*
163 * VIA Apollo KT133 needs PCI latency patch
164 * Made according to a windows driver based patch by George E. Breese
165 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
166 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
167 * the info on which Mr Breese based his work.
168 *
169 * Updated based on further information from the site and also on
170 * information provided by VIA
171 */
172 static void quirk_vialatency(struct pci_dev *dev)
173 {
174 struct pci_dev *p;
175 u8 busarb;
176 /* Ok we have a potential problem chipset here. Now see if we have
177 a buggy southbridge */
178
179 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
180 if (p != NULL) {
181 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
182 /* Check for buggy part revisions */
183 if (p->revision < 0x40 || p->revision > 0x42)
184 goto exit;
185 } else {
186 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
187 if (p == NULL) /* No problem parts */
188 goto exit;
189 /* Check for buggy part revisions */
190 if (p->revision < 0x10 || p->revision > 0x12)
191 goto exit;
192 }
193
194 /*
195 * Ok we have the problem. Now set the PCI master grant to
196 * occur every master grant. The apparent bug is that under high
197 * PCI load (quite common in Linux of course) you can get data
198 * loss when the CPU is held off the bus for 3 bus master requests
199 * This happens to include the IDE controllers....
200 *
201 * VIA only apply this fix when an SB Live! is present but under
202 * both Linux and Windows this isn't enough, and we have seen
203 * corruption without SB Live! but with things like 3 UDMA IDE
204 * controllers. So we ignore that bit of the VIA recommendation..
205 */
206
207 pci_read_config_byte(dev, 0x76, &busarb);
208 /* Set bit 4 and bi 5 of byte 76 to 0x01
209 "Master priority rotation on every PCI master grant */
210 busarb &= ~(1<<5);
211 busarb |= (1<<4);
212 pci_write_config_byte(dev, 0x76, busarb);
213 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
214 exit:
215 pci_dev_put(p);
216 }
217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
220 /* Must restore this on a resume from RAM */
221 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
222 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
223 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
224
225 /*
226 * VIA Apollo VP3 needs ETBF on BT848/878
227 */
228 static void quirk_viaetbf(struct pci_dev *dev)
229 {
230 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
231 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
232 pci_pci_problems |= PCIPCI_VIAETBF;
233 }
234 }
235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
236
237 static void quirk_vsfx(struct pci_dev *dev)
238 {
239 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
240 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
241 pci_pci_problems |= PCIPCI_VSFX;
242 }
243 }
244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
245
246 /*
247 * Ali Magik requires workarounds to be used by the drivers
248 * that DMA to AGP space. Latency must be set to 0xA and triton
249 * workaround applied too
250 * [Info kindly provided by ALi]
251 */
252 static void quirk_alimagik(struct pci_dev *dev)
253 {
254 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
255 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
256 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
257 }
258 }
259 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
261
262 /*
263 * Natoma has some interesting boundary conditions with Zoran stuff
264 * at least
265 */
266 static void quirk_natoma(struct pci_dev *dev)
267 {
268 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
269 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
270 pci_pci_problems |= PCIPCI_NATOMA;
271 }
272 }
273 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
274 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
275 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
279
280 /*
281 * This chip can cause PCI parity errors if config register 0xA0 is read
282 * while DMAs are occurring.
283 */
284 static void quirk_citrine(struct pci_dev *dev)
285 {
286 dev->cfg_size = 0xA0;
287 }
288 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
289
290 /*
291 * This chip can cause bus lockups if config addresses above 0x600
292 * are read or written.
293 */
294 static void quirk_nfp6000(struct pci_dev *dev)
295 {
296 dev->cfg_size = 0x600;
297 }
298 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
299 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
300
301 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
302 static void quirk_extend_bar_to_page(struct pci_dev *dev)
303 {
304 int i;
305
306 for (i = 0; i < PCI_STD_RESOURCE_END; i++) {
307 struct resource *r = &dev->resource[i];
308
309 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
310 r->end = PAGE_SIZE - 1;
311 r->start = 0;
312 r->flags |= IORESOURCE_UNSET;
313 dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n",
314 i, r);
315 }
316 }
317 }
318 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
319
320 /*
321 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
322 * If it's needed, re-allocate the region.
323 */
324 static void quirk_s3_64M(struct pci_dev *dev)
325 {
326 struct resource *r = &dev->resource[0];
327
328 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
329 r->flags |= IORESOURCE_UNSET;
330 r->start = 0;
331 r->end = 0x3ffffff;
332 }
333 }
334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
336
337 static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
338 const char *name)
339 {
340 u32 region;
341 struct pci_bus_region bus_region;
342 struct resource *res = dev->resource + pos;
343
344 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), &region);
345
346 if (!region)
347 return;
348
349 res->name = pci_name(dev);
350 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
351 res->flags |=
352 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
353 region &= ~(size - 1);
354
355 /* Convert from PCI bus to resource space */
356 bus_region.start = region;
357 bus_region.end = region + size - 1;
358 pcibios_bus_to_resource(dev->bus, res, &bus_region);
359
360 dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
361 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
362 }
363
364 /*
365 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
366 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
367 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
368 * (which conflicts w/ BAR1's memory range).
369 *
370 * CS553x's ISA PCI BARs may also be read-only (ref:
371 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
372 */
373 static void quirk_cs5536_vsa(struct pci_dev *dev)
374 {
375 static char *name = "CS5536 ISA bridge";
376
377 if (pci_resource_len(dev, 0) != 8) {
378 quirk_io(dev, 0, 8, name); /* SMB */
379 quirk_io(dev, 1, 256, name); /* GPIO */
380 quirk_io(dev, 2, 64, name); /* MFGPT */
381 dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n",
382 name);
383 }
384 }
385 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
386
387 static void quirk_io_region(struct pci_dev *dev, int port,
388 unsigned size, int nr, const char *name)
389 {
390 u16 region;
391 struct pci_bus_region bus_region;
392 struct resource *res = dev->resource + nr;
393
394 pci_read_config_word(dev, port, &region);
395 region &= ~(size - 1);
396
397 if (!region)
398 return;
399
400 res->name = pci_name(dev);
401 res->flags = IORESOURCE_IO;
402
403 /* Convert from PCI bus to resource space */
404 bus_region.start = region;
405 bus_region.end = region + size - 1;
406 pcibios_bus_to_resource(dev->bus, res, &bus_region);
407
408 if (!pci_claim_resource(dev, nr))
409 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
410 }
411
412 /*
413 * ATI Northbridge setups MCE the processor if you even
414 * read somewhere between 0x3b0->0x3bb or read 0x3d3
415 */
416 static void quirk_ati_exploding_mce(struct pci_dev *dev)
417 {
418 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
419 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
420 request_region(0x3b0, 0x0C, "RadeonIGP");
421 request_region(0x3d3, 0x01, "RadeonIGP");
422 }
423 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
424
425 /*
426 * In the AMD NL platform, this device ([1022:7912]) has a class code of
427 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
428 * claim it.
429 * But the dwc3 driver is a more specific driver for this device, and we'd
430 * prefer to use it instead of xhci. To prevent xhci from claiming the
431 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
432 * defines as "USB device (not host controller)". The dwc3 driver can then
433 * claim it based on its Vendor and Device ID.
434 */
435 static void quirk_amd_nl_class(struct pci_dev *pdev)
436 {
437 u32 class = pdev->class;
438
439 /* Use "USB Device (not host controller)" class */
440 pdev->class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe;
441 dev_info(&pdev->dev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
442 class, pdev->class);
443 }
444 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
445 quirk_amd_nl_class);
446
447 /*
448 * Let's make the southbridge information explicit instead
449 * of having to worry about people probing the ACPI areas,
450 * for example.. (Yes, it happens, and if you read the wrong
451 * ACPI register it will put the machine to sleep with no
452 * way of waking it up again. Bummer).
453 *
454 * ALI M7101: Two IO regions pointed to by words at
455 * 0xE0 (64 bytes of ACPI registers)
456 * 0xE2 (32 bytes of SMB registers)
457 */
458 static void quirk_ali7101_acpi(struct pci_dev *dev)
459 {
460 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
461 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
462 }
463 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
464
465 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
466 {
467 u32 devres;
468 u32 mask, size, base;
469
470 pci_read_config_dword(dev, port, &devres);
471 if ((devres & enable) != enable)
472 return;
473 mask = (devres >> 16) & 15;
474 base = devres & 0xffff;
475 size = 16;
476 for (;;) {
477 unsigned bit = size >> 1;
478 if ((bit & mask) == bit)
479 break;
480 size = bit;
481 }
482 /*
483 * For now we only print it out. Eventually we'll want to
484 * reserve it (at least if it's in the 0x1000+ range), but
485 * let's get enough confirmation reports first.
486 */
487 base &= -size;
488 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base,
489 base + size - 1);
490 }
491
492 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
493 {
494 u32 devres;
495 u32 mask, size, base;
496
497 pci_read_config_dword(dev, port, &devres);
498 if ((devres & enable) != enable)
499 return;
500 base = devres & 0xffff0000;
501 mask = (devres & 0x3f) << 16;
502 size = 128 << 16;
503 for (;;) {
504 unsigned bit = size >> 1;
505 if ((bit & mask) == bit)
506 break;
507 size = bit;
508 }
509 /*
510 * For now we only print it out. Eventually we'll want to
511 * reserve it, but let's get enough confirmation reports first.
512 */
513 base &= -size;
514 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base,
515 base + size - 1);
516 }
517
518 /*
519 * PIIX4 ACPI: Two IO regions pointed to by longwords at
520 * 0x40 (64 bytes of ACPI registers)
521 * 0x90 (16 bytes of SMB registers)
522 * and a few strange programmable PIIX4 device resources.
523 */
524 static void quirk_piix4_acpi(struct pci_dev *dev)
525 {
526 u32 res_a;
527
528 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
529 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
530
531 /* Device resource A has enables for some of the other ones */
532 pci_read_config_dword(dev, 0x5c, &res_a);
533
534 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
535 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
536
537 /* Device resource D is just bitfields for static resources */
538
539 /* Device 12 enabled? */
540 if (res_a & (1 << 29)) {
541 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
542 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
543 }
544 /* Device 13 enabled? */
545 if (res_a & (1 << 30)) {
546 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
547 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
548 }
549 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
550 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
551 }
552 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
553 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
554
555 #define ICH_PMBASE 0x40
556 #define ICH_ACPI_CNTL 0x44
557 #define ICH4_ACPI_EN 0x10
558 #define ICH6_ACPI_EN 0x80
559 #define ICH4_GPIOBASE 0x58
560 #define ICH4_GPIO_CNTL 0x5c
561 #define ICH4_GPIO_EN 0x10
562 #define ICH6_GPIOBASE 0x48
563 #define ICH6_GPIO_CNTL 0x4c
564 #define ICH6_GPIO_EN 0x10
565
566 /*
567 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
568 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
569 * 0x58 (64 bytes of GPIO I/O space)
570 */
571 static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
572 {
573 u8 enable;
574
575 /*
576 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
577 * with low legacy (and fixed) ports. We don't know the decoding
578 * priority and can't tell whether the legacy device or the one created
579 * here is really at that address. This happens on boards with broken
580 * BIOSes.
581 */
582
583 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
584 if (enable & ICH4_ACPI_EN)
585 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
586 "ICH4 ACPI/GPIO/TCO");
587
588 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
589 if (enable & ICH4_GPIO_EN)
590 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
591 "ICH4 GPIO");
592 }
593 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
594 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
595 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
596 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
597 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
598 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
599 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
600 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
601 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
602 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
603
604 static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
605 {
606 u8 enable;
607
608 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
609 if (enable & ICH6_ACPI_EN)
610 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
611 "ICH6 ACPI/GPIO/TCO");
612
613 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
614 if (enable & ICH6_GPIO_EN)
615 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
616 "ICH6 GPIO");
617 }
618
619 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
620 {
621 u32 val;
622 u32 size, base;
623
624 pci_read_config_dword(dev, reg, &val);
625
626 /* Enabled? */
627 if (!(val & 1))
628 return;
629 base = val & 0xfffc;
630 if (dynsize) {
631 /*
632 * This is not correct. It is 16, 32 or 64 bytes depending on
633 * register D31:F0:ADh bits 5:4.
634 *
635 * But this gets us at least _part_ of it.
636 */
637 size = 16;
638 } else {
639 size = 128;
640 }
641 base &= ~(size-1);
642
643 /* Just print it out for now. We should reserve it after more debugging */
644 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
645 }
646
647 static void quirk_ich6_lpc(struct pci_dev *dev)
648 {
649 /* Shared ACPI/GPIO decode with all ICH6+ */
650 ich6_lpc_acpi_gpio(dev);
651
652 /* ICH6-specific generic IO decode */
653 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
654 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
655 }
656 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
657 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
658
659 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
660 {
661 u32 val;
662 u32 mask, base;
663
664 pci_read_config_dword(dev, reg, &val);
665
666 /* Enabled? */
667 if (!(val & 1))
668 return;
669
670 /*
671 * IO base in bits 15:2, mask in bits 23:18, both
672 * are dword-based
673 */
674 base = val & 0xfffc;
675 mask = (val >> 16) & 0xfc;
676 mask |= 3;
677
678 /* Just print it out for now. We should reserve it after more debugging */
679 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
680 }
681
682 /* ICH7-10 has the same common LPC generic IO decode registers */
683 static void quirk_ich7_lpc(struct pci_dev *dev)
684 {
685 /* We share the common ACPI/GPIO decode with ICH6 */
686 ich6_lpc_acpi_gpio(dev);
687
688 /* And have 4 ICH7+ generic decodes */
689 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
690 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
691 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
692 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
693 }
694 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
695 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
696 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
697 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
698 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
699 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
700 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
701 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
702 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
703 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
704 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
705 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
706 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
707
708 /*
709 * VIA ACPI: One IO region pointed to by longword at
710 * 0x48 or 0x20 (256 bytes of ACPI registers)
711 */
712 static void quirk_vt82c586_acpi(struct pci_dev *dev)
713 {
714 if (dev->revision & 0x10)
715 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
716 "vt82c586 ACPI");
717 }
718 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
719
720 /*
721 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
722 * 0x48 (256 bytes of ACPI registers)
723 * 0x70 (128 bytes of hardware monitoring register)
724 * 0x90 (16 bytes of SMB registers)
725 */
726 static void quirk_vt82c686_acpi(struct pci_dev *dev)
727 {
728 quirk_vt82c586_acpi(dev);
729
730 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
731 "vt82c686 HW-mon");
732
733 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
734 }
735 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
736
737 /*
738 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
739 * 0x88 (128 bytes of power management registers)
740 * 0xd0 (16 bytes of SMB registers)
741 */
742 static void quirk_vt8235_acpi(struct pci_dev *dev)
743 {
744 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
745 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
746 }
747 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
748
749 /*
750 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
751 * Disable fast back-to-back on the secondary bus segment
752 */
753 static void quirk_xio2000a(struct pci_dev *dev)
754 {
755 struct pci_dev *pdev;
756 u16 command;
757
758 dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
759 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
760 pci_read_config_word(pdev, PCI_COMMAND, &command);
761 if (command & PCI_COMMAND_FAST_BACK)
762 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
763 }
764 }
765 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
766 quirk_xio2000a);
767
768 #ifdef CONFIG_X86_IO_APIC
769
770 #include <asm/io_apic.h>
771
772 /*
773 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
774 * devices to the external APIC.
775 *
776 * TODO: When we have device-specific interrupt routers,
777 * this code will go away from quirks.
778 */
779 static void quirk_via_ioapic(struct pci_dev *dev)
780 {
781 u8 tmp;
782
783 if (nr_ioapics < 1)
784 tmp = 0; /* nothing routed to external APIC */
785 else
786 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
787
788 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
789 tmp == 0 ? "Disa" : "Ena");
790
791 /* Offset 0x58: External APIC IRQ output control */
792 pci_write_config_byte(dev, 0x58, tmp);
793 }
794 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
795 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
796
797 /*
798 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
799 * This leads to doubled level interrupt rates.
800 * Set this bit to get rid of cycle wastage.
801 * Otherwise uncritical.
802 */
803 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
804 {
805 u8 misc_control2;
806 #define BYPASS_APIC_DEASSERT 8
807
808 pci_read_config_byte(dev, 0x5B, &misc_control2);
809 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
810 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
811 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
812 }
813 }
814 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
815 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
816
817 /*
818 * The AMD io apic can hang the box when an apic irq is masked.
819 * We check all revs >= B0 (yet not in the pre production!) as the bug
820 * is currently marked NoFix
821 *
822 * We have multiple reports of hangs with this chipset that went away with
823 * noapic specified. For the moment we assume it's the erratum. We may be wrong
824 * of course. However the advice is demonstrably good even if so..
825 */
826 static void quirk_amd_ioapic(struct pci_dev *dev)
827 {
828 if (dev->revision >= 0x02) {
829 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
830 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
831 }
832 }
833 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
834 #endif /* CONFIG_X86_IO_APIC */
835
836 /*
837 * Some settings of MMRBC can lead to data corruption so block changes.
838 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
839 */
840 static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
841 {
842 if (dev->subordinate && dev->revision <= 0x12) {
843 dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
844 dev->revision);
845 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
846 }
847 }
848 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
849
850 /*
851 * FIXME: it is questionable that quirk_via_acpi
852 * is needed. It shows up as an ISA bridge, and does not
853 * support the PCI_INTERRUPT_LINE register at all. Therefore
854 * it seems like setting the pci_dev's 'irq' to the
855 * value of the ACPI SCI interrupt is only done for convenience.
856 * -jgarzik
857 */
858 static void quirk_via_acpi(struct pci_dev *d)
859 {
860 /*
861 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
862 */
863 u8 irq;
864 pci_read_config_byte(d, 0x42, &irq);
865 irq &= 0xf;
866 if (irq && (irq != 2))
867 d->irq = irq;
868 }
869 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
870 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
871
872
873 /*
874 * VIA bridges which have VLink
875 */
876
877 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
878
879 static void quirk_via_bridge(struct pci_dev *dev)
880 {
881 /* See what bridge we have and find the device ranges */
882 switch (dev->device) {
883 case PCI_DEVICE_ID_VIA_82C686:
884 /* The VT82C686 is special, it attaches to PCI and can have
885 any device number. All its subdevices are functions of
886 that single device. */
887 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
888 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
889 break;
890 case PCI_DEVICE_ID_VIA_8237:
891 case PCI_DEVICE_ID_VIA_8237A:
892 via_vlink_dev_lo = 15;
893 break;
894 case PCI_DEVICE_ID_VIA_8235:
895 via_vlink_dev_lo = 16;
896 break;
897 case PCI_DEVICE_ID_VIA_8231:
898 case PCI_DEVICE_ID_VIA_8233_0:
899 case PCI_DEVICE_ID_VIA_8233A:
900 case PCI_DEVICE_ID_VIA_8233C_0:
901 via_vlink_dev_lo = 17;
902 break;
903 }
904 }
905 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
906 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
907 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
908 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
909 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
910 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
911 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
912 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
913
914 /**
915 * quirk_via_vlink - VIA VLink IRQ number update
916 * @dev: PCI device
917 *
918 * If the device we are dealing with is on a PIC IRQ we need to
919 * ensure that the IRQ line register which usually is not relevant
920 * for PCI cards, is actually written so that interrupts get sent
921 * to the right place.
922 * We only do this on systems where a VIA south bridge was detected,
923 * and only for VIA devices on the motherboard (see quirk_via_bridge
924 * above).
925 */
926
927 static void quirk_via_vlink(struct pci_dev *dev)
928 {
929 u8 irq, new_irq;
930
931 /* Check if we have VLink at all */
932 if (via_vlink_dev_lo == -1)
933 return;
934
935 new_irq = dev->irq;
936
937 /* Don't quirk interrupts outside the legacy IRQ range */
938 if (!new_irq || new_irq > 15)
939 return;
940
941 /* Internal device ? */
942 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
943 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
944 return;
945
946 /* This is an internal VLink device on a PIC interrupt. The BIOS
947 ought to have set this but may not have, so we redo it */
948
949 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
950 if (new_irq != irq) {
951 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
952 irq, new_irq);
953 udelay(15); /* unknown if delay really needed */
954 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
955 }
956 }
957 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
958
959 /*
960 * VIA VT82C598 has its device ID settable and many BIOSes
961 * set it to the ID of VT82C597 for backward compatibility.
962 * We need to switch it off to be able to recognize the real
963 * type of the chip.
964 */
965 static void quirk_vt82c598_id(struct pci_dev *dev)
966 {
967 pci_write_config_byte(dev, 0xfc, 0);
968 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
969 }
970 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
971
972 /*
973 * CardBus controllers have a legacy base address that enables them
974 * to respond as i82365 pcmcia controllers. We don't want them to
975 * do this even if the Linux CardBus driver is not loaded, because
976 * the Linux i82365 driver does not (and should not) handle CardBus.
977 */
978 static void quirk_cardbus_legacy(struct pci_dev *dev)
979 {
980 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
981 }
982 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
983 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
984 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
985 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
986
987 /*
988 * Following the PCI ordering rules is optional on the AMD762. I'm not
989 * sure what the designers were smoking but let's not inhale...
990 *
991 * To be fair to AMD, it follows the spec by default, its BIOS people
992 * who turn it off!
993 */
994 static void quirk_amd_ordering(struct pci_dev *dev)
995 {
996 u32 pcic;
997 pci_read_config_dword(dev, 0x4C, &pcic);
998 if ((pcic & 6) != 6) {
999 pcic |= 6;
1000 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1001 pci_write_config_dword(dev, 0x4C, pcic);
1002 pci_read_config_dword(dev, 0x84, &pcic);
1003 pcic |= (1 << 23); /* Required in this mode */
1004 pci_write_config_dword(dev, 0x84, pcic);
1005 }
1006 }
1007 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1008 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1009
1010 /*
1011 * DreamWorks provided workaround for Dunord I-3000 problem
1012 *
1013 * This card decodes and responds to addresses not apparently
1014 * assigned to it. We force a larger allocation to ensure that
1015 * nothing gets put too close to it.
1016 */
1017 static void quirk_dunord(struct pci_dev *dev)
1018 {
1019 struct resource *r = &dev->resource[1];
1020
1021 r->flags |= IORESOURCE_UNSET;
1022 r->start = 0;
1023 r->end = 0xffffff;
1024 }
1025 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1026
1027 /*
1028 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1029 * is subtractive decoding (transparent), and does indicate this
1030 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1031 * instead of 0x01.
1032 */
1033 static void quirk_transparent_bridge(struct pci_dev *dev)
1034 {
1035 dev->transparent = 1;
1036 }
1037 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1038 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1039
1040 /*
1041 * Common misconfiguration of the MediaGX/Geode PCI master that will
1042 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
1043 * datasheets found at http://www.national.com/analog for info on what
1044 * these bits do. <christer@weinigel.se>
1045 */
1046 static void quirk_mediagx_master(struct pci_dev *dev)
1047 {
1048 u8 reg;
1049
1050 pci_read_config_byte(dev, 0x41, &reg);
1051 if (reg & 2) {
1052 reg &= ~2;
1053 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1054 reg);
1055 pci_write_config_byte(dev, 0x41, reg);
1056 }
1057 }
1058 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1059 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1060
1061 /*
1062 * Ensure C0 rev restreaming is off. This is normally done by
1063 * the BIOS but in the odd case it is not the results are corruption
1064 * hence the presence of a Linux check
1065 */
1066 static void quirk_disable_pxb(struct pci_dev *pdev)
1067 {
1068 u16 config;
1069
1070 if (pdev->revision != 0x04) /* Only C0 requires this */
1071 return;
1072 pci_read_config_word(pdev, 0x40, &config);
1073 if (config & (1<<6)) {
1074 config &= ~(1<<6);
1075 pci_write_config_word(pdev, 0x40, config);
1076 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1077 }
1078 }
1079 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1080 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1081
1082 static void quirk_amd_ide_mode(struct pci_dev *pdev)
1083 {
1084 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1085 u8 tmp;
1086
1087 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1088 if (tmp == 0x01) {
1089 pci_read_config_byte(pdev, 0x40, &tmp);
1090 pci_write_config_byte(pdev, 0x40, tmp|1);
1091 pci_write_config_byte(pdev, 0x9, 1);
1092 pci_write_config_byte(pdev, 0xa, 6);
1093 pci_write_config_byte(pdev, 0x40, tmp);
1094
1095 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1096 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1097 }
1098 }
1099 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1100 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1101 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1102 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1103 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1104 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1105 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1106 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1107
1108 /*
1109 * Serverworks CSB5 IDE does not fully support native mode
1110 */
1111 static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1112 {
1113 u8 prog;
1114 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1115 if (prog & 5) {
1116 prog &= ~5;
1117 pdev->class &= ~5;
1118 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1119 /* PCI layer will sort out resources */
1120 }
1121 }
1122 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1123
1124 /*
1125 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1126 */
1127 static void quirk_ide_samemode(struct pci_dev *pdev)
1128 {
1129 u8 prog;
1130
1131 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1132
1133 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1134 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1135 prog &= ~5;
1136 pdev->class &= ~5;
1137 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1138 }
1139 }
1140 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1141
1142 /*
1143 * Some ATA devices break if put into D3
1144 */
1145
1146 static void quirk_no_ata_d3(struct pci_dev *pdev)
1147 {
1148 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1149 }
1150 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1151 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1152 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1153 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1154 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1155 /* ALi loses some register settings that we cannot then restore */
1156 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1157 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1158 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1159 occur when mode detecting */
1160 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1161 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1162
1163 /* This was originally an Alpha specific thing, but it really fits here.
1164 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1165 */
1166 static void quirk_eisa_bridge(struct pci_dev *dev)
1167 {
1168 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1169 }
1170 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1171
1172
1173 /*
1174 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1175 * is not activated. The myth is that Asus said that they do not want the
1176 * users to be irritated by just another PCI Device in the Win98 device
1177 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1178 * package 2.7.0 for details)
1179 *
1180 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1181 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1182 * becomes necessary to do this tweak in two steps -- the chosen trigger
1183 * is either the Host bridge (preferred) or on-board VGA controller.
1184 *
1185 * Note that we used to unhide the SMBus that way on Toshiba laptops
1186 * (Satellite A40 and Tecra M2) but then found that the thermal management
1187 * was done by SMM code, which could cause unsynchronized concurrent
1188 * accesses to the SMBus registers, with potentially bad effects. Thus you
1189 * should be very careful when adding new entries: if SMM is accessing the
1190 * Intel SMBus, this is a very good reason to leave it hidden.
1191 *
1192 * Likewise, many recent laptops use ACPI for thermal management. If the
1193 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1194 * natively, and keeping the SMBus hidden is the right thing to do. If you
1195 * are about to add an entry in the table below, please first disassemble
1196 * the DSDT and double-check that there is no code accessing the SMBus.
1197 */
1198 static int asus_hides_smbus;
1199
1200 static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1201 {
1202 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1203 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1204 switch (dev->subsystem_device) {
1205 case 0x8025: /* P4B-LX */
1206 case 0x8070: /* P4B */
1207 case 0x8088: /* P4B533 */
1208 case 0x1626: /* L3C notebook */
1209 asus_hides_smbus = 1;
1210 }
1211 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1212 switch (dev->subsystem_device) {
1213 case 0x80b1: /* P4GE-V */
1214 case 0x80b2: /* P4PE */
1215 case 0x8093: /* P4B533-V */
1216 asus_hides_smbus = 1;
1217 }
1218 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1219 switch (dev->subsystem_device) {
1220 case 0x8030: /* P4T533 */
1221 asus_hides_smbus = 1;
1222 }
1223 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1224 switch (dev->subsystem_device) {
1225 case 0x8070: /* P4G8X Deluxe */
1226 asus_hides_smbus = 1;
1227 }
1228 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1229 switch (dev->subsystem_device) {
1230 case 0x80c9: /* PU-DLS */
1231 asus_hides_smbus = 1;
1232 }
1233 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1234 switch (dev->subsystem_device) {
1235 case 0x1751: /* M2N notebook */
1236 case 0x1821: /* M5N notebook */
1237 case 0x1897: /* A6L notebook */
1238 asus_hides_smbus = 1;
1239 }
1240 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1241 switch (dev->subsystem_device) {
1242 case 0x184b: /* W1N notebook */
1243 case 0x186a: /* M6Ne notebook */
1244 asus_hides_smbus = 1;
1245 }
1246 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1247 switch (dev->subsystem_device) {
1248 case 0x80f2: /* P4P800-X */
1249 asus_hides_smbus = 1;
1250 }
1251 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1252 switch (dev->subsystem_device) {
1253 case 0x1882: /* M6V notebook */
1254 case 0x1977: /* A6VA notebook */
1255 asus_hides_smbus = 1;
1256 }
1257 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1258 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1259 switch (dev->subsystem_device) {
1260 case 0x088C: /* HP Compaq nc8000 */
1261 case 0x0890: /* HP Compaq nc6000 */
1262 asus_hides_smbus = 1;
1263 }
1264 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1265 switch (dev->subsystem_device) {
1266 case 0x12bc: /* HP D330L */
1267 case 0x12bd: /* HP D530 */
1268 case 0x006a: /* HP Compaq nx9500 */
1269 asus_hides_smbus = 1;
1270 }
1271 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1272 switch (dev->subsystem_device) {
1273 case 0x12bf: /* HP xw4100 */
1274 asus_hides_smbus = 1;
1275 }
1276 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1277 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1278 switch (dev->subsystem_device) {
1279 case 0xC00C: /* Samsung P35 notebook */
1280 asus_hides_smbus = 1;
1281 }
1282 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1283 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1284 switch (dev->subsystem_device) {
1285 case 0x0058: /* Compaq Evo N620c */
1286 asus_hides_smbus = 1;
1287 }
1288 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1289 switch (dev->subsystem_device) {
1290 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1291 /* Motherboard doesn't have Host bridge
1292 * subvendor/subdevice IDs, therefore checking
1293 * its on-board VGA controller */
1294 asus_hides_smbus = 1;
1295 }
1296 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1297 switch (dev->subsystem_device) {
1298 case 0x00b8: /* Compaq Evo D510 CMT */
1299 case 0x00b9: /* Compaq Evo D510 SFF */
1300 case 0x00ba: /* Compaq Evo D510 USDT */
1301 /* Motherboard doesn't have Host bridge
1302 * subvendor/subdevice IDs and on-board VGA
1303 * controller is disabled if an AGP card is
1304 * inserted, therefore checking USB UHCI
1305 * Controller #1 */
1306 asus_hides_smbus = 1;
1307 }
1308 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1309 switch (dev->subsystem_device) {
1310 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1311 /* Motherboard doesn't have host bridge
1312 * subvendor/subdevice IDs, therefore checking
1313 * its on-board VGA controller */
1314 asus_hides_smbus = 1;
1315 }
1316 }
1317 }
1318 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1320 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1322 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1323 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1325 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1326 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1327 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1328
1329 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1330 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1331 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1332
1333 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1334 {
1335 u16 val;
1336
1337 if (likely(!asus_hides_smbus))
1338 return;
1339
1340 pci_read_config_word(dev, 0xF2, &val);
1341 if (val & 0x8) {
1342 pci_write_config_word(dev, 0xF2, val & (~0x8));
1343 pci_read_config_word(dev, 0xF2, &val);
1344 if (val & 0x8)
1345 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1346 val);
1347 else
1348 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1349 }
1350 }
1351 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1352 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1353 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1354 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1355 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1356 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1357 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1358 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1359 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1360 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1361 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1362 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1363 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1364 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1365
1366 /* It appears we just have one such device. If not, we have a warning */
1367 static void __iomem *asus_rcba_base;
1368 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1369 {
1370 u32 rcba;
1371
1372 if (likely(!asus_hides_smbus))
1373 return;
1374 WARN_ON(asus_rcba_base);
1375
1376 pci_read_config_dword(dev, 0xF0, &rcba);
1377 /* use bits 31:14, 16 kB aligned */
1378 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1379 if (asus_rcba_base == NULL)
1380 return;
1381 }
1382
1383 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1384 {
1385 u32 val;
1386
1387 if (likely(!asus_hides_smbus || !asus_rcba_base))
1388 return;
1389 /* read the Function Disable register, dword mode only */
1390 val = readl(asus_rcba_base + 0x3418);
1391 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1392 }
1393
1394 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1395 {
1396 if (likely(!asus_hides_smbus || !asus_rcba_base))
1397 return;
1398 iounmap(asus_rcba_base);
1399 asus_rcba_base = NULL;
1400 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1401 }
1402
1403 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1404 {
1405 asus_hides_smbus_lpc_ich6_suspend(dev);
1406 asus_hides_smbus_lpc_ich6_resume_early(dev);
1407 asus_hides_smbus_lpc_ich6_resume(dev);
1408 }
1409 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1410 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1411 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1412 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1413
1414 /*
1415 * SiS 96x south bridge: BIOS typically hides SMBus device...
1416 */
1417 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1418 {
1419 u8 val = 0;
1420 pci_read_config_byte(dev, 0x77, &val);
1421 if (val & 0x10) {
1422 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1423 pci_write_config_byte(dev, 0x77, val & ~0x10);
1424 }
1425 }
1426 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1427 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1428 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1429 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1430 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1431 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1432 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1433 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1434
1435 /*
1436 * ... This is further complicated by the fact that some SiS96x south
1437 * bridges pretend to be 85C503/5513 instead. In that case see if we
1438 * spotted a compatible north bridge to make sure.
1439 * (pci_find_device doesn't work yet)
1440 *
1441 * We can also enable the sis96x bit in the discovery register..
1442 */
1443 #define SIS_DETECT_REGISTER 0x40
1444
1445 static void quirk_sis_503(struct pci_dev *dev)
1446 {
1447 u8 reg;
1448 u16 devid;
1449
1450 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1451 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1452 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1453 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1454 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1455 return;
1456 }
1457
1458 /*
1459 * Ok, it now shows up as a 96x.. run the 96x quirk by
1460 * hand in case it has already been processed.
1461 * (depends on link order, which is apparently not guaranteed)
1462 */
1463 dev->device = devid;
1464 quirk_sis_96x_smbus(dev);
1465 }
1466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1467 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1468
1469
1470 /*
1471 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1472 * and MC97 modem controller are disabled when a second PCI soundcard is
1473 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1474 * -- bjd
1475 */
1476 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1477 {
1478 u8 val;
1479 int asus_hides_ac97 = 0;
1480
1481 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1482 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1483 asus_hides_ac97 = 1;
1484 }
1485
1486 if (!asus_hides_ac97)
1487 return;
1488
1489 pci_read_config_byte(dev, 0x50, &val);
1490 if (val & 0xc0) {
1491 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1492 pci_read_config_byte(dev, 0x50, &val);
1493 if (val & 0xc0)
1494 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1495 val);
1496 else
1497 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1498 }
1499 }
1500 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1501 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1502
1503 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1504
1505 /*
1506 * If we are using libata we can drive this chip properly but must
1507 * do this early on to make the additional device appear during
1508 * the PCI scanning.
1509 */
1510 static void quirk_jmicron_ata(struct pci_dev *pdev)
1511 {
1512 u32 conf1, conf5, class;
1513 u8 hdr;
1514
1515 /* Only poke fn 0 */
1516 if (PCI_FUNC(pdev->devfn))
1517 return;
1518
1519 pci_read_config_dword(pdev, 0x40, &conf1);
1520 pci_read_config_dword(pdev, 0x80, &conf5);
1521
1522 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1523 conf5 &= ~(1 << 24); /* Clear bit 24 */
1524
1525 switch (pdev->device) {
1526 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1527 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1528 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1529 /* The controller should be in single function ahci mode */
1530 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1531 break;
1532
1533 case PCI_DEVICE_ID_JMICRON_JMB365:
1534 case PCI_DEVICE_ID_JMICRON_JMB366:
1535 /* Redirect IDE second PATA port to the right spot */
1536 conf5 |= (1 << 24);
1537 /* Fall through */
1538 case PCI_DEVICE_ID_JMICRON_JMB361:
1539 case PCI_DEVICE_ID_JMICRON_JMB363:
1540 case PCI_DEVICE_ID_JMICRON_JMB369:
1541 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1542 /* Set the class codes correctly and then direct IDE 0 */
1543 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1544 break;
1545
1546 case PCI_DEVICE_ID_JMICRON_JMB368:
1547 /* The controller should be in single function IDE mode */
1548 conf1 |= 0x00C00000; /* Set 22, 23 */
1549 break;
1550 }
1551
1552 pci_write_config_dword(pdev, 0x40, conf1);
1553 pci_write_config_dword(pdev, 0x80, conf5);
1554
1555 /* Update pdev accordingly */
1556 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1557 pdev->hdr_type = hdr & 0x7f;
1558 pdev->multifunction = !!(hdr & 0x80);
1559
1560 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1561 pdev->class = class >> 8;
1562 }
1563 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1564 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1565 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1566 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1567 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1568 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1569 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1570 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1571 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1572 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1573 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1574 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1575 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1576 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1577 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1578 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1579 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1580 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1581
1582 #endif
1583
1584 static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1585 {
1586 if (dev->multifunction) {
1587 device_disable_async_suspend(&dev->dev);
1588 dev_info(&dev->dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1589 }
1590 }
1591 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1592 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1593 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1594 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1595
1596 #ifdef CONFIG_X86_IO_APIC
1597 static void quirk_alder_ioapic(struct pci_dev *pdev)
1598 {
1599 int i;
1600
1601 if ((pdev->class >> 8) != 0xff00)
1602 return;
1603
1604 /* the first BAR is the location of the IO APIC...we must
1605 * not touch this (and it's already covered by the fixmap), so
1606 * forcibly insert it into the resource tree */
1607 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1608 insert_resource(&iomem_resource, &pdev->resource[0]);
1609
1610 /* The next five BARs all seem to be rubbish, so just clean
1611 * them out */
1612 for (i = 1; i < 6; i++)
1613 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1614 }
1615 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1616 #endif
1617
1618 static void quirk_pcie_mch(struct pci_dev *pdev)
1619 {
1620 pdev->no_msi = 1;
1621 }
1622 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1623 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1624 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1625
1626
1627 /*
1628 * It's possible for the MSI to get corrupted if shpc and acpi
1629 * are used together on certain PXH-based systems.
1630 */
1631 static void quirk_pcie_pxh(struct pci_dev *dev)
1632 {
1633 dev->no_msi = 1;
1634 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1635 }
1636 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1637 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1638 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1639 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1640 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1641
1642 /*
1643 * Some Intel PCI Express chipsets have trouble with downstream
1644 * device power management.
1645 */
1646 static void quirk_intel_pcie_pm(struct pci_dev *dev)
1647 {
1648 pci_pm_d3_delay = 120;
1649 dev->no_d1d2 = 1;
1650 }
1651
1652 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1653 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1654 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1655 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1656 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1657 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1658 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1659 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1660 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1661 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1662 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1663 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1664 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1665 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1666 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1667 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1668 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1669 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1670 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1671 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1672 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1673
1674 #ifdef CONFIG_X86_IO_APIC
1675 /*
1676 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1677 * remap the original interrupt in the linux kernel to the boot interrupt, so
1678 * that a PCI device's interrupt handler is installed on the boot interrupt
1679 * line instead.
1680 */
1681 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1682 {
1683 if (noioapicquirk || noioapicreroute)
1684 return;
1685
1686 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1687 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1688 dev->vendor, dev->device);
1689 }
1690 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1691 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1692 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1693 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1694 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1695 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1696 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1697 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1698 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1699 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1700 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1701 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1702 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1703 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1704 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1705 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1706
1707 /*
1708 * On some chipsets we can disable the generation of legacy INTx boot
1709 * interrupts.
1710 */
1711
1712 /*
1713 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1714 * 300641-004US, section 5.7.3.
1715 */
1716 #define INTEL_6300_IOAPIC_ABAR 0x40
1717 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1718
1719 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1720 {
1721 u16 pci_config_word;
1722
1723 if (noioapicquirk)
1724 return;
1725
1726 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1727 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1728 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1729
1730 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1731 dev->vendor, dev->device);
1732 }
1733 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1734 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1735
1736 /*
1737 * disable boot interrupts on HT-1000
1738 */
1739 #define BC_HT1000_FEATURE_REG 0x64
1740 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1741 #define BC_HT1000_MAP_IDX 0xC00
1742 #define BC_HT1000_MAP_DATA 0xC01
1743
1744 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1745 {
1746 u32 pci_config_dword;
1747 u8 irq;
1748
1749 if (noioapicquirk)
1750 return;
1751
1752 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1753 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1754 BC_HT1000_PIC_REGS_ENABLE);
1755
1756 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1757 outb(irq, BC_HT1000_MAP_IDX);
1758 outb(0x00, BC_HT1000_MAP_DATA);
1759 }
1760
1761 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1762
1763 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1764 dev->vendor, dev->device);
1765 }
1766 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1767 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1768
1769 /*
1770 * disable boot interrupts on AMD and ATI chipsets
1771 */
1772 /*
1773 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1774 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1775 * (due to an erratum).
1776 */
1777 #define AMD_813X_MISC 0x40
1778 #define AMD_813X_NOIOAMODE (1<<0)
1779 #define AMD_813X_REV_B1 0x12
1780 #define AMD_813X_REV_B2 0x13
1781
1782 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1783 {
1784 u32 pci_config_dword;
1785
1786 if (noioapicquirk)
1787 return;
1788 if ((dev->revision == AMD_813X_REV_B1) ||
1789 (dev->revision == AMD_813X_REV_B2))
1790 return;
1791
1792 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1793 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1794 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1795
1796 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1797 dev->vendor, dev->device);
1798 }
1799 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1800 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1801 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1802 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1803
1804 #define AMD_8111_PCI_IRQ_ROUTING 0x56
1805
1806 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1807 {
1808 u16 pci_config_word;
1809
1810 if (noioapicquirk)
1811 return;
1812
1813 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1814 if (!pci_config_word) {
1815 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n",
1816 dev->vendor, dev->device);
1817 return;
1818 }
1819 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1820 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1821 dev->vendor, dev->device);
1822 }
1823 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1824 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1825 #endif /* CONFIG_X86_IO_APIC */
1826
1827 /*
1828 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1829 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1830 * Re-allocate the region if needed...
1831 */
1832 static void quirk_tc86c001_ide(struct pci_dev *dev)
1833 {
1834 struct resource *r = &dev->resource[0];
1835
1836 if (r->start & 0x8) {
1837 r->flags |= IORESOURCE_UNSET;
1838 r->start = 0;
1839 r->end = 0xf;
1840 }
1841 }
1842 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1843 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1844 quirk_tc86c001_ide);
1845
1846 /*
1847 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
1848 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1849 * being read correctly if bit 7 of the base address is set.
1850 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
1851 * Re-allocate the regions to a 256-byte boundary if necessary.
1852 */
1853 static void quirk_plx_pci9050(struct pci_dev *dev)
1854 {
1855 unsigned int bar;
1856
1857 /* Fixed in revision 2 (PCI 9052). */
1858 if (dev->revision >= 2)
1859 return;
1860 for (bar = 0; bar <= 1; bar++)
1861 if (pci_resource_len(dev, bar) == 0x80 &&
1862 (pci_resource_start(dev, bar) & 0x80)) {
1863 struct resource *r = &dev->resource[bar];
1864 dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
1865 bar);
1866 r->flags |= IORESOURCE_UNSET;
1867 r->start = 0;
1868 r->end = 0xff;
1869 }
1870 }
1871 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1872 quirk_plx_pci9050);
1873 /*
1874 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
1875 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
1876 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
1877 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
1878 *
1879 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
1880 * driver.
1881 */
1882 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
1883 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
1884
1885 static void quirk_netmos(struct pci_dev *dev)
1886 {
1887 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1888 unsigned int num_serial = dev->subsystem_device & 0xf;
1889
1890 /*
1891 * These Netmos parts are multiport serial devices with optional
1892 * parallel ports. Even when parallel ports are present, they
1893 * are identified as class SERIAL, which means the serial driver
1894 * will claim them. To prevent this, mark them as class OTHER.
1895 * These combo devices should be claimed by parport_serial.
1896 *
1897 * The subdevice ID is of the form 0x00PS, where <P> is the number
1898 * of parallel ports and <S> is the number of serial ports.
1899 */
1900 switch (dev->device) {
1901 case PCI_DEVICE_ID_NETMOS_9835:
1902 /* Well, this rule doesn't hold for the following 9835 device */
1903 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1904 dev->subsystem_device == 0x0299)
1905 return;
1906 case PCI_DEVICE_ID_NETMOS_9735:
1907 case PCI_DEVICE_ID_NETMOS_9745:
1908 case PCI_DEVICE_ID_NETMOS_9845:
1909 case PCI_DEVICE_ID_NETMOS_9855:
1910 if (num_parallel) {
1911 dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
1912 dev->device, num_parallel, num_serial);
1913 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1914 (dev->class & 0xff);
1915 }
1916 }
1917 }
1918 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1919 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1920
1921 /*
1922 * Quirk non-zero PCI functions to route VPD access through function 0 for
1923 * devices that share VPD resources between functions. The functions are
1924 * expected to be identical devices.
1925 */
1926 static void quirk_f0_vpd_link(struct pci_dev *dev)
1927 {
1928 struct pci_dev *f0;
1929
1930 if (!PCI_FUNC(dev->devfn))
1931 return;
1932
1933 f0 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
1934 if (!f0)
1935 return;
1936
1937 if (f0->vpd && dev->class == f0->class &&
1938 dev->vendor == f0->vendor && dev->device == f0->device)
1939 dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0;
1940
1941 pci_dev_put(f0);
1942 }
1943 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1944 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);
1945
1946 static void quirk_e100_interrupt(struct pci_dev *dev)
1947 {
1948 u16 command, pmcsr;
1949 u8 __iomem *csr;
1950 u8 cmd_hi;
1951
1952 switch (dev->device) {
1953 /* PCI IDs taken from drivers/net/e100.c */
1954 case 0x1029:
1955 case 0x1030 ... 0x1034:
1956 case 0x1038 ... 0x103E:
1957 case 0x1050 ... 0x1057:
1958 case 0x1059:
1959 case 0x1064 ... 0x106B:
1960 case 0x1091 ... 0x1095:
1961 case 0x1209:
1962 case 0x1229:
1963 case 0x2449:
1964 case 0x2459:
1965 case 0x245D:
1966 case 0x27DC:
1967 break;
1968 default:
1969 return;
1970 }
1971
1972 /*
1973 * Some firmware hands off the e100 with interrupts enabled,
1974 * which can cause a flood of interrupts if packets are
1975 * received before the driver attaches to the device. So
1976 * disable all e100 interrupts here. The driver will
1977 * re-enable them when it's ready.
1978 */
1979 pci_read_config_word(dev, PCI_COMMAND, &command);
1980
1981 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1982 return;
1983
1984 /*
1985 * Check that the device is in the D0 power state. If it's not,
1986 * there is no point to look any further.
1987 */
1988 if (dev->pm_cap) {
1989 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1990 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1991 return;
1992 }
1993
1994 /* Convert from PCI bus to resource space. */
1995 csr = ioremap(pci_resource_start(dev, 0), 8);
1996 if (!csr) {
1997 dev_warn(&dev->dev, "Can't map e100 registers\n");
1998 return;
1999 }
2000
2001 cmd_hi = readb(csr + 3);
2002 if (cmd_hi == 0) {
2003 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n");
2004 writeb(1, csr + 3);
2005 }
2006
2007 iounmap(csr);
2008 }
2009 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2010 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2011
2012 /*
2013 * The 82575 and 82598 may experience data corruption issues when transitioning
2014 * out of L0S. To prevent this we need to disable L0S on the pci-e link
2015 */
2016 static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2017 {
2018 dev_info(&dev->dev, "Disabling L0s\n");
2019 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2020 }
2021 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2022 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2023 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2024 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2025 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2026 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2027 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2028 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2029 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2030 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2031 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2032 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2033 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2035
2036 static void fixup_rev1_53c810(struct pci_dev *dev)
2037 {
2038 u32 class = dev->class;
2039
2040 /*
2041 * rev 1 ncr53c810 chips don't set the class at all which means
2042 * they don't get their resources remapped. Fix that here.
2043 */
2044 if (class)
2045 return;
2046
2047 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2048 dev_info(&dev->dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2049 class, dev->class);
2050 }
2051 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2052
2053 /* Enable 1k I/O space granularity on the Intel P64H2 */
2054 static void quirk_p64h2_1k_io(struct pci_dev *dev)
2055 {
2056 u16 en1k;
2057
2058 pci_read_config_word(dev, 0x40, &en1k);
2059
2060 if (en1k & 0x200) {
2061 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
2062 dev->io_window_1k = 1;
2063 }
2064 }
2065 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2066
2067 /* Under some circumstances, AER is not linked with extended capabilities.
2068 * Force it to be linked by setting the corresponding control bit in the
2069 * config space.
2070 */
2071 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2072 {
2073 uint8_t b;
2074 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2075 if (!(b & 0x20)) {
2076 pci_write_config_byte(dev, 0xf41, b | 0x20);
2077 dev_info(&dev->dev, "Linking AER extended capability\n");
2078 }
2079 }
2080 }
2081 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2082 quirk_nvidia_ck804_pcie_aer_ext_cap);
2083 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2084 quirk_nvidia_ck804_pcie_aer_ext_cap);
2085
2086 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2087 {
2088 /*
2089 * Disable PCI Bus Parking and PCI Master read caching on CX700
2090 * which causes unspecified timing errors with a VT6212L on the PCI
2091 * bus leading to USB2.0 packet loss.
2092 *
2093 * This quirk is only enabled if a second (on the external PCI bus)
2094 * VT6212L is found -- the CX700 core itself also contains a USB
2095 * host controller with the same PCI ID as the VT6212L.
2096 */
2097
2098 /* Count VT6212L instances */
2099 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2100 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2101 uint8_t b;
2102
2103 /* p should contain the first (internal) VT6212L -- see if we have
2104 an external one by searching again */
2105 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2106 if (!p)
2107 return;
2108 pci_dev_put(p);
2109
2110 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2111 if (b & 0x40) {
2112 /* Turn off PCI Bus Parking */
2113 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2114
2115 dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n");
2116 }
2117 }
2118
2119 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2120 if (b != 0) {
2121 /* Turn off PCI Master read caching */
2122 pci_write_config_byte(dev, 0x72, 0x0);
2123
2124 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2125 pci_write_config_byte(dev, 0x75, 0x1);
2126
2127 /* Disable "Read FIFO Timer" */
2128 pci_write_config_byte(dev, 0x77, 0x0);
2129
2130 dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n");
2131 }
2132 }
2133 }
2134 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2135
2136 /*
2137 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2138 * VPD end tag will hang the device. This problem was initially
2139 * observed when a vpd entry was created in sysfs
2140 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2141 * will dump 32k of data. Reading a full 32k will cause an access
2142 * beyond the VPD end tag causing the device to hang. Once the device
2143 * is hung, the bnx2 driver will not be able to reset the device.
2144 * We believe that it is legal to read beyond the end tag and
2145 * therefore the solution is to limit the read/write length.
2146 */
2147 static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2148 {
2149 /*
2150 * Only disable the VPD capability for 5706, 5706S, 5708,
2151 * 5708S and 5709 rev. A
2152 */
2153 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2154 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2155 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2156 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2157 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2158 (dev->revision & 0xf0) == 0x0)) {
2159 if (dev->vpd)
2160 dev->vpd->len = 0x80;
2161 }
2162 }
2163
2164 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2165 PCI_DEVICE_ID_NX2_5706,
2166 quirk_brcm_570x_limit_vpd);
2167 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2168 PCI_DEVICE_ID_NX2_5706S,
2169 quirk_brcm_570x_limit_vpd);
2170 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2171 PCI_DEVICE_ID_NX2_5708,
2172 quirk_brcm_570x_limit_vpd);
2173 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2174 PCI_DEVICE_ID_NX2_5708S,
2175 quirk_brcm_570x_limit_vpd);
2176 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2177 PCI_DEVICE_ID_NX2_5709,
2178 quirk_brcm_570x_limit_vpd);
2179 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2180 PCI_DEVICE_ID_NX2_5709S,
2181 quirk_brcm_570x_limit_vpd);
2182
2183 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2184 {
2185 u32 rev;
2186
2187 pci_read_config_dword(dev, 0xf4, &rev);
2188
2189 /* Only CAP the MRRS if the device is a 5719 A0 */
2190 if (rev == 0x05719000) {
2191 int readrq = pcie_get_readrq(dev);
2192 if (readrq > 2048)
2193 pcie_set_readrq(dev, 2048);
2194 }
2195 }
2196
2197 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2198 PCI_DEVICE_ID_TIGON3_5719,
2199 quirk_brcm_5719_limit_mrrs);
2200
2201 /* Originally in EDAC sources for i82875P:
2202 * Intel tells BIOS developers to hide device 6 which
2203 * configures the overflow device access containing
2204 * the DRBs - this is where we expose device 6.
2205 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2206 */
2207 static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2208 {
2209 u8 reg;
2210
2211 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2212 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2213 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2214 }
2215 }
2216
2217 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2218 quirk_unhide_mch_dev6);
2219 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2220 quirk_unhide_mch_dev6);
2221
2222 #ifdef CONFIG_TILEPRO
2223 /*
2224 * The Tilera TILEmpower tilepro platform needs to set the link speed
2225 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2226 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2227 * capability register of the PEX8624 PCIe switch. The switch
2228 * supports link speed auto negotiation, but falsely sets
2229 * the link speed to 5GT/s.
2230 */
2231 static void quirk_tile_plx_gen1(struct pci_dev *dev)
2232 {
2233 if (tile_plx_gen1) {
2234 pci_write_config_dword(dev, 0x98, 0x1);
2235 mdelay(50);
2236 }
2237 }
2238 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2239 #endif /* CONFIG_TILEPRO */
2240
2241 #ifdef CONFIG_PCI_MSI
2242 /* Some chipsets do not support MSI. We cannot easily rely on setting
2243 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2244 * some other buses controlled by the chipset even if Linux is not
2245 * aware of it. Instead of setting the flag on all buses in the
2246 * machine, simply disable MSI globally.
2247 */
2248 static void quirk_disable_all_msi(struct pci_dev *dev)
2249 {
2250 pci_no_msi();
2251 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2252 }
2253 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2254 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2255 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2256 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2257 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2258 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2259 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2261
2262 /* Disable MSI on chipsets that are known to not support it */
2263 static void quirk_disable_msi(struct pci_dev *dev)
2264 {
2265 if (dev->subordinate) {
2266 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2267 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2268 }
2269 }
2270 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2271 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2272 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2273
2274 /*
2275 * The APC bridge device in AMD 780 family northbridges has some random
2276 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2277 * we use the possible vendor/device IDs of the host bridge for the
2278 * declared quirk, and search for the APC bridge by slot number.
2279 */
2280 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2281 {
2282 struct pci_dev *apc_bridge;
2283
2284 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2285 if (apc_bridge) {
2286 if (apc_bridge->device == 0x9602)
2287 quirk_disable_msi(apc_bridge);
2288 pci_dev_put(apc_bridge);
2289 }
2290 }
2291 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2292 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2293
2294 /* Go through the list of Hypertransport capabilities and
2295 * return 1 if a HT MSI capability is found and enabled */
2296 static int msi_ht_cap_enabled(struct pci_dev *dev)
2297 {
2298 int pos, ttl = PCI_FIND_CAP_TTL;
2299
2300 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2301 while (pos && ttl--) {
2302 u8 flags;
2303
2304 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2305 &flags) == 0) {
2306 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2307 flags & HT_MSI_FLAGS_ENABLE ?
2308 "enabled" : "disabled");
2309 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2310 }
2311
2312 pos = pci_find_next_ht_capability(dev, pos,
2313 HT_CAPTYPE_MSI_MAPPING);
2314 }
2315 return 0;
2316 }
2317
2318 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2319 static void quirk_msi_ht_cap(struct pci_dev *dev)
2320 {
2321 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2322 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2323 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2324 }
2325 }
2326 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2327 quirk_msi_ht_cap);
2328
2329 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
2330 * MSI are supported if the MSI capability set in any of these mappings.
2331 */
2332 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2333 {
2334 struct pci_dev *pdev;
2335
2336 if (!dev->subordinate)
2337 return;
2338
2339 /* check HT MSI cap on this chipset and the root one.
2340 * a single one having MSI is enough to be sure that MSI are supported.
2341 */
2342 pdev = pci_get_slot(dev->bus, 0);
2343 if (!pdev)
2344 return;
2345 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2346 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2347 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2348 }
2349 pci_dev_put(pdev);
2350 }
2351 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2352 quirk_nvidia_ck804_msi_ht_cap);
2353
2354 /* Force enable MSI mapping capability on HT bridges */
2355 static void ht_enable_msi_mapping(struct pci_dev *dev)
2356 {
2357 int pos, ttl = PCI_FIND_CAP_TTL;
2358
2359 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2360 while (pos && ttl--) {
2361 u8 flags;
2362
2363 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2364 &flags) == 0) {
2365 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2366
2367 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2368 flags | HT_MSI_FLAGS_ENABLE);
2369 }
2370 pos = pci_find_next_ht_capability(dev, pos,
2371 HT_CAPTYPE_MSI_MAPPING);
2372 }
2373 }
2374 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2375 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2376 ht_enable_msi_mapping);
2377
2378 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2379 ht_enable_msi_mapping);
2380
2381 /* The P5N32-SLI motherboards from Asus have a problem with msi
2382 * for the MCP55 NIC. It is not yet determined whether the msi problem
2383 * also affects other devices. As for now, turn off msi for this device.
2384 */
2385 static void nvenet_msi_disable(struct pci_dev *dev)
2386 {
2387 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2388
2389 if (board_name &&
2390 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2391 strstr(board_name, "P5N32-E SLI"))) {
2392 dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2393 dev->no_msi = 1;
2394 }
2395 }
2396 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2397 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2398 nvenet_msi_disable);
2399
2400 /*
2401 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2402 * config register. This register controls the routing of legacy
2403 * interrupts from devices that route through the MCP55. If this register
2404 * is misprogrammed, interrupts are only sent to the BSP, unlike
2405 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2406 * having this register set properly prevents kdump from booting up
2407 * properly, so let's make sure that we have it set correctly.
2408 * Note that this is an undocumented register.
2409 */
2410 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2411 {
2412 u32 cfg;
2413
2414 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2415 return;
2416
2417 pci_read_config_dword(dev, 0x74, &cfg);
2418
2419 if (cfg & ((1 << 2) | (1 << 15))) {
2420 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2421 cfg &= ~((1 << 2) | (1 << 15));
2422 pci_write_config_dword(dev, 0x74, cfg);
2423 }
2424 }
2425
2426 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2427 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2428 nvbridge_check_legacy_irq_routing);
2429
2430 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2431 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2432 nvbridge_check_legacy_irq_routing);
2433
2434 static int ht_check_msi_mapping(struct pci_dev *dev)
2435 {
2436 int pos, ttl = PCI_FIND_CAP_TTL;
2437 int found = 0;
2438
2439 /* check if there is HT MSI cap or enabled on this device */
2440 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2441 while (pos && ttl--) {
2442 u8 flags;
2443
2444 if (found < 1)
2445 found = 1;
2446 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2447 &flags) == 0) {
2448 if (flags & HT_MSI_FLAGS_ENABLE) {
2449 if (found < 2) {
2450 found = 2;
2451 break;
2452 }
2453 }
2454 }
2455 pos = pci_find_next_ht_capability(dev, pos,
2456 HT_CAPTYPE_MSI_MAPPING);
2457 }
2458
2459 return found;
2460 }
2461
2462 static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2463 {
2464 struct pci_dev *dev;
2465 int pos;
2466 int i, dev_no;
2467 int found = 0;
2468
2469 dev_no = host_bridge->devfn >> 3;
2470 for (i = dev_no + 1; i < 0x20; i++) {
2471 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2472 if (!dev)
2473 continue;
2474
2475 /* found next host bridge ?*/
2476 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2477 if (pos != 0) {
2478 pci_dev_put(dev);
2479 break;
2480 }
2481
2482 if (ht_check_msi_mapping(dev)) {
2483 found = 1;
2484 pci_dev_put(dev);
2485 break;
2486 }
2487 pci_dev_put(dev);
2488 }
2489
2490 return found;
2491 }
2492
2493 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2494 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2495
2496 static int is_end_of_ht_chain(struct pci_dev *dev)
2497 {
2498 int pos, ctrl_off;
2499 int end = 0;
2500 u16 flags, ctrl;
2501
2502 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2503
2504 if (!pos)
2505 goto out;
2506
2507 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2508
2509 ctrl_off = ((flags >> 10) & 1) ?
2510 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2511 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2512
2513 if (ctrl & (1 << 6))
2514 end = 1;
2515
2516 out:
2517 return end;
2518 }
2519
2520 static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2521 {
2522 struct pci_dev *host_bridge;
2523 int pos;
2524 int i, dev_no;
2525 int found = 0;
2526
2527 dev_no = dev->devfn >> 3;
2528 for (i = dev_no; i >= 0; i--) {
2529 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2530 if (!host_bridge)
2531 continue;
2532
2533 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2534 if (pos != 0) {
2535 found = 1;
2536 break;
2537 }
2538 pci_dev_put(host_bridge);
2539 }
2540
2541 if (!found)
2542 return;
2543
2544 /* don't enable end_device/host_bridge with leaf directly here */
2545 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2546 host_bridge_with_leaf(host_bridge))
2547 goto out;
2548
2549 /* root did that ! */
2550 if (msi_ht_cap_enabled(host_bridge))
2551 goto out;
2552
2553 ht_enable_msi_mapping(dev);
2554
2555 out:
2556 pci_dev_put(host_bridge);
2557 }
2558
2559 static void ht_disable_msi_mapping(struct pci_dev *dev)
2560 {
2561 int pos, ttl = PCI_FIND_CAP_TTL;
2562
2563 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2564 while (pos && ttl--) {
2565 u8 flags;
2566
2567 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2568 &flags) == 0) {
2569 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2570
2571 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2572 flags & ~HT_MSI_FLAGS_ENABLE);
2573 }
2574 pos = pci_find_next_ht_capability(dev, pos,
2575 HT_CAPTYPE_MSI_MAPPING);
2576 }
2577 }
2578
2579 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2580 {
2581 struct pci_dev *host_bridge;
2582 int pos;
2583 int found;
2584
2585 if (!pci_msi_enabled())
2586 return;
2587
2588 /* check if there is HT MSI cap or enabled on this device */
2589 found = ht_check_msi_mapping(dev);
2590
2591 /* no HT MSI CAP */
2592 if (found == 0)
2593 return;
2594
2595 /*
2596 * HT MSI mapping should be disabled on devices that are below
2597 * a non-Hypertransport host bridge. Locate the host bridge...
2598 */
2599 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2600 if (host_bridge == NULL) {
2601 dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2602 return;
2603 }
2604
2605 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2606 if (pos != 0) {
2607 /* Host bridge is to HT */
2608 if (found == 1) {
2609 /* it is not enabled, try to enable it */
2610 if (all)
2611 ht_enable_msi_mapping(dev);
2612 else
2613 nv_ht_enable_msi_mapping(dev);
2614 }
2615 goto out;
2616 }
2617
2618 /* HT MSI is not enabled */
2619 if (found == 1)
2620 goto out;
2621
2622 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2623 ht_disable_msi_mapping(dev);
2624
2625 out:
2626 pci_dev_put(host_bridge);
2627 }
2628
2629 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2630 {
2631 return __nv_msi_ht_cap_quirk(dev, 1);
2632 }
2633
2634 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2635 {
2636 return __nv_msi_ht_cap_quirk(dev, 0);
2637 }
2638
2639 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2640 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2641
2642 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2643 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2644
2645 static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2646 {
2647 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2648 }
2649 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2650 {
2651 struct pci_dev *p;
2652
2653 /* SB700 MSI issue will be fixed at HW level from revision A21,
2654 * we need check PCI REVISION ID of SMBus controller to get SB700
2655 * revision.
2656 */
2657 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2658 NULL);
2659 if (!p)
2660 return;
2661
2662 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2663 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2664 pci_dev_put(p);
2665 }
2666 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2667 {
2668 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2669 if (dev->revision < 0x18) {
2670 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n");
2671 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2672 }
2673 }
2674 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2675 PCI_DEVICE_ID_TIGON3_5780,
2676 quirk_msi_intx_disable_bug);
2677 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2678 PCI_DEVICE_ID_TIGON3_5780S,
2679 quirk_msi_intx_disable_bug);
2680 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2681 PCI_DEVICE_ID_TIGON3_5714,
2682 quirk_msi_intx_disable_bug);
2683 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2684 PCI_DEVICE_ID_TIGON3_5714S,
2685 quirk_msi_intx_disable_bug);
2686 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2687 PCI_DEVICE_ID_TIGON3_5715,
2688 quirk_msi_intx_disable_bug);
2689 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2690 PCI_DEVICE_ID_TIGON3_5715S,
2691 quirk_msi_intx_disable_bug);
2692
2693 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2694 quirk_msi_intx_disable_ati_bug);
2695 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2696 quirk_msi_intx_disable_ati_bug);
2697 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2698 quirk_msi_intx_disable_ati_bug);
2699 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2700 quirk_msi_intx_disable_ati_bug);
2701 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2702 quirk_msi_intx_disable_ati_bug);
2703
2704 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2705 quirk_msi_intx_disable_bug);
2706 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2707 quirk_msi_intx_disable_bug);
2708 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2709 quirk_msi_intx_disable_bug);
2710
2711 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2712 quirk_msi_intx_disable_bug);
2713 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2714 quirk_msi_intx_disable_bug);
2715 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2716 quirk_msi_intx_disable_bug);
2717 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2718 quirk_msi_intx_disable_bug);
2719 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2720 quirk_msi_intx_disable_bug);
2721 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2722 quirk_msi_intx_disable_bug);
2723 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2724 quirk_msi_intx_disable_qca_bug);
2725 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2726 quirk_msi_intx_disable_qca_bug);
2727 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2728 quirk_msi_intx_disable_qca_bug);
2729 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2730 quirk_msi_intx_disable_qca_bug);
2731 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2732 quirk_msi_intx_disable_qca_bug);
2733 #endif /* CONFIG_PCI_MSI */
2734
2735 /* Allow manual resource allocation for PCI hotplug bridges
2736 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2737 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2738 * kernel fails to allocate resources when hotplug device is
2739 * inserted and PCI bus is rescanned.
2740 */
2741 static void quirk_hotplug_bridge(struct pci_dev *dev)
2742 {
2743 dev->is_hotplug_bridge = 1;
2744 }
2745
2746 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2747
2748 /*
2749 * This is a quirk for the Ricoh MMC controller found as a part of
2750 * some mulifunction chips.
2751
2752 * This is very similar and based on the ricoh_mmc driver written by
2753 * Philip Langdale. Thank you for these magic sequences.
2754 *
2755 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2756 * and one or both of cardbus or firewire.
2757 *
2758 * It happens that they implement SD and MMC
2759 * support as separate controllers (and PCI functions). The linux SDHCI
2760 * driver supports MMC cards but the chip detects MMC cards in hardware
2761 * and directs them to the MMC controller - so the SDHCI driver never sees
2762 * them.
2763 *
2764 * To get around this, we must disable the useless MMC controller.
2765 * At that point, the SDHCI controller will start seeing them
2766 * It seems to be the case that the relevant PCI registers to deactivate the
2767 * MMC controller live on PCI function 0, which might be the cardbus controller
2768 * or the firewire controller, depending on the particular chip in question
2769 *
2770 * This has to be done early, because as soon as we disable the MMC controller
2771 * other pci functions shift up one level, e.g. function #2 becomes function
2772 * #1, and this will confuse the pci core.
2773 */
2774
2775 #ifdef CONFIG_MMC_RICOH_MMC
2776 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2777 {
2778 /* disable via cardbus interface */
2779 u8 write_enable;
2780 u8 write_target;
2781 u8 disable;
2782
2783 /* disable must be done via function #0 */
2784 if (PCI_FUNC(dev->devfn))
2785 return;
2786
2787 pci_read_config_byte(dev, 0xB7, &disable);
2788 if (disable & 0x02)
2789 return;
2790
2791 pci_read_config_byte(dev, 0x8E, &write_enable);
2792 pci_write_config_byte(dev, 0x8E, 0xAA);
2793 pci_read_config_byte(dev, 0x8D, &write_target);
2794 pci_write_config_byte(dev, 0x8D, 0xB7);
2795 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2796 pci_write_config_byte(dev, 0x8E, write_enable);
2797 pci_write_config_byte(dev, 0x8D, write_target);
2798
2799 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2800 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2801 }
2802 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2803 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2804
2805 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2806 {
2807 /* disable via firewire interface */
2808 u8 write_enable;
2809 u8 disable;
2810
2811 /* disable must be done via function #0 */
2812 if (PCI_FUNC(dev->devfn))
2813 return;
2814 /*
2815 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
2816 * certain types of SD/MMC cards. Lowering the SD base
2817 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2818 *
2819 * 0x150 - SD2.0 mode enable for changing base clock
2820 * frequency to 50Mhz
2821 * 0xe1 - Base clock frequency
2822 * 0x32 - 50Mhz new clock frequency
2823 * 0xf9 - Key register for 0x150
2824 * 0xfc - key register for 0xe1
2825 */
2826 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2827 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2828 pci_write_config_byte(dev, 0xf9, 0xfc);
2829 pci_write_config_byte(dev, 0x150, 0x10);
2830 pci_write_config_byte(dev, 0xf9, 0x00);
2831 pci_write_config_byte(dev, 0xfc, 0x01);
2832 pci_write_config_byte(dev, 0xe1, 0x32);
2833 pci_write_config_byte(dev, 0xfc, 0x00);
2834
2835 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2836 }
2837
2838 pci_read_config_byte(dev, 0xCB, &disable);
2839
2840 if (disable & 0x02)
2841 return;
2842
2843 pci_read_config_byte(dev, 0xCA, &write_enable);
2844 pci_write_config_byte(dev, 0xCA, 0x57);
2845 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2846 pci_write_config_byte(dev, 0xCA, write_enable);
2847
2848 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2849 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2850
2851 }
2852 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2853 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2854 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2855 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2856 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2857 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2858 #endif /*CONFIG_MMC_RICOH_MMC*/
2859
2860 #ifdef CONFIG_DMAR_TABLE
2861 #define VTUNCERRMSK_REG 0x1ac
2862 #define VTD_MSK_SPEC_ERRORS (1 << 31)
2863 /*
2864 * This is a quirk for masking vt-d spec defined errors to platform error
2865 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2866 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2867 * on the RAS config settings of the platform) when a vt-d fault happens.
2868 * The resulting SMI caused the system to hang.
2869 *
2870 * VT-d spec related errors are already handled by the VT-d OS code, so no
2871 * need to report the same error through other channels.
2872 */
2873 static void vtd_mask_spec_errors(struct pci_dev *dev)
2874 {
2875 u32 word;
2876
2877 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2878 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2879 }
2880 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2881 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2882 #endif
2883
2884 static void fixup_ti816x_class(struct pci_dev *dev)
2885 {
2886 u32 class = dev->class;
2887
2888 /* TI 816x devices do not have class code set when in PCIe boot mode */
2889 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
2890 dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n",
2891 class, dev->class);
2892 }
2893 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
2894 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
2895
2896 /* Some PCIe devices do not work reliably with the claimed maximum
2897 * payload size supported.
2898 */
2899 static void fixup_mpss_256(struct pci_dev *dev)
2900 {
2901 dev->pcie_mpss = 1; /* 256 bytes */
2902 }
2903 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2904 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2905 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2906 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2907 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2908 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2909
2910 /* Intel 5000 and 5100 Memory controllers have an errata with read completion
2911 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2912 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2913 * until all of the devices are discovered and buses walked, read completion
2914 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2915 * it is possible to hotplug a device with MPS of 256B.
2916 */
2917 static void quirk_intel_mc_errata(struct pci_dev *dev)
2918 {
2919 int err;
2920 u16 rcc;
2921
2922 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2923 pcie_bus_config == PCIE_BUS_DEFAULT)
2924 return;
2925
2926 /* Intel errata specifies bits to change but does not say what they are.
2927 * Keeping them magical until such time as the registers and values can
2928 * be explained.
2929 */
2930 err = pci_read_config_word(dev, 0x48, &rcc);
2931 if (err) {
2932 dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n");
2933 return;
2934 }
2935
2936 if (!(rcc & (1 << 10)))
2937 return;
2938
2939 rcc &= ~(1 << 10);
2940
2941 err = pci_write_config_word(dev, 0x48, rcc);
2942 if (err) {
2943 dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n");
2944 return;
2945 }
2946
2947 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n");
2948 }
2949 /* Intel 5000 series memory controllers and ports 2-7 */
2950 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
2951 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
2952 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
2953 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
2954 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
2955 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
2956 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
2957 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
2958 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
2959 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
2960 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
2961 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
2962 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
2963 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
2964 /* Intel 5100 series memory controllers and ports 2-7 */
2965 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
2966 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
2967 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
2968 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
2969 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
2970 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
2971 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
2972 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
2973 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
2974 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
2975 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
2976
2977
2978 /*
2979 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To
2980 * work around this, query the size it should be configured to by the device and
2981 * modify the resource end to correspond to this new size.
2982 */
2983 static void quirk_intel_ntb(struct pci_dev *dev)
2984 {
2985 int rc;
2986 u8 val;
2987
2988 rc = pci_read_config_byte(dev, 0x00D0, &val);
2989 if (rc)
2990 return;
2991
2992 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
2993
2994 rc = pci_read_config_byte(dev, 0x00D1, &val);
2995 if (rc)
2996 return;
2997
2998 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
2999 }
3000 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3001 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3002
3003 static ktime_t fixup_debug_start(struct pci_dev *dev,
3004 void (*fn)(struct pci_dev *dev))
3005 {
3006 ktime_t calltime = ktime_set(0, 0);
3007
3008 dev_dbg(&dev->dev, "calling %pF\n", fn);
3009 if (initcall_debug) {
3010 pr_debug("calling %pF @ %i for %s\n",
3011 fn, task_pid_nr(current), dev_name(&dev->dev));
3012 calltime = ktime_get();
3013 }
3014
3015 return calltime;
3016 }
3017
3018 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
3019 void (*fn)(struct pci_dev *dev))
3020 {
3021 ktime_t delta, rettime;
3022 unsigned long long duration;
3023
3024 if (initcall_debug) {
3025 rettime = ktime_get();
3026 delta = ktime_sub(rettime, calltime);
3027 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
3028 pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
3029 fn, duration, dev_name(&dev->dev));
3030 }
3031 }
3032
3033 /*
3034 * Some BIOS implementations leave the Intel GPU interrupts enabled,
3035 * even though no one is handling them (f.e. i915 driver is never loaded).
3036 * Additionally the interrupt destination is not set up properly
3037 * and the interrupt ends up -somewhere-.
3038 *
3039 * These spurious interrupts are "sticky" and the kernel disables
3040 * the (shared) interrupt line after 100.000+ generated interrupts.
3041 *
3042 * Fix it by disabling the still enabled interrupts.
3043 * This resolves crashes often seen on monitor unplug.
3044 */
3045 #define I915_DEIER_REG 0x4400c
3046 static void disable_igfx_irq(struct pci_dev *dev)
3047 {
3048 void __iomem *regs = pci_iomap(dev, 0, 0);
3049 if (regs == NULL) {
3050 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
3051 return;
3052 }
3053
3054 /* Check if any interrupt line is still enabled */
3055 if (readl(regs + I915_DEIER_REG) != 0) {
3056 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3057
3058 writel(0, regs + I915_DEIER_REG);
3059 }
3060
3061 pci_iounmap(dev, regs);
3062 }
3063 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3064 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3065 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3066
3067 /*
3068 * PCI devices which are on Intel chips can skip the 10ms delay
3069 * before entering D3 mode.
3070 */
3071 static void quirk_remove_d3_delay(struct pci_dev *dev)
3072 {
3073 dev->d3_delay = 0;
3074 }
3075 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3076 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3077 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3078 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3079 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3080 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3081 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3082 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3083 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3084 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3085 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3086 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3087 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3088 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
3089 /* Intel Cherrytrail devices do not need 10ms d3_delay */
3090 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
3091 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
3092 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3093 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3094 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
3095 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3096 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
3097 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3098 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
3099 /*
3100 * Some devices may pass our check in pci_intx_mask_supported if
3101 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3102 * support this feature.
3103 */
3104 static void quirk_broken_intx_masking(struct pci_dev *dev)
3105 {
3106 dev->broken_intx_masking = 1;
3107 }
3108 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, 0x0030,
3109 quirk_broken_intx_masking);
3110 DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3111 quirk_broken_intx_masking);
3112 /*
3113 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3114 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3115 *
3116 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3117 */
3118 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_REALTEK, 0x8169,
3119 quirk_broken_intx_masking);
3120 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3121 quirk_broken_intx_masking);
3122
3123 static void quirk_no_bus_reset(struct pci_dev *dev)
3124 {
3125 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3126 }
3127
3128 /*
3129 * Atheros AR93xx chips do not behave after a bus reset. The device will
3130 * throw a Link Down error on AER-capable systems and regardless of AER,
3131 * config space of the device is never accessible again and typically
3132 * causes the system to hang or reset when access is attempted.
3133 * http://www.spinics.net/lists/linux-pci/msg34797.html
3134 */
3135 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3136
3137 static void quirk_no_pm_reset(struct pci_dev *dev)
3138 {
3139 /*
3140 * We can't do a bus reset on root bus devices, but an ineffective
3141 * PM reset may be better than nothing.
3142 */
3143 if (!pci_is_root_bus(dev->bus))
3144 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3145 }
3146
3147 /*
3148 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3149 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3150 * to have no effect on the device: it retains the framebuffer contents and
3151 * monitor sync. Advertising this support makes other layers, like VFIO,
3152 * assume pci_reset_function() is viable for this device. Mark it as
3153 * unavailable to skip it when testing reset methods.
3154 */
3155 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3156 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3157
3158 #ifdef CONFIG_ACPI
3159 /*
3160 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3161 *
3162 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3163 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3164 * be present after resume if a device was plugged in before suspend.
3165 *
3166 * The thunderbolt controller consists of a pcie switch with downstream
3167 * bridges leading to the NHI and to the tunnel pci bridges.
3168 *
3169 * This quirk cuts power to the whole chip. Therefore we have to apply it
3170 * during suspend_noirq of the upstream bridge.
3171 *
3172 * Power is automagically restored before resume. No action is needed.
3173 */
3174 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3175 {
3176 acpi_handle bridge, SXIO, SXFP, SXLV;
3177
3178 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc."))
3179 return;
3180 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3181 return;
3182 bridge = ACPI_HANDLE(&dev->dev);
3183 if (!bridge)
3184 return;
3185 /*
3186 * SXIO and SXLV are present only on machines requiring this quirk.
3187 * TB bridges in external devices might have the same device id as those
3188 * on the host, but they will not have the associated ACPI methods. This
3189 * implicitly checks that we are at the right bridge.
3190 */
3191 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3192 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3193 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3194 return;
3195 dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n");
3196
3197 /* magic sequence */
3198 acpi_execute_simple_method(SXIO, NULL, 1);
3199 acpi_execute_simple_method(SXFP, NULL, 0);
3200 msleep(300);
3201 acpi_execute_simple_method(SXLV, NULL, 0);
3202 acpi_execute_simple_method(SXIO, NULL, 0);
3203 acpi_execute_simple_method(SXLV, NULL, 0);
3204 }
3205 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 0x1547,
3206 quirk_apple_poweroff_thunderbolt);
3207
3208 /*
3209 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels.
3210 *
3211 * During suspend the thunderbolt controller is reset and all pci
3212 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3213 * during resume. We have to manually wait for the NHI since there is
3214 * no parent child relationship between the NHI and the tunneled
3215 * bridges.
3216 */
3217 static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3218 {
3219 struct pci_dev *sibling = NULL;
3220 struct pci_dev *nhi = NULL;
3221
3222 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc."))
3223 return;
3224 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3225 return;
3226 /*
3227 * Find the NHI and confirm that we are a bridge on the tb host
3228 * controller and not on a tb endpoint.
3229 */
3230 sibling = pci_get_slot(dev->bus, 0x0);
3231 if (sibling == dev)
3232 goto out; /* we are the downstream bridge to the NHI */
3233 if (!sibling || !sibling->subordinate)
3234 goto out;
3235 nhi = pci_get_slot(sibling->subordinate, 0x0);
3236 if (!nhi)
3237 goto out;
3238 if (nhi->vendor != PCI_VENDOR_ID_INTEL
3239 || (nhi->device != 0x1547 && nhi->device != 0x156c)
3240 || nhi->subsystem_vendor != 0x2222
3241 || nhi->subsystem_device != 0x1111)
3242 goto out;
3243 dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n");
3244 device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3245 out:
3246 pci_dev_put(nhi);
3247 pci_dev_put(sibling);
3248 }
3249 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 0x1547,
3250 quirk_apple_wait_for_thunderbolt);
3251 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 0x156d,
3252 quirk_apple_wait_for_thunderbolt);
3253 #endif
3254
3255 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
3256 struct pci_fixup *end)
3257 {
3258 ktime_t calltime;
3259
3260 for (; f < end; f++)
3261 if ((f->class == (u32) (dev->class >> f->class_shift) ||
3262 f->class == (u32) PCI_ANY_ID) &&
3263 (f->vendor == dev->vendor ||
3264 f->vendor == (u16) PCI_ANY_ID) &&
3265 (f->device == dev->device ||
3266 f->device == (u16) PCI_ANY_ID)) {
3267 calltime = fixup_debug_start(dev, f->hook);
3268 f->hook(dev);
3269 fixup_debug_report(dev, calltime, f->hook);
3270 }
3271 }
3272
3273 extern struct pci_fixup __start_pci_fixups_early[];
3274 extern struct pci_fixup __end_pci_fixups_early[];
3275 extern struct pci_fixup __start_pci_fixups_header[];
3276 extern struct pci_fixup __end_pci_fixups_header[];
3277 extern struct pci_fixup __start_pci_fixups_final[];
3278 extern struct pci_fixup __end_pci_fixups_final[];
3279 extern struct pci_fixup __start_pci_fixups_enable[];
3280 extern struct pci_fixup __end_pci_fixups_enable[];
3281 extern struct pci_fixup __start_pci_fixups_resume[];
3282 extern struct pci_fixup __end_pci_fixups_resume[];
3283 extern struct pci_fixup __start_pci_fixups_resume_early[];
3284 extern struct pci_fixup __end_pci_fixups_resume_early[];
3285 extern struct pci_fixup __start_pci_fixups_suspend[];
3286 extern struct pci_fixup __end_pci_fixups_suspend[];
3287 extern struct pci_fixup __start_pci_fixups_suspend_late[];
3288 extern struct pci_fixup __end_pci_fixups_suspend_late[];
3289
3290 static bool pci_apply_fixup_final_quirks;
3291
3292 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3293 {
3294 struct pci_fixup *start, *end;
3295
3296 switch (pass) {
3297 case pci_fixup_early:
3298 start = __start_pci_fixups_early;
3299 end = __end_pci_fixups_early;
3300 break;
3301
3302 case pci_fixup_header:
3303 start = __start_pci_fixups_header;
3304 end = __end_pci_fixups_header;
3305 break;
3306
3307 case pci_fixup_final:
3308 if (!pci_apply_fixup_final_quirks)
3309 return;
3310 start = __start_pci_fixups_final;
3311 end = __end_pci_fixups_final;
3312 break;
3313
3314 case pci_fixup_enable:
3315 start = __start_pci_fixups_enable;
3316 end = __end_pci_fixups_enable;
3317 break;
3318
3319 case pci_fixup_resume:
3320 start = __start_pci_fixups_resume;
3321 end = __end_pci_fixups_resume;
3322 break;
3323
3324 case pci_fixup_resume_early:
3325 start = __start_pci_fixups_resume_early;
3326 end = __end_pci_fixups_resume_early;
3327 break;
3328
3329 case pci_fixup_suspend:
3330 start = __start_pci_fixups_suspend;
3331 end = __end_pci_fixups_suspend;
3332 break;
3333
3334 case pci_fixup_suspend_late:
3335 start = __start_pci_fixups_suspend_late;
3336 end = __end_pci_fixups_suspend_late;
3337 break;
3338
3339 default:
3340 /* stupid compiler warning, you would think with an enum... */
3341 return;
3342 }
3343 pci_do_fixups(dev, start, end);
3344 }
3345 EXPORT_SYMBOL(pci_fixup_device);
3346
3347
3348 static int __init pci_apply_final_quirks(void)
3349 {
3350 struct pci_dev *dev = NULL;
3351 u8 cls = 0;
3352 u8 tmp;
3353
3354 if (pci_cache_line_size)
3355 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3356 pci_cache_line_size << 2);
3357
3358 pci_apply_fixup_final_quirks = true;
3359 for_each_pci_dev(dev) {
3360 pci_fixup_device(pci_fixup_final, dev);
3361 /*
3362 * If arch hasn't set it explicitly yet, use the CLS
3363 * value shared by all PCI devices. If there's a
3364 * mismatch, fall back to the default value.
3365 */
3366 if (!pci_cache_line_size) {
3367 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3368 if (!cls)
3369 cls = tmp;
3370 if (!tmp || cls == tmp)
3371 continue;
3372
3373 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n",
3374 cls << 2, tmp << 2,
3375 pci_dfl_cache_line_size << 2);
3376 pci_cache_line_size = pci_dfl_cache_line_size;
3377 }
3378 }
3379
3380 if (!pci_cache_line_size) {
3381 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3382 cls << 2, pci_dfl_cache_line_size << 2);
3383 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
3384 }
3385
3386 return 0;
3387 }
3388
3389 fs_initcall_sync(pci_apply_final_quirks);
3390
3391 /*
3392 * Followings are device-specific reset methods which can be used to
3393 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3394 * not available.
3395 */
3396 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3397 {
3398 /*
3399 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3400 *
3401 * The 82599 supports FLR on VFs, but FLR support is reported only
3402 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3403 * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP.
3404 */
3405
3406 if (probe)
3407 return 0;
3408
3409 if (!pci_wait_for_pending_transaction(dev))
3410 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3411
3412 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3413
3414 msleep(100);
3415
3416 return 0;
3417 }
3418
3419 #include "../gpu/drm/i915/i915_reg.h"
3420 #define MSG_CTL 0x45010
3421 #define NSDE_PWR_STATE 0xd0100
3422 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3423
3424 static int reset_ivb_igd(struct pci_dev *dev, int probe)
3425 {
3426 void __iomem *mmio_base;
3427 unsigned long timeout;
3428 u32 val;
3429
3430 if (probe)
3431 return 0;
3432
3433 mmio_base = pci_iomap(dev, 0, 0);
3434 if (!mmio_base)
3435 return -ENOMEM;
3436
3437 iowrite32(0x00000002, mmio_base + MSG_CTL);
3438
3439 /*
3440 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3441 * driver loaded sets the right bits. However, this's a reset and
3442 * the bits have been set by i915 previously, so we clobber
3443 * SOUTH_CHICKEN2 register directly here.
3444 */
3445 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3446
3447 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3448 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3449
3450 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3451 do {
3452 val = ioread32(mmio_base + PCH_PP_STATUS);
3453 if ((val & 0xb0000000) == 0)
3454 goto reset_complete;
3455 msleep(10);
3456 } while (time_before(jiffies, timeout));
3457 dev_warn(&dev->dev, "timeout during reset\n");
3458
3459 reset_complete:
3460 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3461
3462 pci_iounmap(dev, mmio_base);
3463 return 0;
3464 }
3465
3466 /*
3467 * Device-specific reset method for Chelsio T4-based adapters.
3468 */
3469 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3470 {
3471 u16 old_command;
3472 u16 msix_flags;
3473
3474 /*
3475 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3476 * that we have no device-specific reset method.
3477 */
3478 if ((dev->device & 0xf000) != 0x4000)
3479 return -ENOTTY;
3480
3481 /*
3482 * If this is the "probe" phase, return 0 indicating that we can
3483 * reset this device.
3484 */
3485 if (probe)
3486 return 0;
3487
3488 /*
3489 * T4 can wedge if there are DMAs in flight within the chip and Bus
3490 * Master has been disabled. We need to have it on till the Function
3491 * Level Reset completes. (BUS_MASTER is disabled in
3492 * pci_reset_function()).
3493 */
3494 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3495 pci_write_config_word(dev, PCI_COMMAND,
3496 old_command | PCI_COMMAND_MASTER);
3497
3498 /*
3499 * Perform the actual device function reset, saving and restoring
3500 * configuration information around the reset.
3501 */
3502 pci_save_state(dev);
3503
3504 /*
3505 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3506 * are disabled when an MSI-X interrupt message needs to be delivered.
3507 * So we briefly re-enable MSI-X interrupts for the duration of the
3508 * FLR. The pci_restore_state() below will restore the original
3509 * MSI-X state.
3510 */
3511 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3512 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3513 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3514 msix_flags |
3515 PCI_MSIX_FLAGS_ENABLE |
3516 PCI_MSIX_FLAGS_MASKALL);
3517
3518 /*
3519 * Start of pcie_flr() code sequence. This reset code is a copy of
3520 * the guts of pcie_flr() because that's not an exported function.
3521 */
3522
3523 if (!pci_wait_for_pending_transaction(dev))
3524 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3525
3526 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3527 msleep(100);
3528
3529 /*
3530 * End of pcie_flr() code sequence.
3531 */
3532
3533 /*
3534 * Restore the configuration information (BAR values, etc.) including
3535 * the original PCI Configuration Space Command word, and return
3536 * success.
3537 */
3538 pci_restore_state(dev);
3539 pci_write_config_word(dev, PCI_COMMAND, old_command);
3540 return 0;
3541 }
3542
3543 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3544 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3545 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3546
3547 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3548 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3549 reset_intel_82599_sfp_virtfn },
3550 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3551 reset_ivb_igd },
3552 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3553 reset_ivb_igd },
3554 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3555 reset_chelsio_generic_dev },
3556 { 0 }
3557 };
3558
3559 /*
3560 * These device-specific reset methods are here rather than in a driver
3561 * because when a host assigns a device to a guest VM, the host may need
3562 * to reset the device but probably doesn't have a driver for it.
3563 */
3564 int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3565 {
3566 const struct pci_dev_reset_methods *i;
3567
3568 for (i = pci_dev_reset_methods; i->reset; i++) {
3569 if ((i->vendor == dev->vendor ||
3570 i->vendor == (u16)PCI_ANY_ID) &&
3571 (i->device == dev->device ||
3572 i->device == (u16)PCI_ANY_ID))
3573 return i->reset(dev, probe);
3574 }
3575
3576 return -ENOTTY;
3577 }
3578
3579 static void quirk_dma_func0_alias(struct pci_dev *dev)
3580 {
3581 if (PCI_FUNC(dev->devfn) != 0) {
3582 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0);
3583 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
3584 }
3585 }
3586
3587 /*
3588 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3589 *
3590 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3591 */
3592 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
3593 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
3594
3595 static void quirk_dma_func1_alias(struct pci_dev *dev)
3596 {
3597 if (PCI_FUNC(dev->devfn) != 1) {
3598 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 1);
3599 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
3600 }
3601 }
3602
3603 /*
3604 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
3605 * SKUs function 1 is present and is a legacy IDE controller, in other
3606 * SKUs this function is not present, making this a ghost requester.
3607 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
3608 */
3609 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
3610 quirk_dma_func1_alias);
3611 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
3612 quirk_dma_func1_alias);
3613 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3614 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
3615 quirk_dma_func1_alias);
3616 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
3617 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
3618 quirk_dma_func1_alias);
3619 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
3620 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
3621 quirk_dma_func1_alias);
3622 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
3623 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
3624 quirk_dma_func1_alias);
3625 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
3626 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
3627 quirk_dma_func1_alias);
3628 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
3629 quirk_dma_func1_alias);
3630 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
3631 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
3632 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
3633 quirk_dma_func1_alias);
3634
3635 /*
3636 * Some devices DMA with the wrong devfn, not just the wrong function.
3637 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
3638 * the alias is "fixed" and independent of the device devfn.
3639 *
3640 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
3641 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
3642 * single device on the secondary bus. In reality, the single exposed
3643 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
3644 * that provides a bridge to the internal bus of the I/O processor. The
3645 * controller supports private devices, which can be hidden from PCI config
3646 * space. In the case of the Adaptec 3405, a private device at 01.0
3647 * appears to be the DMA engine, which therefore needs to become a DMA
3648 * alias for the device.
3649 */
3650 static const struct pci_device_id fixed_dma_alias_tbl[] = {
3651 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3652 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
3653 .driver_data = PCI_DEVFN(1, 0) },
3654 { 0 }
3655 };
3656
3657 static void quirk_fixed_dma_alias(struct pci_dev *dev)
3658 {
3659 const struct pci_device_id *id;
3660
3661 id = pci_match_id(fixed_dma_alias_tbl, dev);
3662 if (id) {
3663 dev->dma_alias_devfn = id->driver_data;
3664 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
3665 dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n",
3666 PCI_SLOT(dev->dma_alias_devfn),
3667 PCI_FUNC(dev->dma_alias_devfn));
3668 }
3669 }
3670
3671 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
3672
3673 /*
3674 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
3675 * using the wrong DMA alias for the device. Some of these devices can be
3676 * used as either forward or reverse bridges, so we need to test whether the
3677 * device is operating in the correct mode. We could probably apply this
3678 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
3679 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
3680 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
3681 */
3682 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
3683 {
3684 if (!pci_is_root_bus(pdev->bus) &&
3685 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3686 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
3687 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
3688 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
3689 }
3690 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
3691 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
3692 quirk_use_pcie_bridge_dma_alias);
3693 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
3694 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
3695 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
3696 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
3697 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
3698 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
3699
3700 /*
3701 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
3702 * class code. Fix it.
3703 */
3704 static void quirk_tw686x_class(struct pci_dev *pdev)
3705 {
3706 u32 class = pdev->class;
3707
3708 /* Use "Multimedia controller" class */
3709 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
3710 dev_info(&pdev->dev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
3711 class, pdev->class);
3712 }
3713 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
3714 quirk_tw686x_class);
3715 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
3716 quirk_tw686x_class);
3717 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
3718 quirk_tw686x_class);
3719 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
3720 quirk_tw686x_class);
3721
3722 /*
3723 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
3724 * values for the Attribute as were supplied in the header of the
3725 * corresponding Request, except as explicitly allowed when IDO is used."
3726 *
3727 * If a non-compliant device generates a completion with a different
3728 * attribute than the request, the receiver may accept it (which itself
3729 * seems non-compliant based on sec 2.3.2), or it may handle it as a
3730 * Malformed TLP or an Unexpected Completion, which will probably lead to a
3731 * device access timeout.
3732 *
3733 * If the non-compliant device generates completions with zero attributes
3734 * (instead of copying the attributes from the request), we can work around
3735 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
3736 * upstream devices so they always generate requests with zero attributes.
3737 *
3738 * This affects other devices under the same Root Port, but since these
3739 * attributes are performance hints, there should be no functional problem.
3740 *
3741 * Note that Configuration Space accesses are never supposed to have TLP
3742 * Attributes, so we're safe waiting till after any Configuration Space
3743 * accesses to do the Root Port fixup.
3744 */
3745 static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
3746 {
3747 struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
3748
3749 if (!root_port) {
3750 dev_warn(&pdev->dev, "PCIe Completion erratum may cause device errors\n");
3751 return;
3752 }
3753
3754 dev_info(&root_port->dev, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
3755 dev_name(&pdev->dev));
3756 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
3757 PCI_EXP_DEVCTL_RELAX_EN |
3758 PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
3759 }
3760
3761 /*
3762 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
3763 * Completion it generates.
3764 */
3765 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
3766 {
3767 /*
3768 * This mask/compare operation selects for Physical Function 4 on a
3769 * T5. We only need to fix up the Root Port once for any of the
3770 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
3771 * 0x54xx so we use that one,
3772 */
3773 if ((pdev->device & 0xff00) == 0x5400)
3774 quirk_disable_root_port_attributes(pdev);
3775 }
3776 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3777 quirk_chelsio_T5_disable_root_port_attributes);
3778
3779 /*
3780 * AMD has indicated that the devices below do not support peer-to-peer
3781 * in any system where they are found in the southbridge with an AMD
3782 * IOMMU in the system. Multifunction devices that do not support
3783 * peer-to-peer between functions can claim to support a subset of ACS.
3784 * Such devices effectively enable request redirect (RR) and completion
3785 * redirect (CR) since all transactions are redirected to the upstream
3786 * root complex.
3787 *
3788 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
3789 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
3790 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
3791 *
3792 * 1002:4385 SBx00 SMBus Controller
3793 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
3794 * 1002:4383 SBx00 Azalia (Intel HDA)
3795 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
3796 * 1002:4384 SBx00 PCI to PCI Bridge
3797 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
3798 *
3799 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
3800 *
3801 * 1022:780f [AMD] FCH PCI Bridge
3802 * 1022:7809 [AMD] FCH USB OHCI Controller
3803 */
3804 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
3805 {
3806 #ifdef CONFIG_ACPI
3807 struct acpi_table_header *header = NULL;
3808 acpi_status status;
3809
3810 /* Targeting multifunction devices on the SB (appears on root bus) */
3811 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
3812 return -ENODEV;
3813
3814 /* The IVRS table describes the AMD IOMMU */
3815 status = acpi_get_table("IVRS", 0, &header);
3816 if (ACPI_FAILURE(status))
3817 return -ENODEV;
3818
3819 /* Filter out flags not applicable to multifunction */
3820 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
3821
3822 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
3823 #else
3824 return -ENODEV;
3825 #endif
3826 }
3827
3828 /*
3829 * Many Intel PCH root ports do provide ACS-like features to disable peer
3830 * transactions and validate bus numbers in requests, but do not provide an
3831 * actual PCIe ACS capability. This is the list of device IDs known to fall
3832 * into that category as provided by Intel in Red Hat bugzilla 1037684.
3833 */
3834 static const u16 pci_quirk_intel_pch_acs_ids[] = {
3835 /* Ibexpeak PCH */
3836 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
3837 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
3838 /* Cougarpoint PCH */
3839 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
3840 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
3841 /* Pantherpoint PCH */
3842 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
3843 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
3844 /* Lynxpoint-H PCH */
3845 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
3846 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
3847 /* Lynxpoint-LP PCH */
3848 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
3849 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
3850 /* Wildcat PCH */
3851 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
3852 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
3853 /* Patsburg (X79) PCH */
3854 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
3855 /* Wellsburg (X99) PCH */
3856 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
3857 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
3858 /* Lynx Point (9 series) PCH */
3859 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
3860 };
3861
3862 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
3863 {
3864 int i;
3865
3866 /* Filter out a few obvious non-matches first */
3867 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
3868 return false;
3869
3870 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
3871 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
3872 return true;
3873
3874 return false;
3875 }
3876
3877 #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
3878
3879 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
3880 {
3881 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
3882 INTEL_PCH_ACS_FLAGS : 0;
3883
3884 if (!pci_quirk_intel_pch_acs_match(dev))
3885 return -ENOTTY;
3886
3887 return acs_flags & ~flags ? 0 : 1;
3888 }
3889
3890 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
3891 {
3892 /*
3893 * SV, TB, and UF are not relevant to multifunction endpoints.
3894 *
3895 * Multifunction devices are only required to implement RR, CR, and DT
3896 * in their ACS capability if they support peer-to-peer transactions.
3897 * Devices matching this quirk have been verified by the vendor to not
3898 * perform peer-to-peer with other functions, allowing us to mask out
3899 * these bits as if they were unimplemented in the ACS capability.
3900 */
3901 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
3902 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
3903
3904 return acs_flags ? 0 : 1;
3905 }
3906
3907 static const struct pci_dev_acs_enabled {
3908 u16 vendor;
3909 u16 device;
3910 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
3911 } pci_dev_acs_enabled[] = {
3912 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
3913 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
3914 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
3915 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
3916 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
3917 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
3918 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
3919 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
3920 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
3921 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
3922 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
3923 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
3924 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
3925 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
3926 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
3927 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
3928 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
3929 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
3930 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
3931 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
3932 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
3933 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
3934 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
3935 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
3936 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
3937 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
3938 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
3939 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
3940 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
3941 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
3942 /* 82580 */
3943 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
3944 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
3945 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
3946 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
3947 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
3948 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
3949 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
3950 /* 82576 */
3951 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
3952 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
3953 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
3954 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
3955 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
3956 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
3957 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
3958 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
3959 /* 82575 */
3960 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
3961 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
3962 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
3963 /* I350 */
3964 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
3965 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
3966 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
3967 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
3968 /* 82571 (Quads omitted due to non-ACS switch) */
3969 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
3970 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
3971 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
3972 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
3973 /* I219 */
3974 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
3975 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
3976 /* Intel PCH root ports */
3977 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
3978 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
3979 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
3980 { 0 }
3981 };
3982
3983 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
3984 {
3985 const struct pci_dev_acs_enabled *i;
3986 int ret;
3987
3988 /*
3989 * Allow devices that do not expose standard PCIe ACS capabilities
3990 * or control to indicate their support here. Multi-function express
3991 * devices which do not allow internal peer-to-peer between functions,
3992 * but do not implement PCIe ACS may wish to return true here.
3993 */
3994 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
3995 if ((i->vendor == dev->vendor ||
3996 i->vendor == (u16)PCI_ANY_ID) &&
3997 (i->device == dev->device ||
3998 i->device == (u16)PCI_ANY_ID)) {
3999 ret = i->acs_enabled(dev, acs_flags);
4000 if (ret >= 0)
4001 return ret;
4002 }
4003 }
4004
4005 return -ENOTTY;
4006 }
4007
4008 /* Config space offset of Root Complex Base Address register */
4009 #define INTEL_LPC_RCBA_REG 0xf0
4010 /* 31:14 RCBA address */
4011 #define INTEL_LPC_RCBA_MASK 0xffffc000
4012 /* RCBA Enable */
4013 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
4014
4015 /* Backbone Scratch Pad Register */
4016 #define INTEL_BSPR_REG 0x1104
4017 /* Backbone Peer Non-Posted Disable */
4018 #define INTEL_BSPR_REG_BPNPD (1 << 8)
4019 /* Backbone Peer Posted Disable */
4020 #define INTEL_BSPR_REG_BPPD (1 << 9)
4021
4022 /* Upstream Peer Decode Configuration Register */
4023 #define INTEL_UPDCR_REG 0x1114
4024 /* 5:0 Peer Decode Enable bits */
4025 #define INTEL_UPDCR_REG_MASK 0x3f
4026
4027 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4028 {
4029 u32 rcba, bspr, updcr;
4030 void __iomem *rcba_mem;
4031
4032 /*
4033 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4034 * are D28:F* and therefore get probed before LPC, thus we can't
4035 * use pci_get_slot/pci_read_config_dword here.
4036 */
4037 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4038 INTEL_LPC_RCBA_REG, &rcba);
4039 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
4040 return -EINVAL;
4041
4042 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
4043 PAGE_ALIGN(INTEL_UPDCR_REG));
4044 if (!rcba_mem)
4045 return -ENOMEM;
4046
4047 /*
4048 * The BSPR can disallow peer cycles, but it's set by soft strap and
4049 * therefore read-only. If both posted and non-posted peer cycles are
4050 * disallowed, we're ok. If either are allowed, then we need to use
4051 * the UPDCR to disable peer decodes for each port. This provides the
4052 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4053 */
4054 bspr = readl(rcba_mem + INTEL_BSPR_REG);
4055 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
4056 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
4057 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
4058 if (updcr & INTEL_UPDCR_REG_MASK) {
4059 dev_info(&dev->dev, "Disabling UPDCR peer decodes\n");
4060 updcr &= ~INTEL_UPDCR_REG_MASK;
4061 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
4062 }
4063 }
4064
4065 iounmap(rcba_mem);
4066 return 0;
4067 }
4068
4069 /* Miscellaneous Port Configuration register */
4070 #define INTEL_MPC_REG 0xd8
4071 /* MPC: Invalid Receive Bus Number Check Enable */
4072 #define INTEL_MPC_REG_IRBNCE (1 << 26)
4073
4074 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
4075 {
4076 u32 mpc;
4077
4078 /*
4079 * When enabled, the IRBNCE bit of the MPC register enables the
4080 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4081 * ensures that requester IDs fall within the bus number range
4082 * of the bridge. Enable if not already.
4083 */
4084 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
4085 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
4086 dev_info(&dev->dev, "Enabling MPC IRBNCE\n");
4087 mpc |= INTEL_MPC_REG_IRBNCE;
4088 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
4089 }
4090 }
4091
4092 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4093 {
4094 if (!pci_quirk_intel_pch_acs_match(dev))
4095 return -ENOTTY;
4096
4097 if (pci_quirk_enable_intel_lpc_acs(dev)) {
4098 dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n");
4099 return 0;
4100 }
4101
4102 pci_quirk_enable_intel_rp_mpc_acs(dev);
4103
4104 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4105
4106 dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n");
4107
4108 return 0;
4109 }
4110
4111 static const struct pci_dev_enable_acs {
4112 u16 vendor;
4113 u16 device;
4114 int (*enable_acs)(struct pci_dev *dev);
4115 } pci_dev_enable_acs[] = {
4116 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs },
4117 { 0 }
4118 };
4119
4120 void pci_dev_specific_enable_acs(struct pci_dev *dev)
4121 {
4122 const struct pci_dev_enable_acs *i;
4123 int ret;
4124
4125 for (i = pci_dev_enable_acs; i->enable_acs; i++) {
4126 if ((i->vendor == dev->vendor ||
4127 i->vendor == (u16)PCI_ANY_ID) &&
4128 (i->device == dev->device ||
4129 i->device == (u16)PCI_ANY_ID)) {
4130 ret = i->enable_acs(dev);
4131 if (ret >= 0)
4132 return;
4133 }
4134 }
4135 }
4136
4137 /*
4138 * The PCI capabilities list for Intel DH895xCC VFs (device id 0x0443) with
4139 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
4140 * Next Capability pointer in the MSI Capability Structure should point to
4141 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
4142 * the list.
4143 */
4144 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
4145 {
4146 int pos, i = 0;
4147 u8 next_cap;
4148 u16 reg16, *cap;
4149 struct pci_cap_saved_state *state;
4150
4151 /* Bail if the hardware bug is fixed */
4152 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
4153 return;
4154
4155 /* Bail if MSI Capability Structure is not found for some reason */
4156 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
4157 if (!pos)
4158 return;
4159
4160 /*
4161 * Bail if Next Capability pointer in the MSI Capability Structure
4162 * is not the expected incorrect 0x00.
4163 */
4164 pci_read_config_byte(pdev, pos + 1, &next_cap);
4165 if (next_cap)
4166 return;
4167
4168 /*
4169 * PCIe Capability Structure is expected to be at 0x50 and should
4170 * terminate the list (Next Capability pointer is 0x00). Verify
4171 * Capability Id and Next Capability pointer is as expected.
4172 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
4173 * to correctly set kernel data structures which have already been
4174 * set incorrectly due to the hardware bug.
4175 */
4176 pos = 0x50;
4177 pci_read_config_word(pdev, pos, &reg16);
4178 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
4179 u32 status;
4180 #ifndef PCI_EXP_SAVE_REGS
4181 #define PCI_EXP_SAVE_REGS 7
4182 #endif
4183 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
4184
4185 pdev->pcie_cap = pos;
4186 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
4187 pdev->pcie_flags_reg = reg16;
4188 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
4189 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
4190
4191 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
4192 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
4193 PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
4194 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
4195
4196 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
4197 return;
4198
4199 /*
4200 * Save PCIE cap
4201 */
4202 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
4203 if (!state)
4204 return;
4205
4206 state->cap.cap_nr = PCI_CAP_ID_EXP;
4207 state->cap.cap_extended = 0;
4208 state->cap.size = size;
4209 cap = (u16 *)&state->cap.data[0];
4210 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
4211 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
4212 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
4213 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
4214 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
4215 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
4216 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
4217 hlist_add_head(&state->next, &pdev->saved_cap_space);
4218 }
4219 }
4220 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
Linux kernel - Deliverables
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