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Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6
[deliverable/linux.git] / drivers / pci / quirks.c
1 /*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/acpi.h>
24 #include "pci.h"
25
26 /* The Mellanox Tavor device gives false positive parity errors
27 * Mark this device with a broken_parity_status, to allow
28 * PCI scanning code to "skip" this now blacklisted device.
29 */
30 static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
31 {
32 dev->broken_parity_status = 1; /* This device gives false positives */
33 }
34 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
35 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
36
37 /* Deal with broken BIOS'es that neglect to enable passive release,
38 which can cause problems in combination with the 82441FX/PPro MTRRs */
39 static void quirk_passive_release(struct pci_dev *dev)
40 {
41 struct pci_dev *d = NULL;
42 unsigned char dlc;
43
44 /* We have to make sure a particular bit is set in the PIIX3
45 ISA bridge, so we have to go out and find it. */
46 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
47 pci_read_config_byte(d, 0x82, &dlc);
48 if (!(dlc & 1<<1)) {
49 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d));
50 dlc |= 1<<1;
51 pci_write_config_byte(d, 0x82, dlc);
52 }
53 }
54 }
55 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release );
56 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release );
57
58 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
59 but VIA don't answer queries. If you happen to have good contacts at VIA
60 ask them for me please -- Alan
61
62 This appears to be BIOS not version dependent. So presumably there is a
63 chipset level fix */
64 int isa_dma_bridge_buggy;
65 EXPORT_SYMBOL(isa_dma_bridge_buggy);
66
67 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
68 {
69 if (!isa_dma_bridge_buggy) {
70 isa_dma_bridge_buggy=1;
71 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
72 }
73 }
74 /*
75 * Its not totally clear which chipsets are the problematic ones
76 * We know 82C586 and 82C596 variants are affected.
77 */
78 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs );
79 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs );
80 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs );
81 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs );
82 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs );
83 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs );
84 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs );
85
86 int pci_pci_problems;
87 EXPORT_SYMBOL(pci_pci_problems);
88
89 /*
90 * Chipsets where PCI->PCI transfers vanish or hang
91 */
92 static void __devinit quirk_nopcipci(struct pci_dev *dev)
93 {
94 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
95 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
96 pci_pci_problems |= PCIPCI_FAIL;
97 }
98 }
99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci );
100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci );
101
102 static void __devinit quirk_nopciamd(struct pci_dev *dev)
103 {
104 u8 rev;
105 pci_read_config_byte(dev, 0x08, &rev);
106 if (rev == 0x13) {
107 /* Erratum 24 */
108 printk(KERN_INFO "Chipset erratum: Disabling direct PCI/AGP transfers.\n");
109 pci_pci_problems |= PCIAGP_FAIL;
110 }
111 }
112 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd );
113
114 /*
115 * Triton requires workarounds to be used by the drivers
116 */
117 static void __devinit quirk_triton(struct pci_dev *dev)
118 {
119 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
120 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
121 pci_pci_problems |= PCIPCI_TRITON;
122 }
123 }
124 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton );
125 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton );
126 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton );
127 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton );
128
129 /*
130 * VIA Apollo KT133 needs PCI latency patch
131 * Made according to a windows driver based patch by George E. Breese
132 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
133 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
134 * the info on which Mr Breese based his work.
135 *
136 * Updated based on further information from the site and also on
137 * information provided by VIA
138 */
139 static void quirk_vialatency(struct pci_dev *dev)
140 {
141 struct pci_dev *p;
142 u8 rev;
143 u8 busarb;
144 /* Ok we have a potential problem chipset here. Now see if we have
145 a buggy southbridge */
146
147 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
148 if (p!=NULL) {
149 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
150 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
151 /* Check for buggy part revisions */
152 if (rev < 0x40 || rev > 0x42)
153 goto exit;
154 } else {
155 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
156 if (p==NULL) /* No problem parts */
157 goto exit;
158 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
159 /* Check for buggy part revisions */
160 if (rev < 0x10 || rev > 0x12)
161 goto exit;
162 }
163
164 /*
165 * Ok we have the problem. Now set the PCI master grant to
166 * occur every master grant. The apparent bug is that under high
167 * PCI load (quite common in Linux of course) you can get data
168 * loss when the CPU is held off the bus for 3 bus master requests
169 * This happens to include the IDE controllers....
170 *
171 * VIA only apply this fix when an SB Live! is present but under
172 * both Linux and Windows this isnt enough, and we have seen
173 * corruption without SB Live! but with things like 3 UDMA IDE
174 * controllers. So we ignore that bit of the VIA recommendation..
175 */
176
177 pci_read_config_byte(dev, 0x76, &busarb);
178 /* Set bit 4 and bi 5 of byte 76 to 0x01
179 "Master priority rotation on every PCI master grant */
180 busarb &= ~(1<<5);
181 busarb |= (1<<4);
182 pci_write_config_byte(dev, 0x76, busarb);
183 printk(KERN_INFO "Applying VIA southbridge workaround.\n");
184 exit:
185 pci_dev_put(p);
186 }
187 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency );
188 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency );
189 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency );
190 /* Must restore this on a resume from RAM */
191 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency );
192 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency );
193 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency );
194
195 /*
196 * VIA Apollo VP3 needs ETBF on BT848/878
197 */
198 static void __devinit quirk_viaetbf(struct pci_dev *dev)
199 {
200 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
201 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
202 pci_pci_problems |= PCIPCI_VIAETBF;
203 }
204 }
205 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf );
206
207 static void __devinit quirk_vsfx(struct pci_dev *dev)
208 {
209 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
210 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
211 pci_pci_problems |= PCIPCI_VSFX;
212 }
213 }
214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx );
215
216 /*
217 * Ali Magik requires workarounds to be used by the drivers
218 * that DMA to AGP space. Latency must be set to 0xA and triton
219 * workaround applied too
220 * [Info kindly provided by ALi]
221 */
222 static void __init quirk_alimagik(struct pci_dev *dev)
223 {
224 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
225 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
226 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
227 }
228 }
229 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik );
230 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik );
231
232 /*
233 * Natoma has some interesting boundary conditions with Zoran stuff
234 * at least
235 */
236 static void __devinit quirk_natoma(struct pci_dev *dev)
237 {
238 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
239 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
240 pci_pci_problems |= PCIPCI_NATOMA;
241 }
242 }
243 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma );
244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma );
245 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma );
246 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma );
247 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma );
248 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma );
249
250 /*
251 * This chip can cause PCI parity errors if config register 0xA0 is read
252 * while DMAs are occurring.
253 */
254 static void __devinit quirk_citrine(struct pci_dev *dev)
255 {
256 dev->cfg_size = 0xA0;
257 }
258 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine );
259
260 /*
261 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
262 * If it's needed, re-allocate the region.
263 */
264 static void __devinit quirk_s3_64M(struct pci_dev *dev)
265 {
266 struct resource *r = &dev->resource[0];
267
268 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
269 r->start = 0;
270 r->end = 0x3ffffff;
271 }
272 }
273 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M );
274 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M );
275
276 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
277 unsigned size, int nr, const char *name)
278 {
279 region &= ~(size-1);
280 if (region) {
281 struct pci_bus_region bus_region;
282 struct resource *res = dev->resource + nr;
283
284 res->name = pci_name(dev);
285 res->start = region;
286 res->end = region + size - 1;
287 res->flags = IORESOURCE_IO;
288
289 /* Convert from PCI bus to resource space. */
290 bus_region.start = res->start;
291 bus_region.end = res->end;
292 pcibios_bus_to_resource(dev, res, &bus_region);
293
294 pci_claim_resource(dev, nr);
295 printk("PCI quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
296 }
297 }
298
299 /*
300 * ATI Northbridge setups MCE the processor if you even
301 * read somewhere between 0x3b0->0x3bb or read 0x3d3
302 */
303 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
304 {
305 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
306 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
307 request_region(0x3b0, 0x0C, "RadeonIGP");
308 request_region(0x3d3, 0x01, "RadeonIGP");
309 }
310 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce );
311
312 /*
313 * Let's make the southbridge information explicit instead
314 * of having to worry about people probing the ACPI areas,
315 * for example.. (Yes, it happens, and if you read the wrong
316 * ACPI register it will put the machine to sleep with no
317 * way of waking it up again. Bummer).
318 *
319 * ALI M7101: Two IO regions pointed to by words at
320 * 0xE0 (64 bytes of ACPI registers)
321 * 0xE2 (32 bytes of SMB registers)
322 */
323 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
324 {
325 u16 region;
326
327 pci_read_config_word(dev, 0xE0, &region);
328 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
329 pci_read_config_word(dev, 0xE2, &region);
330 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
331 }
332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi );
333
334 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
335 {
336 u32 devres;
337 u32 mask, size, base;
338
339 pci_read_config_dword(dev, port, &devres);
340 if ((devres & enable) != enable)
341 return;
342 mask = (devres >> 16) & 15;
343 base = devres & 0xffff;
344 size = 16;
345 for (;;) {
346 unsigned bit = size >> 1;
347 if ((bit & mask) == bit)
348 break;
349 size = bit;
350 }
351 /*
352 * For now we only print it out. Eventually we'll want to
353 * reserve it (at least if it's in the 0x1000+ range), but
354 * let's get enough confirmation reports first.
355 */
356 base &= -size;
357 printk("%s PIO at %04x-%04x\n", name, base, base + size - 1);
358 }
359
360 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
361 {
362 u32 devres;
363 u32 mask, size, base;
364
365 pci_read_config_dword(dev, port, &devres);
366 if ((devres & enable) != enable)
367 return;
368 base = devres & 0xffff0000;
369 mask = (devres & 0x3f) << 16;
370 size = 128 << 16;
371 for (;;) {
372 unsigned bit = size >> 1;
373 if ((bit & mask) == bit)
374 break;
375 size = bit;
376 }
377 /*
378 * For now we only print it out. Eventually we'll want to
379 * reserve it, but let's get enough confirmation reports first.
380 */
381 base &= -size;
382 printk("%s MMIO at %04x-%04x\n", name, base, base + size - 1);
383 }
384
385 /*
386 * PIIX4 ACPI: Two IO regions pointed to by longwords at
387 * 0x40 (64 bytes of ACPI registers)
388 * 0x90 (16 bytes of SMB registers)
389 * and a few strange programmable PIIX4 device resources.
390 */
391 static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
392 {
393 u32 region, res_a;
394
395 pci_read_config_dword(dev, 0x40, &region);
396 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
397 pci_read_config_dword(dev, 0x90, &region);
398 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
399
400 /* Device resource A has enables for some of the other ones */
401 pci_read_config_dword(dev, 0x5c, &res_a);
402
403 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
404 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
405
406 /* Device resource D is just bitfields for static resources */
407
408 /* Device 12 enabled? */
409 if (res_a & (1 << 29)) {
410 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
411 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
412 }
413 /* Device 13 enabled? */
414 if (res_a & (1 << 30)) {
415 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
416 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
417 }
418 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
419 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
420 }
421 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi );
422 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi );
423
424 /*
425 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
426 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
427 * 0x58 (64 bytes of GPIO I/O space)
428 */
429 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
430 {
431 u32 region;
432
433 pci_read_config_dword(dev, 0x40, &region);
434 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
435
436 pci_read_config_dword(dev, 0x58, &region);
437 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
438 }
439 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi );
440 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi );
441 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi );
442 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi );
443 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi );
444 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi );
445 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi );
446 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi );
447 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi );
448 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi );
449
450 static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
451 {
452 u32 region;
453
454 pci_read_config_dword(dev, 0x40, &region);
455 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
456
457 pci_read_config_dword(dev, 0x48, &region);
458 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
459 }
460 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi );
461 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi );
462 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich6_lpc_acpi );
463 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich6_lpc_acpi );
464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich6_lpc_acpi );
465 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich6_lpc_acpi );
466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich6_lpc_acpi );
467 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich6_lpc_acpi );
468
469 /*
470 * VIA ACPI: One IO region pointed to by longword at
471 * 0x48 or 0x20 (256 bytes of ACPI registers)
472 */
473 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
474 {
475 u32 region;
476
477 if (dev->revision & 0x10) {
478 pci_read_config_dword(dev, 0x48, &region);
479 region &= PCI_BASE_ADDRESS_IO_MASK;
480 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
481 }
482 }
483 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi );
484
485 /*
486 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
487 * 0x48 (256 bytes of ACPI registers)
488 * 0x70 (128 bytes of hardware monitoring register)
489 * 0x90 (16 bytes of SMB registers)
490 */
491 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
492 {
493 u16 hm;
494 u32 smb;
495
496 quirk_vt82c586_acpi(dev);
497
498 pci_read_config_word(dev, 0x70, &hm);
499 hm &= PCI_BASE_ADDRESS_IO_MASK;
500 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
501
502 pci_read_config_dword(dev, 0x90, &smb);
503 smb &= PCI_BASE_ADDRESS_IO_MASK;
504 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
505 }
506 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi );
507
508 /*
509 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
510 * 0x88 (128 bytes of power management registers)
511 * 0xd0 (16 bytes of SMB registers)
512 */
513 static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
514 {
515 u16 pm, smb;
516
517 pci_read_config_word(dev, 0x88, &pm);
518 pm &= PCI_BASE_ADDRESS_IO_MASK;
519 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
520
521 pci_read_config_word(dev, 0xd0, &smb);
522 smb &= PCI_BASE_ADDRESS_IO_MASK;
523 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
524 }
525 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
526
527
528 #ifdef CONFIG_X86_IO_APIC
529
530 #include <asm/io_apic.h>
531
532 /*
533 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
534 * devices to the external APIC.
535 *
536 * TODO: When we have device-specific interrupt routers,
537 * this code will go away from quirks.
538 */
539 static void quirk_via_ioapic(struct pci_dev *dev)
540 {
541 u8 tmp;
542
543 if (nr_ioapics < 1)
544 tmp = 0; /* nothing routed to external APIC */
545 else
546 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
547
548 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
549 tmp == 0 ? "Disa" : "Ena");
550
551 /* Offset 0x58: External APIC IRQ output control */
552 pci_write_config_byte (dev, 0x58, tmp);
553 }
554 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic );
555 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic );
556
557 /*
558 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
559 * This leads to doubled level interrupt rates.
560 * Set this bit to get rid of cycle wastage.
561 * Otherwise uncritical.
562 */
563 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
564 {
565 u8 misc_control2;
566 #define BYPASS_APIC_DEASSERT 8
567
568 pci_read_config_byte(dev, 0x5B, &misc_control2);
569 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
570 printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n");
571 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
572 }
573 }
574 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
575 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
576
577 /*
578 * The AMD io apic can hang the box when an apic irq is masked.
579 * We check all revs >= B0 (yet not in the pre production!) as the bug
580 * is currently marked NoFix
581 *
582 * We have multiple reports of hangs with this chipset that went away with
583 * noapic specified. For the moment we assume it's the erratum. We may be wrong
584 * of course. However the advice is demonstrably good even if so..
585 */
586 static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
587 {
588 if (dev->revision >= 0x02) {
589 printk(KERN_WARNING "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
590 printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
591 }
592 }
593 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic );
594
595 static void __init quirk_ioapic_rmw(struct pci_dev *dev)
596 {
597 if (dev->devfn == 0 && dev->bus->number == 0)
598 sis_apic_bug = 1;
599 }
600 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw );
601
602 #define AMD8131_revA0 0x01
603 #define AMD8131_revB0 0x11
604 #define AMD8131_MISC 0x40
605 #define AMD8131_NIOAMODE_BIT 0
606 static void quirk_amd_8131_ioapic(struct pci_dev *dev)
607 {
608 unsigned char tmp;
609
610 if (nr_ioapics == 0)
611 return;
612
613 if (dev->revision == AMD8131_revA0 || dev->revision == AMD8131_revB0) {
614 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
615 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
616 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
617 pci_write_config_byte( dev, AMD8131_MISC, tmp);
618 }
619 }
620 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
621 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
622 #endif /* CONFIG_X86_IO_APIC */
623
624 /*
625 * Some settings of MMRBC can lead to data corruption so block changes.
626 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
627 */
628 static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
629 {
630 if (dev->subordinate && dev->revision <= 0x12) {
631 printk(KERN_INFO "AMD8131 rev %x detected, disabling PCI-X "
632 "MMRBC\n", dev->revision);
633 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
634 }
635 }
636 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
637
638 /*
639 * FIXME: it is questionable that quirk_via_acpi
640 * is needed. It shows up as an ISA bridge, and does not
641 * support the PCI_INTERRUPT_LINE register at all. Therefore
642 * it seems like setting the pci_dev's 'irq' to the
643 * value of the ACPI SCI interrupt is only done for convenience.
644 * -jgarzik
645 */
646 static void __devinit quirk_via_acpi(struct pci_dev *d)
647 {
648 /*
649 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
650 */
651 u8 irq;
652 pci_read_config_byte(d, 0x42, &irq);
653 irq &= 0xf;
654 if (irq && (irq != 2))
655 d->irq = irq;
656 }
657 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi );
658 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi );
659
660
661 /*
662 * VIA bridges which have VLink
663 */
664
665 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
666
667 static void quirk_via_bridge(struct pci_dev *dev)
668 {
669 /* See what bridge we have and find the device ranges */
670 switch (dev->device) {
671 case PCI_DEVICE_ID_VIA_82C686:
672 /* The VT82C686 is special, it attaches to PCI and can have
673 any device number. All its subdevices are functions of
674 that single device. */
675 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
676 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
677 break;
678 case PCI_DEVICE_ID_VIA_8237:
679 case PCI_DEVICE_ID_VIA_8237A:
680 via_vlink_dev_lo = 15;
681 break;
682 case PCI_DEVICE_ID_VIA_8235:
683 via_vlink_dev_lo = 16;
684 break;
685 case PCI_DEVICE_ID_VIA_8231:
686 case PCI_DEVICE_ID_VIA_8233_0:
687 case PCI_DEVICE_ID_VIA_8233A:
688 case PCI_DEVICE_ID_VIA_8233C_0:
689 via_vlink_dev_lo = 17;
690 break;
691 }
692 }
693 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
694 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
695 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
696 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
697 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
698 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
699 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
700 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
701
702 /**
703 * quirk_via_vlink - VIA VLink IRQ number update
704 * @dev: PCI device
705 *
706 * If the device we are dealing with is on a PIC IRQ we need to
707 * ensure that the IRQ line register which usually is not relevant
708 * for PCI cards, is actually written so that interrupts get sent
709 * to the right place.
710 * We only do this on systems where a VIA south bridge was detected,
711 * and only for VIA devices on the motherboard (see quirk_via_bridge
712 * above).
713 */
714
715 static void quirk_via_vlink(struct pci_dev *dev)
716 {
717 u8 irq, new_irq;
718
719 /* Check if we have VLink at all */
720 if (via_vlink_dev_lo == -1)
721 return;
722
723 new_irq = dev->irq;
724
725 /* Don't quirk interrupts outside the legacy IRQ range */
726 if (!new_irq || new_irq > 15)
727 return;
728
729 /* Internal device ? */
730 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
731 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
732 return;
733
734 /* This is an internal VLink device on a PIC interrupt. The BIOS
735 ought to have set this but may not have, so we redo it */
736
737 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
738 if (new_irq != irq) {
739 printk(KERN_INFO "PCI: VIA VLink IRQ fixup for %s, from %d to %d\n",
740 pci_name(dev), irq, new_irq);
741 udelay(15); /* unknown if delay really needed */
742 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
743 }
744 }
745 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
746
747 /*
748 * VIA VT82C598 has its device ID settable and many BIOSes
749 * set it to the ID of VT82C597 for backward compatibility.
750 * We need to switch it off to be able to recognize the real
751 * type of the chip.
752 */
753 static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
754 {
755 pci_write_config_byte(dev, 0xfc, 0);
756 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
757 }
758 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id );
759
760 /*
761 * CardBus controllers have a legacy base address that enables them
762 * to respond as i82365 pcmcia controllers. We don't want them to
763 * do this even if the Linux CardBus driver is not loaded, because
764 * the Linux i82365 driver does not (and should not) handle CardBus.
765 */
766 static void quirk_cardbus_legacy(struct pci_dev *dev)
767 {
768 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
769 return;
770 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
771 }
772 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
773 DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
774
775 /*
776 * Following the PCI ordering rules is optional on the AMD762. I'm not
777 * sure what the designers were smoking but let's not inhale...
778 *
779 * To be fair to AMD, it follows the spec by default, its BIOS people
780 * who turn it off!
781 */
782 static void quirk_amd_ordering(struct pci_dev *dev)
783 {
784 u32 pcic;
785 pci_read_config_dword(dev, 0x4C, &pcic);
786 if ((pcic&6)!=6) {
787 pcic |= 6;
788 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
789 pci_write_config_dword(dev, 0x4C, pcic);
790 pci_read_config_dword(dev, 0x84, &pcic);
791 pcic |= (1<<23); /* Required in this mode */
792 pci_write_config_dword(dev, 0x84, pcic);
793 }
794 }
795 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );
796 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );
797
798 /*
799 * DreamWorks provided workaround for Dunord I-3000 problem
800 *
801 * This card decodes and responds to addresses not apparently
802 * assigned to it. We force a larger allocation to ensure that
803 * nothing gets put too close to it.
804 */
805 static void __devinit quirk_dunord ( struct pci_dev * dev )
806 {
807 struct resource *r = &dev->resource [1];
808 r->start = 0;
809 r->end = 0xffffff;
810 }
811 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord );
812
813 /*
814 * i82380FB mobile docking controller: its PCI-to-PCI bridge
815 * is subtractive decoding (transparent), and does indicate this
816 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
817 * instead of 0x01.
818 */
819 static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
820 {
821 dev->transparent = 1;
822 }
823 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge );
824 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge );
825
826 /*
827 * Common misconfiguration of the MediaGX/Geode PCI master that will
828 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
829 * datasheets found at http://www.national.com/ds/GX for info on what
830 * these bits do. <christer@weinigel.se>
831 */
832 static void quirk_mediagx_master(struct pci_dev *dev)
833 {
834 u8 reg;
835 pci_read_config_byte(dev, 0x41, &reg);
836 if (reg & 2) {
837 reg &= ~2;
838 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
839 pci_write_config_byte(dev, 0x41, reg);
840 }
841 }
842 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );
843 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );
844
845 /*
846 * Ensure C0 rev restreaming is off. This is normally done by
847 * the BIOS but in the odd case it is not the results are corruption
848 * hence the presence of a Linux check
849 */
850 static void quirk_disable_pxb(struct pci_dev *pdev)
851 {
852 u16 config;
853
854 if (pdev->revision != 0x04) /* Only C0 requires this */
855 return;
856 pci_read_config_word(pdev, 0x40, &config);
857 if (config & (1<<6)) {
858 config &= ~(1<<6);
859 pci_write_config_word(pdev, 0x40, config);
860 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
861 }
862 }
863 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb );
864 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb );
865
866
867 static void __devinit quirk_sb600_sata(struct pci_dev *pdev)
868 {
869 /* set sb600 sata to ahci mode */
870 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
871 u8 tmp;
872
873 pci_read_config_byte(pdev, 0x40, &tmp);
874 pci_write_config_byte(pdev, 0x40, tmp|1);
875 pci_write_config_byte(pdev, 0x9, 1);
876 pci_write_config_byte(pdev, 0xa, 6);
877 pci_write_config_byte(pdev, 0x40, tmp);
878
879 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
880 }
881 }
882 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_sb600_sata);
883 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_sb600_sata);
884
885 /*
886 * Serverworks CSB5 IDE does not fully support native mode
887 */
888 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
889 {
890 u8 prog;
891 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
892 if (prog & 5) {
893 prog &= ~5;
894 pdev->class &= ~5;
895 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
896 /* PCI layer will sort out resources */
897 }
898 }
899 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide );
900
901 /*
902 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
903 */
904 static void __init quirk_ide_samemode(struct pci_dev *pdev)
905 {
906 u8 prog;
907
908 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
909
910 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
911 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n");
912 prog &= ~5;
913 pdev->class &= ~5;
914 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
915 }
916 }
917 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
918
919 /* This was originally an Alpha specific thing, but it really fits here.
920 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
921 */
922 static void __init quirk_eisa_bridge(struct pci_dev *dev)
923 {
924 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
925 }
926 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge );
927
928
929 /*
930 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
931 * is not activated. The myth is that Asus said that they do not want the
932 * users to be irritated by just another PCI Device in the Win98 device
933 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
934 * package 2.7.0 for details)
935 *
936 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
937 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
938 * becomes necessary to do this tweak in two steps -- the chosen trigger
939 * is either the Host bridge (preferred) or on-board VGA controller.
940 *
941 * Note that we used to unhide the SMBus that way on Toshiba laptops
942 * (Satellite A40 and Tecra M2) but then found that the thermal management
943 * was done by SMM code, which could cause unsynchronized concurrent
944 * accesses to the SMBus registers, with potentially bad effects. Thus you
945 * should be very careful when adding new entries: if SMM is accessing the
946 * Intel SMBus, this is a very good reason to leave it hidden.
947 */
948 static int asus_hides_smbus;
949
950 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
951 {
952 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
953 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
954 switch(dev->subsystem_device) {
955 case 0x8025: /* P4B-LX */
956 case 0x8070: /* P4B */
957 case 0x8088: /* P4B533 */
958 case 0x1626: /* L3C notebook */
959 asus_hides_smbus = 1;
960 }
961 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
962 switch(dev->subsystem_device) {
963 case 0x80b1: /* P4GE-V */
964 case 0x80b2: /* P4PE */
965 case 0x8093: /* P4B533-V */
966 asus_hides_smbus = 1;
967 }
968 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
969 switch(dev->subsystem_device) {
970 case 0x8030: /* P4T533 */
971 asus_hides_smbus = 1;
972 }
973 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
974 switch (dev->subsystem_device) {
975 case 0x8070: /* P4G8X Deluxe */
976 asus_hides_smbus = 1;
977 }
978 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
979 switch (dev->subsystem_device) {
980 case 0x80c9: /* PU-DLS */
981 asus_hides_smbus = 1;
982 }
983 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
984 switch (dev->subsystem_device) {
985 case 0x1751: /* M2N notebook */
986 case 0x1821: /* M5N notebook */
987 asus_hides_smbus = 1;
988 }
989 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
990 switch (dev->subsystem_device) {
991 case 0x184b: /* W1N notebook */
992 case 0x186a: /* M6Ne notebook */
993 asus_hides_smbus = 1;
994 }
995 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
996 switch (dev->subsystem_device) {
997 case 0x80f2: /* P4P800-X */
998 asus_hides_smbus = 1;
999 }
1000 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1001 switch (dev->subsystem_device) {
1002 case 0x1882: /* M6V notebook */
1003 case 0x1977: /* A6VA notebook */
1004 asus_hides_smbus = 1;
1005 }
1006 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1007 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1008 switch(dev->subsystem_device) {
1009 case 0x088C: /* HP Compaq nc8000 */
1010 case 0x0890: /* HP Compaq nc6000 */
1011 asus_hides_smbus = 1;
1012 }
1013 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1014 switch (dev->subsystem_device) {
1015 case 0x12bc: /* HP D330L */
1016 case 0x12bd: /* HP D530 */
1017 asus_hides_smbus = 1;
1018 }
1019 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1020 switch (dev->subsystem_device) {
1021 case 0x099c: /* HP Compaq nx6110 */
1022 asus_hides_smbus = 1;
1023 }
1024 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1025 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1026 switch(dev->subsystem_device) {
1027 case 0xC00C: /* Samsung P35 notebook */
1028 asus_hides_smbus = 1;
1029 }
1030 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1031 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1032 switch(dev->subsystem_device) {
1033 case 0x0058: /* Compaq Evo N620c */
1034 asus_hides_smbus = 1;
1035 }
1036 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1037 switch(dev->subsystem_device) {
1038 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1039 /* Motherboard doesn't have Host bridge
1040 * subvendor/subdevice IDs, therefore checking
1041 * its on-board VGA controller */
1042 asus_hides_smbus = 1;
1043 }
1044 }
1045 }
1046 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge );
1047 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge );
1048 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge );
1049 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge );
1050 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge );
1051 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge );
1052 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge );
1053 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge );
1054 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge );
1055
1056 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge );
1057
1058 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1059 {
1060 u16 val;
1061
1062 if (likely(!asus_hides_smbus))
1063 return;
1064
1065 pci_read_config_word(dev, 0xF2, &val);
1066 if (val & 0x8) {
1067 pci_write_config_word(dev, 0xF2, val & (~0x8));
1068 pci_read_config_word(dev, 0xF2, &val);
1069 if (val & 0x8)
1070 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1071 else
1072 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
1073 }
1074 }
1075 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc );
1076 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc );
1077 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc );
1078 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc );
1079 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc );
1080 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
1081 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
1082 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc );
1083 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc );
1084 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc );
1085 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc );
1086 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc );
1087 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
1088 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
1089
1090 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1091 {
1092 u32 val, rcba;
1093 void __iomem *base;
1094
1095 if (likely(!asus_hides_smbus))
1096 return;
1097 pci_read_config_dword(dev, 0xF0, &rcba);
1098 base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */
1099 if (base == NULL) return;
1100 val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */
1101 writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */
1102 iounmap(base);
1103 printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n");
1104 }
1105 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 );
1106 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 );
1107
1108 /*
1109 * SiS 96x south bridge: BIOS typically hides SMBus device...
1110 */
1111 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1112 {
1113 u8 val = 0;
1114 pci_read_config_byte(dev, 0x77, &val);
1115 if (val & 0x10) {
1116 printk(KERN_INFO "Enabling SiS 96x SMBus.\n");
1117 pci_write_config_byte(dev, 0x77, val & ~0x10);
1118 }
1119 }
1120 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus );
1121 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus );
1122 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus );
1123 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus );
1124 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus );
1125 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus );
1126 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus );
1127 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus );
1128
1129 /*
1130 * ... This is further complicated by the fact that some SiS96x south
1131 * bridges pretend to be 85C503/5513 instead. In that case see if we
1132 * spotted a compatible north bridge to make sure.
1133 * (pci_find_device doesn't work yet)
1134 *
1135 * We can also enable the sis96x bit in the discovery register..
1136 */
1137 #define SIS_DETECT_REGISTER 0x40
1138
1139 static void quirk_sis_503(struct pci_dev *dev)
1140 {
1141 u8 reg;
1142 u16 devid;
1143
1144 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1145 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1146 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1147 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1148 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1149 return;
1150 }
1151
1152 /*
1153 * Ok, it now shows up as a 96x.. run the 96x quirk by
1154 * hand in case it has already been processed.
1155 * (depends on link order, which is apparently not guaranteed)
1156 */
1157 dev->device = devid;
1158 quirk_sis_96x_smbus(dev);
1159 }
1160 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 );
1161 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 );
1162
1163
1164 /*
1165 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1166 * and MC97 modem controller are disabled when a second PCI soundcard is
1167 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1168 * -- bjd
1169 */
1170 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1171 {
1172 u8 val;
1173 int asus_hides_ac97 = 0;
1174
1175 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1176 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1177 asus_hides_ac97 = 1;
1178 }
1179
1180 if (!asus_hides_ac97)
1181 return;
1182
1183 pci_read_config_byte(dev, 0x50, &val);
1184 if (val & 0xc0) {
1185 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1186 pci_read_config_byte(dev, 0x50, &val);
1187 if (val & 0xc0)
1188 printk(KERN_INFO "PCI: onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1189 else
1190 printk(KERN_INFO "PCI: enabled onboard AC97/MC97 devices\n");
1191 }
1192 }
1193 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc );
1194 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc );
1195
1196 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1197
1198 /*
1199 * If we are using libata we can drive this chip properly but must
1200 * do this early on to make the additional device appear during
1201 * the PCI scanning.
1202 */
1203 static void quirk_jmicron_ata(struct pci_dev *pdev)
1204 {
1205 u32 conf1, conf5, class;
1206 u8 hdr;
1207
1208 /* Only poke fn 0 */
1209 if (PCI_FUNC(pdev->devfn))
1210 return;
1211
1212 pci_read_config_dword(pdev, 0x40, &conf1);
1213 pci_read_config_dword(pdev, 0x80, &conf5);
1214
1215 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1216 conf5 &= ~(1 << 24); /* Clear bit 24 */
1217
1218 switch (pdev->device) {
1219 case PCI_DEVICE_ID_JMICRON_JMB360:
1220 /* The controller should be in single function ahci mode */
1221 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1222 break;
1223
1224 case PCI_DEVICE_ID_JMICRON_JMB365:
1225 case PCI_DEVICE_ID_JMICRON_JMB366:
1226 /* Redirect IDE second PATA port to the right spot */
1227 conf5 |= (1 << 24);
1228 /* Fall through */
1229 case PCI_DEVICE_ID_JMICRON_JMB361:
1230 case PCI_DEVICE_ID_JMICRON_JMB363:
1231 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1232 /* Set the class codes correctly and then direct IDE 0 */
1233 conf1 |= 0x00C2A102; /* Set 1, 8, 13, 15, 17, 22, 23 */
1234 break;
1235
1236 case PCI_DEVICE_ID_JMICRON_JMB368:
1237 /* The controller should be in single function IDE mode */
1238 conf1 |= 0x00C00000; /* Set 22, 23 */
1239 break;
1240 }
1241
1242 pci_write_config_dword(pdev, 0x40, conf1);
1243 pci_write_config_dword(pdev, 0x80, conf5);
1244
1245 /* Update pdev accordingly */
1246 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1247 pdev->hdr_type = hdr & 0x7f;
1248 pdev->multifunction = !!(hdr & 0x80);
1249
1250 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1251 pdev->class = class >> 8;
1252 }
1253 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1254 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1255 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1256 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1257 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1258 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1259 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1260 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1261 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1262 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1263 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1264 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1265
1266 #endif
1267
1268 #ifdef CONFIG_X86_IO_APIC
1269 static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1270 {
1271 int i;
1272
1273 if ((pdev->class >> 8) != 0xff00)
1274 return;
1275
1276 /* the first BAR is the location of the IO APIC...we must
1277 * not touch this (and it's already covered by the fixmap), so
1278 * forcibly insert it into the resource tree */
1279 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1280 insert_resource(&iomem_resource, &pdev->resource[0]);
1281
1282 /* The next five BARs all seem to be rubbish, so just clean
1283 * them out */
1284 for (i=1; i < 6; i++) {
1285 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1286 }
1287
1288 }
1289 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic );
1290 #endif
1291
1292 int pcie_mch_quirk;
1293 EXPORT_SYMBOL(pcie_mch_quirk);
1294
1295 static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1296 {
1297 pcie_mch_quirk = 1;
1298 }
1299 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch );
1300 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch );
1301 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch );
1302
1303
1304 /*
1305 * It's possible for the MSI to get corrupted if shpc and acpi
1306 * are used together on certain PXH-based systems.
1307 */
1308 static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1309 {
1310 pci_msi_off(dev);
1311
1312 dev->no_msi = 1;
1313
1314 printk(KERN_WARNING "PCI: PXH quirk detected, "
1315 "disabling MSI for SHPC device\n");
1316 }
1317 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1318 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1319 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1320 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1321 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1322
1323 /*
1324 * Some Intel PCI Express chipsets have trouble with downstream
1325 * device power management.
1326 */
1327 static void quirk_intel_pcie_pm(struct pci_dev * dev)
1328 {
1329 pci_pm_d3_delay = 120;
1330 dev->no_d1d2 = 1;
1331 }
1332
1333 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1334 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1335 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1336 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1337 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1338 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1339 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1340 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1341 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1342 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1343 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1344 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1345 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1346 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1347 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1348 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1349 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1350 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1351 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1352 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1353 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1354
1355 /*
1356 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1357 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1358 * Re-allocate the region if needed...
1359 */
1360 static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1361 {
1362 struct resource *r = &dev->resource[0];
1363
1364 if (r->start & 0x8) {
1365 r->start = 0;
1366 r->end = 0xf;
1367 }
1368 }
1369 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1370 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1371 quirk_tc86c001_ide);
1372
1373 static void __devinit quirk_netmos(struct pci_dev *dev)
1374 {
1375 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1376 unsigned int num_serial = dev->subsystem_device & 0xf;
1377
1378 /*
1379 * These Netmos parts are multiport serial devices with optional
1380 * parallel ports. Even when parallel ports are present, they
1381 * are identified as class SERIAL, which means the serial driver
1382 * will claim them. To prevent this, mark them as class OTHER.
1383 * These combo devices should be claimed by parport_serial.
1384 *
1385 * The subdevice ID is of the form 0x00PS, where <P> is the number
1386 * of parallel ports and <S> is the number of serial ports.
1387 */
1388 switch (dev->device) {
1389 case PCI_DEVICE_ID_NETMOS_9735:
1390 case PCI_DEVICE_ID_NETMOS_9745:
1391 case PCI_DEVICE_ID_NETMOS_9835:
1392 case PCI_DEVICE_ID_NETMOS_9845:
1393 case PCI_DEVICE_ID_NETMOS_9855:
1394 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1395 num_parallel) {
1396 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, "
1397 "%u serial); changing class SERIAL to OTHER "
1398 "(use parport_serial)\n",
1399 dev->device, num_parallel, num_serial);
1400 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1401 (dev->class & 0xff);
1402 }
1403 }
1404 }
1405 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1406
1407 static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1408 {
1409 u16 command;
1410 u8 __iomem *csr;
1411 u8 cmd_hi;
1412
1413 switch (dev->device) {
1414 /* PCI IDs taken from drivers/net/e100.c */
1415 case 0x1029:
1416 case 0x1030 ... 0x1034:
1417 case 0x1038 ... 0x103E:
1418 case 0x1050 ... 0x1057:
1419 case 0x1059:
1420 case 0x1064 ... 0x106B:
1421 case 0x1091 ... 0x1095:
1422 case 0x1209:
1423 case 0x1229:
1424 case 0x2449:
1425 case 0x2459:
1426 case 0x245D:
1427 case 0x27DC:
1428 break;
1429 default:
1430 return;
1431 }
1432
1433 /*
1434 * Some firmware hands off the e100 with interrupts enabled,
1435 * which can cause a flood of interrupts if packets are
1436 * received before the driver attaches to the device. So
1437 * disable all e100 interrupts here. The driver will
1438 * re-enable them when it's ready.
1439 */
1440 pci_read_config_word(dev, PCI_COMMAND, &command);
1441
1442 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1443 return;
1444
1445 /* Convert from PCI bus to resource space. */
1446 csr = ioremap(pci_resource_start(dev, 0), 8);
1447 if (!csr) {
1448 printk(KERN_WARNING "PCI: Can't map %s e100 registers\n",
1449 pci_name(dev));
1450 return;
1451 }
1452
1453 cmd_hi = readb(csr + 3);
1454 if (cmd_hi == 0) {
1455 printk(KERN_WARNING "PCI: Firmware left %s e100 interrupts "
1456 "enabled, disabling\n", pci_name(dev));
1457 writeb(1, csr + 3);
1458 }
1459
1460 iounmap(csr);
1461 }
1462 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
1463
1464 static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1465 {
1466 /* rev 1 ncr53c810 chips don't set the class at all which means
1467 * they don't get their resources remapped. Fix that here.
1468 */
1469
1470 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1471 printk(KERN_INFO "NCR 53c810 rev 1 detected, setting PCI class.\n");
1472 dev->class = PCI_CLASS_STORAGE_SCSI;
1473 }
1474 }
1475 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1476
1477 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1478 {
1479 while (f < end) {
1480 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1481 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1482 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev));
1483 f->hook(dev);
1484 }
1485 f++;
1486 }
1487 }
1488
1489 extern struct pci_fixup __start_pci_fixups_early[];
1490 extern struct pci_fixup __end_pci_fixups_early[];
1491 extern struct pci_fixup __start_pci_fixups_header[];
1492 extern struct pci_fixup __end_pci_fixups_header[];
1493 extern struct pci_fixup __start_pci_fixups_final[];
1494 extern struct pci_fixup __end_pci_fixups_final[];
1495 extern struct pci_fixup __start_pci_fixups_enable[];
1496 extern struct pci_fixup __end_pci_fixups_enable[];
1497 extern struct pci_fixup __start_pci_fixups_resume[];
1498 extern struct pci_fixup __end_pci_fixups_resume[];
1499
1500
1501 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1502 {
1503 struct pci_fixup *start, *end;
1504
1505 switch(pass) {
1506 case pci_fixup_early:
1507 start = __start_pci_fixups_early;
1508 end = __end_pci_fixups_early;
1509 break;
1510
1511 case pci_fixup_header:
1512 start = __start_pci_fixups_header;
1513 end = __end_pci_fixups_header;
1514 break;
1515
1516 case pci_fixup_final:
1517 start = __start_pci_fixups_final;
1518 end = __end_pci_fixups_final;
1519 break;
1520
1521 case pci_fixup_enable:
1522 start = __start_pci_fixups_enable;
1523 end = __end_pci_fixups_enable;
1524 break;
1525
1526 case pci_fixup_resume:
1527 start = __start_pci_fixups_resume;
1528 end = __end_pci_fixups_resume;
1529 break;
1530
1531 default:
1532 /* stupid compiler warning, you would think with an enum... */
1533 return;
1534 }
1535 pci_do_fixups(dev, start, end);
1536 }
1537 EXPORT_SYMBOL(pci_fixup_device);
1538
1539 /* Enable 1k I/O space granularity on the Intel P64H2 */
1540 static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1541 {
1542 u16 en1k;
1543 u8 io_base_lo, io_limit_lo;
1544 unsigned long base, limit;
1545 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1546
1547 pci_read_config_word(dev, 0x40, &en1k);
1548
1549 if (en1k & 0x200) {
1550 printk(KERN_INFO "PCI: Enable I/O Space to 1 KB Granularity\n");
1551
1552 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1553 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1554 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1555 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1556
1557 if (base <= limit) {
1558 res->start = base;
1559 res->end = limit + 0x3ff;
1560 }
1561 }
1562 }
1563 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1564
1565 /* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1566 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1567 * in drivers/pci/setup-bus.c
1568 */
1569 static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1570 {
1571 u16 en1k, iobl_adr, iobl_adr_1k;
1572 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1573
1574 pci_read_config_word(dev, 0x40, &en1k);
1575
1576 if (en1k & 0x200) {
1577 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1578
1579 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1580
1581 if (iobl_adr != iobl_adr_1k) {
1582 printk(KERN_INFO "PCI: Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1 KB Granularity\n",
1583 iobl_adr,iobl_adr_1k);
1584 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1585 }
1586 }
1587 }
1588 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1589
1590 /* Under some circumstances, AER is not linked with extended capabilities.
1591 * Force it to be linked by setting the corresponding control bit in the
1592 * config space.
1593 */
1594 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1595 {
1596 uint8_t b;
1597 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1598 if (!(b & 0x20)) {
1599 pci_write_config_byte(dev, 0xf41, b | 0x20);
1600 printk(KERN_INFO
1601 "PCI: Linking AER extended capability on %s\n",
1602 pci_name(dev));
1603 }
1604 }
1605 }
1606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1607 quirk_nvidia_ck804_pcie_aer_ext_cap);
1608 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1609 quirk_nvidia_ck804_pcie_aer_ext_cap);
1610
1611 #ifdef CONFIG_PCI_MSI
1612 /* Some chipsets do not support MSI. We cannot easily rely on setting
1613 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
1614 * some other busses controlled by the chipset even if Linux is not
1615 * aware of it. Instead of setting the flag on all busses in the
1616 * machine, simply disable MSI globally.
1617 */
1618 static void __init quirk_disable_all_msi(struct pci_dev *dev)
1619 {
1620 pci_no_msi();
1621 printk(KERN_WARNING "PCI: MSI quirk detected. MSI deactivated.\n");
1622 }
1623 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
1624 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000_PCIX, quirk_disable_all_msi);
1625 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
1626 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
1627 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RD580, quirk_disable_all_msi);
1628 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RX790, quirk_disable_all_msi);
1629 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS690, quirk_disable_all_msi);
1630 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
1631
1632 /* Disable MSI on chipsets that are known to not support it */
1633 static void __devinit quirk_disable_msi(struct pci_dev *dev)
1634 {
1635 if (dev->subordinate) {
1636 printk(KERN_WARNING "PCI: MSI quirk detected. "
1637 "PCI_BUS_FLAGS_NO_MSI set for %s subordinate bus.\n",
1638 pci_name(dev));
1639 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1640 }
1641 }
1642 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
1643
1644 /* Go through the list of Hypertransport capabilities and
1645 * return 1 if a HT MSI capability is found and enabled */
1646 static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
1647 {
1648 int pos, ttl = 48;
1649
1650 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1651 while (pos && ttl--) {
1652 u8 flags;
1653
1654 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1655 &flags) == 0)
1656 {
1657 printk(KERN_INFO "PCI: Found %s HT MSI Mapping on %s\n",
1658 flags & HT_MSI_FLAGS_ENABLE ?
1659 "enabled" : "disabled", pci_name(dev));
1660 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
1661 }
1662
1663 pos = pci_find_next_ht_capability(dev, pos,
1664 HT_CAPTYPE_MSI_MAPPING);
1665 }
1666 return 0;
1667 }
1668
1669 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
1670 static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
1671 {
1672 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
1673 printk(KERN_WARNING "PCI: MSI quirk detected. "
1674 "MSI disabled on chipset %s.\n",
1675 pci_name(dev));
1676 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1677 }
1678 }
1679 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
1680 quirk_msi_ht_cap);
1681
1682 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
1683 * MSI are supported if the MSI capability set in any of these mappings.
1684 */
1685 static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
1686 {
1687 struct pci_dev *pdev;
1688
1689 if (!dev->subordinate)
1690 return;
1691
1692 /* check HT MSI cap on this chipset and the root one.
1693 * a single one having MSI is enough to be sure that MSI are supported.
1694 */
1695 pdev = pci_get_slot(dev->bus, 0);
1696 if (!pdev)
1697 return;
1698 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
1699 printk(KERN_WARNING "PCI: MSI quirk detected. "
1700 "MSI disabled on chipset %s.\n",
1701 pci_name(dev));
1702 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1703 }
1704 pci_dev_put(pdev);
1705 }
1706 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1707 quirk_nvidia_ck804_msi_ht_cap);
1708 #endif /* CONFIG_PCI_MSI */
Linux kernel - Deliverables
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