2 * drivers/pci/setup-bus.c
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
9 * Support routines for initializing a PCI subsystem.
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/pci.h>
24 #include <linux/errno.h>
25 #include <linux/ioport.h>
26 #include <linux/cache.h>
27 #include <linux/slab.h>
30 static void pbus_assign_resources_sorted(const struct pci_bus
*bus
)
34 struct resource_list head
, *list
, *tmp
;
38 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
39 u16
class = dev
->class >> 8;
41 /* Don't touch classless devices or host bridges or ioapics. */
42 if (class == PCI_CLASS_NOT_DEFINED
||
43 class == PCI_CLASS_BRIDGE_HOST
)
46 /* Don't touch ioapic devices already enabled by firmware */
47 if (class == PCI_CLASS_SYSTEM_PIC
) {
49 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
50 if (command
& (PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
))
54 pdev_sort_resources(dev
, &head
);
57 for (list
= head
.next
; list
;) {
59 idx
= res
- &list
->dev
->resource
[0];
60 if (pci_assign_resource(list
->dev
, idx
)) {
71 void pci_setup_cardbus(struct pci_bus
*bus
)
73 struct pci_dev
*bridge
= bus
->self
;
75 struct pci_bus_region region
;
77 dev_info(&bridge
->dev
, "CardBus bridge to [bus %02x-%02x]\n",
78 bus
->secondary
, bus
->subordinate
);
80 res
= bus
->resource
[0];
81 pcibios_resource_to_bus(bridge
, ®ion
, res
);
82 if (res
->flags
& IORESOURCE_IO
) {
84 * The IO resource is allocated a range twice as large as it
85 * would normally need. This allows us to set both IO regs.
87 dev_info(&bridge
->dev
, " bridge window %pR\n", res
);
88 pci_write_config_dword(bridge
, PCI_CB_IO_BASE_0
,
90 pci_write_config_dword(bridge
, PCI_CB_IO_LIMIT_0
,
94 res
= bus
->resource
[1];
95 pcibios_resource_to_bus(bridge
, ®ion
, res
);
96 if (res
->flags
& IORESOURCE_IO
) {
97 dev_info(&bridge
->dev
, " bridge window %pR\n", res
);
98 pci_write_config_dword(bridge
, PCI_CB_IO_BASE_1
,
100 pci_write_config_dword(bridge
, PCI_CB_IO_LIMIT_1
,
104 res
= bus
->resource
[2];
105 pcibios_resource_to_bus(bridge
, ®ion
, res
);
106 if (res
->flags
& IORESOURCE_MEM
) {
107 dev_info(&bridge
->dev
, " bridge window %pR\n", res
);
108 pci_write_config_dword(bridge
, PCI_CB_MEMORY_BASE_0
,
110 pci_write_config_dword(bridge
, PCI_CB_MEMORY_LIMIT_0
,
114 res
= bus
->resource
[3];
115 pcibios_resource_to_bus(bridge
, ®ion
, res
);
116 if (res
->flags
& IORESOURCE_MEM
) {
117 dev_info(&bridge
->dev
, " bridge window %pR\n", res
);
118 pci_write_config_dword(bridge
, PCI_CB_MEMORY_BASE_1
,
120 pci_write_config_dword(bridge
, PCI_CB_MEMORY_LIMIT_1
,
124 EXPORT_SYMBOL(pci_setup_cardbus
);
126 /* Initialize bridges with base/limit values we have collected.
127 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
128 requires that if there is no I/O ports or memory behind the
129 bridge, corresponding range must be turned off by writing base
130 value greater than limit to the bridge's base/limit registers.
132 Note: care must be taken when updating I/O base/limit registers
133 of bridges which support 32-bit I/O. This update requires two
134 config space writes, so it's quite possible that an I/O window of
135 the bridge will have some undesirable address (e.g. 0) after the
136 first write. Ditto 64-bit prefetchable MMIO. */
137 static void pci_setup_bridge(struct pci_bus
*bus
)
139 struct pci_dev
*bridge
= bus
->self
;
140 struct resource
*res
;
141 struct pci_bus_region region
;
142 u32 l
, bu
, lu
, io_upper16
;
145 if (pci_is_enabled(bridge
))
148 dev_info(&bridge
->dev
, "PCI bridge to [bus %02x-%02x]\n",
149 bus
->secondary
, bus
->subordinate
);
151 /* Set up the top and bottom of the PCI I/O segment for this bus. */
152 res
= bus
->resource
[0];
153 pcibios_resource_to_bus(bridge
, ®ion
, res
);
154 if (res
->flags
& IORESOURCE_IO
) {
155 pci_read_config_dword(bridge
, PCI_IO_BASE
, &l
);
157 l
|= (region
.start
>> 8) & 0x00f0;
158 l
|= region
.end
& 0xf000;
159 /* Set up upper 16 bits of I/O base/limit. */
160 io_upper16
= (region
.end
& 0xffff0000) | (region
.start
>> 16);
161 dev_info(&bridge
->dev
, " bridge window %pR\n", res
);
164 /* Clear upper 16 bits of I/O base/limit. */
167 dev_info(&bridge
->dev
, " bridge window [io disabled]\n");
169 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
170 pci_write_config_dword(bridge
, PCI_IO_BASE_UPPER16
, 0x0000ffff);
171 /* Update lower 16 bits of I/O base/limit. */
172 pci_write_config_dword(bridge
, PCI_IO_BASE
, l
);
173 /* Update upper 16 bits of I/O base/limit. */
174 pci_write_config_dword(bridge
, PCI_IO_BASE_UPPER16
, io_upper16
);
176 /* Set up the top and bottom of the PCI Memory segment
178 res
= bus
->resource
[1];
179 pcibios_resource_to_bus(bridge
, ®ion
, res
);
180 if (res
->flags
& IORESOURCE_MEM
) {
181 l
= (region
.start
>> 16) & 0xfff0;
182 l
|= region
.end
& 0xfff00000;
183 dev_info(&bridge
->dev
, " bridge window %pR\n", res
);
187 dev_info(&bridge
->dev
, " bridge window [mem disabled]\n");
189 pci_write_config_dword(bridge
, PCI_MEMORY_BASE
, l
);
191 /* Clear out the upper 32 bits of PREF limit.
192 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
193 disables PREF range, which is ok. */
194 pci_write_config_dword(bridge
, PCI_PREF_LIMIT_UPPER32
, 0);
196 /* Set up PREF base/limit. */
199 res
= bus
->resource
[2];
200 pcibios_resource_to_bus(bridge
, ®ion
, res
);
201 if (res
->flags
& IORESOURCE_PREFETCH
) {
202 l
= (region
.start
>> 16) & 0xfff0;
203 l
|= region
.end
& 0xfff00000;
204 if (res
->flags
& IORESOURCE_MEM_64
) {
206 bu
= upper_32_bits(region
.start
);
207 lu
= upper_32_bits(region
.end
);
209 dev_info(&bridge
->dev
, " bridge window %pR\n", res
);
213 dev_info(&bridge
->dev
, " bridge window [mem pref disabled]\n");
215 pci_write_config_dword(bridge
, PCI_PREF_MEMORY_BASE
, l
);
218 /* Set the upper 32 bits of PREF base & limit. */
219 pci_write_config_dword(bridge
, PCI_PREF_BASE_UPPER32
, bu
);
220 pci_write_config_dword(bridge
, PCI_PREF_LIMIT_UPPER32
, lu
);
223 pci_write_config_word(bridge
, PCI_BRIDGE_CONTROL
, bus
->bridge_ctl
);
226 /* Check whether the bridge supports optional I/O and
227 prefetchable memory ranges. If not, the respective
228 base/limit registers must be read-only and read as 0. */
229 static void pci_bridge_check_ranges(struct pci_bus
*bus
)
233 struct pci_dev
*bridge
= bus
->self
;
234 struct resource
*b_res
;
236 b_res
= &bridge
->resource
[PCI_BRIDGE_RESOURCES
];
237 b_res
[1].flags
|= IORESOURCE_MEM
;
239 pci_read_config_word(bridge
, PCI_IO_BASE
, &io
);
241 pci_write_config_word(bridge
, PCI_IO_BASE
, 0xf0f0);
242 pci_read_config_word(bridge
, PCI_IO_BASE
, &io
);
243 pci_write_config_word(bridge
, PCI_IO_BASE
, 0x0);
246 b_res
[0].flags
|= IORESOURCE_IO
;
247 /* DECchip 21050 pass 2 errata: the bridge may miss an address
248 disconnect boundary by one PCI data phase.
249 Workaround: do not use prefetching on this device. */
250 if (bridge
->vendor
== PCI_VENDOR_ID_DEC
&& bridge
->device
== 0x0001)
252 pci_read_config_dword(bridge
, PCI_PREF_MEMORY_BASE
, &pmem
);
254 pci_write_config_dword(bridge
, PCI_PREF_MEMORY_BASE
,
256 pci_read_config_dword(bridge
, PCI_PREF_MEMORY_BASE
, &pmem
);
257 pci_write_config_dword(bridge
, PCI_PREF_MEMORY_BASE
, 0x0);
260 b_res
[2].flags
|= IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
261 if ((pmem
& PCI_PREF_RANGE_TYPE_MASK
) == PCI_PREF_RANGE_TYPE_64
)
262 b_res
[2].flags
|= IORESOURCE_MEM_64
;
265 /* double check if bridge does support 64 bit pref */
266 if (b_res
[2].flags
& IORESOURCE_MEM_64
) {
267 u32 mem_base_hi
, tmp
;
268 pci_read_config_dword(bridge
, PCI_PREF_BASE_UPPER32
,
270 pci_write_config_dword(bridge
, PCI_PREF_BASE_UPPER32
,
272 pci_read_config_dword(bridge
, PCI_PREF_BASE_UPPER32
, &tmp
);
274 b_res
[2].flags
&= ~IORESOURCE_MEM_64
;
275 pci_write_config_dword(bridge
, PCI_PREF_BASE_UPPER32
,
280 /* Helper function for sizing routines: find first available
281 bus resource of a given type. Note: we intentionally skip
282 the bus resources which have already been assigned (that is,
283 have non-NULL parent resource). */
284 static struct resource
*find_free_bus_resource(struct pci_bus
*bus
, unsigned long type
)
288 unsigned long type_mask
= IORESOURCE_IO
| IORESOURCE_MEM
|
291 for (i
= 0; i
< PCI_BUS_NUM_RESOURCES
; i
++) {
292 r
= bus
->resource
[i
];
293 if (r
== &ioport_resource
|| r
== &iomem_resource
)
295 if (r
&& (r
->flags
& type_mask
) == type
&& !r
->parent
)
301 /* Sizing the IO windows of the PCI-PCI bridge is trivial,
302 since these windows have 4K granularity and the IO ranges
303 of non-bridge PCI devices are limited to 256 bytes.
304 We must be careful with the ISA aliasing though. */
305 static void pbus_size_io(struct pci_bus
*bus
, resource_size_t min_size
)
308 struct resource
*b_res
= find_free_bus_resource(bus
, IORESOURCE_IO
);
309 unsigned long size
= 0, size1
= 0;
314 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
317 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
318 struct resource
*r
= &dev
->resource
[i
];
319 unsigned long r_size
;
321 if (r
->parent
|| !(r
->flags
& IORESOURCE_IO
))
323 r_size
= resource_size(r
);
326 /* Might be re-aligned for ISA */
334 /* To be fixed in 2.5: we should have sort of HAVE_ISA
335 flag in the struct pci_bus. */
336 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
337 size
= (size
& 0xff) + ((size
& ~0xffUL
) << 2);
339 size
= ALIGN(size
+ size1
, 4096);
341 if (b_res
->start
|| b_res
->end
)
342 dev_info(&bus
->self
->dev
, "disabling bridge window "
343 "%pR to [bus %02x-%02x] (unused)\n", b_res
,
344 bus
->secondary
, bus
->subordinate
);
348 /* Alignment of the IO window is always 4K */
350 b_res
->end
= b_res
->start
+ size
- 1;
351 b_res
->flags
|= IORESOURCE_STARTALIGN
;
354 /* Calculate the size of the bus and minimal alignment which
355 guarantees that all child resources fit in this size. */
356 static int pbus_size_mem(struct pci_bus
*bus
, unsigned long mask
,
357 unsigned long type
, resource_size_t min_size
)
360 resource_size_t min_align
, align
, size
;
361 resource_size_t aligns
[12]; /* Alignments from 1Mb to 2Gb */
362 int order
, max_order
;
363 struct resource
*b_res
= find_free_bus_resource(bus
, type
);
364 unsigned int mem64_mask
= 0;
369 memset(aligns
, 0, sizeof(aligns
));
373 mem64_mask
= b_res
->flags
& IORESOURCE_MEM_64
;
374 b_res
->flags
&= ~IORESOURCE_MEM_64
;
376 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
379 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
380 struct resource
*r
= &dev
->resource
[i
];
381 resource_size_t r_size
;
383 if (r
->parent
|| (r
->flags
& mask
) != type
)
385 r_size
= resource_size(r
);
386 /* For bridges size != alignment */
387 align
= pci_resource_alignment(dev
, r
);
388 order
= __ffs(align
) - 20;
390 dev_warn(&dev
->dev
, "disabling BAR %d: %pR "
391 "(bad alignment %#llx)\n", i
, r
,
392 (unsigned long long) align
);
399 /* Exclude ranges with size > align from
400 calculation of the alignment. */
402 aligns
[order
] += align
;
403 if (order
> max_order
)
405 mem64_mask
&= r
->flags
& IORESOURCE_MEM_64
;
413 for (order
= 0; order
<= max_order
; order
++) {
414 resource_size_t align1
= 1;
416 align1
<<= (order
+ 20);
420 else if (ALIGN(align
+ min_align
, min_align
) < align1
)
421 min_align
= align1
>> 1;
422 align
+= aligns
[order
];
424 size
= ALIGN(size
, min_align
);
426 if (b_res
->start
|| b_res
->end
)
427 dev_info(&bus
->self
->dev
, "disabling bridge window "
428 "%pR to [bus %02x-%02x] (unused)\n", b_res
,
429 bus
->secondary
, bus
->subordinate
);
433 b_res
->start
= min_align
;
434 b_res
->end
= size
+ min_align
- 1;
435 b_res
->flags
|= IORESOURCE_STARTALIGN
;
436 b_res
->flags
|= mem64_mask
;
440 static void pci_bus_size_cardbus(struct pci_bus
*bus
)
442 struct pci_dev
*bridge
= bus
->self
;
443 struct resource
*b_res
= &bridge
->resource
[PCI_BRIDGE_RESOURCES
];
447 * Reserve some resources for CardBus. We reserve
448 * a fixed amount of bus space for CardBus bridges.
451 b_res
[0].end
= pci_cardbus_io_size
- 1;
452 b_res
[0].flags
|= IORESOURCE_IO
| IORESOURCE_SIZEALIGN
;
455 b_res
[1].end
= pci_cardbus_io_size
- 1;
456 b_res
[1].flags
|= IORESOURCE_IO
| IORESOURCE_SIZEALIGN
;
459 * Check whether prefetchable memory is supported
462 pci_read_config_word(bridge
, PCI_CB_BRIDGE_CONTROL
, &ctrl
);
463 if (!(ctrl
& PCI_CB_BRIDGE_CTL_PREFETCH_MEM0
)) {
464 ctrl
|= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0
;
465 pci_write_config_word(bridge
, PCI_CB_BRIDGE_CONTROL
, ctrl
);
466 pci_read_config_word(bridge
, PCI_CB_BRIDGE_CONTROL
, &ctrl
);
470 * If we have prefetchable memory support, allocate
471 * two regions. Otherwise, allocate one region of
474 if (ctrl
& PCI_CB_BRIDGE_CTL_PREFETCH_MEM0
) {
476 b_res
[2].end
= pci_cardbus_mem_size
- 1;
477 b_res
[2].flags
|= IORESOURCE_MEM
| IORESOURCE_PREFETCH
| IORESOURCE_SIZEALIGN
;
480 b_res
[3].end
= pci_cardbus_mem_size
- 1;
481 b_res
[3].flags
|= IORESOURCE_MEM
| IORESOURCE_SIZEALIGN
;
484 b_res
[3].end
= pci_cardbus_mem_size
* 2 - 1;
485 b_res
[3].flags
|= IORESOURCE_MEM
| IORESOURCE_SIZEALIGN
;
489 void __ref
pci_bus_size_bridges(struct pci_bus
*bus
)
492 unsigned long mask
, prefmask
;
493 resource_size_t min_mem_size
= 0, min_io_size
= 0;
495 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
496 struct pci_bus
*b
= dev
->subordinate
;
500 switch (dev
->class >> 8) {
501 case PCI_CLASS_BRIDGE_CARDBUS
:
502 pci_bus_size_cardbus(b
);
505 case PCI_CLASS_BRIDGE_PCI
:
507 pci_bus_size_bridges(b
);
516 switch (bus
->self
->class >> 8) {
517 case PCI_CLASS_BRIDGE_CARDBUS
:
518 /* don't size cardbuses yet. */
521 case PCI_CLASS_BRIDGE_PCI
:
522 pci_bridge_check_ranges(bus
);
523 if (bus
->self
->is_hotplug_bridge
) {
524 min_io_size
= pci_hotplug_io_size
;
525 min_mem_size
= pci_hotplug_mem_size
;
528 pbus_size_io(bus
, min_io_size
);
529 /* If the bridge supports prefetchable range, size it
530 separately. If it doesn't, or its prefetchable window
531 has already been allocated by arch code, try
532 non-prefetchable range for both types of PCI memory
534 mask
= IORESOURCE_MEM
;
535 prefmask
= IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
536 if (pbus_size_mem(bus
, prefmask
, prefmask
, min_mem_size
))
537 mask
= prefmask
; /* Success, size non-prefetch only. */
539 min_mem_size
+= min_mem_size
;
540 pbus_size_mem(bus
, mask
, IORESOURCE_MEM
, min_mem_size
);
544 EXPORT_SYMBOL(pci_bus_size_bridges
);
546 void __ref
pci_bus_assign_resources(const struct pci_bus
*bus
)
551 pbus_assign_resources_sorted(bus
);
553 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
554 b
= dev
->subordinate
;
558 pci_bus_assign_resources(b
);
560 switch (dev
->class >> 8) {
561 case PCI_CLASS_BRIDGE_PCI
:
565 case PCI_CLASS_BRIDGE_CARDBUS
:
566 pci_setup_cardbus(b
);
570 dev_info(&dev
->dev
, "not setting up bridge for bus "
571 "%04x:%02x\n", pci_domain_nr(b
), b
->number
);
576 EXPORT_SYMBOL(pci_bus_assign_resources
);
578 static void pci_bus_dump_res(struct pci_bus
*bus
)
582 for (i
= 0; i
< PCI_BUS_NUM_RESOURCES
; i
++) {
583 struct resource
*res
= bus
->resource
[i
];
584 if (!res
|| !res
->end
)
587 dev_printk(KERN_DEBUG
, &bus
->dev
, "resource %d %pR\n", i
, res
);
591 static void pci_bus_dump_resources(struct pci_bus
*bus
)
597 pci_bus_dump_res(bus
);
599 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
600 b
= dev
->subordinate
;
604 pci_bus_dump_resources(b
);
609 pci_assign_unassigned_resources(void)
613 /* Depth first, calculate sizes and alignments of all
614 subordinate buses. */
615 list_for_each_entry(bus
, &pci_root_buses
, node
) {
616 pci_bus_size_bridges(bus
);
618 /* Depth last, allocate resources and update the hardware. */
619 list_for_each_entry(bus
, &pci_root_buses
, node
) {
620 pci_bus_assign_resources(bus
);
621 pci_enable_bridges(bus
);
624 /* dump the resource on buses */
625 list_for_each_entry(bus
, &pci_root_buses
, node
) {
626 pci_bus_dump_resources(bus
);