drivers/pci/setup-bus.c

   1 /*
   2  *      drivers/pci/setup-bus.c
   3  *
   4  * Extruded from code written by
   5  *      Dave Rusling (david.rusling@reo.mts.dec.com)
   6  *      David Mosberger (davidm@cs.arizona.edu)
   7  *      David Miller (davem@redhat.com)
   8  *
   9  * Support routines for initializing a PCI subsystem.
  10  */
  11
  12 /*
  13  * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
  14  *           PCI-PCI bridges cleanup, sorted resource allocation.
  15  * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
  16  *           Converted to allocation in 3 passes, which gives
  17  *           tighter packing. Prefetchable range support.
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/pci.h>
  24 #include <linux/errno.h>
  25 #include <linux/ioport.h>
  26 #include <linux/cache.h>
  27 #include <linux/slab.h>
  28
  29
  30 #define DEBUG_CONFIG 1
  31 #if DEBUG_CONFIG
  32 #define DBG(x...)     printk(x)
  33 #else
  34 #define DBG(x...)
  35 #endif
  36
  37 #define ROUND_UP(x, a)          (((x) + (a) - 1) & ~((a) - 1))
  38
  39 /*
  40  * FIXME: IO should be max 256 bytes.  However, since we may
  41  * have a P2P bridge below a cardbus bridge, we need 4K.
  42  */
  43 #define CARDBUS_IO_SIZE         (4096)
  44 #define CARDBUS_MEM_SIZE        (32*1024*1024)
  45
  46 static void __devinit
  47 pbus_assign_resources_sorted(struct pci_bus *bus)
  48 {
  49         struct pci_dev *dev;
  50         struct resource *res;
  51         struct resource_list head, *list, *tmp;
  52         int idx;
  53
  54         bus->bridge_ctl &= ~PCI_BRIDGE_CTL_VGA;
  55
  56         head.next = NULL;
  57         list_for_each_entry(dev, &bus->devices, bus_list) {
  58                 u16 class = dev->class >> 8;
  59
  60                 /* Don't touch classless devices and host bridges.  */
  61                 if (class == PCI_CLASS_NOT_DEFINED ||
  62                     class == PCI_CLASS_BRIDGE_HOST)
  63                         continue;
  64
  65                 if (class == PCI_CLASS_DISPLAY_VGA ||
  66                     class == PCI_CLASS_NOT_DEFINED_VGA)
  67                         bus->bridge_ctl |= PCI_BRIDGE_CTL_VGA;
  68
  69                 pdev_sort_resources(dev, &head);
  70         }
  71
  72         for (list = head.next; list;) {
  73                 res = list->res;
  74                 idx = res - &list->dev->resource[0];
  75                 if (pci_assign_resource(list->dev, idx)) {
  76                         res->start = 0;
  77                         res->end = 0;
  78                         res->flags = 0;
  79                 }
  80                 tmp = list;
  81                 list = list->next;
  82                 kfree(tmp);
  83         }
  84 }
  85
  86 static void __devinit
  87 pci_setup_cardbus(struct pci_bus *bus)
  88 {
  89         struct pci_dev *bridge = bus->self;
  90         struct pci_bus_region region;
  91
  92         printk("PCI: Bus %d, cardbus bridge: %s\n",
  93                 bus->number, pci_name(bridge));
  94
  95         pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
  96         if (bus->resource[0]->flags & IORESOURCE_IO) {
  97                 /*
  98                  * The IO resource is allocated a range twice as large as it
  99                  * would normally need.  This allows us to set both IO regs.
 100                  */
 101                 printk("  IO window: %08lx-%08lx\n",
 102                         region.start, region.end);
 103                 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
 104                                         region.start);
 105                 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
 106                                         region.end);
 107         }
 108
 109         pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
 110         if (bus->resource[1]->flags & IORESOURCE_IO) {
 111                 printk("  IO window: %08lx-%08lx\n",
 112                         region.start, region.end);
 113                 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
 114                                         region.start);
 115                 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
 116                                         region.end);
 117         }
 118
 119         pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
 120         if (bus->resource[2]->flags & IORESOURCE_MEM) {
 121                 printk("  PREFETCH window: %08lx-%08lx\n",
 122                         region.start, region.end);
 123                 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
 124                                         region.start);
 125                 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
 126                                         region.end);
 127         }
 128
 129         pcibios_resource_to_bus(bridge, &region, bus->resource[3]);
 130         if (bus->resource[3]->flags & IORESOURCE_MEM) {
 131                 printk("  MEM window: %08lx-%08lx\n",
 132                         region.start, region.end);
 133                 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
 134                                         region.start);
 135                 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
 136                                         region.end);
 137         }
 138 }
 139
 140 /* Initialize bridges with base/limit values we have collected.
 141    PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
 142    requires that if there is no I/O ports or memory behind the
 143    bridge, corresponding range must be turned off by writing base
 144    value greater than limit to the bridge's base/limit registers.
 145
 146    Note: care must be taken when updating I/O base/limit registers
 147    of bridges which support 32-bit I/O. This update requires two
 148    config space writes, so it's quite possible that an I/O window of
 149    the bridge will have some undesirable address (e.g. 0) after the
 150    first write. Ditto 64-bit prefetchable MMIO.  */
 151 static void __devinit
 152 pci_setup_bridge(struct pci_bus *bus)
 153 {
 154         struct pci_dev *bridge = bus->self;
 155         struct pci_bus_region region;
 156         u32 l, io_upper16;
 157
 158         DBG(KERN_INFO "PCI: Bridge: %s\n", pci_name(bridge));
 159
 160         /* Set up the top and bottom of the PCI I/O segment for this bus. */
 161         pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
 162         if (bus->resource[0]->flags & IORESOURCE_IO) {
 163                 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
 164                 l &= 0xffff0000;
 165                 l |= (region.start >> 8) & 0x00f0;
 166                 l |= region.end & 0xf000;
 167                 /* Set up upper 16 bits of I/O base/limit. */
 168                 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
 169                 DBG(KERN_INFO "  IO window: %04lx-%04lx\n",
 170                                 region.start, region.end);
 171         }
 172         else {
 173                 /* Clear upper 16 bits of I/O base/limit. */
 174                 io_upper16 = 0;
 175                 l = 0x00f0;
 176                 DBG(KERN_INFO "  IO window: disabled.\n");
 177         }
 178         /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
 179         pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
 180         /* Update lower 16 bits of I/O base/limit. */
 181         pci_write_config_dword(bridge, PCI_IO_BASE, l);
 182         /* Update upper 16 bits of I/O base/limit. */
 183         pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
 184
 185         /* Set up the top and bottom of the PCI Memory segment
 186            for this bus. */
 187         pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
 188         if (bus->resource[1]->flags & IORESOURCE_MEM) {
 189                 l = (region.start >> 16) & 0xfff0;
 190                 l |= region.end & 0xfff00000;
 191                 DBG(KERN_INFO "  MEM window: %08lx-%08lx\n",
 192                                 region.start, region.end);
 193         }
 194         else {
 195                 l = 0x0000fff0;
 196                 DBG(KERN_INFO "  MEM window: disabled.\n");
 197         }
 198         pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
 199
 200         /* Clear out the upper 32 bits of PREF limit.
 201            If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
 202            disables PREF range, which is ok. */
 203         pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
 204
 205         /* Set up PREF base/limit. */
 206         pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
 207         if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
 208                 l = (region.start >> 16) & 0xfff0;
 209                 l |= region.end & 0xfff00000;
 210                 DBG(KERN_INFO "  PREFETCH window: %08lx-%08lx\n",
 211                                 region.start, region.end);
 212         }
 213         else {
 214                 l = 0x0000fff0;
 215                 DBG(KERN_INFO "  PREFETCH window: disabled.\n");
 216         }
 217         pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
 218
 219         /* Clear out the upper 32 bits of PREF base. */
 220         pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 0);
 221
 222         pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
 223 }
 224
 225 /* Check whether the bridge supports optional I/O and
 226    prefetchable memory ranges. If not, the respective
 227    base/limit registers must be read-only and read as 0. */
 228 static void __devinit
 229 pci_bridge_check_ranges(struct pci_bus *bus)
 230 {
 231         u16 io;
 232         u32 pmem;
 233         struct pci_dev *bridge = bus->self;
 234         struct resource *b_res;
 235
 236         b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
 237         b_res[1].flags |= IORESOURCE_MEM;
 238
 239         pci_read_config_word(bridge, PCI_IO_BASE, &io);
 240         if (!io) {
 241                 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
 242                 pci_read_config_word(bridge, PCI_IO_BASE, &io);
 243                 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
 244         }
 245         if (io)
 246                 b_res[0].flags |= IORESOURCE_IO;
 247         /*  DECchip 21050 pass 2 errata: the bridge may miss an address
 248             disconnect boundary by one PCI data phase.
 249             Workaround: do not use prefetching on this device. */
 250         if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
 251                 return;
 252         pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
 253         if (!pmem) {
 254                 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
 255                                                0xfff0fff0);
 256                 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
 257                 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
 258         }
 259         if (pmem)
 260                 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
 261 }
 262
 263 /* Helper function for sizing routines: find first available
 264    bus resource of a given type. Note: we intentionally skip
 265    the bus resources which have already been assigned (that is,
 266    have non-NULL parent resource). */
 267 static struct resource * __devinit
 268 find_free_bus_resource(struct pci_bus *bus, unsigned long type)
 269 {
 270         int i;
 271         struct resource *r;
 272         unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
 273                                   IORESOURCE_PREFETCH;
 274
 275         for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
 276                 r = bus->resource[i];
 277                 if (r == &ioport_resource || r == &iomem_resource)
 278                         continue;
 279                 if (r && (r->flags & type_mask) == type && !r->parent)
 280                         return r;
 281         }
 282         return NULL;
 283 }
 284
 285 /* Sizing the IO windows of the PCI-PCI bridge is trivial,
 286    since these windows have 4K granularity and the IO ranges
 287    of non-bridge PCI devices are limited to 256 bytes.
 288    We must be careful with the ISA aliasing though. */
 289 static void __devinit
 290 pbus_size_io(struct pci_bus *bus)
 291 {
 292         struct pci_dev *dev;
 293         struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
 294         unsigned long size = 0, size1 = 0;
 295
 296         if (!b_res)
 297                 return;
 298
 299         list_for_each_entry(dev, &bus->devices, bus_list) {
 300                 int i;
 301
 302                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 303                         struct resource *r = &dev->resource[i];
 304                         unsigned long r_size;
 305
 306                         if (r->parent || !(r->flags & IORESOURCE_IO))
 307                                 continue;
 308                         r_size = r->end - r->start + 1;
 309
 310                         if (r_size < 0x400)
 311                                 /* Might be re-aligned for ISA */
 312                                 size += r_size;
 313                         else
 314                                 size1 += r_size;
 315                 }
 316         }
 317 /* To be fixed in 2.5: we should have sort of HAVE_ISA
 318    flag in the struct pci_bus. */
 319 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
 320         size = (size & 0xff) + ((size & ~0xffUL) << 2);
 321 #endif
 322         size = ROUND_UP(size + size1, 4096);
 323         if (!size) {
 324                 b_res->flags = 0;
 325                 return;
 326         }
 327         /* Alignment of the IO window is always 4K */
 328         b_res->start = 4096;
 329         b_res->end = b_res->start + size - 1;
 330 }
 331
 332 /* Calculate the size of the bus and minimal alignment which
 333    guarantees that all child resources fit in this size. */
 334 static int __devinit
 335 pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type)
 336 {
 337         struct pci_dev *dev;
 338         unsigned long min_align, align, size;
 339         unsigned long aligns[12];       /* Alignments from 1Mb to 2Gb */
 340         int order, max_order;
 341         struct resource *b_res = find_free_bus_resource(bus, type);
 342
 343         if (!b_res)
 344                 return 0;
 345
 346         memset(aligns, 0, sizeof(aligns));
 347         max_order = 0;
 348         size = 0;
 349
 350         list_for_each_entry(dev, &bus->devices, bus_list) {
 351                 int i;
 352
 353                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 354                         struct resource *r = &dev->resource[i];
 355                         unsigned long r_size;
 356
 357                         if (r->parent || (r->flags & mask) != type)
 358                                 continue;
 359                         r_size = r->end - r->start + 1;
 360                         /* For bridges size != alignment */
 361                         align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start;
 362                         order = __ffs(align) - 20;
 363                         if (order > 11) {
 364                                 printk(KERN_WARNING "PCI: region %s/%d "
 365                                        "too large: %lx-%lx\n",
 366                                        pci_name(dev), i, r->start, r->end);
 367                                 r->flags = 0;
 368                                 continue;
 369                         }
 370                         size += r_size;
 371                         if (order < 0)
 372                                 order = 0;
 373                         /* Exclude ranges with size > align from
 374                            calculation of the alignment. */
 375                         if (r_size == align)
 376                                 aligns[order] += align;
 377                         if (order > max_order)
 378                                 max_order = order;
 379                 }
 380         }
 381
 382         align = 0;
 383         min_align = 0;
 384         for (order = 0; order <= max_order; order++) {
 385                 unsigned long align1 = 1UL << (order + 20);
 386
 387                 if (!align)
 388                         min_align = align1;
 389                 else if (ROUND_UP(align + min_align, min_align) < align1)
 390                         min_align = align1 >> 1;
 391                 align += aligns[order];
 392         }
 393         size = ROUND_UP(size, min_align);
 394         if (!size) {
 395                 b_res->flags = 0;
 396                 return 1;
 397         }
 398         b_res->start = min_align;
 399         b_res->end = size + min_align - 1;
 400         return 1;
 401 }
 402
 403 static void __devinit
 404 pci_bus_size_cardbus(struct pci_bus *bus)
 405 {
 406         struct pci_dev *bridge = bus->self;
 407         struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
 408         u16 ctrl;
 409
 410         /*
 411          * Reserve some resources for CardBus.  We reserve
 412          * a fixed amount of bus space for CardBus bridges.
 413          */
 414         b_res[0].start = CARDBUS_IO_SIZE;
 415         b_res[0].end = b_res[0].start + CARDBUS_IO_SIZE - 1;
 416         b_res[0].flags |= IORESOURCE_IO;
 417
 418         b_res[1].start = CARDBUS_IO_SIZE;
 419         b_res[1].end = b_res[1].start + CARDBUS_IO_SIZE - 1;
 420         b_res[1].flags |= IORESOURCE_IO;
 421
 422         /*
 423          * Check whether prefetchable memory is supported
 424          * by this bridge.
 425          */
 426         pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
 427         if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
 428                 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
 429                 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
 430                 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
 431         }
 432
 433         /*
 434          * If we have prefetchable memory support, allocate
 435          * two regions.  Otherwise, allocate one region of
 436          * twice the size.
 437          */
 438         if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
 439                 b_res[2].start = CARDBUS_MEM_SIZE;
 440                 b_res[2].end = b_res[2].start + CARDBUS_MEM_SIZE - 1;
 441                 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
 442
 443                 b_res[3].start = CARDBUS_MEM_SIZE;
 444                 b_res[3].end = b_res[3].start + CARDBUS_MEM_SIZE - 1;
 445                 b_res[3].flags |= IORESOURCE_MEM;
 446         } else {
 447                 b_res[3].start = CARDBUS_MEM_SIZE * 2;
 448                 b_res[3].end = b_res[3].start + CARDBUS_MEM_SIZE * 2 - 1;
 449                 b_res[3].flags |= IORESOURCE_MEM;
 450         }
 451 }
 452
 453 void __devinit
 454 pci_bus_size_bridges(struct pci_bus *bus)
 455 {
 456         struct pci_dev *dev;
 457         unsigned long mask, prefmask;
 458
 459         list_for_each_entry(dev, &bus->devices, bus_list) {
 460                 struct pci_bus *b = dev->subordinate;
 461                 if (!b)
 462                         continue;
 463
 464                 switch (dev->class >> 8) {
 465                 case PCI_CLASS_BRIDGE_CARDBUS:
 466                         pci_bus_size_cardbus(b);
 467                         break;
 468
 469                 case PCI_CLASS_BRIDGE_PCI:
 470                 default:
 471                         pci_bus_size_bridges(b);
 472                         break;
 473                 }
 474         }
 475
 476         /* The root bus? */
 477         if (!bus->self)
 478                 return;
 479
 480         switch (bus->self->class >> 8) {
 481         case PCI_CLASS_BRIDGE_CARDBUS:
 482                 /* don't size cardbuses yet. */
 483                 break;
 484
 485         case PCI_CLASS_BRIDGE_PCI:
 486                 pci_bridge_check_ranges(bus);
 487         default:
 488                 pbus_size_io(bus);
 489                 /* If the bridge supports prefetchable range, size it
 490                    separately. If it doesn't, or its prefetchable window
 491                    has already been allocated by arch code, try
 492                    non-prefetchable range for both types of PCI memory
 493                    resources. */
 494                 mask = IORESOURCE_MEM;
 495                 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
 496                 if (pbus_size_mem(bus, prefmask, prefmask))
 497                         mask = prefmask; /* Success, size non-prefetch only. */
 498                 pbus_size_mem(bus, mask, IORESOURCE_MEM);
 499                 break;
 500         }
 501 }
 502 EXPORT_SYMBOL(pci_bus_size_bridges);
 503
 504 void __devinit
 505 pci_bus_assign_resources(struct pci_bus *bus)
 506 {
 507         struct pci_bus *b;
 508         struct pci_dev *dev;
 509
 510         pbus_assign_resources_sorted(bus);
 511
 512         if (bus->bridge_ctl & PCI_BRIDGE_CTL_VGA) {
 513                 /* Propagate presence of the VGA to upstream bridges */
 514                 for (b = bus; b->parent; b = b->parent) {
 515                         b->bridge_ctl |= PCI_BRIDGE_CTL_VGA;
 516                 }
 517         }
 518         list_for_each_entry(dev, &bus->devices, bus_list) {
 519                 b = dev->subordinate;
 520                 if (!b)
 521                         continue;
 522
 523                 pci_bus_assign_resources(b);
 524
 525                 switch (dev->class >> 8) {
 526                 case PCI_CLASS_BRIDGE_PCI:
 527                         pci_setup_bridge(b);
 528                         break;
 529
 530                 case PCI_CLASS_BRIDGE_CARDBUS:
 531                         pci_setup_cardbus(b);
 532                         break;
 533
 534                 default:
 535                         printk(KERN_INFO "PCI: not setting up bridge %s "
 536                                "for bus %d\n", pci_name(dev), b->number);
 537                         break;
 538                 }
 539         }
 540 }
 541 EXPORT_SYMBOL(pci_bus_assign_resources);
 542
 543 void __init
 544 pci_assign_unassigned_resources(void)
 545 {
 546         struct pci_bus *bus;
 547
 548         /* Depth first, calculate sizes and alignments of all
 549            subordinate buses. */
 550         list_for_each_entry(bus, &pci_root_buses, node) {
 551                 pci_bus_size_bridges(bus);
 552         }
 553         /* Depth last, allocate resources and update the hardware. */
 554         list_for_each_entry(bus, &pci_root_buses, node) {
 555                 pci_bus_assign_resources(bus);
 556                 pci_enable_bridges(bus);
 557         }
 558 }