2 * drivers/pci/setup-res.c
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
9 * Support routines for initializing a PCI subsystem.
12 /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
15 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/export.h>
22 #include <linux/pci.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/cache.h>
26 #include <linux/slab.h>
30 void pci_update_resource(struct pci_dev
*dev
, int resno
)
32 struct pci_bus_region region
;
37 enum pci_bar_type type
;
38 struct resource
*res
= dev
->resource
+ resno
;
41 * Ignore resources for unimplemented BARs and unused resource slots
48 * Ignore non-moveable resources. This might be legacy resources for
49 * which no functional BAR register exists or another important
50 * system resource we shouldn't move around.
52 if (res
->flags
& IORESOURCE_PCI_FIXED
)
55 pcibios_resource_to_bus(dev
, ®ion
, res
);
57 new = region
.start
| (res
->flags
& PCI_REGION_FLAG_MASK
);
58 if (res
->flags
& IORESOURCE_IO
)
59 mask
= (u32
)PCI_BASE_ADDRESS_IO_MASK
;
61 mask
= (u32
)PCI_BASE_ADDRESS_MEM_MASK
;
63 reg
= pci_resource_bar(dev
, resno
, &type
);
66 if (type
!= pci_bar_unknown
) {
67 if (!(res
->flags
& IORESOURCE_ROM_ENABLE
))
69 new |= PCI_ROM_ADDRESS_ENABLE
;
73 * We can't update a 64-bit BAR atomically, so when possible,
74 * disable decoding so that a half-updated BAR won't conflict
75 * with another device.
77 disable
= (res
->flags
& IORESOURCE_MEM_64
) && !dev
->mmio_always_on
;
79 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
80 pci_write_config_word(dev
, PCI_COMMAND
,
81 cmd
& ~PCI_COMMAND_MEMORY
);
84 pci_write_config_dword(dev
, reg
, new);
85 pci_read_config_dword(dev
, reg
, &check
);
87 if ((new ^ check
) & mask
) {
88 dev_err(&dev
->dev
, "BAR %d: error updating (%#08x != %#08x)\n",
92 if (res
->flags
& IORESOURCE_MEM_64
) {
93 new = region
.start
>> 16 >> 16;
94 pci_write_config_dword(dev
, reg
+ 4, new);
95 pci_read_config_dword(dev
, reg
+ 4, &check
);
97 dev_err(&dev
->dev
, "BAR %d: error updating "
98 "(high %#08x != %#08x)\n", resno
, new, check
);
103 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
105 res
->flags
&= ~IORESOURCE_UNSET
;
106 dev_dbg(&dev
->dev
, "BAR %d: set to %pR (PCI address [%#llx-%#llx])\n",
107 resno
, res
, (unsigned long long)region
.start
,
108 (unsigned long long)region
.end
);
111 int pci_claim_resource(struct pci_dev
*dev
, int resource
)
113 struct resource
*res
= &dev
->resource
[resource
];
114 struct resource
*root
, *conflict
;
116 root
= pci_find_parent_resource(dev
, res
);
118 dev_info(&dev
->dev
, "no compatible bridge window for %pR\n",
123 conflict
= request_resource_conflict(root
, res
);
126 "address space collision: %pR conflicts with %s %pR\n",
127 res
, conflict
->name
, conflict
);
133 EXPORT_SYMBOL(pci_claim_resource
);
135 void pci_disable_bridge_window(struct pci_dev
*dev
)
137 dev_info(&dev
->dev
, "disabling bridge mem windows\n");
139 /* MMIO Base/Limit */
140 pci_write_config_dword(dev
, PCI_MEMORY_BASE
, 0x0000fff0);
142 /* Prefetchable MMIO Base/Limit */
143 pci_write_config_dword(dev
, PCI_PREF_LIMIT_UPPER32
, 0);
144 pci_write_config_dword(dev
, PCI_PREF_MEMORY_BASE
, 0x0000fff0);
145 pci_write_config_dword(dev
, PCI_PREF_BASE_UPPER32
, 0xffffffff);
148 static int __pci_assign_resource(struct pci_bus
*bus
, struct pci_dev
*dev
,
149 int resno
, resource_size_t size
, resource_size_t align
)
151 struct resource
*res
= dev
->resource
+ resno
;
155 min
= (res
->flags
& IORESOURCE_IO
) ? PCIBIOS_MIN_IO
: PCIBIOS_MIN_MEM
;
157 /* First, try exact prefetching match.. */
158 ret
= pci_bus_alloc_resource(bus
, res
, size
, align
, min
,
160 pcibios_align_resource
, dev
);
162 if (ret
< 0 && (res
->flags
& IORESOURCE_PREFETCH
)) {
166 * But a prefetching area can handle a non-prefetching
167 * window (it will just not perform as well).
169 ret
= pci_bus_alloc_resource(bus
, res
, size
, align
, min
, 0,
170 pcibios_align_resource
, dev
);
176 * Generic function that returns a value indicating that the device's
177 * original BIOS BAR address was not saved and so is not available for
180 * Can be over-ridden by architecture specific code that implements
181 * reinstatement functionality rather than leaving it disabled when
182 * normal allocation attempts fail.
184 resource_size_t __weak
pcibios_retrieve_fw_addr(struct pci_dev
*dev
, int idx
)
189 static int pci_revert_fw_address(struct resource
*res
, struct pci_dev
*dev
,
190 int resno
, resource_size_t size
)
192 struct resource
*root
, *conflict
;
193 resource_size_t fw_addr
, start
, end
;
196 fw_addr
= pcibios_retrieve_fw_addr(dev
, resno
);
202 res
->start
= fw_addr
;
203 res
->end
= res
->start
+ size
- 1;
205 root
= pci_find_parent_resource(dev
, res
);
207 if (res
->flags
& IORESOURCE_IO
)
208 root
= &ioport_resource
;
210 root
= &iomem_resource
;
213 dev_info(&dev
->dev
, "BAR %d: trying firmware assignment %pR\n",
215 conflict
= request_resource_conflict(root
, res
);
218 "BAR %d: %pR conflicts with %s %pR\n", resno
,
219 res
, conflict
->name
, conflict
);
227 static int _pci_assign_resource(struct pci_dev
*dev
, int resno
, int size
, resource_size_t min_align
)
229 struct resource
*res
= dev
->resource
+ resno
;
235 while ((ret
= __pci_assign_resource(bus
, dev
, resno
, size
, min_align
))) {
236 if (!bus
->parent
|| !bus
->self
->transparent
)
242 if (res
->flags
& IORESOURCE_MEM
)
243 if (res
->flags
& IORESOURCE_PREFETCH
)
247 else if (res
->flags
& IORESOURCE_IO
)
252 "BAR %d: can't assign %s (size %#llx)\n",
253 resno
, type
, (unsigned long long) resource_size(res
));
259 int pci_reassign_resource(struct pci_dev
*dev
, int resno
, resource_size_t addsize
,
260 resource_size_t min_align
)
262 struct resource
*res
= dev
->resource
+ resno
;
263 resource_size_t new_size
;
267 dev_info(&dev
->dev
, "BAR %d: can't reassign an unassigned resource %pR "
272 /* already aligned with min_align */
273 new_size
= resource_size(res
) + addsize
;
274 ret
= _pci_assign_resource(dev
, resno
, new_size
, min_align
);
276 res
->flags
&= ~IORESOURCE_STARTALIGN
;
277 dev_info(&dev
->dev
, "BAR %d: reassigned %pR\n", resno
, res
);
278 if (resno
< PCI_BRIDGE_RESOURCES
)
279 pci_update_resource(dev
, resno
);
284 int pci_assign_resource(struct pci_dev
*dev
, int resno
)
286 struct resource
*res
= dev
->resource
+ resno
;
287 resource_size_t align
, size
;
291 align
= pci_resource_alignment(dev
, res
);
293 dev_info(&dev
->dev
, "BAR %d: can't assign %pR "
294 "(bogus alignment)\n", resno
, res
);
299 size
= resource_size(res
);
300 ret
= _pci_assign_resource(dev
, resno
, size
, align
);
303 * If we failed to assign anything, let's try the address
304 * where firmware left it. That at least has a chance of
305 * working, which is better than just leaving it disabled.
308 ret
= pci_revert_fw_address(res
, dev
, resno
, size
);
311 res
->flags
&= ~IORESOURCE_STARTALIGN
;
312 dev_info(&dev
->dev
, "BAR %d: assigned %pR\n", resno
, res
);
313 if (resno
< PCI_BRIDGE_RESOURCES
)
314 pci_update_resource(dev
, resno
);
319 int pci_enable_resources(struct pci_dev
*dev
, int mask
)
325 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
328 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
329 if (!(mask
& (1 << i
)))
332 r
= &dev
->resource
[i
];
334 if (!(r
->flags
& (IORESOURCE_IO
| IORESOURCE_MEM
)))
336 if ((i
== PCI_ROM_RESOURCE
) &&
337 (!(r
->flags
& IORESOURCE_ROM_ENABLE
)))
341 dev_err(&dev
->dev
, "device not available "
342 "(can't reserve %pR)\n", r
);
346 if (r
->flags
& IORESOURCE_IO
)
347 cmd
|= PCI_COMMAND_IO
;
348 if (r
->flags
& IORESOURCE_MEM
)
349 cmd
|= PCI_COMMAND_MEMORY
;
352 if (cmd
!= old_cmd
) {
353 dev_info(&dev
->dev
, "enabling device (%04x -> %04x)\n",
355 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);