drivers/pci/setup-res.c

   1 /*
   2  *      drivers/pci/setup-res.c
   3  *
   4  * Extruded from code written by
   5  *      Dave Rusling (david.rusling@reo.mts.dec.com)
   6  *      David Mosberger (davidm@cs.arizona.edu)
   7  *      David Miller (davem@redhat.com)
   8  *
   9  * Support routines for initializing a PCI subsystem.
  10  */
  11
  12 /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
  13
  14 /*
  15  * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
  16  *           Resource sorting
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/export.h>
  21 #include <linux/pci.h>
  22 #include <linux/errno.h>
  23 #include <linux/ioport.h>
  24 #include <linux/cache.h>
  25 #include <linux/slab.h>
  26 #include "pci.h"
  27
  28
  29 void pci_update_resource(struct pci_dev *dev, int resno)
  30 {
  31         struct pci_bus_region region;
  32         bool disable;
  33         u16 cmd;
  34         u32 new, check, mask;
  35         int reg;
  36         enum pci_bar_type type;
  37         struct resource *res = dev->resource + resno;
  38
  39         /*
  40          * Ignore resources for unimplemented BARs and unused resource slots
  41          * for 64 bit BARs.
  42          */
  43         if (!res->flags)
  44                 return;
  45
  46         if (res->flags & IORESOURCE_UNSET)
  47                 return;
  48
  49         /*
  50          * Ignore non-moveable resources.  This might be legacy resources for
  51          * which no functional BAR register exists or another important
  52          * system resource we shouldn't move around.
  53          */
  54         if (res->flags & IORESOURCE_PCI_FIXED)
  55                 return;
  56
  57         pcibios_resource_to_bus(dev->bus, &region, res);
  58
  59         new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
  60         if (res->flags & IORESOURCE_IO)
  61                 mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
  62         else
  63                 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
  64
  65         reg = pci_resource_bar(dev, resno, &type);
  66         if (!reg)
  67                 return;
  68         if (type != pci_bar_unknown) {
  69                 if (!(res->flags & IORESOURCE_ROM_ENABLE))
  70                         return;
  71                 new |= PCI_ROM_ADDRESS_ENABLE;
  72         }
  73
  74         /*
  75          * We can't update a 64-bit BAR atomically, so when possible,
  76          * disable decoding so that a half-updated BAR won't conflict
  77          * with another device.
  78          */
  79         disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
  80         if (disable) {
  81                 pci_read_config_word(dev, PCI_COMMAND, &cmd);
  82                 pci_write_config_word(dev, PCI_COMMAND,
  83                                       cmd & ~PCI_COMMAND_MEMORY);
  84         }
  85
  86         pci_write_config_dword(dev, reg, new);
  87         pci_read_config_dword(dev, reg, &check);
  88
  89         if ((new ^ check) & mask) {
  90                 dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
  91                         resno, new, check);
  92         }
  93
  94         if (res->flags & IORESOURCE_MEM_64) {
  95                 new = region.start >> 16 >> 16;
  96                 pci_write_config_dword(dev, reg + 4, new);
  97                 pci_read_config_dword(dev, reg + 4, &check);
  98                 if (check != new) {
  99                         dev_err(&dev->dev, "BAR %d: error updating (high %#08x != %#08x)\n",
 100                                 resno, new, check);
 101                 }
 102         }
 103
 104         if (disable)
 105                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 106 }
 107
 108 int pci_claim_resource(struct pci_dev *dev, int resource)
 109 {
 110         struct resource *res = &dev->resource[resource];
 111         struct resource *root, *conflict;
 112
 113         if (res->flags & IORESOURCE_UNSET) {
 114                 dev_info(&dev->dev, "can't claim BAR %d %pR: no address assigned\n",
 115                          resource, res);
 116                 return -EINVAL;
 117         }
 118
 119         root = pci_find_parent_resource(dev, res);
 120         if (!root) {
 121                 dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n",
 122                          resource, res);
 123                 res->flags |= IORESOURCE_UNSET;
 124                 return -EINVAL;
 125         }
 126
 127         conflict = request_resource_conflict(root, res);
 128         if (conflict) {
 129                 dev_info(&dev->dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
 130                          resource, res, conflict->name, conflict);
 131                 res->flags |= IORESOURCE_UNSET;
 132                 return -EBUSY;
 133         }
 134
 135         return 0;
 136 }
 137 EXPORT_SYMBOL(pci_claim_resource);
 138
 139 void pci_disable_bridge_window(struct pci_dev *dev)
 140 {
 141         dev_info(&dev->dev, "disabling bridge mem windows\n");
 142
 143         /* MMIO Base/Limit */
 144         pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
 145
 146         /* Prefetchable MMIO Base/Limit */
 147         pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
 148         pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
 149         pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
 150 }
 151
 152 /*
 153  * Generic function that returns a value indicating that the device's
 154  * original BIOS BAR address was not saved and so is not available for
 155  * reinstatement.
 156  *
 157  * Can be over-ridden by architecture specific code that implements
 158  * reinstatement functionality rather than leaving it disabled when
 159  * normal allocation attempts fail.
 160  */
 161 resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
 162 {
 163         return 0;
 164 }
 165
 166 static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
 167                 int resno, resource_size_t size)
 168 {
 169         struct resource *root, *conflict;
 170         resource_size_t fw_addr, start, end;
 171
 172         fw_addr = pcibios_retrieve_fw_addr(dev, resno);
 173         if (!fw_addr)
 174                 return -ENOMEM;
 175
 176         start = res->start;
 177         end = res->end;
 178         res->start = fw_addr;
 179         res->end = res->start + size - 1;
 180         res->flags &= ~IORESOURCE_UNSET;
 181
 182         root = pci_find_parent_resource(dev, res);
 183         if (!root) {
 184                 if (res->flags & IORESOURCE_IO)
 185                         root = &ioport_resource;
 186                 else
 187                         root = &iomem_resource;
 188         }
 189
 190         dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
 191                  resno, res);
 192         conflict = request_resource_conflict(root, res);
 193         if (conflict) {
 194                 dev_info(&dev->dev, "BAR %d: %pR conflicts with %s %pR\n",
 195                          resno, res, conflict->name, conflict);
 196                 res->start = start;
 197                 res->end = end;
 198                 res->flags |= IORESOURCE_UNSET;
 199                 return -EBUSY;
 200         }
 201         return 0;
 202 }
 203
 204 static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
 205                 int resno, resource_size_t size, resource_size_t align)
 206 {
 207         struct resource *res = dev->resource + resno;
 208         resource_size_t min;
 209         int ret;
 210
 211         min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
 212
 213         /*
 214          * First, try exact prefetching match.  Even if a 64-bit
 215          * prefetchable bridge window is below 4GB, we can't put a 32-bit
 216          * prefetchable resource in it because pbus_size_mem() assumes a
 217          * 64-bit window will contain no 32-bit resources.  If we assign
 218          * things differently than they were sized, not everything will fit.
 219          */
 220         ret = pci_bus_alloc_resource(bus, res, size, align, min,
 221                                      IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
 222                                      pcibios_align_resource, dev);
 223         if (ret == 0)
 224                 return 0;
 225
 226         /*
 227          * If the prefetchable window is only 32 bits wide, we can put
 228          * 64-bit prefetchable resources in it.
 229          */
 230         if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
 231              (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
 232                 ret = pci_bus_alloc_resource(bus, res, size, align, min,
 233                                              IORESOURCE_PREFETCH,
 234                                              pcibios_align_resource, dev);
 235                 if (ret == 0)
 236                         return 0;
 237         }
 238
 239         /*
 240          * If we didn't find a better match, we can put any memory resource
 241          * in a non-prefetchable window.  If this resource is 32 bits and
 242          * non-prefetchable, the first call already tried the only possibility
 243          * so we don't need to try again.
 244          */
 245         if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
 246                 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
 247                                              pcibios_align_resource, dev);
 248
 249         return ret;
 250 }
 251
 252 static int _pci_assign_resource(struct pci_dev *dev, int resno,
 253                                 resource_size_t size, resource_size_t min_align)
 254 {
 255         struct pci_bus *bus;
 256         int ret;
 257
 258         bus = dev->bus;
 259         while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
 260                 if (!bus->parent || !bus->self->transparent)
 261                         break;
 262                 bus = bus->parent;
 263         }
 264
 265         return ret;
 266 }
 267
 268 int pci_assign_resource(struct pci_dev *dev, int resno)
 269 {
 270         struct resource *res = dev->resource + resno;
 271         resource_size_t align, size;
 272         int ret;
 273
 274         res->flags |= IORESOURCE_UNSET;
 275         align = pci_resource_alignment(dev, res);
 276         if (!align) {
 277                 dev_info(&dev->dev, "BAR %d: can't assign %pR (bogus alignment)\n",
 278                          resno, res);
 279                 return -EINVAL;
 280         }
 281
 282         size = resource_size(res);
 283         ret = _pci_assign_resource(dev, resno, size, align);
 284
 285         /*
 286          * If we failed to assign anything, let's try the address
 287          * where firmware left it.  That at least has a chance of
 288          * working, which is better than just leaving it disabled.
 289          */
 290         if (ret < 0) {
 291                 dev_info(&dev->dev, "BAR %d: no space for %pR\n", resno, res);
 292                 ret = pci_revert_fw_address(res, dev, resno, size);
 293         }
 294
 295         if (ret < 0) {
 296                 dev_info(&dev->dev, "BAR %d: failed to assign %pR\n", resno,
 297                          res);
 298                 return ret;
 299         }
 300
 301         res->flags &= ~IORESOURCE_UNSET;
 302         res->flags &= ~IORESOURCE_STARTALIGN;
 303         dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
 304         if (resno < PCI_BRIDGE_RESOURCES)
 305                 pci_update_resource(dev, resno);
 306
 307         return 0;
 308 }
 309 EXPORT_SYMBOL(pci_assign_resource);
 310
 311 int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
 312                         resource_size_t min_align)
 313 {
 314         struct resource *res = dev->resource + resno;
 315         unsigned long flags;
 316         resource_size_t new_size;
 317         int ret;
 318
 319         flags = res->flags;
 320         res->flags |= IORESOURCE_UNSET;
 321         if (!res->parent) {
 322                 dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR\n",
 323                          resno, res);
 324                 return -EINVAL;
 325         }
 326
 327         /* already aligned with min_align */
 328         new_size = resource_size(res) + addsize;
 329         ret = _pci_assign_resource(dev, resno, new_size, min_align);
 330         if (ret) {
 331                 res->flags = flags;
 332                 dev_info(&dev->dev, "BAR %d: %pR (failed to expand by %#llx)\n",
 333                          resno, res, (unsigned long long) addsize);
 334                 return ret;
 335         }
 336
 337         res->flags &= ~IORESOURCE_UNSET;
 338         res->flags &= ~IORESOURCE_STARTALIGN;
 339         dev_info(&dev->dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
 340                  resno, res, (unsigned long long) addsize);
 341         if (resno < PCI_BRIDGE_RESOURCES)
 342                 pci_update_resource(dev, resno);
 343
 344         return 0;
 345 }
 346
 347 int pci_enable_resources(struct pci_dev *dev, int mask)
 348 {
 349         u16 cmd, old_cmd;
 350         int i;
 351         struct resource *r;
 352
 353         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 354         old_cmd = cmd;
 355
 356         for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 357                 if (!(mask & (1 << i)))
 358                         continue;
 359
 360                 r = &dev->resource[i];
 361
 362                 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
 363                         continue;
 364                 if ((i == PCI_ROM_RESOURCE) &&
 365                                 (!(r->flags & IORESOURCE_ROM_ENABLE)))
 366                         continue;
 367
 368                 if (r->flags & IORESOURCE_UNSET) {
 369                         dev_err(&dev->dev, "can't enable device: BAR %d %pR not assigned\n",
 370                                 i, r);
 371                         return -EINVAL;
 372                 }
 373
 374                 if (!r->parent) {
 375                         dev_err(&dev->dev, "can't enable device: BAR %d %pR not claimed\n",
 376                                 i, r);
 377                         return -EINVAL;
 378                 }
 379
 380                 if (r->flags & IORESOURCE_IO)
 381                         cmd |= PCI_COMMAND_IO;
 382                 if (r->flags & IORESOURCE_MEM)
 383                         cmd |= PCI_COMMAND_MEMORY;
 384         }
 385
 386         if (cmd != old_cmd) {
 387                 dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
 388                          old_cmd, cmd);
 389                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 390         }
 391         return 0;
 392 }