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pcmcia: remove Motorola MBX860 support
[deliverable/linux.git] / drivers / pcmcia / m8xx_pcmcia.c
1 /*
2 * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series.
3 *
4 * (C) 1999-2000 Magnus Damm <damm@opensource.se>
5 * (C) 2001-2002 Montavista Software, Inc.
6 * <mlocke@mvista.com>
7 *
8 * Support for two slots by Cyclades Corporation
9 * <oliver.kurth@cyclades.de>
10 * Further fixes, v2.6 kernel port
11 * <marcelo.tosatti@cyclades.com>
12 *
13 * Some fixes, additions (C) 2005-2007 Montavista Software, Inc.
14 * <vbordug@ru.mvista.com>
15 *
16 * "The ExCA standard specifies that socket controllers should provide
17 * two IO and five memory windows per socket, which can be independently
18 * configured and positioned in the host address space and mapped to
19 * arbitrary segments of card address space. " - David A Hinds. 1999
20 *
21 * This controller does _not_ meet the ExCA standard.
22 *
23 * m8xx pcmcia controller brief info:
24 * + 8 windows (attrib, mem, i/o)
25 * + up to two slots (SLOT_A and SLOT_B)
26 * + inputpins, outputpins, event and mask registers.
27 * - no offset register. sigh.
28 *
29 * Because of the lacking offset register we must map the whole card.
30 * We assign each memory window PCMCIA_MEM_WIN_SIZE address space.
31 * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO
32 * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE.
33 * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE.
34 * They are maximum 64KByte each...
35 */
36
37 #include <linux/module.h>
38 #include <linux/init.h>
39 #include <linux/types.h>
40 #include <linux/fcntl.h>
41 #include <linux/string.h>
42
43 #include <linux/kernel.h>
44 #include <linux/errno.h>
45 #include <linux/timer.h>
46 #include <linux/ioport.h>
47 #include <linux/delay.h>
48 #include <linux/interrupt.h>
49 #include <linux/fsl_devices.h>
50 #include <linux/bitops.h>
51 #include <linux/of_device.h>
52 #include <linux/of_platform.h>
53
54 #include <asm/io.h>
55 #include <asm/time.h>
56 #include <asm/mpc8xx.h>
57 #include <asm/8xx_immap.h>
58 #include <asm/irq.h>
59 #include <asm/fs_pd.h>
60
61 #include <pcmcia/ss.h>
62
63 #define pcmcia_info(args...) printk(KERN_INFO "m8xx_pcmcia: "args)
64 #define pcmcia_error(args...) printk(KERN_ERR "m8xx_pcmcia: "args)
65
66 static const char *version = "Version 0.06, Aug 2005";
67 MODULE_LICENSE("Dual MPL/GPL");
68
69 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
70
71 /* The RPX series use SLOT_B */
72 #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
73 #define CONFIG_PCMCIA_SLOT_B
74 #define CONFIG_BD_IS_MHZ
75 #endif
76
77 /* The ADS board use SLOT_A */
78 #ifdef CONFIG_ADS
79 #define CONFIG_PCMCIA_SLOT_A
80 #define CONFIG_BD_IS_MHZ
81 #endif
82
83 /* The FADS series are a mess */
84 #ifdef CONFIG_FADS
85 #if defined(CONFIG_MPC860T) || defined(CONFIG_MPC860) || defined(CONFIG_MPC821)
86 #define CONFIG_PCMCIA_SLOT_A
87 #else
88 #define CONFIG_PCMCIA_SLOT_B
89 #endif
90 #endif
91
92 #if defined(CONFIG_MPC885ADS)
93 #define CONFIG_PCMCIA_SLOT_A
94 #define PCMCIA_GLITCHY_CD
95 #endif
96
97 /* Cyclades ACS uses both slots */
98 #ifdef CONFIG_PRxK
99 #define CONFIG_PCMCIA_SLOT_A
100 #define CONFIG_PCMCIA_SLOT_B
101 #endif
102
103 #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
104
105 #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
106
107 #define PCMCIA_SOCKETS_NO 2
108 /* We have only 8 windows, dualsocket support will be limited. */
109 #define PCMCIA_MEM_WIN_NO 2
110 #define PCMCIA_IO_WIN_NO 2
111 #define PCMCIA_SLOT_MSG "SLOT_A and SLOT_B"
112
113 #elif defined(CONFIG_PCMCIA_SLOT_A) || defined(CONFIG_PCMCIA_SLOT_B)
114
115 #define PCMCIA_SOCKETS_NO 1
116 /* full support for one slot */
117 #define PCMCIA_MEM_WIN_NO 5
118 #define PCMCIA_IO_WIN_NO 2
119
120 /* define _slot_ to be able to optimize macros */
121
122 #ifdef CONFIG_PCMCIA_SLOT_A
123 #define _slot_ 0
124 #define PCMCIA_SLOT_MSG "SLOT_A"
125 #else
126 #define _slot_ 1
127 #define PCMCIA_SLOT_MSG "SLOT_B"
128 #endif
129
130 #else
131 #error m8xx_pcmcia: Bad configuration!
132 #endif
133
134 /* ------------------------------------------------------------------------- */
135
136 #define PCMCIA_MEM_WIN_BASE 0xe0000000 /* base address for memory window 0 */
137 #define PCMCIA_MEM_WIN_SIZE 0x04000000 /* each memory window is 64 MByte */
138 #define PCMCIA_IO_WIN_BASE _IO_BASE /* base address for io window 0 */
139 /* ------------------------------------------------------------------------- */
140
141 static int pcmcia_schlvl;
142
143 static DEFINE_SPINLOCK(events_lock);
144
145 #define PCMCIA_SOCKET_KEY_5V 1
146 #define PCMCIA_SOCKET_KEY_LV 2
147
148 /* look up table for pgcrx registers */
149 static u32 *m8xx_pgcrx[2];
150
151 /*
152 * This structure is used to address each window in the PCMCIA controller.
153 *
154 * Keep in mind that we assume that pcmcia_win[n+1] is mapped directly
155 * after pcmcia_win[n]...
156 */
157
158 struct pcmcia_win {
159 u32 br;
160 u32 or;
161 };
162
163 /*
164 * For some reason the hardware guys decided to make both slots share
165 * some registers.
166 *
167 * Could someone invent object oriented hardware ?
168 *
169 * The macros are used to get the right bit from the registers.
170 * SLOT_A : slot = 0
171 * SLOT_B : slot = 1
172 */
173
174 #define M8XX_PCMCIA_VS1(slot) (0x80000000 >> (slot << 4))
175 #define M8XX_PCMCIA_VS2(slot) (0x40000000 >> (slot << 4))
176 #define M8XX_PCMCIA_VS_MASK(slot) (0xc0000000 >> (slot << 4))
177 #define M8XX_PCMCIA_VS_SHIFT(slot) (30 - (slot << 4))
178
179 #define M8XX_PCMCIA_WP(slot) (0x20000000 >> (slot << 4))
180 #define M8XX_PCMCIA_CD2(slot) (0x10000000 >> (slot << 4))
181 #define M8XX_PCMCIA_CD1(slot) (0x08000000 >> (slot << 4))
182 #define M8XX_PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4))
183 #define M8XX_PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4))
184 #define M8XX_PCMCIA_RDY(slot) (0x01000000 >> (slot << 4))
185 #define M8XX_PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4))
186 #define M8XX_PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4))
187 #define M8XX_PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4))
188 #define M8XX_PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4))
189 #define M8XX_PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4))
190
191 #define M8XX_PCMCIA_POR_VALID 0x00000001
192 #define M8XX_PCMCIA_POR_WRPROT 0x00000002
193 #define M8XX_PCMCIA_POR_ATTRMEM 0x00000010
194 #define M8XX_PCMCIA_POR_IO 0x00000018
195 #define M8XX_PCMCIA_POR_16BIT 0x00000040
196
197 #define M8XX_PGCRX(slot) m8xx_pgcrx[slot]
198
199 #define M8XX_PGCRX_CXOE 0x00000080
200 #define M8XX_PGCRX_CXRESET 0x00000040
201
202 /* we keep one lookup table per socket to check flags */
203
204 #define PCMCIA_EVENTS_MAX 5 /* 4 max at a time + termination */
205
206 struct event_table {
207 u32 regbit;
208 u32 eventbit;
209 };
210
211 static const char driver_name[] = "m8xx-pcmcia";
212
213 struct socket_info {
214 void (*handler) (void *info, u32 events);
215 void *info;
216
217 u32 slot;
218 pcmconf8xx_t *pcmcia;
219 u32 bus_freq;
220 int hwirq;
221
222 socket_state_t state;
223 struct pccard_mem_map mem_win[PCMCIA_MEM_WIN_NO];
224 struct pccard_io_map io_win[PCMCIA_IO_WIN_NO];
225 struct event_table events[PCMCIA_EVENTS_MAX];
226 struct pcmcia_socket socket;
227 };
228
229 static struct socket_info socket[PCMCIA_SOCKETS_NO];
230
231 /*
232 * Search this table to see if the windowsize is
233 * supported...
234 */
235
236 #define M8XX_SIZES_NO 32
237
238 static const u32 m8xx_size_to_gray[M8XX_SIZES_NO] = {
239 0x00000001, 0x00000002, 0x00000008, 0x00000004,
240 0x00000080, 0x00000040, 0x00000010, 0x00000020,
241 0x00008000, 0x00004000, 0x00001000, 0x00002000,
242 0x00000100, 0x00000200, 0x00000800, 0x00000400,
243
244 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff,
245 0x01000000, 0x02000000, 0xffffffff, 0x04000000,
246 0x00010000, 0x00020000, 0x00080000, 0x00040000,
247 0x00800000, 0x00400000, 0x00100000, 0x00200000
248 };
249
250 /* ------------------------------------------------------------------------- */
251
252 static irqreturn_t m8xx_interrupt(int irq, void *dev);
253
254 #define PCMCIA_BMT_LIMIT (15*4) /* Bus Monitor Timeout value */
255
256 /* ------------------------------------------------------------------------- */
257 /* board specific stuff: */
258 /* voltage_set(), hardware_enable() and hardware_disable() */
259 /* ------------------------------------------------------------------------- */
260 /* RPX Boards from Embedded Planet */
261
262 #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
263
264 /* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks.
265 * SYPCR is write once only, therefore must the slowest memory be faster
266 * than the bus monitor or we will get a machine check due to the bus timeout.
267 */
268
269 #define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE"
270
271 #undef PCMCIA_BMT_LIMIT
272 #define PCMCIA_BMT_LIMIT (6*8)
273
274 static int voltage_set(int slot, int vcc, int vpp)
275 {
276 u32 reg = 0;
277
278 switch (vcc) {
279 case 0:
280 break;
281 case 33:
282 reg |= BCSR1_PCVCTL4;
283 break;
284 case 50:
285 reg |= BCSR1_PCVCTL5;
286 break;
287 default:
288 return 1;
289 }
290
291 switch (vpp) {
292 case 0:
293 break;
294 case 33:
295 case 50:
296 if (vcc == vpp)
297 reg |= BCSR1_PCVCTL6;
298 else
299 return 1;
300 break;
301 case 120:
302 reg |= BCSR1_PCVCTL7;
303 default:
304 return 1;
305 }
306
307 if (!((vcc == 50) || (vcc == 0)))
308 return 1;
309
310 /* first, turn off all power */
311
312 out_be32(((u32 *) RPX_CSR_ADDR),
313 in_be32(((u32 *) RPX_CSR_ADDR)) & ~(BCSR1_PCVCTL4 |
314 BCSR1_PCVCTL5 |
315 BCSR1_PCVCTL6 |
316 BCSR1_PCVCTL7));
317
318 /* enable new powersettings */
319
320 out_be32(((u32 *) RPX_CSR_ADDR), in_be32(((u32 *) RPX_CSR_ADDR)) | reg);
321
322 return 0;
323 }
324
325 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
326 #define hardware_enable(_slot_) /* No hardware to enable */
327 #define hardware_disable(_slot_) /* No hardware to disable */
328
329 #endif /* CONFIG_RPXCLASSIC */
330
331 /* FADS Boards from Motorola */
332
333 #if defined(CONFIG_FADS)
334
335 #define PCMCIA_BOARD_MSG "FADS"
336
337 static int voltage_set(int slot, int vcc, int vpp)
338 {
339 u32 reg = 0;
340
341 switch (vcc) {
342 case 0:
343 break;
344 case 33:
345 reg |= BCSR1_PCCVCC0;
346 break;
347 case 50:
348 reg |= BCSR1_PCCVCC1;
349 break;
350 default:
351 return 1;
352 }
353
354 switch (vpp) {
355 case 0:
356 break;
357 case 33:
358 case 50:
359 if (vcc == vpp)
360 reg |= BCSR1_PCCVPP1;
361 else
362 return 1;
363 break;
364 case 120:
365 if ((vcc == 33) || (vcc == 50))
366 reg |= BCSR1_PCCVPP0;
367 else
368 return 1;
369 default:
370 return 1;
371 }
372
373 /* first, turn off all power */
374 out_be32((u32 *) BCSR1,
375 in_be32((u32 *) BCSR1) & ~(BCSR1_PCCVCC_MASK |
376 BCSR1_PCCVPP_MASK));
377
378 /* enable new powersettings */
379 out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) | reg);
380
381 return 0;
382 }
383
384 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
385
386 static void hardware_enable(int slot)
387 {
388 out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) & ~BCSR1_PCCEN);
389 }
390
391 static void hardware_disable(int slot)
392 {
393 out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) | BCSR1_PCCEN);
394 }
395
396 #endif
397
398 /* MPC885ADS Boards */
399
400 #if defined(CONFIG_MPC885ADS)
401
402 #define PCMCIA_BOARD_MSG "MPC885ADS"
403 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
404
405 static inline void hardware_enable(int slot)
406 {
407 m8xx_pcmcia_ops.hw_ctrl(slot, 1);
408 }
409
410 static inline void hardware_disable(int slot)
411 {
412 m8xx_pcmcia_ops.hw_ctrl(slot, 0);
413 }
414
415 static inline int voltage_set(int slot, int vcc, int vpp)
416 {
417 return m8xx_pcmcia_ops.voltage_set(slot, vcc, vpp);
418 }
419
420 #endif
421
422 #if defined(CONFIG_PRxK)
423 #include <asm/cpld.h>
424 extern volatile fpga_pc_regs *fpga_pc;
425
426 #define PCMCIA_BOARD_MSG "MPC855T"
427
428 static int voltage_set(int slot, int vcc, int vpp)
429 {
430 u8 reg = 0;
431 u8 regread;
432 cpld_regs *ccpld = get_cpld();
433
434 switch (vcc) {
435 case 0:
436 break;
437 case 33:
438 reg |= PCMCIA_VCC_33;
439 break;
440 case 50:
441 reg |= PCMCIA_VCC_50;
442 break;
443 default:
444 return 1;
445 }
446
447 switch (vpp) {
448 case 0:
449 break;
450 case 33:
451 case 50:
452 if (vcc == vpp)
453 reg |= PCMCIA_VPP_VCC;
454 else
455 return 1;
456 break;
457 case 120:
458 if ((vcc == 33) || (vcc == 50))
459 reg |= PCMCIA_VPP_12;
460 else
461 return 1;
462 default:
463 return 1;
464 }
465
466 reg = reg >> (slot << 2);
467 regread = in_8(&ccpld->fpga_pc_ctl);
468 if (reg !=
469 (regread & ((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2)))) {
470 /* enable new powersettings */
471 regread =
472 regread & ~((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >>
473 (slot << 2));
474 out_8(&ccpld->fpga_pc_ctl, reg | regread);
475 msleep(100);
476 }
477
478 return 0;
479 }
480
481 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_LV
482 #define hardware_enable(_slot_) /* No hardware to enable */
483 #define hardware_disable(_slot_) /* No hardware to disable */
484
485 #endif /* CONFIG_PRxK */
486
487 static u32 pending_events[PCMCIA_SOCKETS_NO];
488 static DEFINE_SPINLOCK(pending_event_lock);
489
490 static irqreturn_t m8xx_interrupt(int irq, void *dev)
491 {
492 struct socket_info *s;
493 struct event_table *e;
494 unsigned int i, events, pscr, pipr, per;
495 pcmconf8xx_t *pcmcia = socket[0].pcmcia;
496
497 pr_debug("m8xx_pcmcia: Interrupt!\n");
498 /* get interrupt sources */
499
500 pscr = in_be32(&pcmcia->pcmc_pscr);
501 pipr = in_be32(&pcmcia->pcmc_pipr);
502 per = in_be32(&pcmcia->pcmc_per);
503
504 for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
505 s = &socket[i];
506 e = &s->events[0];
507 events = 0;
508
509 while (e->regbit) {
510 if (pscr & e->regbit)
511 events |= e->eventbit;
512
513 e++;
514 }
515
516 /*
517 * report only if both card detect signals are the same
518 * not too nice done,
519 * we depend on that CD2 is the bit to the left of CD1...
520 */
521 if (events & SS_DETECT)
522 if (((pipr & M8XX_PCMCIA_CD2(i)) >> 1) ^
523 (pipr & M8XX_PCMCIA_CD1(i))) {
524 events &= ~SS_DETECT;
525 }
526 #ifdef PCMCIA_GLITCHY_CD
527 /*
528 * I've experienced CD problems with my ADS board.
529 * We make an extra check to see if there was a
530 * real change of Card detection.
531 */
532
533 if ((events & SS_DETECT) &&
534 ((pipr &
535 (M8XX_PCMCIA_CD2(i) | M8XX_PCMCIA_CD1(i))) == 0) &&
536 (s->state.Vcc | s->state.Vpp)) {
537 events &= ~SS_DETECT;
538 /*printk( "CD glitch workaround - CD = 0x%08x!\n",
539 (pipr & (M8XX_PCMCIA_CD2(i)
540 | M8XX_PCMCIA_CD1(i)))); */
541 }
542 #endif
543
544 /* call the handler */
545
546 pr_debug("m8xx_pcmcia: slot %u: events = 0x%02x, pscr = 0x%08x, "
547 "pipr = 0x%08x\n", i, events, pscr, pipr);
548
549 if (events) {
550 spin_lock(&pending_event_lock);
551 pending_events[i] |= events;
552 spin_unlock(&pending_event_lock);
553 /*
554 * Turn off RDY_L bits in the PER mask on
555 * CD interrupt receival.
556 *
557 * They can generate bad interrupts on the
558 * ACS4,8,16,32. - marcelo
559 */
560 per &= ~M8XX_PCMCIA_RDY_L(0);
561 per &= ~M8XX_PCMCIA_RDY_L(1);
562
563 out_be32(&pcmcia->pcmc_per, per);
564
565 if (events)
566 pcmcia_parse_events(&socket[i].socket, events);
567 }
568 }
569
570 /* clear the interrupt sources */
571 out_be32(&pcmcia->pcmc_pscr, pscr);
572
573 pr_debug("m8xx_pcmcia: Interrupt done.\n");
574
575 return IRQ_HANDLED;
576 }
577
578 static u32 m8xx_get_graycode(u32 size)
579 {
580 u32 k;
581
582 for (k = 0; k < M8XX_SIZES_NO; k++)
583 if (m8xx_size_to_gray[k] == size)
584 break;
585
586 if ((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1))
587 k = -1;
588
589 return k;
590 }
591
592 static u32 m8xx_get_speed(u32 ns, u32 is_io, u32 bus_freq)
593 {
594 u32 reg, clocks, psst, psl, psht;
595
596 if (!ns) {
597
598 /*
599 * We get called with IO maps setup to 0ns
600 * if not specified by the user.
601 * They should be 255ns.
602 */
603
604 if (is_io)
605 ns = 255;
606 else
607 ns = 100; /* fast memory if 0 */
608 }
609
610 /*
611 * In PSST, PSL, PSHT fields we tell the controller
612 * timing parameters in CLKOUT clock cycles.
613 * CLKOUT is the same as GCLK2_50.
614 */
615
616 /* how we want to adjust the timing - in percent */
617
618 #define ADJ 180 /* 80 % longer accesstime - to be sure */
619
620 clocks = ((bus_freq / 1000) * ns) / 1000;
621 clocks = (clocks * ADJ) / (100 * 1000);
622 if (clocks >= PCMCIA_BMT_LIMIT) {
623 printk("Max access time limit reached\n");
624 clocks = PCMCIA_BMT_LIMIT - 1;
625 }
626
627 psst = clocks / 7; /* setup time */
628 psht = clocks / 7; /* hold time */
629 psl = (clocks * 5) / 7; /* strobe length */
630
631 psst += clocks - (psst + psht + psl);
632
633 reg = psst << 12;
634 reg |= psl << 7;
635 reg |= psht << 16;
636
637 return reg;
638 }
639
640 static int m8xx_get_status(struct pcmcia_socket *sock, unsigned int *value)
641 {
642 int lsock = container_of(sock, struct socket_info, socket)->slot;
643 struct socket_info *s = &socket[lsock];
644 unsigned int pipr, reg;
645 pcmconf8xx_t *pcmcia = s->pcmcia;
646
647 pipr = in_be32(&pcmcia->pcmc_pipr);
648
649 *value = ((pipr & (M8XX_PCMCIA_CD1(lsock)
650 | M8XX_PCMCIA_CD2(lsock))) == 0) ? SS_DETECT : 0;
651 *value |= (pipr & M8XX_PCMCIA_WP(lsock)) ? SS_WRPROT : 0;
652
653 if (s->state.flags & SS_IOCARD)
654 *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_STSCHG : 0;
655 else {
656 *value |= (pipr & M8XX_PCMCIA_RDY(lsock)) ? SS_READY : 0;
657 *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_BATDEAD : 0;
658 *value |= (pipr & M8XX_PCMCIA_BVD2(lsock)) ? SS_BATWARN : 0;
659 }
660
661 if (s->state.Vcc | s->state.Vpp)
662 *value |= SS_POWERON;
663
664 /*
665 * Voltage detection:
666 * This driver only supports 16-Bit pc-cards.
667 * Cardbus is not handled here.
668 *
669 * To determine what voltage to use we must read the VS1 and VS2 pin.
670 * Depending on what socket type is present,
671 * different combinations mean different things.
672 *
673 * Card Key Socket Key VS1 VS2 Card Vcc for CIS parse
674 *
675 * 5V 5V, LV* NC NC 5V only 5V (if available)
676 *
677 * 5V 5V, LV* GND NC 5 or 3.3V as low as possible
678 *
679 * 5V 5V, LV* GND GND 5, 3.3, x.xV as low as possible
680 *
681 * LV* 5V - - shall not fit into socket
682 *
683 * LV* LV* GND NC 3.3V only 3.3V
684 *
685 * LV* LV* NC GND x.xV x.xV (if avail.)
686 *
687 * LV* LV* GND GND 3.3 or x.xV as low as possible
688 *
689 * *LV means Low Voltage
690 *
691 *
692 * That gives us the following table:
693 *
694 * Socket VS1 VS2 Voltage
695 *
696 * 5V NC NC 5V
697 * 5V NC GND none (should not be possible)
698 * 5V GND NC >= 3.3V
699 * 5V GND GND >= x.xV
700 *
701 * LV NC NC 5V (if available)
702 * LV NC GND x.xV (if available)
703 * LV GND NC 3.3V
704 * LV GND GND >= x.xV
705 *
706 * So, how do I determine if I have a 5V or a LV
707 * socket on my board? Look at the socket!
708 *
709 *
710 * Socket with 5V key:
711 * ++--------------------------------------------+
712 * || |
713 * || ||
714 * || ||
715 * | |
716 * +---------------------------------------------+
717 *
718 * Socket with LV key:
719 * ++--------------------------------------------+
720 * || |
721 * | ||
722 * | ||
723 * | |
724 * +---------------------------------------------+
725 *
726 *
727 * With other words - LV only cards does not fit
728 * into the 5V socket!
729 */
730
731 /* read out VS1 and VS2 */
732
733 reg = (pipr & M8XX_PCMCIA_VS_MASK(lsock))
734 >> M8XX_PCMCIA_VS_SHIFT(lsock);
735
736 if (socket_get(lsock) == PCMCIA_SOCKET_KEY_LV) {
737 switch (reg) {
738 case 1:
739 *value |= SS_3VCARD;
740 break; /* GND, NC - 3.3V only */
741 case 2:
742 *value |= SS_XVCARD;
743 break; /* NC. GND - x.xV only */
744 };
745 }
746
747 pr_debug("m8xx_pcmcia: GetStatus(%d) = %#2.2x\n", lsock, *value);
748 return 0;
749 }
750
751 static int m8xx_set_socket(struct pcmcia_socket *sock, socket_state_t * state)
752 {
753 int lsock = container_of(sock, struct socket_info, socket)->slot;
754 struct socket_info *s = &socket[lsock];
755 struct event_table *e;
756 unsigned int reg;
757 unsigned long flags;
758 pcmconf8xx_t *pcmcia = socket[0].pcmcia;
759
760 pr_debug("m8xx_pcmcia: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
761 "io_irq %d, csc_mask %#2.2x)\n", lsock, state->flags,
762 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
763
764 /* First, set voltage - bail out if invalid */
765 if (voltage_set(lsock, state->Vcc, state->Vpp))
766 return -EINVAL;
767
768 /* Take care of reset... */
769 if (state->flags & SS_RESET)
770 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXRESET); /* active high */
771 else
772 out_be32(M8XX_PGCRX(lsock),
773 in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXRESET);
774
775 /* ... and output enable. */
776
777 /* The CxOE signal is connected to a 74541 on the ADS.
778 I guess most other boards used the ADS as a reference.
779 I tried to control the CxOE signal with SS_OUTPUT_ENA,
780 but the reset signal seems connected via the 541.
781 If the CxOE is left high are some signals tristated and
782 no pullups are present -> the cards act weird.
783 So right now the buffers are enabled if the power is on. */
784
785 if (state->Vcc || state->Vpp)
786 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXOE); /* active low */
787 else
788 out_be32(M8XX_PGCRX(lsock),
789 in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXOE);
790
791 /*
792 * We'd better turn off interrupts before
793 * we mess with the events-table..
794 */
795
796 spin_lock_irqsave(&events_lock, flags);
797
798 /*
799 * Play around with the interrupt mask to be able to
800 * give the events the generic pcmcia driver wants us to.
801 */
802
803 e = &s->events[0];
804 reg = 0;
805
806 if (state->csc_mask & SS_DETECT) {
807 e->eventbit = SS_DETECT;
808 reg |= e->regbit = (M8XX_PCMCIA_CD2(lsock)
809 | M8XX_PCMCIA_CD1(lsock));
810 e++;
811 }
812 if (state->flags & SS_IOCARD) {
813 /*
814 * I/O card
815 */
816 if (state->csc_mask & SS_STSCHG) {
817 e->eventbit = SS_STSCHG;
818 reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
819 e++;
820 }
821 /*
822 * If io_irq is non-zero we should enable irq.
823 */
824 if (state->io_irq) {
825 out_be32(M8XX_PGCRX(lsock),
826 in_be32(M8XX_PGCRX(lsock)) |
827 mk_int_int_mask(s->hwirq) << 24);
828 /*
829 * Strange thing here:
830 * The manual does not tell us which interrupt
831 * the sources generate.
832 * Anyhow, I found out that RDY_L generates IREQLVL.
833 *
834 * We use level triggerd interrupts, and they don't
835 * have to be cleared in PSCR in the interrupt handler.
836 */
837 reg |= M8XX_PCMCIA_RDY_L(lsock);
838 } else
839 out_be32(M8XX_PGCRX(lsock),
840 in_be32(M8XX_PGCRX(lsock)) & 0x00ffffff);
841 } else {
842 /*
843 * Memory card
844 */
845 if (state->csc_mask & SS_BATDEAD) {
846 e->eventbit = SS_BATDEAD;
847 reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
848 e++;
849 }
850 if (state->csc_mask & SS_BATWARN) {
851 e->eventbit = SS_BATWARN;
852 reg |= e->regbit = M8XX_PCMCIA_BVD2(lsock);
853 e++;
854 }
855 /* What should I trigger on - low/high,raise,fall? */
856 if (state->csc_mask & SS_READY) {
857 e->eventbit = SS_READY;
858 reg |= e->regbit = 0; //??
859 e++;
860 }
861 }
862
863 e->regbit = 0; /* terminate list */
864
865 /*
866 * Clear the status changed .
867 * Port A and Port B share the same port.
868 * Writing ones will clear the bits.
869 */
870
871 out_be32(&pcmcia->pcmc_pscr, reg);
872
873 /*
874 * Write the mask.
875 * Port A and Port B share the same port.
876 * Need for read-modify-write.
877 * Ones will enable the interrupt.
878 */
879
880 reg |=
881 in_be32(&pcmcia->
882 pcmc_per) & (M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
883 out_be32(&pcmcia->pcmc_per, reg);
884
885 spin_unlock_irqrestore(&events_lock, flags);
886
887 /* copy the struct and modify the copy */
888
889 s->state = *state;
890
891 return 0;
892 }
893
894 static int m8xx_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *io)
895 {
896 int lsock = container_of(sock, struct socket_info, socket)->slot;
897
898 struct socket_info *s = &socket[lsock];
899 struct pcmcia_win *w;
900 unsigned int reg, winnr;
901 pcmconf8xx_t *pcmcia = s->pcmcia;
902
903 #define M8XX_SIZE (io->stop - io->start + 1)
904 #define M8XX_BASE (PCMCIA_IO_WIN_BASE + io->start)
905
906 pr_debug("m8xx_pcmcia: SetIOMap(%d, %d, %#2.2x, %d ns, "
907 "%#4.4llx-%#4.4llx)\n", lsock, io->map, io->flags,
908 io->speed, (unsigned long long)io->start,
909 (unsigned long long)io->stop);
910
911 if ((io->map >= PCMCIA_IO_WIN_NO) || (io->start > 0xffff)
912 || (io->stop > 0xffff) || (io->stop < io->start))
913 return -EINVAL;
914
915 if ((reg = m8xx_get_graycode(M8XX_SIZE)) == -1)
916 return -EINVAL;
917
918 if (io->flags & MAP_ACTIVE) {
919
920 pr_debug("m8xx_pcmcia: io->flags & MAP_ACTIVE\n");
921
922 winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
923 + (lsock * PCMCIA_IO_WIN_NO) + io->map;
924
925 /* setup registers */
926
927 w = (void *)&pcmcia->pcmc_pbr0;
928 w += winnr;
929
930 out_be32(&w->or, 0); /* turn off window first */
931 out_be32(&w->br, M8XX_BASE);
932
933 reg <<= 27;
934 reg |= M8XX_PCMCIA_POR_IO | (lsock << 2);
935
936 reg |= m8xx_get_speed(io->speed, 1, s->bus_freq);
937
938 if (io->flags & MAP_WRPROT)
939 reg |= M8XX_PCMCIA_POR_WRPROT;
940
941 /*if(io->flags & (MAP_16BIT | MAP_AUTOSZ)) */
942 if (io->flags & MAP_16BIT)
943 reg |= M8XX_PCMCIA_POR_16BIT;
944
945 if (io->flags & MAP_ACTIVE)
946 reg |= M8XX_PCMCIA_POR_VALID;
947
948 out_be32(&w->or, reg);
949
950 pr_debug("m8xx_pcmcia: Socket %u: Mapped io window %u at "
951 "%#8.8x, OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
952 } else {
953 /* shutdown IO window */
954 winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
955 + (lsock * PCMCIA_IO_WIN_NO) + io->map;
956
957 /* setup registers */
958
959 w = (void *)&pcmcia->pcmc_pbr0;
960 w += winnr;
961
962 out_be32(&w->or, 0); /* turn off window */
963 out_be32(&w->br, 0); /* turn off base address */
964
965 pr_debug("m8xx_pcmcia: Socket %u: Unmapped io window %u at "
966 "%#8.8x, OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
967 }
968
969 /* copy the struct and modify the copy */
970 s->io_win[io->map] = *io;
971 s->io_win[io->map].flags &= (MAP_WRPROT | MAP_16BIT | MAP_ACTIVE);
972 pr_debug("m8xx_pcmcia: SetIOMap exit\n");
973
974 return 0;
975 }
976
977 static int m8xx_set_mem_map(struct pcmcia_socket *sock,
978 struct pccard_mem_map *mem)
979 {
980 int lsock = container_of(sock, struct socket_info, socket)->slot;
981 struct socket_info *s = &socket[lsock];
982 struct pcmcia_win *w;
983 struct pccard_mem_map *old;
984 unsigned int reg, winnr;
985 pcmconf8xx_t *pcmcia = s->pcmcia;
986
987 pr_debug("m8xx_pcmcia: SetMemMap(%d, %d, %#2.2x, %d ns, "
988 "%#5.5llx, %#5.5x)\n", lsock, mem->map, mem->flags,
989 mem->speed, (unsigned long long)mem->static_start,
990 mem->card_start);
991
992 if ((mem->map >= PCMCIA_MEM_WIN_NO)
993 // || ((mem->s) >= PCMCIA_MEM_WIN_SIZE)
994 || (mem->card_start >= 0x04000000)
995 || (mem->static_start & 0xfff) /* 4KByte resolution */
996 ||(mem->card_start & 0xfff))
997 return -EINVAL;
998
999 if ((reg = m8xx_get_graycode(PCMCIA_MEM_WIN_SIZE)) == -1) {
1000 printk("Cannot set size to 0x%08x.\n", PCMCIA_MEM_WIN_SIZE);
1001 return -EINVAL;
1002 }
1003 reg <<= 27;
1004
1005 winnr = (lsock * PCMCIA_MEM_WIN_NO) + mem->map;
1006
1007 /* Setup the window in the pcmcia controller */
1008
1009 w = (void *)&pcmcia->pcmc_pbr0;
1010 w += winnr;
1011
1012 reg |= lsock << 2;
1013
1014 reg |= m8xx_get_speed(mem->speed, 0, s->bus_freq);
1015
1016 if (mem->flags & MAP_ATTRIB)
1017 reg |= M8XX_PCMCIA_POR_ATTRMEM;
1018
1019 if (mem->flags & MAP_WRPROT)
1020 reg |= M8XX_PCMCIA_POR_WRPROT;
1021
1022 if (mem->flags & MAP_16BIT)
1023 reg |= M8XX_PCMCIA_POR_16BIT;
1024
1025 if (mem->flags & MAP_ACTIVE)
1026 reg |= M8XX_PCMCIA_POR_VALID;
1027
1028 out_be32(&w->or, reg);
1029
1030 pr_debug("m8xx_pcmcia: Socket %u: Mapped memory window %u at %#8.8x, "
1031 "OR = %#8.8x.\n", lsock, mem->map, w->br, w->or);
1032
1033 if (mem->flags & MAP_ACTIVE) {
1034 /* get the new base address */
1035 mem->static_start = PCMCIA_MEM_WIN_BASE +
1036 (PCMCIA_MEM_WIN_SIZE * winnr)
1037 + mem->card_start;
1038 }
1039
1040 pr_debug("m8xx_pcmcia: SetMemMap(%d, %d, %#2.2x, %d ns, "
1041 "%#5.5llx, %#5.5x)\n", lsock, mem->map, mem->flags,
1042 mem->speed, (unsigned long long)mem->static_start,
1043 mem->card_start);
1044
1045 /* copy the struct and modify the copy */
1046
1047 old = &s->mem_win[mem->map];
1048
1049 *old = *mem;
1050 old->flags &= (MAP_ATTRIB | MAP_WRPROT | MAP_16BIT | MAP_ACTIVE);
1051
1052 return 0;
1053 }
1054
1055 static int m8xx_sock_init(struct pcmcia_socket *sock)
1056 {
1057 int i;
1058 pccard_io_map io = { 0, 0, 0, 0, 1 };
1059 pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 };
1060
1061 pr_debug("m8xx_pcmcia: sock_init(%d)\n", s);
1062
1063 m8xx_set_socket(sock, &dead_socket);
1064 for (i = 0; i < PCMCIA_IO_WIN_NO; i++) {
1065 io.map = i;
1066 m8xx_set_io_map(sock, &io);
1067 }
1068 for (i = 0; i < PCMCIA_MEM_WIN_NO; i++) {
1069 mem.map = i;
1070 m8xx_set_mem_map(sock, &mem);
1071 }
1072
1073 return 0;
1074
1075 }
1076
1077 static int m8xx_sock_suspend(struct pcmcia_socket *sock)
1078 {
1079 return m8xx_set_socket(sock, &dead_socket);
1080 }
1081
1082 static struct pccard_operations m8xx_services = {
1083 .init = m8xx_sock_init,
1084 .suspend = m8xx_sock_suspend,
1085 .get_status = m8xx_get_status,
1086 .set_socket = m8xx_set_socket,
1087 .set_io_map = m8xx_set_io_map,
1088 .set_mem_map = m8xx_set_mem_map,
1089 };
1090
1091 static int __init m8xx_probe(struct platform_device *ofdev)
1092 {
1093 struct pcmcia_win *w;
1094 unsigned int i, m, hwirq;
1095 pcmconf8xx_t *pcmcia;
1096 int status;
1097 struct device_node *np = ofdev->dev.of_node;
1098
1099 pcmcia_info("%s\n", version);
1100
1101 pcmcia = of_iomap(np, 0);
1102 if (pcmcia == NULL)
1103 return -EINVAL;
1104
1105 pcmcia_schlvl = irq_of_parse_and_map(np, 0);
1106 hwirq = irq_map[pcmcia_schlvl].hwirq;
1107 if (pcmcia_schlvl < 0) {
1108 iounmap(pcmcia);
1109 return -EINVAL;
1110 }
1111
1112 m8xx_pgcrx[0] = &pcmcia->pcmc_pgcra;
1113 m8xx_pgcrx[1] = &pcmcia->pcmc_pgcrb;
1114
1115 pcmcia_info(PCMCIA_BOARD_MSG " using " PCMCIA_SLOT_MSG
1116 " with IRQ %u (%d). \n", pcmcia_schlvl, hwirq);
1117
1118 /* Configure Status change interrupt */
1119
1120 if (request_irq(pcmcia_schlvl, m8xx_interrupt, IRQF_SHARED,
1121 driver_name, socket)) {
1122 pcmcia_error("Cannot allocate IRQ %u for SCHLVL!\n",
1123 pcmcia_schlvl);
1124 iounmap(pcmcia);
1125 return -1;
1126 }
1127
1128 w = (void *)&pcmcia->pcmc_pbr0;
1129
1130 out_be32(&pcmcia->pcmc_pscr, M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
1131 clrbits32(&pcmcia->pcmc_per, M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
1132
1133 /* connect interrupt and disable CxOE */
1134
1135 out_be32(M8XX_PGCRX(0),
1136 M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16));
1137 out_be32(M8XX_PGCRX(1),
1138 M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16));
1139
1140 /* initialize the fixed memory windows */
1141
1142 for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1143 for (m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
1144 out_be32(&w->br, PCMCIA_MEM_WIN_BASE +
1145 (PCMCIA_MEM_WIN_SIZE
1146 * (m + i * PCMCIA_MEM_WIN_NO)));
1147
1148 out_be32(&w->or, 0); /* set to not valid */
1149
1150 w++;
1151 }
1152 }
1153
1154 /* turn off voltage */
1155 voltage_set(0, 0, 0);
1156 voltage_set(1, 0, 0);
1157
1158 /* Enable external hardware */
1159 hardware_enable(0);
1160 hardware_enable(1);
1161
1162 for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1163 socket[i].slot = i;
1164 socket[i].socket.owner = THIS_MODULE;
1165 socket[i].socket.features =
1166 SS_CAP_PCCARD | SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP;
1167 socket[i].socket.irq_mask = 0x000;
1168 socket[i].socket.map_size = 0x1000;
1169 socket[i].socket.io_offset = 0;
1170 socket[i].socket.pci_irq = pcmcia_schlvl;
1171 socket[i].socket.ops = &m8xx_services;
1172 socket[i].socket.resource_ops = &pccard_iodyn_ops;
1173 socket[i].socket.cb_dev = NULL;
1174 socket[i].socket.dev.parent = &ofdev->dev;
1175 socket[i].pcmcia = pcmcia;
1176 socket[i].bus_freq = ppc_proc_freq;
1177 socket[i].hwirq = hwirq;
1178
1179 }
1180
1181 for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1182 status = pcmcia_register_socket(&socket[i].socket);
1183 if (status < 0)
1184 pcmcia_error("Socket register failed\n");
1185 }
1186
1187 return 0;
1188 }
1189
1190 static int m8xx_remove(struct platform_device *ofdev)
1191 {
1192 u32 m, i;
1193 struct pcmcia_win *w;
1194 pcmconf8xx_t *pcmcia = socket[0].pcmcia;
1195
1196 for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1197 w = (void *)&pcmcia->pcmc_pbr0;
1198
1199 out_be32(&pcmcia->pcmc_pscr, M8XX_PCMCIA_MASK(i));
1200 out_be32(&pcmcia->pcmc_per,
1201 in_be32(&pcmcia->pcmc_per) & ~M8XX_PCMCIA_MASK(i));
1202
1203 /* turn off interrupt and disable CxOE */
1204 out_be32(M8XX_PGCRX(i), M8XX_PGCRX_CXOE);
1205
1206 /* turn off memory windows */
1207 for (m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
1208 out_be32(&w->or, 0); /* set to not valid */
1209 w++;
1210 }
1211
1212 /* turn off voltage */
1213 voltage_set(i, 0, 0);
1214
1215 /* disable external hardware */
1216 hardware_disable(i);
1217 }
1218 for (i = 0; i < PCMCIA_SOCKETS_NO; i++)
1219 pcmcia_unregister_socket(&socket[i].socket);
1220 iounmap(pcmcia);
1221
1222 free_irq(pcmcia_schlvl, NULL);
1223
1224 return 0;
1225 }
1226
1227 static const struct of_device_id m8xx_pcmcia_match[] = {
1228 {
1229 .type = "pcmcia",
1230 .compatible = "fsl,pq-pcmcia",
1231 },
1232 {},
1233 };
1234
1235 MODULE_DEVICE_TABLE(of, m8xx_pcmcia_match);
1236
1237 static struct platform_driver m8xx_pcmcia_driver = {
1238 .driver = {
1239 .name = driver_name,
1240 .owner = THIS_MODULE,
1241 .of_match_table = m8xx_pcmcia_match,
1242 },
1243 .probe = m8xx_probe,
1244 .remove = m8xx_remove,
1245 };
1246
1247 module_platform_driver(m8xx_pcmcia_driver);
Linux kernel - Deliverables
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