2 * Marvell Berlin SATA PHY driver
4 * Copyright (C) 2014 Marvell Technology Group Ltd.
6 * Antoine Ténart <antoine.tenart@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
13 #include <linux/clk.h>
14 #include <linux/module.h>
15 #include <linux/phy/phy.h>
17 #include <linux/platform_device.h>
19 #define HOST_VSA_ADDR 0x0
20 #define HOST_VSA_DATA 0x4
21 #define PORT_SCR_CTL 0x2c
22 #define PORT_VSR_ADDR 0x78
23 #define PORT_VSR_DATA 0x7c
25 #define CONTROL_REGISTER 0x0
26 #define MBUS_SIZE_CONTROL 0x4
28 #define POWER_DOWN_PHY0 BIT(6)
29 #define POWER_DOWN_PHY1 BIT(14)
30 #define MBUS_WRITE_REQUEST_SIZE_128 (BIT(2) << 16)
31 #define MBUS_READ_REQUEST_SIZE_128 (BIT(2) << 19)
33 #define PHY_BASE 0x200
36 #define REF_FREF_SEL_25 BIT(0)
37 #define PHY_MODE_SATA (0x0 << 5)
40 #define USE_MAX_PLL_RATE BIT(12)
43 #define DATA_BIT_WIDTH_10 (0x0 << 10)
44 #define DATA_BIT_WIDTH_20 (0x1 << 10)
45 #define DATA_BIT_WIDTH_40 (0x2 << 10)
48 #define PHY_GEN_MAX_1_5 (0x0 << 10)
49 #define PHY_GEN_MAX_3_0 (0x1 << 10)
50 #define PHY_GEN_MAX_6_0 (0x2 << 10)
52 struct phy_berlin_desc
{
58 struct phy_berlin_priv
{
62 struct phy_berlin_desc
**phys
;
66 static inline void phy_berlin_sata_reg_setbits(void __iomem
*ctrl_reg
, u32 reg
,
72 writel(PHY_BASE
+ reg
, ctrl_reg
+ PORT_VSR_ADDR
);
75 regval
= readl(ctrl_reg
+ PORT_VSR_DATA
);
78 writel(regval
, ctrl_reg
+ PORT_VSR_DATA
);
81 static int phy_berlin_sata_power_on(struct phy
*phy
)
83 struct phy_berlin_desc
*desc
= phy_get_drvdata(phy
);
84 struct phy_berlin_priv
*priv
= dev_get_drvdata(phy
->dev
.parent
);
85 void __iomem
*ctrl_reg
= priv
->base
+ 0x60 + (desc
->index
* 0x80);
89 clk_prepare_enable(priv
->clk
);
91 spin_lock(&priv
->lock
);
94 writel(CONTROL_REGISTER
, priv
->base
+ HOST_VSA_ADDR
);
95 regval
= readl(priv
->base
+ HOST_VSA_DATA
);
96 regval
&= ~desc
->power_bit
;
97 writel(regval
, priv
->base
+ HOST_VSA_DATA
);
100 writel(MBUS_SIZE_CONTROL
, priv
->base
+ HOST_VSA_ADDR
);
101 regval
= readl(priv
->base
+ HOST_VSA_DATA
);
102 regval
|= MBUS_WRITE_REQUEST_SIZE_128
| MBUS_READ_REQUEST_SIZE_128
;
103 writel(regval
, priv
->base
+ HOST_VSA_DATA
);
105 /* set PHY mode and ref freq to 25 MHz */
106 phy_berlin_sata_reg_setbits(ctrl_reg
, 0x1, 0xff,
107 REF_FREF_SEL_25
| PHY_MODE_SATA
);
109 /* set PHY up to 6 Gbps */
110 phy_berlin_sata_reg_setbits(ctrl_reg
, 0x25, 0xc00, PHY_GEN_MAX_6_0
);
112 /* set 40 bits width */
113 phy_berlin_sata_reg_setbits(ctrl_reg
, 0x23, 0xc00, DATA_BIT_WIDTH_40
);
115 /* use max pll rate */
116 phy_berlin_sata_reg_setbits(ctrl_reg
, 0x2, 0x0, USE_MAX_PLL_RATE
);
118 /* set Gen3 controller speed */
119 regval
= readl(ctrl_reg
+ PORT_SCR_CTL
);
120 regval
&= ~GENMASK(7, 4);
122 writel(regval
, ctrl_reg
+ PORT_SCR_CTL
);
124 spin_unlock(&priv
->lock
);
126 clk_disable_unprepare(priv
->clk
);
131 static int phy_berlin_sata_power_off(struct phy
*phy
)
133 struct phy_berlin_desc
*desc
= phy_get_drvdata(phy
);
134 struct phy_berlin_priv
*priv
= dev_get_drvdata(phy
->dev
.parent
);
137 clk_prepare_enable(priv
->clk
);
139 spin_lock(&priv
->lock
);
142 writel(CONTROL_REGISTER
, priv
->base
+ HOST_VSA_ADDR
);
143 regval
= readl(priv
->base
+ HOST_VSA_DATA
);
144 regval
|= desc
->power_bit
;
145 writel(regval
, priv
->base
+ HOST_VSA_DATA
);
147 spin_unlock(&priv
->lock
);
149 clk_disable_unprepare(priv
->clk
);
154 static struct phy
*phy_berlin_sata_phy_xlate(struct device
*dev
,
155 struct of_phandle_args
*args
)
157 struct phy_berlin_priv
*priv
= dev_get_drvdata(dev
);
160 if (WARN_ON(args
->args
[0] >= priv
->nphys
))
161 return ERR_PTR(-ENODEV
);
163 for (i
= 0; i
< priv
->nphys
; i
++) {
164 if (priv
->phys
[i
]->index
== args
->args
[0])
168 if (i
== priv
->nphys
)
169 return ERR_PTR(-ENODEV
);
171 return priv
->phys
[i
]->phy
;
174 static struct phy_ops phy_berlin_sata_ops
= {
175 .power_on
= phy_berlin_sata_power_on
,
176 .power_off
= phy_berlin_sata_power_off
,
177 .owner
= THIS_MODULE
,
180 static u32 phy_berlin_power_down_bits
[] = {
185 static int phy_berlin_sata_probe(struct platform_device
*pdev
)
187 struct device
*dev
= &pdev
->dev
;
188 struct device_node
*child
;
190 struct phy_provider
*phy_provider
;
191 struct phy_berlin_priv
*priv
;
192 struct resource
*res
;
196 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
200 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
204 priv
->base
= devm_ioremap(dev
, res
->start
, resource_size(res
));
208 priv
->clk
= devm_clk_get(dev
, NULL
);
209 if (IS_ERR(priv
->clk
))
210 return PTR_ERR(priv
->clk
);
212 priv
->nphys
= of_get_child_count(dev
->of_node
);
213 if (priv
->nphys
== 0)
216 priv
->phys
= devm_kzalloc(dev
, priv
->nphys
* sizeof(*priv
->phys
),
221 dev_set_drvdata(dev
, priv
);
222 spin_lock_init(&priv
->lock
);
224 for_each_available_child_of_node(dev
->of_node
, child
) {
225 struct phy_berlin_desc
*phy_desc
;
227 if (of_property_read_u32(child
, "reg", &phy_id
)) {
228 dev_err(dev
, "missing reg property in node %s\n",
233 if (phy_id
>= ARRAY_SIZE(phy_berlin_power_down_bits
)) {
234 dev_err(dev
, "invalid reg in node %s\n", child
->name
);
238 phy_desc
= devm_kzalloc(dev
, sizeof(*phy_desc
), GFP_KERNEL
);
242 phy
= devm_phy_create(dev
, NULL
, &phy_berlin_sata_ops
, NULL
);
244 dev_err(dev
, "failed to create PHY %d\n", phy_id
);
249 phy_desc
->power_bit
= phy_berlin_power_down_bits
[phy_id
];
250 phy_desc
->index
= phy_id
;
251 phy_set_drvdata(phy
, phy_desc
);
253 priv
->phys
[i
++] = phy_desc
;
255 /* Make sure the PHY is off */
256 phy_berlin_sata_power_off(phy
);
260 devm_of_phy_provider_register(dev
, phy_berlin_sata_phy_xlate
);
261 if (IS_ERR(phy_provider
))
262 return PTR_ERR(phy_provider
);
267 static const struct of_device_id phy_berlin_sata_of_match
[] = {
268 { .compatible
= "marvell,berlin2q-sata-phy" },
272 static struct platform_driver phy_berlin_sata_driver
= {
273 .probe
= phy_berlin_sata_probe
,
275 .name
= "phy-berlin-sata",
276 .owner
= THIS_MODULE
,
277 .of_match_table
= phy_berlin_sata_of_match
,
280 module_platform_driver(phy_berlin_sata_driver
);
282 MODULE_DESCRIPTION("Marvell Berlin SATA PHY driver");
283 MODULE_AUTHOR("Antoine Ténart <antoine.tenart@free-electrons.com>");
284 MODULE_LICENSE("GPL v2");