drivers/phy/phy-berlin-usb.c

   1 /*
   2  * Copyright (C) 2014 Marvell Technology Group Ltd.
   3  *
   4  * Antoine Tenart <antoine.tenart@free-electrons.com>
   5  * Jisheng Zhang <jszhang@marvell.com>
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2. This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #include <linux/gpio.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/of_device.h>
  16 #include <linux/of_gpio.h>
  17 #include <linux/phy/phy.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/reset.h>
  20
  21 #define USB_PHY_PLL             0x04
  22 #define USB_PHY_PLL_CONTROL     0x08
  23 #define USB_PHY_TX_CTRL0        0x10
  24 #define USB_PHY_TX_CTRL1        0x14
  25 #define USB_PHY_TX_CTRL2        0x18
  26 #define USB_PHY_RX_CTRL         0x20
  27 #define USB_PHY_ANALOG          0x34
  28
  29 /* USB_PHY_PLL */
  30 #define CLK_REF_DIV(x)          ((x) << 4)
  31 #define FEEDBACK_CLK_DIV(x)     ((x) << 8)
  32
  33 /* USB_PHY_PLL_CONTROL */
  34 #define CLK_STABLE              BIT(0)
  35 #define PLL_CTRL_PIN            BIT(1)
  36 #define PLL_CTRL_REG            BIT(2)
  37 #define PLL_ON                  BIT(3)
  38 #define PHASE_OFF_TOL_125       (0x0 << 5)
  39 #define PHASE_OFF_TOL_250       BIT(5)
  40 #define KVC0_CALIB              (0x0 << 9)
  41 #define KVC0_REG_CTRL           BIT(9)
  42 #define KVC0_HIGH               (0x0 << 10)
  43 #define KVC0_LOW                (0x3 << 10)
  44 #define CLK_BLK_EN              BIT(13)
  45
  46 /* USB_PHY_TX_CTRL0 */
  47 #define EXT_HS_RCAL_EN          BIT(3)
  48 #define EXT_FS_RCAL_EN          BIT(4)
  49 #define IMPCAL_VTH_DIV(x)       ((x) << 5)
  50 #define EXT_RS_RCAL_DIV(x)      ((x) << 8)
  51 #define EXT_FS_RCAL_DIV(x)      ((x) << 12)
  52
  53 /* USB_PHY_TX_CTRL1 */
  54 #define TX_VDD15_14             (0x0 << 4)
  55 #define TX_VDD15_15             BIT(4)
  56 #define TX_VDD15_16             (0x2 << 4)
  57 #define TX_VDD15_17             (0x3 << 4)
  58 #define TX_VDD12_VDD            (0x0 << 6)
  59 #define TX_VDD12_11             BIT(6)
  60 #define TX_VDD12_12             (0x2 << 6)
  61 #define TX_VDD12_13             (0x3 << 6)
  62 #define LOW_VDD_EN              BIT(8)
  63 #define TX_OUT_AMP(x)           ((x) << 9)
  64
  65 /* USB_PHY_TX_CTRL2 */
  66 #define TX_CHAN_CTRL_REG(x)     ((x) << 0)
  67 #define DRV_SLEWRATE(x)         ((x) << 4)
  68 #define IMP_CAL_FS_HS_DLY_0     (0x0 << 6)
  69 #define IMP_CAL_FS_HS_DLY_1     BIT(6)
  70 #define IMP_CAL_FS_HS_DLY_2     (0x2 << 6)
  71 #define IMP_CAL_FS_HS_DLY_3     (0x3 << 6)
  72 #define FS_DRV_EN_MASK(x)       ((x) << 8)
  73 #define HS_DRV_EN_MASK(x)       ((x) << 12)
  74
  75 /* USB_PHY_RX_CTRL */
  76 #define PHASE_FREEZE_DLY_2_CL   (0x0 << 0)
  77 #define PHASE_FREEZE_DLY_4_CL   BIT(0)
  78 #define ACK_LENGTH_8_CL         (0x0 << 2)
  79 #define ACK_LENGTH_12_CL        BIT(2)
  80 #define ACK_LENGTH_16_CL        (0x2 << 2)
  81 #define ACK_LENGTH_20_CL        (0x3 << 2)
  82 #define SQ_LENGTH_3             (0x0 << 4)
  83 #define SQ_LENGTH_6             BIT(4)
  84 #define SQ_LENGTH_9             (0x2 << 4)
  85 #define SQ_LENGTH_12            (0x3 << 4)
  86 #define DISCON_THRESHOLD_260    (0x0 << 6)
  87 #define DISCON_THRESHOLD_270    BIT(6)
  88 #define DISCON_THRESHOLD_280    (0x2 << 6)
  89 #define DISCON_THRESHOLD_290    (0x3 << 6)
  90 #define SQ_THRESHOLD(x)         ((x) << 8)
  91 #define LPF_COEF(x)             ((x) << 12)
  92 #define INTPL_CUR_10            (0x0 << 14)
  93 #define INTPL_CUR_20            BIT(14)
  94 #define INTPL_CUR_30            (0x2 << 14)
  95 #define INTPL_CUR_40            (0x3 << 14)
  96
  97 /* USB_PHY_ANALOG */
  98 #define ANA_PWR_UP              BIT(1)
  99 #define ANA_PWR_DOWN            BIT(2)
 100 #define V2I_VCO_RATIO(x)        ((x) << 7)
 101 #define R_ROTATE_90             (0x0 << 10)
 102 #define R_ROTATE_0              BIT(10)
 103 #define MODE_TEST_EN            BIT(11)
 104 #define ANA_TEST_DC_CTRL(x)     ((x) << 12)
 105
 106 #define to_phy_berlin_usb_priv(p)       \
 107         container_of((p), struct phy_berlin_usb_priv, phy)
 108
 109 static const u32 phy_berlin_pll_dividers[] = {
 110         /* Berlin 2 */
 111         CLK_REF_DIV(0xc) | FEEDBACK_CLK_DIV(0x54),
 112         /* Berlin 2CD */
 113         CLK_REF_DIV(0x6) | FEEDBACK_CLK_DIV(0x55),
 114 };
 115
 116 struct phy_berlin_usb_priv {
 117         void __iomem            *base;
 118         struct phy              *phy;
 119         struct reset_control    *rst_ctrl;
 120         u32                     pll_divider;
 121 };
 122
 123 static int phy_berlin_usb_power_on(struct phy *phy)
 124 {
 125         struct phy_berlin_usb_priv *priv = dev_get_drvdata(phy->dev.parent);
 126
 127         reset_control_reset(priv->rst_ctrl);
 128
 129         writel(priv->pll_divider,
 130                priv->base + USB_PHY_PLL);
 131         writel(CLK_STABLE | PLL_CTRL_REG | PHASE_OFF_TOL_250 | KVC0_REG_CTRL |
 132                CLK_BLK_EN, priv->base + USB_PHY_PLL_CONTROL);
 133         writel(V2I_VCO_RATIO(0x5) | R_ROTATE_0 | ANA_TEST_DC_CTRL(0x5),
 134                priv->base + USB_PHY_ANALOG);
 135         writel(PHASE_FREEZE_DLY_4_CL | ACK_LENGTH_16_CL | SQ_LENGTH_12 |
 136                DISCON_THRESHOLD_260 | SQ_THRESHOLD(0xa) | LPF_COEF(0x2) |
 137                INTPL_CUR_30, priv->base + USB_PHY_RX_CTRL);
 138
 139         writel(TX_VDD12_13 | TX_OUT_AMP(0x3), priv->base + USB_PHY_TX_CTRL1);
 140         writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4),
 141                priv->base + USB_PHY_TX_CTRL0);
 142
 143         writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4) |
 144                EXT_FS_RCAL_DIV(0x2), priv->base + USB_PHY_TX_CTRL0);
 145
 146         writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4),
 147                priv->base + USB_PHY_TX_CTRL0);
 148         writel(TX_CHAN_CTRL_REG(0xf) | DRV_SLEWRATE(0x3) | IMP_CAL_FS_HS_DLY_3 |
 149                FS_DRV_EN_MASK(0xd), priv->base + USB_PHY_TX_CTRL2);
 150
 151         return 0;
 152 }
 153
 154 static struct phy_ops phy_berlin_usb_ops = {
 155         .power_on       = phy_berlin_usb_power_on,
 156         .owner          = THIS_MODULE,
 157 };
 158
 159 static const struct of_device_id phy_berlin_sata_of_match[] = {
 160         {
 161                 .compatible = "marvell,berlin2-usb-phy",
 162                 .data = &phy_berlin_pll_dividers[0],
 163         },
 164         {
 165                 .compatible = "marvell,berlin2cd-usb-phy",
 166                 .data = &phy_berlin_pll_dividers[1],
 167         },
 168         { },
 169 };
 170 MODULE_DEVICE_TABLE(of, phy_berlin_sata_of_match);
 171
 172 static int phy_berlin_usb_probe(struct platform_device *pdev)
 173 {
 174         const struct of_device_id *match =
 175                 of_match_device(phy_berlin_sata_of_match, &pdev->dev);
 176         struct phy_berlin_usb_priv *priv;
 177         struct resource *res;
 178         struct phy_provider *phy_provider;
 179
 180         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 181         if (!priv)
 182                 return -ENOMEM;
 183
 184         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 185         priv->base = devm_ioremap_resource(&pdev->dev, res);
 186         if (IS_ERR(priv->base))
 187                 return PTR_ERR(priv->base);
 188
 189         priv->rst_ctrl = devm_reset_control_get(&pdev->dev, NULL);
 190         if (IS_ERR(priv->rst_ctrl))
 191                 return PTR_ERR(priv->rst_ctrl);
 192
 193         priv->pll_divider = *((u32 *)match->data);
 194
 195         priv->phy = devm_phy_create(&pdev->dev, NULL, &phy_berlin_usb_ops);
 196         if (IS_ERR(priv->phy)) {
 197                 dev_err(&pdev->dev, "failed to create PHY\n");
 198                 return PTR_ERR(priv->phy);
 199         }
 200
 201         platform_set_drvdata(pdev, priv);
 202
 203         phy_provider =
 204                 devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
 205         if (IS_ERR(phy_provider))
 206                 return PTR_ERR(phy_provider);
 207
 208         return 0;
 209 }
 210
 211 static struct platform_driver phy_berlin_usb_driver = {
 212         .probe  = phy_berlin_usb_probe,
 213         .driver = {
 214                 .name           = "phy-berlin-usb",
 215                 .owner          = THIS_MODULE,
 216                 .of_match_table = phy_berlin_sata_of_match,
 217          },
 218 };
 219 module_platform_driver(phy_berlin_usb_driver);
 220
 221 MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>");
 222 MODULE_DESCRIPTION("Marvell Berlin PHY driver for USB");
 223 MODULE_LICENSE("GPL");