2 * Copyright (C) 2014 STMicroelectronics
4 * STMicroelectronics PHY driver MiPHY28lp (for SoC STiH407).
6 * Author: Alexandre Torgue <alexandre.torgue@st.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2, as
10 * published by the Free Software Foundation.
14 #include <linux/platform_device.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
19 #include <linux/of_platform.h>
20 #include <linux/of_address.h>
21 #include <linux/clk.h>
22 #include <linux/phy/phy.h>
23 #include <linux/delay.h>
24 #include <linux/mfd/syscon.h>
25 #include <linux/regmap.h>
26 #include <linux/reset.h>
28 #include <dt-bindings/phy/phy.h>
31 #define MIPHY_CONF_RESET 0x00
32 #define RST_APPLI_SW BIT(0)
33 #define RST_CONF_SW BIT(1)
34 #define RST_MACRO_SW BIT(2)
36 #define MIPHY_RESET 0x01
37 #define RST_PLL_SW BIT(0)
38 #define RST_COMP_SW BIT(2)
40 #define MIPHY_STATUS_1 0x02
41 #define PHY_RDY BIT(0)
42 #define HFC_RDY BIT(1)
43 #define HFC_PLL BIT(2)
45 #define MIPHY_CONTROL 0x04
46 #define TERM_EN_SW BIT(2)
47 #define DIS_LINK_RST BIT(3)
48 #define AUTO_RST_RX BIT(4)
49 #define PX_RX_POL BIT(5)
51 #define MIPHY_BOUNDARY_SEL 0x0a
53 #define SSC_SEL BIT(4)
54 #define GENSEL_SEL BIT(0)
56 #define MIPHY_BOUNDARY_1 0x0b
57 #define MIPHY_BOUNDARY_2 0x0c
58 #define SSC_EN_SW BIT(2)
60 #define MIPHY_PLL_CLKREF_FREQ 0x0d
61 #define MIPHY_SPEED 0x0e
62 #define TX_SPDSEL_80DEC 0
63 #define TX_SPDSEL_40DEC 1
64 #define TX_SPDSEL_20DEC 2
65 #define RX_SPDSEL_80DEC 0
66 #define RX_SPDSEL_40DEC (1 << 2)
67 #define RX_SPDSEL_20DEC (2 << 2)
69 #define MIPHY_CONF 0x0f
70 #define MIPHY_CTRL_TEST_SEL 0x20
71 #define MIPHY_CTRL_TEST_1 0x21
72 #define MIPHY_CTRL_TEST_2 0x22
73 #define MIPHY_CTRL_TEST_3 0x23
74 #define MIPHY_CTRL_TEST_4 0x24
75 #define MIPHY_FEEDBACK_TEST 0x25
76 #define MIPHY_DEBUG_BUS 0x26
77 #define MIPHY_DEBUG_STATUS_MSB 0x27
78 #define MIPHY_DEBUG_STATUS_LSB 0x28
79 #define MIPHY_PWR_RAIL_1 0x29
80 #define MIPHY_PWR_RAIL_2 0x2a
81 #define MIPHY_SYNCHAR_CONTROL 0x30
83 #define MIPHY_COMP_FSM_1 0x3a
84 #define COMP_START BIT(6)
86 #define MIPHY_COMP_FSM_6 0x3f
87 #define COMP_DONE BIT(7)
89 #define MIPHY_COMP_POSTP 0x42
90 #define MIPHY_TX_CTRL_1 0x49
91 #define TX_REG_STEP_0V 0
92 #define TX_REG_STEP_P_25MV 1
93 #define TX_REG_STEP_P_50MV 2
94 #define TX_REG_STEP_N_25MV 7
95 #define TX_REG_STEP_N_50MV 6
96 #define TX_REG_STEP_N_75MV 5
98 #define MIPHY_TX_CTRL_2 0x4a
99 #define TX_SLEW_SW_40_PS 0
100 #define TX_SLEW_SW_80_PS 1
101 #define TX_SLEW_SW_120_PS 2
103 #define MIPHY_TX_CTRL_3 0x4b
104 #define MIPHY_TX_CAL_MAN 0x4e
105 #define TX_SLEW_CAL_MAN_EN BIT(0)
107 #define MIPHY_TST_BIAS_BOOST_2 0x62
108 #define MIPHY_BIAS_BOOST_1 0x63
109 #define MIPHY_BIAS_BOOST_2 0x64
110 #define MIPHY_RX_DESBUFF_FDB_2 0x67
111 #define MIPHY_RX_DESBUFF_FDB_3 0x68
112 #define MIPHY_SIGDET_COMPENS1 0x69
113 #define MIPHY_SIGDET_COMPENS2 0x6a
114 #define MIPHY_JITTER_PERIOD 0x6b
115 #define MIPHY_JITTER_AMPLITUDE_1 0x6c
116 #define MIPHY_JITTER_AMPLITUDE_2 0x6d
117 #define MIPHY_JITTER_AMPLITUDE_3 0x6e
118 #define MIPHY_RX_K_GAIN 0x78
119 #define MIPHY_RX_BUFFER_CTRL 0x7a
120 #define VGA_GAIN BIT(0)
121 #define EQ_DC_GAIN BIT(2)
122 #define EQ_BOOST_GAIN BIT(3)
124 #define MIPHY_RX_VGA_GAIN 0x7b
125 #define MIPHY_RX_EQU_GAIN_1 0x7f
126 #define MIPHY_RX_EQU_GAIN_2 0x80
127 #define MIPHY_RX_EQU_GAIN_3 0x81
128 #define MIPHY_RX_CAL_CTRL_1 0x97
129 #define MIPHY_RX_CAL_CTRL_2 0x98
131 #define MIPHY_RX_CAL_OFFSET_CTRL 0x99
132 #define CAL_OFFSET_VGA_64 (0x03 << 0)
133 #define CAL_OFFSET_THRESHOLD_64 (0x03 << 2)
134 #define VGA_OFFSET_POLARITY BIT(4)
135 #define OFFSET_COMPENSATION_EN BIT(6)
137 #define MIPHY_RX_CAL_VGA_STEP 0x9a
138 #define MIPHY_RX_CAL_EYE_MIN 0x9d
139 #define MIPHY_RX_CAL_OPT_LENGTH 0x9f
140 #define MIPHY_RX_LOCK_CTRL_1 0xc1
141 #define MIPHY_RX_LOCK_SETTINGS_OPT 0xc2
142 #define MIPHY_RX_LOCK_STEP 0xc4
144 #define MIPHY_RX_SIGDET_SLEEP_OA 0xc9
145 #define MIPHY_RX_SIGDET_SLEEP_SEL 0xca
146 #define MIPHY_RX_SIGDET_WAIT_SEL 0xcb
147 #define MIPHY_RX_SIGDET_DATA_SEL 0xcc
148 #define EN_ULTRA_LOW_POWER BIT(0)
149 #define EN_FIRST_HALF BIT(1)
150 #define EN_SECOND_HALF BIT(2)
151 #define EN_DIGIT_SIGNAL_CHECK BIT(3)
153 #define MIPHY_RX_POWER_CTRL_1 0xcd
154 #define MIPHY_RX_POWER_CTRL_2 0xce
155 #define MIPHY_PLL_CALSET_CTRL 0xd3
156 #define MIPHY_PLL_CALSET_1 0xd4
157 #define MIPHY_PLL_CALSET_2 0xd5
158 #define MIPHY_PLL_CALSET_3 0xd6
159 #define MIPHY_PLL_CALSET_4 0xd7
160 #define MIPHY_PLL_SBR_1 0xe3
161 #define SET_NEW_CHANGE BIT(1)
163 #define MIPHY_PLL_SBR_2 0xe4
164 #define MIPHY_PLL_SBR_3 0xe5
165 #define MIPHY_PLL_SBR_4 0xe6
166 #define MIPHY_PLL_COMMON_MISC_2 0xe9
167 #define START_ACT_FILT BIT(6)
169 #define MIPHY_PLL_SPAREIN 0xeb
172 * On STiH407 the glue logic can be different among MiPHY devices; for example:
173 * MiPHY0: OSC_FORCE_EXT means:
174 * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1
175 * MiPHY1: OSC_FORCE_EXT means:
176 * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1
177 * Some devices have not the possibility to check if the osc is ready.
179 #define MIPHY_OSC_FORCE_EXT BIT(3)
180 #define MIPHY_OSC_RDY BIT(5)
182 #define MIPHY_CTRL_MASK 0x0f
183 #define MIPHY_CTRL_DEFAULT 0
184 #define MIPHY_CTRL_SYNC_D_EN BIT(2)
186 /* SATA / PCIe defines */
187 #define SATA_CTRL_MASK 0x07
188 #define PCIE_CTRL_MASK 0xff
189 #define SATA_CTRL_SELECT_SATA 1
190 #define SATA_CTRL_SELECT_PCIE 0
191 #define SYSCFG_PCIE_PCIE_VAL 0x80
192 #define SATA_SPDMODE 1
194 #define MIPHY_SATA_BANK_NB 3
195 #define MIPHY_PCIE_BANK_NB 2
205 struct miphy28lp_phy
{
207 struct miphy28lp_dev
*phydev
;
209 void __iomem
*pipebase
;
217 struct reset_control
*miphy_rst
;
221 /* Sysconfig registers offsets needed to configure the device */
222 u32 syscfg_reg
[SYSCFG_REG_MAX
];
226 struct miphy28lp_dev
{
228 struct regmap
*regmap
;
229 struct mutex miphy_mutex
;
230 struct miphy28lp_phy
**phys
;
233 struct miphy_initval
{
238 enum miphy_sata_gen
{ SATA_GEN1
, SATA_GEN2
, SATA_GEN3
};
240 static char *PHY_TYPE_name
[] = { "sata-up", "pcie-up", "", "usb3-up" };
251 static struct pll_ratio sata_pll_ratio
= {
260 static struct pll_ratio pcie_pll_ratio
= {
269 static struct pll_ratio usb3_pll_ratio
= {
278 struct miphy28lp_pll_gen
{
294 static struct miphy28lp_pll_gen sata_pll_gen
[] = {
297 .speed
= TX_SPDSEL_80DEC
| RX_SPDSEL_80DEC
,
298 .bias_boost_1
= 0x00,
299 .bias_boost_2
= 0xae,
302 .rx_buff_ctrl
= EQ_BOOST_GAIN
| EQ_DC_GAIN
| VGA_GAIN
,
304 .rx_equ_gain_1
= 0x7d,
305 .rx_equ_gain_2
= 0x56,
306 .rx_equ_gain_3
= 0x00,
310 .speed
= TX_SPDSEL_40DEC
| RX_SPDSEL_40DEC
,
311 .bias_boost_1
= 0x00,
312 .bias_boost_2
= 0xae,
315 .rx_buff_ctrl
= EQ_BOOST_GAIN
| EQ_DC_GAIN
| VGA_GAIN
,
317 .rx_equ_gain_1
= 0x7d,
318 .rx_equ_gain_2
= 0x56,
319 .rx_equ_gain_3
= 0x00,
323 .speed
= TX_SPDSEL_20DEC
| RX_SPDSEL_20DEC
,
324 .bias_boost_1
= 0x00,
325 .bias_boost_2
= 0xae,
328 .rx_buff_ctrl
= EQ_BOOST_GAIN
| EQ_DC_GAIN
| VGA_GAIN
,
330 .rx_equ_gain_1
= 0x7d,
331 .rx_equ_gain_2
= 0x56,
332 .rx_equ_gain_3
= 0x00,
336 static struct miphy28lp_pll_gen pcie_pll_gen
[] = {
339 .speed
= TX_SPDSEL_40DEC
| RX_SPDSEL_40DEC
,
340 .bias_boost_1
= 0x00,
341 .bias_boost_2
= 0xa5,
342 .tx_ctrl_1
= TX_REG_STEP_N_25MV
,
346 .rx_buff_ctrl
= EQ_BOOST_GAIN
| EQ_DC_GAIN
| VGA_GAIN
,
348 .rx_equ_gain_1
= 0x79,
349 .rx_equ_gain_2
= 0x56,
353 .speed
= TX_SPDSEL_20DEC
| RX_SPDSEL_20DEC
,
354 .bias_boost_1
= 0x00,
355 .bias_boost_2
= 0xa5,
356 .tx_ctrl_1
= TX_REG_STEP_N_25MV
,
360 .rx_buff_ctrl
= EQ_BOOST_GAIN
| EQ_DC_GAIN
| VGA_GAIN
,
362 .rx_equ_gain_1
= 0x78,
363 .rx_equ_gain_2
= 0x07,
367 static inline void miphy28lp_set_reset(struct miphy28lp_phy
*miphy_phy
)
369 void *base
= miphy_phy
->base
;
372 /* Putting Macro in reset */
373 writeb_relaxed(RST_APPLI_SW
, base
+ MIPHY_CONF_RESET
);
375 val
= RST_APPLI_SW
| RST_CONF_SW
;
376 writeb_relaxed(val
, base
+ MIPHY_CONF_RESET
);
378 writeb_relaxed(RST_APPLI_SW
, base
+ MIPHY_CONF_RESET
);
380 /* Bringing the MIPHY-CPU registers out of reset */
381 if (miphy_phy
->type
== PHY_TYPE_PCIE
) {
382 val
= AUTO_RST_RX
| TERM_EN_SW
;
383 writeb_relaxed(val
, base
+ MIPHY_CONTROL
);
385 val
= AUTO_RST_RX
| TERM_EN_SW
| DIS_LINK_RST
;
386 writeb_relaxed(val
, base
+ MIPHY_CONTROL
);
390 static inline void miphy28lp_pll_calibration(struct miphy28lp_phy
*miphy_phy
,
391 struct pll_ratio
*pll_ratio
)
393 void *base
= miphy_phy
->base
;
396 /* Applying PLL Settings */
397 writeb_relaxed(0x1d, base
+ MIPHY_PLL_SPAREIN
);
398 writeb_relaxed(pll_ratio
->clk_ref
, base
+ MIPHY_PLL_CLKREF_FREQ
);
401 writeb_relaxed(pll_ratio
->calset_1
, base
+ MIPHY_PLL_CALSET_1
);
402 writeb_relaxed(pll_ratio
->calset_2
, base
+ MIPHY_PLL_CALSET_2
);
403 writeb_relaxed(pll_ratio
->calset_3
, base
+ MIPHY_PLL_CALSET_3
);
404 writeb_relaxed(pll_ratio
->calset_4
, base
+ MIPHY_PLL_CALSET_4
);
405 writeb_relaxed(pll_ratio
->cal_ctrl
, base
+ MIPHY_PLL_CALSET_CTRL
);
407 writeb_relaxed(TX_SEL
, base
+ MIPHY_BOUNDARY_SEL
);
409 val
= (0x68 << 1) | TX_SLEW_CAL_MAN_EN
;
410 writeb_relaxed(val
, base
+ MIPHY_TX_CAL_MAN
);
412 val
= VGA_OFFSET_POLARITY
| CAL_OFFSET_THRESHOLD_64
| CAL_OFFSET_VGA_64
;
414 if (miphy_phy
->type
!= PHY_TYPE_SATA
)
415 val
|= OFFSET_COMPENSATION_EN
;
417 writeb_relaxed(val
, base
+ MIPHY_RX_CAL_OFFSET_CTRL
);
419 if (miphy_phy
->type
== PHY_TYPE_USB3
) {
420 writeb_relaxed(0x00, base
+ MIPHY_CONF
);
421 writeb_relaxed(0x70, base
+ MIPHY_RX_LOCK_STEP
);
422 writeb_relaxed(EN_FIRST_HALF
, base
+ MIPHY_RX_SIGDET_SLEEP_OA
);
423 writeb_relaxed(EN_FIRST_HALF
, base
+ MIPHY_RX_SIGDET_SLEEP_SEL
);
424 writeb_relaxed(EN_FIRST_HALF
, base
+ MIPHY_RX_SIGDET_WAIT_SEL
);
426 val
= EN_DIGIT_SIGNAL_CHECK
| EN_FIRST_HALF
;
427 writeb_relaxed(val
, base
+ MIPHY_RX_SIGDET_DATA_SEL
);
432 static inline void miphy28lp_sata_config_gen(struct miphy28lp_phy
*miphy_phy
)
434 void __iomem
*base
= miphy_phy
->base
;
437 for (i
= 0; i
< ARRAY_SIZE(sata_pll_gen
); i
++) {
438 struct miphy28lp_pll_gen
*gen
= &sata_pll_gen
[i
];
440 /* Banked settings */
441 writeb_relaxed(gen
->bank
, base
+ MIPHY_CONF
);
442 writeb_relaxed(gen
->speed
, base
+ MIPHY_SPEED
);
443 writeb_relaxed(gen
->bias_boost_1
, base
+ MIPHY_BIAS_BOOST_1
);
444 writeb_relaxed(gen
->bias_boost_2
, base
+ MIPHY_BIAS_BOOST_2
);
446 /* TX buffer Settings */
447 writeb_relaxed(gen
->tx_ctrl_2
, base
+ MIPHY_TX_CTRL_2
);
448 writeb_relaxed(gen
->tx_ctrl_3
, base
+ MIPHY_TX_CTRL_3
);
450 /* RX Buffer Settings */
451 writeb_relaxed(gen
->rx_buff_ctrl
, base
+ MIPHY_RX_BUFFER_CTRL
);
452 writeb_relaxed(gen
->rx_vga_gain
, base
+ MIPHY_RX_VGA_GAIN
);
453 writeb_relaxed(gen
->rx_equ_gain_1
, base
+ MIPHY_RX_EQU_GAIN_1
);
454 writeb_relaxed(gen
->rx_equ_gain_2
, base
+ MIPHY_RX_EQU_GAIN_2
);
455 writeb_relaxed(gen
->rx_equ_gain_3
, base
+ MIPHY_RX_EQU_GAIN_3
);
459 static inline void miphy28lp_pcie_config_gen(struct miphy28lp_phy
*miphy_phy
)
461 void __iomem
*base
= miphy_phy
->base
;
464 for (i
= 0; i
< ARRAY_SIZE(pcie_pll_gen
); i
++) {
465 struct miphy28lp_pll_gen
*gen
= &pcie_pll_gen
[i
];
467 /* Banked settings */
468 writeb_relaxed(gen
->bank
, base
+ MIPHY_CONF
);
469 writeb_relaxed(gen
->speed
, base
+ MIPHY_SPEED
);
470 writeb_relaxed(gen
->bias_boost_1
, base
+ MIPHY_BIAS_BOOST_1
);
471 writeb_relaxed(gen
->bias_boost_2
, base
+ MIPHY_BIAS_BOOST_2
);
473 /* TX buffer Settings */
474 writeb_relaxed(gen
->tx_ctrl_1
, base
+ MIPHY_TX_CTRL_1
);
475 writeb_relaxed(gen
->tx_ctrl_2
, base
+ MIPHY_TX_CTRL_2
);
476 writeb_relaxed(gen
->tx_ctrl_3
, base
+ MIPHY_TX_CTRL_3
);
478 writeb_relaxed(gen
->rx_k_gain
, base
+ MIPHY_RX_K_GAIN
);
480 /* RX Buffer Settings */
481 writeb_relaxed(gen
->rx_buff_ctrl
, base
+ MIPHY_RX_BUFFER_CTRL
);
482 writeb_relaxed(gen
->rx_vga_gain
, base
+ MIPHY_RX_VGA_GAIN
);
483 writeb_relaxed(gen
->rx_equ_gain_1
, base
+ MIPHY_RX_EQU_GAIN_1
);
484 writeb_relaxed(gen
->rx_equ_gain_2
, base
+ MIPHY_RX_EQU_GAIN_2
);
488 static inline int miphy28lp_wait_compensation(struct miphy28lp_phy
*miphy_phy
)
490 unsigned long finish
= jiffies
+ 5 * HZ
;
493 /* Waiting for Compensation to complete */
495 val
= readb_relaxed(miphy_phy
->base
+ MIPHY_COMP_FSM_6
);
497 if (time_after_eq(jiffies
, finish
))
500 } while (!(val
& COMP_DONE
));
506 static inline int miphy28lp_compensation(struct miphy28lp_phy
*miphy_phy
,
507 struct pll_ratio
*pll_ratio
)
509 void __iomem
*base
= miphy_phy
->base
;
511 /* Poll for HFC ready after reset release */
512 /* Compensation measurement */
513 writeb_relaxed(RST_PLL_SW
| RST_COMP_SW
, base
+ MIPHY_RESET
);
515 writeb_relaxed(0x00, base
+ MIPHY_PLL_COMMON_MISC_2
);
516 writeb_relaxed(pll_ratio
->clk_ref
, base
+ MIPHY_PLL_CLKREF_FREQ
);
517 writeb_relaxed(COMP_START
, base
+ MIPHY_COMP_FSM_1
);
519 if (miphy_phy
->type
== PHY_TYPE_PCIE
)
520 writeb_relaxed(RST_PLL_SW
, base
+ MIPHY_RESET
);
522 writeb_relaxed(0x00, base
+ MIPHY_RESET
);
523 writeb_relaxed(START_ACT_FILT
, base
+ MIPHY_PLL_COMMON_MISC_2
);
524 writeb_relaxed(SET_NEW_CHANGE
, base
+ MIPHY_PLL_SBR_1
);
526 /* TX compensation offset to re-center TX impedance */
527 writeb_relaxed(0x00, base
+ MIPHY_COMP_POSTP
);
529 if (miphy_phy
->type
== PHY_TYPE_PCIE
)
530 return miphy28lp_wait_compensation(miphy_phy
);
535 static inline void miphy28_usb3_miphy_reset(struct miphy28lp_phy
*miphy_phy
)
537 void __iomem
*base
= miphy_phy
->base
;
541 writeb_relaxed(RST_APPLI_SW
, base
+ MIPHY_CONF_RESET
);
542 writeb_relaxed(0x00, base
+ MIPHY_CONF_RESET
);
543 writeb_relaxed(RST_COMP_SW
, base
+ MIPHY_RESET
);
545 val
= RST_COMP_SW
| RST_PLL_SW
;
546 writeb_relaxed(val
, base
+ MIPHY_RESET
);
548 writeb_relaxed(0x00, base
+ MIPHY_PLL_COMMON_MISC_2
);
549 writeb_relaxed(0x1e, base
+ MIPHY_PLL_CLKREF_FREQ
);
550 writeb_relaxed(COMP_START
, base
+ MIPHY_COMP_FSM_1
);
551 writeb_relaxed(RST_PLL_SW
, base
+ MIPHY_RESET
);
552 writeb_relaxed(0x00, base
+ MIPHY_RESET
);
553 writeb_relaxed(START_ACT_FILT
, base
+ MIPHY_PLL_COMMON_MISC_2
);
554 writeb_relaxed(0x00, base
+ MIPHY_CONF
);
555 writeb_relaxed(0x00, base
+ MIPHY_BOUNDARY_1
);
556 writeb_relaxed(0x00, base
+ MIPHY_TST_BIAS_BOOST_2
);
557 writeb_relaxed(0x00, base
+ MIPHY_CONF
);
558 writeb_relaxed(SET_NEW_CHANGE
, base
+ MIPHY_PLL_SBR_1
);
559 writeb_relaxed(0xa5, base
+ MIPHY_DEBUG_BUS
);
560 writeb_relaxed(0x00, base
+ MIPHY_CONF
);
563 static void miphy_sata_tune_ssc(struct miphy28lp_phy
*miphy_phy
)
565 void __iomem
*base
= miphy_phy
->base
;
568 /* Compensate Tx impedance to avoid out of range values */
570 * Enable the SSC on PLL for all banks
571 * SSC Modulation @ 31 KHz and 4000 ppm modulation amp
573 val
= readb_relaxed(base
+ MIPHY_BOUNDARY_2
);
575 writeb_relaxed(val
, base
+ MIPHY_BOUNDARY_2
);
577 val
= readb_relaxed(base
+ MIPHY_BOUNDARY_SEL
);
579 writeb_relaxed(val
, base
+ MIPHY_BOUNDARY_SEL
);
581 for (val
= 0; val
< MIPHY_SATA_BANK_NB
; val
++) {
582 writeb_relaxed(val
, base
+ MIPHY_CONF
);
584 /* Add value to each reference clock cycle */
585 /* and define the period length of the SSC */
586 writeb_relaxed(0x3c, base
+ MIPHY_PLL_SBR_2
);
587 writeb_relaxed(0x6c, base
+ MIPHY_PLL_SBR_3
);
588 writeb_relaxed(0x81, base
+ MIPHY_PLL_SBR_4
);
590 /* Clear any previous request */
591 writeb_relaxed(0x00, base
+ MIPHY_PLL_SBR_1
);
593 /* requests the PLL to take in account new parameters */
594 writeb_relaxed(SET_NEW_CHANGE
, base
+ MIPHY_PLL_SBR_1
);
596 /* To be sure there is no other pending requests */
597 writeb_relaxed(0x00, base
+ MIPHY_PLL_SBR_1
);
601 static void miphy_pcie_tune_ssc(struct miphy28lp_phy
*miphy_phy
)
603 void __iomem
*base
= miphy_phy
->base
;
606 /* Compensate Tx impedance to avoid out of range values */
608 * Enable the SSC on PLL for all banks
609 * SSC Modulation @ 31 KHz and 4000 ppm modulation amp
611 val
= readb_relaxed(base
+ MIPHY_BOUNDARY_2
);
613 writeb_relaxed(val
, base
+ MIPHY_BOUNDARY_2
);
615 val
= readb_relaxed(base
+ MIPHY_BOUNDARY_SEL
);
617 writeb_relaxed(val
, base
+ MIPHY_BOUNDARY_SEL
);
619 for (val
= 0; val
< MIPHY_PCIE_BANK_NB
; val
++) {
620 writeb_relaxed(val
, base
+ MIPHY_CONF
);
622 /* Validate Step component */
623 writeb_relaxed(0x69, base
+ MIPHY_PLL_SBR_3
);
624 writeb_relaxed(0x21, base
+ MIPHY_PLL_SBR_4
);
626 /* Validate Period component */
627 writeb_relaxed(0x3c, base
+ MIPHY_PLL_SBR_2
);
628 writeb_relaxed(0x21, base
+ MIPHY_PLL_SBR_4
);
630 /* Clear any previous request */
631 writeb_relaxed(0x00, base
+ MIPHY_PLL_SBR_1
);
633 /* requests the PLL to take in account new parameters */
634 writeb_relaxed(SET_NEW_CHANGE
, base
+ MIPHY_PLL_SBR_1
);
636 /* To be sure there is no other pending requests */
637 writeb_relaxed(0x00, base
+ MIPHY_PLL_SBR_1
);
641 static inline void miphy_tune_tx_impedance(struct miphy28lp_phy
*miphy_phy
)
643 /* Compensate Tx impedance to avoid out of range values */
644 writeb_relaxed(0x02, miphy_phy
->base
+ MIPHY_COMP_POSTP
);
647 static inline int miphy28lp_configure_sata(struct miphy28lp_phy
*miphy_phy
)
649 void __iomem
*base
= miphy_phy
->base
;
653 /* Putting Macro in reset */
654 miphy28lp_set_reset(miphy_phy
);
656 /* PLL calibration */
657 miphy28lp_pll_calibration(miphy_phy
, &sata_pll_ratio
);
659 /* Banked settings Gen1/Gen2/Gen3 */
660 miphy28lp_sata_config_gen(miphy_phy
);
663 /* Input bridge enable, manual input bridge control */
664 writeb_relaxed(0x21, base
+ MIPHY_RX_POWER_CTRL_1
);
666 /* Macro out of reset */
667 writeb_relaxed(0x00, base
+ MIPHY_CONF_RESET
);
669 /* Poll for HFC ready after reset release */
670 /* Compensation measurement */
671 err
= miphy28lp_compensation(miphy_phy
, &sata_pll_ratio
);
675 if (miphy_phy
->px_rx_pol_inv
) {
676 /* Invert Rx polarity */
677 val
= readb_relaxed(miphy_phy
->base
+ MIPHY_CONTROL
);
679 writeb_relaxed(val
, miphy_phy
->base
+ MIPHY_CONTROL
);
683 miphy_sata_tune_ssc(miphy_phy
);
685 if (miphy_phy
->tx_impedance
)
686 miphy_tune_tx_impedance(miphy_phy
);
691 static inline int miphy28lp_configure_pcie(struct miphy28lp_phy
*miphy_phy
)
693 void __iomem
*base
= miphy_phy
->base
;
696 /* Putting Macro in reset */
697 miphy28lp_set_reset(miphy_phy
);
699 /* PLL calibration */
700 miphy28lp_pll_calibration(miphy_phy
, &pcie_pll_ratio
);
702 /* Banked settings Gen1/Gen2 */
703 miphy28lp_pcie_config_gen(miphy_phy
);
706 /* Input bridge enable, manual input bridge control */
707 writeb_relaxed(0x21, base
+ MIPHY_RX_POWER_CTRL_1
);
709 /* Macro out of reset */
710 writeb_relaxed(0x00, base
+ MIPHY_CONF_RESET
);
712 /* Poll for HFC ready after reset release */
713 /* Compensation measurement */
714 err
= miphy28lp_compensation(miphy_phy
, &pcie_pll_ratio
);
719 miphy_pcie_tune_ssc(miphy_phy
);
721 if (miphy_phy
->tx_impedance
)
722 miphy_tune_tx_impedance(miphy_phy
);
728 static inline void miphy28lp_configure_usb3(struct miphy28lp_phy
*miphy_phy
)
730 void __iomem
*base
= miphy_phy
->base
;
733 /* Putting Macro in reset */
734 miphy28lp_set_reset(miphy_phy
);
736 /* PLL calibration */
737 miphy28lp_pll_calibration(miphy_phy
, &usb3_pll_ratio
);
739 /* Writing The Speed Rate */
740 writeb_relaxed(0x00, base
+ MIPHY_CONF
);
742 val
= RX_SPDSEL_20DEC
| TX_SPDSEL_20DEC
;
743 writeb_relaxed(val
, base
+ MIPHY_SPEED
);
745 /* RX Channel compensation and calibration */
746 writeb_relaxed(0x1c, base
+ MIPHY_RX_LOCK_SETTINGS_OPT
);
747 writeb_relaxed(0x51, base
+ MIPHY_RX_CAL_CTRL_1
);
748 writeb_relaxed(0x70, base
+ MIPHY_RX_CAL_CTRL_2
);
750 val
= OFFSET_COMPENSATION_EN
| VGA_OFFSET_POLARITY
|
751 CAL_OFFSET_THRESHOLD_64
| CAL_OFFSET_VGA_64
;
752 writeb_relaxed(val
, base
+ MIPHY_RX_CAL_OFFSET_CTRL
);
753 writeb_relaxed(0x22, base
+ MIPHY_RX_CAL_VGA_STEP
);
754 writeb_relaxed(0x0e, base
+ MIPHY_RX_CAL_OPT_LENGTH
);
756 val
= EQ_DC_GAIN
| VGA_GAIN
;
757 writeb_relaxed(val
, base
+ MIPHY_RX_BUFFER_CTRL
);
758 writeb_relaxed(0x78, base
+ MIPHY_RX_EQU_GAIN_1
);
759 writeb_relaxed(0x1b, base
+ MIPHY_SYNCHAR_CONTROL
);
761 /* TX compensation offset to re-center TX impedance */
762 writeb_relaxed(0x02, base
+ MIPHY_COMP_POSTP
);
764 /* Enable GENSEL_SEL and SSC */
765 /* TX_SEL=0 swing preemp forced by pipe registres */
766 val
= SSC_SEL
| GENSEL_SEL
;
767 writeb_relaxed(val
, base
+ MIPHY_BOUNDARY_SEL
);
769 /* MIPHY Bias boost */
770 writeb_relaxed(0x00, base
+ MIPHY_BIAS_BOOST_1
);
771 writeb_relaxed(0xa7, base
+ MIPHY_BIAS_BOOST_2
);
774 writeb_relaxed(SSC_EN_SW
, base
+ MIPHY_BOUNDARY_2
);
776 /* MIPHY TX control */
777 writeb_relaxed(0x00, base
+ MIPHY_CONF
);
779 /* Validate Step component */
780 writeb_relaxed(0x5a, base
+ MIPHY_PLL_SBR_3
);
781 writeb_relaxed(0xa0, base
+ MIPHY_PLL_SBR_4
);
783 /* Validate Period component */
784 writeb_relaxed(0x3c, base
+ MIPHY_PLL_SBR_2
);
785 writeb_relaxed(0xa1, base
+ MIPHY_PLL_SBR_4
);
787 /* Clear any previous request */
788 writeb_relaxed(0x00, base
+ MIPHY_PLL_SBR_1
);
790 /* requests the PLL to take in account new parameters */
791 writeb_relaxed(0x02, base
+ MIPHY_PLL_SBR_1
);
793 /* To be sure there is no other pending requests */
794 writeb_relaxed(0x00, base
+ MIPHY_PLL_SBR_1
);
796 /* Rx PI controller settings */
797 writeb_relaxed(0xca, base
+ MIPHY_RX_K_GAIN
);
799 /* MIPHY RX input bridge control */
800 /* INPUT_BRIDGE_EN_SW=1, manual input bridge control[0]=1 */
801 writeb_relaxed(0x21, base
+ MIPHY_RX_POWER_CTRL_1
);
802 writeb_relaxed(0x29, base
+ MIPHY_RX_POWER_CTRL_1
);
803 writeb_relaxed(0x1a, base
+ MIPHY_RX_POWER_CTRL_2
);
805 /* MIPHY Reset for usb3 */
806 miphy28_usb3_miphy_reset(miphy_phy
);
809 static inline int miphy_is_ready(struct miphy28lp_phy
*miphy_phy
)
811 unsigned long finish
= jiffies
+ 5 * HZ
;
812 u8 mask
= HFC_PLL
| HFC_RDY
;
816 * For PCIe and USB3 check only that PLL and HFC are ready
817 * For SATA check also that phy is ready!
819 if (miphy_phy
->type
== PHY_TYPE_SATA
)
823 val
= readb_relaxed(miphy_phy
->base
+ MIPHY_STATUS_1
);
824 if ((val
& mask
) != mask
)
828 } while (!time_after_eq(jiffies
, finish
));
833 static int miphy_osc_is_ready(struct miphy28lp_phy
*miphy_phy
)
835 struct miphy28lp_dev
*miphy_dev
= miphy_phy
->phydev
;
836 unsigned long finish
= jiffies
+ 5 * HZ
;
839 if (!miphy_phy
->osc_rdy
)
842 if (!miphy_phy
->syscfg_reg
[SYSCFG_STATUS
])
846 regmap_read(miphy_dev
->regmap
,
847 miphy_phy
->syscfg_reg
[SYSCFG_STATUS
], &val
);
849 if ((val
& MIPHY_OSC_RDY
) != MIPHY_OSC_RDY
)
853 } while (!time_after_eq(jiffies
, finish
));
858 static int miphy28lp_get_resource_byname(struct device_node
*child
,
859 char *rname
, struct resource
*res
)
863 index
= of_property_match_string(child
, "reg-names", rname
);
867 return of_address_to_resource(child
, index
, res
);
870 static int miphy28lp_get_one_addr(struct device
*dev
,
871 struct device_node
*child
, char *rname
,
877 ret
= miphy28lp_get_resource_byname(child
, rname
, &res
);
879 *base
= devm_ioremap(dev
, res
.start
, resource_size(&res
));
881 dev_err(dev
, "failed to ioremap %s address region\n"
890 /* MiPHY reset and sysconf setup */
891 static int miphy28lp_setup(struct miphy28lp_phy
*miphy_phy
, u32 miphy_val
)
894 struct miphy28lp_dev
*miphy_dev
= miphy_phy
->phydev
;
896 if (!miphy_phy
->syscfg_reg
[SYSCFG_CTRL
])
899 err
= reset_control_assert(miphy_phy
->miphy_rst
);
901 dev_err(miphy_dev
->dev
, "unable to bring out of miphy reset\n");
905 if (miphy_phy
->osc_force_ext
)
906 miphy_val
|= MIPHY_OSC_FORCE_EXT
;
908 regmap_update_bits(miphy_dev
->regmap
,
909 miphy_phy
->syscfg_reg
[SYSCFG_CTRL
],
910 MIPHY_CTRL_MASK
, miphy_val
);
912 err
= reset_control_deassert(miphy_phy
->miphy_rst
);
914 dev_err(miphy_dev
->dev
, "unable to bring out of miphy reset\n");
918 return miphy_osc_is_ready(miphy_phy
);
921 static int miphy28lp_init_sata(struct miphy28lp_phy
*miphy_phy
)
923 struct miphy28lp_dev
*miphy_dev
= miphy_phy
->phydev
;
924 int err
, sata_conf
= SATA_CTRL_SELECT_SATA
;
926 if ((!miphy_phy
->syscfg_reg
[SYSCFG_SATA
]) ||
927 (!miphy_phy
->syscfg_reg
[SYSCFG_PCI
]) ||
931 dev_info(miphy_dev
->dev
, "sata-up mode, addr 0x%p\n", miphy_phy
->base
);
933 /* Configure the glue-logic */
934 sata_conf
|= ((miphy_phy
->sata_gen
- SATA_GEN1
) << SATA_SPDMODE
);
936 regmap_update_bits(miphy_dev
->regmap
,
937 miphy_phy
->syscfg_reg
[SYSCFG_SATA
],
938 SATA_CTRL_MASK
, sata_conf
);
940 regmap_update_bits(miphy_dev
->regmap
, miphy_phy
->syscfg_reg
[SYSCFG_PCI
],
941 PCIE_CTRL_MASK
, SATA_CTRL_SELECT_PCIE
);
943 /* MiPHY path and clocking init */
944 err
= miphy28lp_setup(miphy_phy
, MIPHY_CTRL_DEFAULT
);
947 dev_err(miphy_dev
->dev
, "SATA phy setup failed\n");
951 /* initialize miphy */
952 miphy28lp_configure_sata(miphy_phy
);
954 return miphy_is_ready(miphy_phy
);
957 static int miphy28lp_init_pcie(struct miphy28lp_phy
*miphy_phy
)
959 struct miphy28lp_dev
*miphy_dev
= miphy_phy
->phydev
;
962 if ((!miphy_phy
->syscfg_reg
[SYSCFG_SATA
]) ||
963 (!miphy_phy
->syscfg_reg
[SYSCFG_PCI
])
964 || (!miphy_phy
->base
) || (!miphy_phy
->pipebase
))
967 dev_info(miphy_dev
->dev
, "pcie-up mode, addr 0x%p\n", miphy_phy
->base
);
969 /* Configure the glue-logic */
970 regmap_update_bits(miphy_dev
->regmap
,
971 miphy_phy
->syscfg_reg
[SYSCFG_SATA
],
972 SATA_CTRL_MASK
, SATA_CTRL_SELECT_PCIE
);
974 regmap_update_bits(miphy_dev
->regmap
, miphy_phy
->syscfg_reg
[SYSCFG_PCI
],
975 PCIE_CTRL_MASK
, SYSCFG_PCIE_PCIE_VAL
);
977 /* MiPHY path and clocking init */
978 err
= miphy28lp_setup(miphy_phy
, MIPHY_CTRL_DEFAULT
);
981 dev_err(miphy_dev
->dev
, "PCIe phy setup failed\n");
985 /* initialize miphy */
986 err
= miphy28lp_configure_pcie(miphy_phy
);
990 /* PIPE Wrapper Configuration */
991 writeb_relaxed(0x68, miphy_phy
->pipebase
+ 0x104); /* Rise_0 */
992 writeb_relaxed(0x61, miphy_phy
->pipebase
+ 0x105); /* Rise_1 */
993 writeb_relaxed(0x68, miphy_phy
->pipebase
+ 0x108); /* Fall_0 */
994 writeb_relaxed(0x61, miphy_phy
->pipebase
+ 0x109); /* Fall-1 */
995 writeb_relaxed(0x68, miphy_phy
->pipebase
+ 0x10c); /* Threshold_0 */
996 writeb_relaxed(0x60, miphy_phy
->pipebase
+ 0x10d); /* Threshold_1 */
998 /* Wait for phy_ready */
999 return miphy_is_ready(miphy_phy
);
1002 static int miphy28lp_init_usb3(struct miphy28lp_phy
*miphy_phy
)
1004 struct miphy28lp_dev
*miphy_dev
= miphy_phy
->phydev
;
1007 if ((!miphy_phy
->base
) || (!miphy_phy
->pipebase
))
1010 dev_info(miphy_dev
->dev
, "usb3-up mode, addr 0x%p\n", miphy_phy
->base
);
1012 /* MiPHY path and clocking init */
1013 err
= miphy28lp_setup(miphy_phy
, MIPHY_CTRL_SYNC_D_EN
);
1015 dev_err(miphy_dev
->dev
, "USB3 phy setup failed\n");
1019 /* initialize miphy */
1020 miphy28lp_configure_usb3(miphy_phy
);
1022 /* PIPE Wrapper Configuration */
1023 writeb_relaxed(0x68, miphy_phy
->pipebase
+ 0x23);
1024 writeb_relaxed(0x61, miphy_phy
->pipebase
+ 0x24);
1025 writeb_relaxed(0x68, miphy_phy
->pipebase
+ 0x26);
1026 writeb_relaxed(0x61, miphy_phy
->pipebase
+ 0x27);
1027 writeb_relaxed(0x18, miphy_phy
->pipebase
+ 0x29);
1028 writeb_relaxed(0x61, miphy_phy
->pipebase
+ 0x2a);
1030 /* pipe Wrapper usb3 TX swing de-emph margin PREEMPH[7:4], SWING[3:0] */
1031 writeb_relaxed(0X67, miphy_phy
->pipebase
+ 0x68);
1032 writeb_relaxed(0x0d, miphy_phy
->pipebase
+ 0x69);
1033 writeb_relaxed(0X67, miphy_phy
->pipebase
+ 0x6a);
1034 writeb_relaxed(0X0d, miphy_phy
->pipebase
+ 0x6b);
1035 writeb_relaxed(0X67, miphy_phy
->pipebase
+ 0x6c);
1036 writeb_relaxed(0X0d, miphy_phy
->pipebase
+ 0x6d);
1037 writeb_relaxed(0X67, miphy_phy
->pipebase
+ 0x6e);
1038 writeb_relaxed(0X0d, miphy_phy
->pipebase
+ 0x6f);
1040 return miphy_is_ready(miphy_phy
);
1043 static int miphy28lp_init(struct phy
*phy
)
1045 struct miphy28lp_phy
*miphy_phy
= phy_get_drvdata(phy
);
1046 struct miphy28lp_dev
*miphy_dev
= miphy_phy
->phydev
;
1049 mutex_lock(&miphy_dev
->miphy_mutex
);
1051 switch (miphy_phy
->type
) {
1054 ret
= miphy28lp_init_sata(miphy_phy
);
1057 ret
= miphy28lp_init_pcie(miphy_phy
);
1060 ret
= miphy28lp_init_usb3(miphy_phy
);
1067 mutex_unlock(&miphy_dev
->miphy_mutex
);
1072 static int miphy28lp_get_addr(struct miphy28lp_phy
*miphy_phy
)
1074 struct miphy28lp_dev
*miphy_dev
= miphy_phy
->phydev
;
1075 struct device_node
*phynode
= miphy_phy
->phy
->dev
.of_node
;
1078 if ((miphy_phy
->type
!= PHY_TYPE_SATA
) &&
1079 (miphy_phy
->type
!= PHY_TYPE_PCIE
) &&
1080 (miphy_phy
->type
!= PHY_TYPE_USB3
)) {
1084 err
= miphy28lp_get_one_addr(miphy_dev
->dev
, phynode
,
1085 PHY_TYPE_name
[miphy_phy
->type
- PHY_TYPE_SATA
],
1090 if ((miphy_phy
->type
== PHY_TYPE_PCIE
) ||
1091 (miphy_phy
->type
== PHY_TYPE_USB3
)) {
1092 err
= miphy28lp_get_one_addr(miphy_dev
->dev
, phynode
, "pipew",
1093 &miphy_phy
->pipebase
);
1101 static struct phy
*miphy28lp_xlate(struct device
*dev
,
1102 struct of_phandle_args
*args
)
1104 struct miphy28lp_dev
*miphy_dev
= dev_get_drvdata(dev
);
1105 struct miphy28lp_phy
*miphy_phy
= NULL
;
1106 struct device_node
*phynode
= args
->np
;
1109 if (!of_device_is_available(phynode
)) {
1110 dev_warn(dev
, "Requested PHY is disabled\n");
1111 return ERR_PTR(-ENODEV
);
1114 if (args
->args_count
!= 1) {
1115 dev_err(dev
, "Invalid number of cells in 'phy' property\n");
1116 return ERR_PTR(-EINVAL
);
1119 for (index
= 0; index
< of_get_child_count(dev
->of_node
); index
++)
1120 if (phynode
== miphy_dev
->phys
[index
]->phy
->dev
.of_node
) {
1121 miphy_phy
= miphy_dev
->phys
[index
];
1126 dev_err(dev
, "Failed to find appropriate phy\n");
1127 return ERR_PTR(-EINVAL
);
1130 miphy_phy
->type
= args
->args
[0];
1132 ret
= miphy28lp_get_addr(miphy_phy
);
1134 return ERR_PTR(ret
);
1136 return miphy_phy
->phy
;
1139 static struct phy_ops miphy28lp_ops
= {
1140 .init
= miphy28lp_init
,
1143 static int miphy28lp_probe_resets(struct device_node
*node
,
1144 struct miphy28lp_phy
*miphy_phy
)
1146 struct miphy28lp_dev
*miphy_dev
= miphy_phy
->phydev
;
1149 miphy_phy
->miphy_rst
= of_reset_control_get(node
, "miphy-sw-rst");
1151 if (IS_ERR(miphy_phy
->miphy_rst
)) {
1152 dev_err(miphy_dev
->dev
,
1153 "miphy soft reset control not defined\n");
1154 return PTR_ERR(miphy_phy
->miphy_rst
);
1157 err
= reset_control_deassert(miphy_phy
->miphy_rst
);
1159 dev_err(miphy_dev
->dev
, "unable to bring out of miphy reset\n");
1166 static int miphy28lp_of_probe(struct device_node
*np
,
1167 struct miphy28lp_phy
*miphy_phy
)
1172 miphy_phy
->osc_force_ext
=
1173 of_property_read_bool(np
, "st,osc-force-ext");
1175 miphy_phy
->osc_rdy
= of_property_read_bool(np
, "st,osc-rdy");
1177 miphy_phy
->px_rx_pol_inv
=
1178 of_property_read_bool(np
, "st,px_rx_pol_inv");
1180 miphy_phy
->ssc
= of_property_read_bool(np
, "st,ssc-on");
1182 miphy_phy
->tx_impedance
=
1183 of_property_read_bool(np
, "st,tx-impedance-comp");
1185 of_property_read_u32(np
, "st,sata-gen", &miphy_phy
->sata_gen
);
1186 if (!miphy_phy
->sata_gen
)
1187 miphy_phy
->sata_gen
= SATA_GEN1
;
1189 for (i
= 0; i
< SYSCFG_REG_MAX
; i
++) {
1190 if (!of_property_read_u32_index(np
, "st,syscfg", i
, &ctrlreg
))
1191 miphy_phy
->syscfg_reg
[i
] = ctrlreg
;
1197 static int miphy28lp_probe(struct platform_device
*pdev
)
1199 struct device_node
*child
, *np
= pdev
->dev
.of_node
;
1200 struct miphy28lp_dev
*miphy_dev
;
1201 struct phy_provider
*provider
;
1203 int chancount
, port
= 0;
1206 miphy_dev
= devm_kzalloc(&pdev
->dev
, sizeof(*miphy_dev
), GFP_KERNEL
);
1210 chancount
= of_get_child_count(np
);
1211 miphy_dev
->phys
= devm_kzalloc(&pdev
->dev
, sizeof(phy
) * chancount
,
1213 if (!miphy_dev
->phys
)
1216 miphy_dev
->regmap
= syscon_regmap_lookup_by_phandle(np
, "st,syscfg");
1217 if (IS_ERR(miphy_dev
->regmap
)) {
1218 dev_err(miphy_dev
->dev
, "No syscfg phandle specified\n");
1219 return PTR_ERR(miphy_dev
->regmap
);
1222 miphy_dev
->dev
= &pdev
->dev
;
1224 dev_set_drvdata(&pdev
->dev
, miphy_dev
);
1226 mutex_init(&miphy_dev
->miphy_mutex
);
1228 for_each_child_of_node(np
, child
) {
1229 struct miphy28lp_phy
*miphy_phy
;
1231 miphy_phy
= devm_kzalloc(&pdev
->dev
, sizeof(*miphy_phy
),
1236 miphy_dev
->phys
[port
] = miphy_phy
;
1238 phy
= devm_phy_create(&pdev
->dev
, child
, &miphy28lp_ops
);
1240 dev_err(&pdev
->dev
, "failed to create PHY\n");
1241 return PTR_ERR(phy
);
1244 miphy_dev
->phys
[port
]->phy
= phy
;
1245 miphy_dev
->phys
[port
]->phydev
= miphy_dev
;
1247 ret
= miphy28lp_of_probe(child
, miphy_phy
);
1251 ret
= miphy28lp_probe_resets(child
, miphy_dev
->phys
[port
]);
1255 phy_set_drvdata(phy
, miphy_dev
->phys
[port
]);
1260 provider
= devm_of_phy_provider_register(&pdev
->dev
, miphy28lp_xlate
);
1261 if (IS_ERR(provider
))
1262 return PTR_ERR(provider
);
1267 static const struct of_device_id miphy28lp_of_match
[] = {
1268 {.compatible
= "st,miphy28lp-phy", },
1272 MODULE_DEVICE_TABLE(of
, miphy28lp_of_match
);
1274 static struct platform_driver miphy28lp_driver
= {
1275 .probe
= miphy28lp_probe
,
1277 .name
= "miphy28lp-phy",
1278 .owner
= THIS_MODULE
,
1279 .of_match_table
= miphy28lp_of_match
,
1283 module_platform_driver(miphy28lp_driver
);
1285 MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@st.com>");
1286 MODULE_DESCRIPTION("STMicroelectronics miphy28lp driver");
1287 MODULE_LICENSE("GPL v2");