drivers/phy/phy-miphy365x.c

   1 /*
   2  * Copyright (C) 2014 STMicroelectronics – All Rights Reserved
   3  *
   4  * STMicroelectronics PHY driver MiPHY365 (for SoC STiH416).
   5  *
   6  * Authors: Alexandre Torgue <alexandre.torgue@st.com>
   7  *          Lee Jones <lee.jones@linaro.org>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  */
  14
  15 #include <linux/platform_device.h>
  16 #include <linux/io.h>
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/of_address.h>
  22 #include <linux/clk.h>
  23 #include <linux/phy/phy.h>
  24 #include <linux/delay.h>
  25 #include <linux/mfd/syscon.h>
  26 #include <linux/regmap.h>
  27
  28 #include <dt-bindings/phy/phy-miphy365x.h>
  29
  30 #define HFC_TIMEOUT             100
  31
  32 #define SYSCFG_SELECT_SATA_MASK BIT(1)
  33 #define SYSCFG_SELECT_SATA_POS  1
  34
  35 /* MiPHY365x register definitions */
  36 #define RESET_REG               0x00
  37 #define RST_PLL                 BIT(1)
  38 #define RST_PLL_CAL             BIT(2)
  39 #define RST_RX                  BIT(4)
  40 #define RST_MACRO               BIT(7)
  41
  42 #define STATUS_REG              0x01
  43 #define IDLL_RDY                BIT(0)
  44 #define PLL_RDY                 BIT(1)
  45 #define DES_BIT_LOCK            BIT(2)
  46 #define DES_SYMBOL_LOCK         BIT(3)
  47
  48 #define CTRL_REG                0x02
  49 #define TERM_EN                 BIT(0)
  50 #define PCI_EN                  BIT(2)
  51 #define DES_BIT_LOCK_EN         BIT(3)
  52 #define TX_POL                  BIT(5)
  53
  54 #define INT_CTRL_REG            0x03
  55
  56 #define BOUNDARY1_REG           0x10
  57 #define SPDSEL_SEL              BIT(0)
  58
  59 #define BOUNDARY3_REG           0x12
  60 #define TX_SPDSEL_GEN1_VAL      0
  61 #define TX_SPDSEL_GEN2_VAL      0x01
  62 #define TX_SPDSEL_GEN3_VAL      0x02
  63 #define RX_SPDSEL_GEN1_VAL      0
  64 #define RX_SPDSEL_GEN2_VAL      (0x01 << 3)
  65 #define RX_SPDSEL_GEN3_VAL      (0x02 << 3)
  66
  67 #define PCIE_REG                0x16
  68
  69 #define BUF_SEL_REG             0x20
  70 #define CONF_GEN_SEL_GEN3       0x02
  71 #define CONF_GEN_SEL_GEN2       0x01
  72 #define PD_VDDTFILTER           BIT(4)
  73
  74 #define TXBUF1_REG              0x21
  75 #define SWING_VAL               0x04
  76 #define SWING_VAL_GEN1          0x03
  77 #define PREEMPH_VAL             (0x3 << 5)
  78
  79 #define TXBUF2_REG              0x22
  80 #define TXSLEW_VAL              0x2
  81 #define TXSLEW_VAL_GEN1         0x4
  82
  83 #define RXBUF_OFFSET_CTRL_REG   0x23
  84
  85 #define RXBUF_REG               0x25
  86 #define SDTHRES_VAL             0x01
  87 #define EQ_ON3                  (0x03 << 4)
  88 #define EQ_ON1                  (0x01 << 4)
  89
  90 #define COMP_CTRL1_REG          0x40
  91 #define START_COMSR             BIT(0)
  92 #define START_COMZC             BIT(1)
  93 #define COMSR_DONE              BIT(2)
  94 #define COMZC_DONE              BIT(3)
  95 #define COMP_AUTO_LOAD          BIT(4)
  96
  97 #define COMP_CTRL2_REG          0x41
  98 #define COMP_2MHZ_RAT_GEN1      0x1e
  99 #define COMP_2MHZ_RAT           0xf
 100
 101 #define COMP_CTRL3_REG          0x42
 102 #define COMSR_COMP_REF          0x33
 103
 104 #define COMP_IDLL_REG           0x47
 105 #define COMZC_IDLL              0x2a
 106
 107 #define PLL_CTRL1_REG           0x50
 108 #define PLL_START_CAL           BIT(0)
 109 #define BUF_EN                  BIT(2)
 110 #define SYNCHRO_TX              BIT(3)
 111 #define SSC_EN                  BIT(6)
 112 #define CONFIG_PLL              BIT(7)
 113
 114 #define PLL_CTRL2_REG           0x51
 115 #define BYPASS_PLL_CAL          BIT(1)
 116
 117 #define PLL_RAT_REG             0x52
 118
 119 #define PLL_SSC_STEP_MSB_REG    0x56
 120 #define PLL_SSC_STEP_MSB_VAL    0x03
 121
 122 #define PLL_SSC_STEP_LSB_REG    0x57
 123 #define PLL_SSC_STEP_LSB_VAL    0x63
 124
 125 #define PLL_SSC_PER_MSB_REG     0x58
 126 #define PLL_SSC_PER_MSB_VAL     0
 127
 128 #define PLL_SSC_PER_LSB_REG     0x59
 129 #define PLL_SSC_PER_LSB_VAL     0xf1
 130
 131 #define IDLL_TEST_REG           0x72
 132 #define START_CLK_HF            BIT(6)
 133
 134 #define DES_BITLOCK_REG         0x86
 135 #define BIT_LOCK_LEVEL          0x01
 136 #define BIT_LOCK_CNT_512        (0x03 << 5)
 137
 138 struct miphy365x_phy {
 139         struct phy *phy;
 140         void __iomem *base;
 141         bool pcie_tx_pol_inv;
 142         bool sata_tx_pol_inv;
 143         u32 sata_gen;
 144         u64 ctrlreg;
 145         u8 type;
 146 };
 147
 148 struct miphy365x_dev {
 149         struct device *dev;
 150         struct regmap *regmap;
 151         struct mutex miphy_mutex;
 152         struct miphy365x_phy **phys;
 153 };
 154
 155 /*
 156  * These values are represented in Device tree. They are considered to be ABI
 157  * and although they can be extended any existing values must not change.
 158  */
 159 enum miphy_sata_gen {
 160         SATA_GEN1 = 1,
 161         SATA_GEN2,
 162         SATA_GEN3
 163 };
 164
 165 static u8 rx_tx_spd[] = {
 166         TX_SPDSEL_GEN1_VAL | RX_SPDSEL_GEN1_VAL,
 167         TX_SPDSEL_GEN2_VAL | RX_SPDSEL_GEN2_VAL,
 168         TX_SPDSEL_GEN3_VAL | RX_SPDSEL_GEN3_VAL
 169 };
 170
 171 /*
 172  * This function selects the system configuration,
 173  * either two SATA, one SATA and one PCIe, or two PCIe lanes.
 174  */
 175 static int miphy365x_set_path(struct miphy365x_phy *miphy_phy,
 176                               struct miphy365x_dev *miphy_dev)
 177 {
 178         bool sata = (miphy_phy->type == MIPHY_TYPE_SATA);
 179
 180         return regmap_update_bits(miphy_dev->regmap,
 181                                   (unsigned int)miphy_phy->ctrlreg,
 182                                   SYSCFG_SELECT_SATA_MASK,
 183                                   sata << SYSCFG_SELECT_SATA_POS);
 184 }
 185
 186 static int miphy365x_init_pcie_port(struct miphy365x_phy *miphy_phy,
 187                                     struct miphy365x_dev *miphy_dev)
 188 {
 189         u8 val;
 190
 191         if (miphy_phy->pcie_tx_pol_inv) {
 192                 /* Invert Tx polarity and clear pci_txdetect_pol bit */
 193                 val = TERM_EN | PCI_EN | DES_BIT_LOCK_EN | TX_POL;
 194                 writeb_relaxed(val, miphy_phy->base + CTRL_REG);
 195                 writeb_relaxed(0x00, miphy_phy->base + PCIE_REG);
 196         }
 197
 198         return 0;
 199 }
 200
 201 static inline int miphy365x_hfc_not_rdy(struct miphy365x_phy *miphy_phy,
 202                                         struct miphy365x_dev *miphy_dev)
 203 {
 204         unsigned long timeout = jiffies + msecs_to_jiffies(HFC_TIMEOUT);
 205         u8 mask = IDLL_RDY | PLL_RDY;
 206         u8 regval;
 207
 208         do {
 209                 regval = readb_relaxed(miphy_phy->base + STATUS_REG);
 210                 if (!(regval & mask))
 211                         return 0;
 212
 213                 usleep_range(2000, 2500);
 214         } while (time_before(jiffies, timeout));
 215
 216         dev_err(miphy_dev->dev, "HFC ready timeout!\n");
 217         return -EBUSY;
 218 }
 219
 220 static inline int miphy365x_rdy(struct miphy365x_phy *miphy_phy,
 221                                 struct miphy365x_dev *miphy_dev)
 222 {
 223         unsigned long timeout = jiffies + msecs_to_jiffies(HFC_TIMEOUT);
 224         u8 mask = IDLL_RDY | PLL_RDY;
 225         u8 regval;
 226
 227         do {
 228                 regval = readb_relaxed(miphy_phy->base + STATUS_REG);
 229                 if ((regval & mask) == mask)
 230                         return 0;
 231
 232                 usleep_range(2000, 2500);
 233         } while (time_before(jiffies, timeout));
 234
 235         dev_err(miphy_dev->dev, "PHY not ready timeout!\n");
 236         return -EBUSY;
 237 }
 238
 239 static inline void miphy365x_set_comp(struct miphy365x_phy *miphy_phy,
 240                                       struct miphy365x_dev *miphy_dev)
 241 {
 242         u8 val, mask;
 243
 244         if (miphy_phy->sata_gen == SATA_GEN1)
 245                 writeb_relaxed(COMP_2MHZ_RAT_GEN1,
 246                                miphy_phy->base + COMP_CTRL2_REG);
 247         else
 248                 writeb_relaxed(COMP_2MHZ_RAT,
 249                                miphy_phy->base + COMP_CTRL2_REG);
 250
 251         if (miphy_phy->sata_gen != SATA_GEN3) {
 252                 writeb_relaxed(COMSR_COMP_REF,
 253                                miphy_phy->base + COMP_CTRL3_REG);
 254                 /*
 255                  * Force VCO current to value defined by address 0x5A
 256                  * and disable PCIe100Mref bit
 257                  * Enable auto load compensation for pll_i_bias
 258                  */
 259                 writeb_relaxed(BYPASS_PLL_CAL, miphy_phy->base + PLL_CTRL2_REG);
 260                 writeb_relaxed(COMZC_IDLL, miphy_phy->base + COMP_IDLL_REG);
 261         }
 262
 263         /*
 264          * Force restart compensation and enable auto load
 265          * for Comzc_Tx, Comzc_Rx and Comsr on macro
 266          */
 267         val = START_COMSR | START_COMZC | COMP_AUTO_LOAD;
 268         writeb_relaxed(val, miphy_phy->base + COMP_CTRL1_REG);
 269
 270         mask = COMSR_DONE | COMZC_DONE;
 271         while ((readb_relaxed(miphy_phy->base + COMP_CTRL1_REG) & mask) != mask)
 272                 cpu_relax();
 273 }
 274
 275 static inline void miphy365x_set_ssc(struct miphy365x_phy *miphy_phy,
 276                                      struct miphy365x_dev *miphy_dev)
 277 {
 278         u8 val;
 279
 280         /*
 281          * SSC Settings. SSC will be enabled through Link
 282          * SSC Ampl. = 0.4%
 283          * SSC Freq = 31KHz
 284          */
 285         writeb_relaxed(PLL_SSC_STEP_MSB_VAL,
 286                        miphy_phy->base + PLL_SSC_STEP_MSB_REG);
 287         writeb_relaxed(PLL_SSC_STEP_LSB_VAL,
 288                        miphy_phy->base + PLL_SSC_STEP_LSB_REG);
 289         writeb_relaxed(PLL_SSC_PER_MSB_VAL,
 290                        miphy_phy->base + PLL_SSC_PER_MSB_REG);
 291         writeb_relaxed(PLL_SSC_PER_LSB_VAL,
 292                        miphy_phy->base + PLL_SSC_PER_LSB_REG);
 293
 294         /* SSC Settings complete */
 295         if (miphy_phy->sata_gen == SATA_GEN1) {
 296                 val = PLL_START_CAL | BUF_EN | SYNCHRO_TX | CONFIG_PLL;
 297                 writeb_relaxed(val, miphy_phy->base + PLL_CTRL1_REG);
 298         } else {
 299                 val = SSC_EN | PLL_START_CAL | BUF_EN | SYNCHRO_TX | CONFIG_PLL;
 300                 writeb_relaxed(val, miphy_phy->base + PLL_CTRL1_REG);
 301         }
 302 }
 303
 304 static int miphy365x_init_sata_port(struct miphy365x_phy *miphy_phy,
 305                                     struct miphy365x_dev *miphy_dev)
 306 {
 307         int ret;
 308         u8 val;
 309
 310         /*
 311          * Force PHY macro reset, PLL calibration reset, PLL reset
 312          * and assert Deserializer Reset
 313          */
 314         val = RST_PLL | RST_PLL_CAL | RST_RX | RST_MACRO;
 315         writeb_relaxed(val, miphy_phy->base + RESET_REG);
 316
 317         if (miphy_phy->sata_tx_pol_inv)
 318                 writeb_relaxed(TX_POL, miphy_phy->base + CTRL_REG);
 319
 320         /*
 321          * Force macro1 to use rx_lspd, tx_lspd
 322          * Force Rx_Clock on first I-DLL phase
 323          * Force Des in HP mode on macro, rx_lspd, tx_lspd for Gen2/3
 324          */
 325         writeb_relaxed(SPDSEL_SEL, miphy_phy->base + BOUNDARY1_REG);
 326         writeb_relaxed(START_CLK_HF, miphy_phy->base + IDLL_TEST_REG);
 327         val = rx_tx_spd[miphy_phy->sata_gen];
 328         writeb_relaxed(val, miphy_phy->base + BOUNDARY3_REG);
 329
 330         /* Wait for HFC_READY = 0 */
 331         ret = miphy365x_hfc_not_rdy(miphy_phy, miphy_dev);
 332         if (ret)
 333                 return ret;
 334
 335         /* Compensation Recalibration */
 336         miphy365x_set_comp(miphy_phy, miphy_dev);
 337
 338         switch (miphy_phy->sata_gen) {
 339         case SATA_GEN3:
 340                 /*
 341                  * TX Swing target 550-600mv peak to peak diff
 342                  * Tx Slew target 90-110ps rising/falling time
 343                  * Rx Eq ON3, Sigdet threshold SDTH1
 344                  */
 345                 val = PD_VDDTFILTER | CONF_GEN_SEL_GEN3;
 346                 writeb_relaxed(val, miphy_phy->base + BUF_SEL_REG);
 347                 val = SWING_VAL | PREEMPH_VAL;
 348                 writeb_relaxed(val, miphy_phy->base + TXBUF1_REG);
 349                 writeb_relaxed(TXSLEW_VAL, miphy_phy->base + TXBUF2_REG);
 350                 writeb_relaxed(0x00, miphy_phy->base + RXBUF_OFFSET_CTRL_REG);
 351                 val = SDTHRES_VAL | EQ_ON3;
 352                 writeb_relaxed(val, miphy_phy->base + RXBUF_REG);
 353                 break;
 354         case SATA_GEN2:
 355                 /*
 356                  * conf gen sel=0x1 to program Gen2 banked registers
 357                  * VDDT filter ON
 358                  * Tx Swing target 550-600mV peak-to-peak diff
 359                  * Tx Slew target 90-110 ps rising/falling time
 360                  * RX Equalization ON1, Sigdet threshold SDTH1
 361                  */
 362                 writeb_relaxed(CONF_GEN_SEL_GEN2,
 363                                miphy_phy->base + BUF_SEL_REG);
 364                 writeb_relaxed(SWING_VAL, miphy_phy->base + TXBUF1_REG);
 365                 writeb_relaxed(TXSLEW_VAL, miphy_phy->base + TXBUF2_REG);
 366                 val = SDTHRES_VAL | EQ_ON1;
 367                 writeb_relaxed(val, miphy_phy->base + RXBUF_REG);
 368                 break;
 369         case SATA_GEN1:
 370                 /*
 371                  * conf gen sel = 00b to program Gen1 banked registers
 372                  * VDDT filter ON
 373                  * Tx Swing target 500-550mV peak-to-peak diff
 374                  * Tx Slew target120-140 ps rising/falling time
 375                  */
 376                 writeb_relaxed(PD_VDDTFILTER, miphy_phy->base + BUF_SEL_REG);
 377                 writeb_relaxed(SWING_VAL_GEN1, miphy_phy->base + TXBUF1_REG);
 378                 writeb_relaxed(TXSLEW_VAL_GEN1, miphy_phy->base + TXBUF2_REG);
 379                 break;
 380         default:
 381                 break;
 382         }
 383
 384         /* Force Macro1 in partial mode & release pll cal reset */
 385         writeb_relaxed(RST_RX, miphy_phy->base + RESET_REG);
 386         usleep_range(100, 150);
 387
 388         miphy365x_set_ssc(miphy_phy, miphy_dev);
 389
 390         /* Wait for phy_ready */
 391         ret = miphy365x_rdy(miphy_phy, miphy_dev);
 392         if (ret)
 393                 return ret;
 394
 395         /*
 396          * Enable macro1 to use rx_lspd & tx_lspd
 397          * Release Rx_Clock on first I-DLL phase on macro1
 398          * Assert deserializer reset
 399          * des_bit_lock_en is set
 400          * bit lock detection strength
 401          * Deassert deserializer reset
 402          */
 403         writeb_relaxed(0x00, miphy_phy->base + BOUNDARY1_REG);
 404         writeb_relaxed(0x00, miphy_phy->base + IDLL_TEST_REG);
 405         writeb_relaxed(RST_RX, miphy_phy->base + RESET_REG);
 406         val = miphy_phy->sata_tx_pol_inv ?
 407                 (TX_POL | DES_BIT_LOCK_EN) : DES_BIT_LOCK_EN;
 408         writeb_relaxed(val, miphy_phy->base + CTRL_REG);
 409
 410         val = BIT_LOCK_CNT_512 | BIT_LOCK_LEVEL;
 411         writeb_relaxed(val, miphy_phy->base + DES_BITLOCK_REG);
 412         writeb_relaxed(0x00, miphy_phy->base + RESET_REG);
 413
 414         return 0;
 415 }
 416
 417 static int miphy365x_init(struct phy *phy)
 418 {
 419         struct miphy365x_phy *miphy_phy = phy_get_drvdata(phy);
 420         struct miphy365x_dev *miphy_dev = dev_get_drvdata(phy->dev.parent);
 421         int ret = 0;
 422
 423         mutex_lock(&miphy_dev->miphy_mutex);
 424
 425         ret = miphy365x_set_path(miphy_phy, miphy_dev);
 426         if (ret) {
 427                 mutex_unlock(&miphy_dev->miphy_mutex);
 428                 return ret;
 429         }
 430
 431         /* Initialise Miphy for PCIe or SATA */
 432         if (miphy_phy->type == MIPHY_TYPE_PCIE)
 433                 ret = miphy365x_init_pcie_port(miphy_phy, miphy_dev);
 434         else
 435                 ret = miphy365x_init_sata_port(miphy_phy, miphy_dev);
 436
 437         mutex_unlock(&miphy_dev->miphy_mutex);
 438
 439         return ret;
 440 }
 441
 442 int miphy365x_get_addr(struct device *dev, struct miphy365x_phy *miphy_phy,
 443                        int index)
 444 {
 445         struct device_node *phynode = miphy_phy->phy->dev.of_node;
 446         const char *name;
 447         const __be32 *taddr;
 448         int type = miphy_phy->type;
 449         int ret;
 450
 451         ret = of_property_read_string_index(phynode, "reg-names", index, &name);
 452         if (ret) {
 453                 dev_err(dev, "no reg-names property not found\n");
 454                 return ret;
 455         }
 456
 457         if (!strncmp(name, "syscfg", 6)) {
 458                 taddr = of_get_address(phynode, index, NULL, NULL);
 459                 if (!taddr) {
 460                         dev_err(dev, "failed to fetch syscfg address\n");
 461                         return -EINVAL;
 462                 }
 463
 464                 miphy_phy->ctrlreg = of_translate_address(phynode, taddr);
 465                 if (miphy_phy->ctrlreg == OF_BAD_ADDR) {
 466                         dev_err(dev, "failed to translate syscfg address\n");
 467                         return -EINVAL;
 468                 }
 469
 470                 return 0;
 471         }
 472
 473         if (!((!strncmp(name, "sata", 4) && type == MIPHY_TYPE_SATA) ||
 474               (!strncmp(name, "pcie", 4) && type == MIPHY_TYPE_PCIE)))
 475                 return 0;
 476
 477         miphy_phy->base = of_iomap(phynode, index);
 478         if (!miphy_phy->base) {
 479                 dev_err(dev, "Failed to map %s\n", phynode->full_name);
 480                 return -EINVAL;
 481         }
 482
 483         return 0;
 484 }
 485
 486 static struct phy *miphy365x_xlate(struct device *dev,
 487                                    struct of_phandle_args *args)
 488 {
 489         struct miphy365x_dev *miphy_dev = dev_get_drvdata(dev);
 490         struct miphy365x_phy *miphy_phy = NULL;
 491         struct device_node *phynode = args->np;
 492         int ret, index;
 493
 494         if (!of_device_is_available(phynode)) {
 495                 dev_warn(dev, "Requested PHY is disabled\n");
 496                 return ERR_PTR(-ENODEV);
 497         }
 498
 499         if (args->args_count != 1) {
 500                 dev_err(dev, "Invalid number of cells in 'phy' property\n");
 501                 return ERR_PTR(-EINVAL);
 502         }
 503
 504         for (index = 0; index < of_get_child_count(dev->of_node); index++)
 505                 if (phynode == miphy_dev->phys[index]->phy->dev.of_node) {
 506                         miphy_phy = miphy_dev->phys[index];
 507                         break;
 508                 }
 509
 510         if (!miphy_phy) {
 511                 dev_err(dev, "Failed to find appropriate phy\n");
 512                 return ERR_PTR(-EINVAL);
 513         }
 514
 515         miphy_phy->type = args->args[0];
 516
 517         if (!(miphy_phy->type == MIPHY_TYPE_SATA ||
 518               miphy_phy->type == MIPHY_TYPE_PCIE)) {
 519                 dev_err(dev, "Unsupported device type: %d\n", miphy_phy->type);
 520                 return ERR_PTR(-EINVAL);
 521         }
 522
 523         /* Each port handles SATA and PCIE - third entry is always sysconf. */
 524         for (index = 0; index < 3; index++) {
 525                 ret = miphy365x_get_addr(dev, miphy_phy, index);
 526                 if (ret < 0)
 527                         return ERR_PTR(ret);
 528         }
 529
 530         return miphy_phy->phy;
 531 }
 532
 533 static struct phy_ops miphy365x_ops = {
 534         .init           = miphy365x_init,
 535         .owner          = THIS_MODULE,
 536 };
 537
 538 static int miphy365x_of_probe(struct device_node *phynode,
 539                               struct miphy365x_phy *miphy_phy)
 540 {
 541         of_property_read_u32(phynode, "st,sata-gen", &miphy_phy->sata_gen);
 542         if (!miphy_phy->sata_gen)
 543                 miphy_phy->sata_gen = SATA_GEN1;
 544
 545         miphy_phy->pcie_tx_pol_inv =
 546                 of_property_read_bool(phynode, "st,pcie-tx-pol-inv");
 547
 548         miphy_phy->sata_tx_pol_inv =
 549                 of_property_read_bool(phynode, "st,sata-tx-pol-inv");
 550
 551         return 0;
 552 }
 553
 554 static int miphy365x_probe(struct platform_device *pdev)
 555 {
 556         struct device_node *child, *np = pdev->dev.of_node;
 557         struct miphy365x_dev *miphy_dev;
 558         struct phy_provider *provider;
 559         struct phy *phy;
 560         int chancount, port = 0;
 561         int ret;
 562
 563         miphy_dev = devm_kzalloc(&pdev->dev, sizeof(*miphy_dev), GFP_KERNEL);
 564         if (!miphy_dev)
 565                 return -ENOMEM;
 566
 567         chancount = of_get_child_count(np);
 568         miphy_dev->phys = devm_kzalloc(&pdev->dev, sizeof(phy) * chancount,
 569                                        GFP_KERNEL);
 570         if (!miphy_dev->phys)
 571                 return -ENOMEM;
 572
 573         miphy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
 574         if (IS_ERR(miphy_dev->regmap)) {
 575                 dev_err(miphy_dev->dev, "No syscfg phandle specified\n");
 576                 return PTR_ERR(miphy_dev->regmap);
 577         }
 578
 579         miphy_dev->dev = &pdev->dev;
 580
 581         dev_set_drvdata(&pdev->dev, miphy_dev);
 582
 583         mutex_init(&miphy_dev->miphy_mutex);
 584
 585         for_each_child_of_node(np, child) {
 586                 struct miphy365x_phy *miphy_phy;
 587
 588                 miphy_phy = devm_kzalloc(&pdev->dev, sizeof(*miphy_phy),
 589                                          GFP_KERNEL);
 590                 if (!miphy_phy)
 591                         return -ENOMEM;
 592
 593                 miphy_dev->phys[port] = miphy_phy;
 594
 595                 phy = devm_phy_create(&pdev->dev, child, &miphy365x_ops, NULL);
 596                 if (IS_ERR(phy)) {
 597                         dev_err(&pdev->dev, "failed to create PHY\n");
 598                         return PTR_ERR(phy);
 599                 }
 600
 601                 miphy_dev->phys[port]->phy = phy;
 602
 603                 ret = miphy365x_of_probe(child, miphy_phy);
 604                 if (ret)
 605                         return ret;
 606
 607                 phy_set_drvdata(phy, miphy_dev->phys[port]);
 608                 port++;
 609         }
 610
 611         provider = devm_of_phy_provider_register(&pdev->dev, miphy365x_xlate);
 612         if (IS_ERR(provider))
 613                 return PTR_ERR(provider);
 614
 615         return 0;
 616 }
 617
 618 static const struct of_device_id miphy365x_of_match[] = {
 619         { .compatible = "st,miphy365x-phy", },
 620         { },
 621 };
 622 MODULE_DEVICE_TABLE(of, miphy365x_of_match);
 623
 624 static struct platform_driver miphy365x_driver = {
 625         .probe  = miphy365x_probe,
 626         .driver = {
 627                 .name   = "miphy365x-phy",
 628                 .owner  = THIS_MODULE,
 629                 .of_match_table = miphy365x_of_match,
 630         }
 631 };
 632 module_platform_driver(miphy365x_driver);
 633
 634 MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@st.com>");
 635 MODULE_DESCRIPTION("STMicroelectronics miphy365x driver");
 636 MODULE_LICENSE("GPL v2");