2 * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
15 #include "phy-qcom-ufs-i.h"
17 #define MAX_PROP_NAME 32
18 #define VDDA_PHY_MIN_UV 1000000
19 #define VDDA_PHY_MAX_UV 1000000
20 #define VDDA_PLL_MIN_UV 1800000
21 #define VDDA_PLL_MAX_UV 1800000
22 #define VDDP_REF_CLK_MIN_UV 1200000
23 #define VDDP_REF_CLK_MAX_UV 1200000
25 static int __ufs_qcom_phy_init_vreg(struct phy
*, struct ufs_qcom_phy_vreg
*,
27 static int ufs_qcom_phy_init_vreg(struct phy
*, struct ufs_qcom_phy_vreg
*,
29 static int ufs_qcom_phy_base_init(struct platform_device
*pdev
,
30 struct ufs_qcom_phy
*phy_common
);
32 int ufs_qcom_phy_calibrate(struct ufs_qcom_phy
*ufs_qcom_phy
,
33 struct ufs_qcom_phy_calibration
*tbl_A
,
35 struct ufs_qcom_phy_calibration
*tbl_B
,
36 int tbl_size_B
, bool is_rate_B
)
42 dev_err(ufs_qcom_phy
->dev
, "%s: tbl_A is NULL", __func__
);
47 for (i
= 0; i
< tbl_size_A
; i
++)
48 writel_relaxed(tbl_A
[i
].cfg_value
,
49 ufs_qcom_phy
->mmio
+ tbl_A
[i
].reg_offset
);
52 * In case we would like to work in rate B, we need
53 * to override a registers that were configured in rate A table
54 * with registers of rate B table.
59 dev_err(ufs_qcom_phy
->dev
, "%s: tbl_B is NULL",
65 for (i
= 0; i
< tbl_size_B
; i
++)
66 writel_relaxed(tbl_B
[i
].cfg_value
,
67 ufs_qcom_phy
->mmio
+ tbl_B
[i
].reg_offset
);
70 /* flush buffered writes */
77 struct phy
*ufs_qcom_phy_generic_probe(struct platform_device
*pdev
,
78 struct ufs_qcom_phy
*common_cfg
,
79 struct phy_ops
*ufs_qcom_phy_gen_ops
,
80 struct ufs_qcom_phy_specific_ops
*phy_spec_ops
)
83 struct device
*dev
= &pdev
->dev
;
84 struct phy
*generic_phy
= NULL
;
85 struct phy_provider
*phy_provider
;
87 err
= ufs_qcom_phy_base_init(pdev
, common_cfg
);
89 dev_err(dev
, "%s: phy base init failed %d\n", __func__
, err
);
93 phy_provider
= devm_of_phy_provider_register(dev
, of_phy_simple_xlate
);
94 if (IS_ERR(phy_provider
)) {
95 err
= PTR_ERR(phy_provider
);
96 dev_err(dev
, "%s: failed to register phy %d\n", __func__
, err
);
100 generic_phy
= devm_phy_create(dev
, NULL
, ufs_qcom_phy_gen_ops
);
101 if (IS_ERR(generic_phy
)) {
102 err
= PTR_ERR(generic_phy
);
103 dev_err(dev
, "%s: failed to create phy %d\n", __func__
, err
);
107 common_cfg
->phy_spec_ops
= phy_spec_ops
;
108 common_cfg
->dev
= dev
;
115 * This assumes the embedded phy structure inside generic_phy is of type
116 * struct ufs_qcom_phy. In order to function properly it's crucial
117 * to keep the embedded struct "struct ufs_qcom_phy common_cfg"
118 * as the first inside generic_phy.
120 struct ufs_qcom_phy
*get_ufs_qcom_phy(struct phy
*generic_phy
)
122 return (struct ufs_qcom_phy
*)phy_get_drvdata(generic_phy
);
126 int ufs_qcom_phy_base_init(struct platform_device
*pdev
,
127 struct ufs_qcom_phy
*phy_common
)
129 struct device
*dev
= &pdev
->dev
;
130 struct resource
*res
;
133 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "phy_mem");
135 dev_err(dev
, "%s: phy_mem resource not found\n", __func__
);
140 phy_common
->mmio
= devm_ioremap_resource(dev
, res
);
141 if (IS_ERR((void const *)phy_common
->mmio
)) {
142 err
= PTR_ERR((void const *)phy_common
->mmio
);
143 phy_common
->mmio
= NULL
;
144 dev_err(dev
, "%s: ioremap for phy_mem resource failed %d\n",
149 /* "dev_ref_clk_ctrl_mem" is optional resource */
150 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
,
151 "dev_ref_clk_ctrl_mem");
153 dev_dbg(dev
, "%s: dev_ref_clk_ctrl_mem resource not found\n",
158 phy_common
->dev_ref_clk_ctrl_mmio
= devm_ioremap_resource(dev
, res
);
159 if (IS_ERR((void const *)phy_common
->dev_ref_clk_ctrl_mmio
)) {
160 err
= PTR_ERR((void const *)phy_common
->dev_ref_clk_ctrl_mmio
);
161 phy_common
->dev_ref_clk_ctrl_mmio
= NULL
;
162 dev_err(dev
, "%s: ioremap for dev_ref_clk_ctrl_mem resource failed %d\n",
170 static int __ufs_qcom_phy_clk_get(struct phy
*phy
,
171 const char *name
, struct clk
**clk_out
, bool err_print
)
175 struct ufs_qcom_phy
*ufs_qcom_phy
= get_ufs_qcom_phy(phy
);
176 struct device
*dev
= ufs_qcom_phy
->dev
;
178 clk
= devm_clk_get(dev
, name
);
182 dev_err(dev
, "failed to get %s err %d", name
, err
);
191 int ufs_qcom_phy_clk_get(struct phy
*phy
,
192 const char *name
, struct clk
**clk_out
)
194 return __ufs_qcom_phy_clk_get(phy
, name
, clk_out
, true);
198 ufs_qcom_phy_init_clks(struct phy
*generic_phy
,
199 struct ufs_qcom_phy
*phy_common
)
203 err
= ufs_qcom_phy_clk_get(generic_phy
, "tx_iface_clk",
204 &phy_common
->tx_iface_clk
);
208 err
= ufs_qcom_phy_clk_get(generic_phy
, "rx_iface_clk",
209 &phy_common
->rx_iface_clk
);
213 err
= ufs_qcom_phy_clk_get(generic_phy
, "ref_clk_src",
214 &phy_common
->ref_clk_src
);
219 * "ref_clk_parent" is optional hence don't abort init if it's not
222 __ufs_qcom_phy_clk_get(generic_phy
, "ref_clk_parent",
223 &phy_common
->ref_clk_parent
, false);
225 err
= ufs_qcom_phy_clk_get(generic_phy
, "ref_clk",
226 &phy_common
->ref_clk
);
233 ufs_qcom_phy_init_vregulators(struct phy
*generic_phy
,
234 struct ufs_qcom_phy
*phy_common
)
238 err
= ufs_qcom_phy_init_vreg(generic_phy
, &phy_common
->vdda_pll
,
243 err
= ufs_qcom_phy_init_vreg(generic_phy
, &phy_common
->vdda_phy
,
249 /* vddp-ref-clk-* properties are optional */
250 __ufs_qcom_phy_init_vreg(generic_phy
, &phy_common
->vddp_ref_clk
,
251 "vddp-ref-clk", true);
256 static int __ufs_qcom_phy_init_vreg(struct phy
*phy
,
257 struct ufs_qcom_phy_vreg
*vreg
, const char *name
, bool optional
)
260 struct ufs_qcom_phy
*ufs_qcom_phy
= get_ufs_qcom_phy(phy
);
261 struct device
*dev
= ufs_qcom_phy
->dev
;
263 char prop_name
[MAX_PROP_NAME
];
265 vreg
->name
= kstrdup(name
, GFP_KERNEL
);
271 vreg
->reg
= devm_regulator_get(dev
, name
);
272 if (IS_ERR(vreg
->reg
)) {
273 err
= PTR_ERR(vreg
->reg
);
276 dev_err(dev
, "failed to get %s, %d\n", name
, err
);
281 snprintf(prop_name
, MAX_PROP_NAME
, "%s-max-microamp", name
);
282 err
= of_property_read_u32(dev
->of_node
,
283 prop_name
, &vreg
->max_uA
);
284 if (err
&& err
!= -EINVAL
) {
285 dev_err(dev
, "%s: failed to read %s\n",
286 __func__
, prop_name
);
288 } else if (err
== -EINVAL
|| !vreg
->max_uA
) {
289 if (regulator_count_voltages(vreg
->reg
) > 0) {
290 dev_err(dev
, "%s: %s is mandatory\n",
291 __func__
, prop_name
);
296 snprintf(prop_name
, MAX_PROP_NAME
, "%s-always-on", name
);
297 if (of_get_property(dev
->of_node
, prop_name
, NULL
))
298 vreg
->is_always_on
= true;
300 vreg
->is_always_on
= false;
303 if (!strcmp(name
, "vdda-pll")) {
304 vreg
->max_uV
= VDDA_PLL_MAX_UV
;
305 vreg
->min_uV
= VDDA_PLL_MIN_UV
;
306 } else if (!strcmp(name
, "vdda-phy")) {
307 vreg
->max_uV
= VDDA_PHY_MAX_UV
;
308 vreg
->min_uV
= VDDA_PHY_MIN_UV
;
309 } else if (!strcmp(name
, "vddp-ref-clk")) {
310 vreg
->max_uV
= VDDP_REF_CLK_MAX_UV
;
311 vreg
->min_uV
= VDDP_REF_CLK_MIN_UV
;
320 static int ufs_qcom_phy_init_vreg(struct phy
*phy
,
321 struct ufs_qcom_phy_vreg
*vreg
, const char *name
)
323 return __ufs_qcom_phy_init_vreg(phy
, vreg
, name
, false);
327 int ufs_qcom_phy_cfg_vreg(struct phy
*phy
,
328 struct ufs_qcom_phy_vreg
*vreg
, bool on
)
331 struct regulator
*reg
= vreg
->reg
;
332 const char *name
= vreg
->name
;
335 struct ufs_qcom_phy
*ufs_qcom_phy
= get_ufs_qcom_phy(phy
);
336 struct device
*dev
= ufs_qcom_phy
->dev
;
340 if (regulator_count_voltages(reg
) > 0) {
341 min_uV
= on
? vreg
->min_uV
: 0;
342 ret
= regulator_set_voltage(reg
, min_uV
, vreg
->max_uV
);
344 dev_err(dev
, "%s: %s set voltage failed, err=%d\n",
345 __func__
, name
, ret
);
348 uA_load
= on
? vreg
->max_uA
: 0;
349 ret
= regulator_set_optimum_mode(reg
, uA_load
);
352 * regulator_set_optimum_mode() returns new regulator
357 dev_err(dev
, "%s: %s set optimum mode(uA_load=%d) failed, err=%d\n",
358 __func__
, name
, uA_load
, ret
);
367 int ufs_qcom_phy_enable_vreg(struct phy
*phy
,
368 struct ufs_qcom_phy_vreg
*vreg
)
370 struct ufs_qcom_phy
*ufs_qcom_phy
= get_ufs_qcom_phy(phy
);
371 struct device
*dev
= ufs_qcom_phy
->dev
;
374 if (!vreg
|| vreg
->enabled
)
377 ret
= ufs_qcom_phy_cfg_vreg(phy
, vreg
, true);
379 dev_err(dev
, "%s: ufs_qcom_phy_cfg_vreg() failed, err=%d\n",
384 ret
= regulator_enable(vreg
->reg
);
386 dev_err(dev
, "%s: enable failed, err=%d\n",
391 vreg
->enabled
= true;
396 int ufs_qcom_phy_enable_ref_clk(struct phy
*generic_phy
)
399 struct ufs_qcom_phy
*phy
= get_ufs_qcom_phy(generic_phy
);
401 if (phy
->is_ref_clk_enabled
)
405 * reference clock is propagated in a daisy-chained manner from
406 * source to phy, so ungate them at each stage.
408 ret
= clk_prepare_enable(phy
->ref_clk_src
);
410 dev_err(phy
->dev
, "%s: ref_clk_src enable failed %d\n",
416 * "ref_clk_parent" is optional clock hence make sure that clk reference
417 * is available before trying to enable the clock.
419 if (phy
->ref_clk_parent
) {
420 ret
= clk_prepare_enable(phy
->ref_clk_parent
);
422 dev_err(phy
->dev
, "%s: ref_clk_parent enable failed %d\n",
424 goto out_disable_src
;
428 ret
= clk_prepare_enable(phy
->ref_clk
);
430 dev_err(phy
->dev
, "%s: ref_clk enable failed %d\n",
432 goto out_disable_parent
;
435 phy
->is_ref_clk_enabled
= true;
439 if (phy
->ref_clk_parent
)
440 clk_disable_unprepare(phy
->ref_clk_parent
);
442 clk_disable_unprepare(phy
->ref_clk_src
);
448 int ufs_qcom_phy_disable_vreg(struct phy
*phy
,
449 struct ufs_qcom_phy_vreg
*vreg
)
451 struct ufs_qcom_phy
*ufs_qcom_phy
= get_ufs_qcom_phy(phy
);
452 struct device
*dev
= ufs_qcom_phy
->dev
;
455 if (!vreg
|| !vreg
->enabled
|| vreg
->is_always_on
)
458 ret
= regulator_disable(vreg
->reg
);
461 /* ignore errors on applying disable config */
462 ufs_qcom_phy_cfg_vreg(phy
, vreg
, false);
463 vreg
->enabled
= false;
465 dev_err(dev
, "%s: %s disable failed, err=%d\n",
466 __func__
, vreg
->name
, ret
);
472 void ufs_qcom_phy_disable_ref_clk(struct phy
*generic_phy
)
474 struct ufs_qcom_phy
*phy
= get_ufs_qcom_phy(generic_phy
);
476 if (phy
->is_ref_clk_enabled
) {
477 clk_disable_unprepare(phy
->ref_clk
);
479 * "ref_clk_parent" is optional clock hence make sure that clk
480 * reference is available before trying to disable the clock.
482 if (phy
->ref_clk_parent
)
483 clk_disable_unprepare(phy
->ref_clk_parent
);
484 clk_disable_unprepare(phy
->ref_clk_src
);
485 phy
->is_ref_clk_enabled
= false;
489 #define UFS_REF_CLK_EN (1 << 5)
491 static void ufs_qcom_phy_dev_ref_clk_ctrl(struct phy
*generic_phy
, bool enable
)
493 struct ufs_qcom_phy
*phy
= get_ufs_qcom_phy(generic_phy
);
495 if (phy
->dev_ref_clk_ctrl_mmio
&&
496 (enable
^ phy
->is_dev_ref_clk_enabled
)) {
497 u32 temp
= readl_relaxed(phy
->dev_ref_clk_ctrl_mmio
);
500 temp
|= UFS_REF_CLK_EN
;
502 temp
&= ~UFS_REF_CLK_EN
;
505 * If we are here to disable this clock immediately after
506 * entering into hibern8, we need to make sure that device
507 * ref_clk is active atleast 1us after the hibern8 enter.
512 writel_relaxed(temp
, phy
->dev_ref_clk_ctrl_mmio
);
513 /* ensure that ref_clk is enabled/disabled before we return */
516 * If we call hibern8 exit after this, we need to make sure that
517 * device ref_clk is stable for atleast 1us before the hibern8
523 phy
->is_dev_ref_clk_enabled
= enable
;
527 void ufs_qcom_phy_enable_dev_ref_clk(struct phy
*generic_phy
)
529 ufs_qcom_phy_dev_ref_clk_ctrl(generic_phy
, true);
532 void ufs_qcom_phy_disable_dev_ref_clk(struct phy
*generic_phy
)
534 ufs_qcom_phy_dev_ref_clk_ctrl(generic_phy
, false);
537 /* Turn ON M-PHY RMMI interface clocks */
538 int ufs_qcom_phy_enable_iface_clk(struct phy
*generic_phy
)
540 struct ufs_qcom_phy
*phy
= get_ufs_qcom_phy(generic_phy
);
543 if (phy
->is_iface_clk_enabled
)
546 ret
= clk_prepare_enable(phy
->tx_iface_clk
);
548 dev_err(phy
->dev
, "%s: tx_iface_clk enable failed %d\n",
552 ret
= clk_prepare_enable(phy
->rx_iface_clk
);
554 clk_disable_unprepare(phy
->tx_iface_clk
);
555 dev_err(phy
->dev
, "%s: rx_iface_clk enable failed %d. disabling also tx_iface_clk\n",
559 phy
->is_iface_clk_enabled
= true;
565 /* Turn OFF M-PHY RMMI interface clocks */
566 void ufs_qcom_phy_disable_iface_clk(struct phy
*generic_phy
)
568 struct ufs_qcom_phy
*phy
= get_ufs_qcom_phy(generic_phy
);
570 if (phy
->is_iface_clk_enabled
) {
571 clk_disable_unprepare(phy
->tx_iface_clk
);
572 clk_disable_unprepare(phy
->rx_iface_clk
);
573 phy
->is_iface_clk_enabled
= false;
577 int ufs_qcom_phy_start_serdes(struct phy
*generic_phy
)
579 struct ufs_qcom_phy
*ufs_qcom_phy
= get_ufs_qcom_phy(generic_phy
);
582 if (!ufs_qcom_phy
->phy_spec_ops
->start_serdes
) {
583 dev_err(ufs_qcom_phy
->dev
, "%s: start_serdes() callback is not supported\n",
587 ufs_qcom_phy
->phy_spec_ops
->start_serdes(ufs_qcom_phy
);
593 int ufs_qcom_phy_set_tx_lane_enable(struct phy
*generic_phy
, u32 tx_lanes
)
595 struct ufs_qcom_phy
*ufs_qcom_phy
= get_ufs_qcom_phy(generic_phy
);
598 if (!ufs_qcom_phy
->phy_spec_ops
->set_tx_lane_enable
) {
599 dev_err(ufs_qcom_phy
->dev
, "%s: set_tx_lane_enable() callback is not supported\n",
603 ufs_qcom_phy
->phy_spec_ops
->set_tx_lane_enable(ufs_qcom_phy
,
610 void ufs_qcom_phy_save_controller_version(struct phy
*generic_phy
,
611 u8 major
, u16 minor
, u16 step
)
613 struct ufs_qcom_phy
*ufs_qcom_phy
= get_ufs_qcom_phy(generic_phy
);
615 ufs_qcom_phy
->host_ctrl_rev_major
= major
;
616 ufs_qcom_phy
->host_ctrl_rev_minor
= minor
;
617 ufs_qcom_phy
->host_ctrl_rev_step
= step
;
620 int ufs_qcom_phy_calibrate_phy(struct phy
*generic_phy
, bool is_rate_B
)
622 struct ufs_qcom_phy
*ufs_qcom_phy
= get_ufs_qcom_phy(generic_phy
);
625 if (!ufs_qcom_phy
->phy_spec_ops
->calibrate_phy
) {
626 dev_err(ufs_qcom_phy
->dev
, "%s: calibrate_phy() callback is not supported\n",
630 ret
= ufs_qcom_phy
->phy_spec_ops
->
631 calibrate_phy(ufs_qcom_phy
, is_rate_B
);
633 dev_err(ufs_qcom_phy
->dev
, "%s: calibrate_phy() failed %d\n",
640 int ufs_qcom_phy_remove(struct phy
*generic_phy
,
641 struct ufs_qcom_phy
*ufs_qcom_phy
)
643 phy_power_off(generic_phy
);
645 kfree(ufs_qcom_phy
->vdda_pll
.name
);
646 kfree(ufs_qcom_phy
->vdda_phy
.name
);
651 int ufs_qcom_phy_exit(struct phy
*generic_phy
)
653 struct ufs_qcom_phy
*ufs_qcom_phy
= get_ufs_qcom_phy(generic_phy
);
655 if (ufs_qcom_phy
->is_powered_on
)
656 phy_power_off(generic_phy
);
661 int ufs_qcom_phy_is_pcs_ready(struct phy
*generic_phy
)
663 struct ufs_qcom_phy
*ufs_qcom_phy
= get_ufs_qcom_phy(generic_phy
);
665 if (!ufs_qcom_phy
->phy_spec_ops
->is_physical_coding_sublayer_ready
) {
666 dev_err(ufs_qcom_phy
->dev
, "%s: is_physical_coding_sublayer_ready() callback is not supported\n",
671 return ufs_qcom_phy
->phy_spec_ops
->
672 is_physical_coding_sublayer_ready(ufs_qcom_phy
);
675 int ufs_qcom_phy_power_on(struct phy
*generic_phy
)
677 struct ufs_qcom_phy
*phy_common
= get_ufs_qcom_phy(generic_phy
);
678 struct device
*dev
= phy_common
->dev
;
681 err
= ufs_qcom_phy_enable_vreg(generic_phy
, &phy_common
->vdda_phy
);
683 dev_err(dev
, "%s enable vdda_phy failed, err=%d\n",
688 phy_common
->phy_spec_ops
->power_control(phy_common
, true);
690 /* vdda_pll also enables ref clock LDOs so enable it first */
691 err
= ufs_qcom_phy_enable_vreg(generic_phy
, &phy_common
->vdda_pll
);
693 dev_err(dev
, "%s enable vdda_pll failed, err=%d\n",
695 goto out_disable_phy
;
698 err
= ufs_qcom_phy_enable_ref_clk(generic_phy
);
700 dev_err(dev
, "%s enable phy ref clock failed, err=%d\n",
702 goto out_disable_pll
;
705 /* enable device PHY ref_clk pad rail */
706 if (phy_common
->vddp_ref_clk
.reg
) {
707 err
= ufs_qcom_phy_enable_vreg(generic_phy
,
708 &phy_common
->vddp_ref_clk
);
710 dev_err(dev
, "%s enable vddp_ref_clk failed, err=%d\n",
712 goto out_disable_ref_clk
;
716 phy_common
->is_powered_on
= true;
720 ufs_qcom_phy_disable_ref_clk(generic_phy
);
722 ufs_qcom_phy_disable_vreg(generic_phy
, &phy_common
->vdda_pll
);
724 ufs_qcom_phy_disable_vreg(generic_phy
, &phy_common
->vdda_phy
);
729 int ufs_qcom_phy_power_off(struct phy
*generic_phy
)
731 struct ufs_qcom_phy
*phy_common
= get_ufs_qcom_phy(generic_phy
);
733 phy_common
->phy_spec_ops
->power_control(phy_common
, false);
735 if (phy_common
->vddp_ref_clk
.reg
)
736 ufs_qcom_phy_disable_vreg(generic_phy
,
737 &phy_common
->vddp_ref_clk
);
738 ufs_qcom_phy_disable_ref_clk(generic_phy
);
740 ufs_qcom_phy_disable_vreg(generic_phy
, &phy_common
->vdda_pll
);
741 ufs_qcom_phy_disable_vreg(generic_phy
, &phy_common
->vdda_phy
);
742 phy_common
->is_powered_on
= false;