drivers/phy/phy-rcar-gen3-usb2.c

   1 /*
   2  * Renesas R-Car Gen3 for USB2.0 PHY driver
   3  *
   4  * Copyright (C) 2015 Renesas Electronics Corporation
   5  *
   6  * This is based on the phy-rcar-gen2 driver:
   7  * Copyright (C) 2014 Renesas Solutions Corp.
   8  * Copyright (C) 2014 Cogent Embedded, Inc.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/extcon.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_address.h>
  21 #include <linux/phy/phy.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/regulator/consumer.h>
  24
  25 /******* USB2.0 Host registers (original offset is +0x200) *******/
  26 #define USB2_INT_ENABLE         0x000
  27 #define USB2_USBCTR             0x00c
  28 #define USB2_SPD_RSM_TIMSET     0x10c
  29 #define USB2_OC_TIMSET          0x110
  30 #define USB2_COMMCTRL           0x600
  31 #define USB2_OBINTSTA           0x604
  32 #define USB2_OBINTEN            0x608
  33 #define USB2_VBCTRL             0x60c
  34 #define USB2_LINECTRL1          0x610
  35 #define USB2_ADPCTRL            0x630
  36
  37 /* INT_ENABLE */
  38 #define USB2_INT_ENABLE_UCOM_INTEN      BIT(3)
  39 #define USB2_INT_ENABLE_USBH_INTB_EN    BIT(2)
  40 #define USB2_INT_ENABLE_USBH_INTA_EN    BIT(1)
  41 #define USB2_INT_ENABLE_INIT            (USB2_INT_ENABLE_UCOM_INTEN | \
  42                                          USB2_INT_ENABLE_USBH_INTB_EN | \
  43                                          USB2_INT_ENABLE_USBH_INTA_EN)
  44
  45 /* USBCTR */
  46 #define USB2_USBCTR_DIRPD       BIT(2)
  47 #define USB2_USBCTR_PLL_RST     BIT(1)
  48
  49 /* SPD_RSM_TIMSET */
  50 #define USB2_SPD_RSM_TIMSET_INIT        0x014e029b
  51
  52 /* OC_TIMSET */
  53 #define USB2_OC_TIMSET_INIT             0x000209ab
  54
  55 /* COMMCTRL */
  56 #define USB2_COMMCTRL_OTG_PERI          BIT(31) /* 1 = Peripheral mode */
  57
  58 /* OBINTSTA and OBINTEN */
  59 #define USB2_OBINT_SESSVLDCHG           BIT(12)
  60 #define USB2_OBINT_IDDIGCHG             BIT(11)
  61 #define USB2_OBINT_BITS                 (USB2_OBINT_SESSVLDCHG | \
  62                                          USB2_OBINT_IDDIGCHG)
  63
  64 /* VBCTRL */
  65 #define USB2_VBCTRL_DRVVBUSSEL          BIT(8)
  66
  67 /* LINECTRL1 */
  68 #define USB2_LINECTRL1_DPRPD_EN         BIT(19)
  69 #define USB2_LINECTRL1_DP_RPD           BIT(18)
  70 #define USB2_LINECTRL1_DMRPD_EN         BIT(17)
  71 #define USB2_LINECTRL1_DM_RPD           BIT(16)
  72
  73 /* ADPCTRL */
  74 #define USB2_ADPCTRL_OTGSESSVLD         BIT(20)
  75 #define USB2_ADPCTRL_IDDIG              BIT(19)
  76 #define USB2_ADPCTRL_IDPULLUP           BIT(5)  /* 1 = ID sampling is enabled */
  77 #define USB2_ADPCTRL_DRVVBUS            BIT(4)
  78
  79 struct rcar_gen3_chan {
  80         void __iomem *base;
  81         struct extcon_dev *extcon;
  82         struct phy *phy;
  83         struct regulator *vbus;
  84         bool has_otg;
  85 };
  86
  87 static void rcar_gen3_set_host_mode(struct rcar_gen3_chan *ch, int host)
  88 {
  89         void __iomem *usb2_base = ch->base;
  90         u32 val = readl(usb2_base + USB2_COMMCTRL);
  91
  92         dev_vdbg(&ch->phy->dev, "%s: %08x, %d\n", __func__, val, host);
  93         if (host)
  94                 val &= ~USB2_COMMCTRL_OTG_PERI;
  95         else
  96                 val |= USB2_COMMCTRL_OTG_PERI;
  97         writel(val, usb2_base + USB2_COMMCTRL);
  98 }
  99
 100 static void rcar_gen3_set_linectrl(struct rcar_gen3_chan *ch, int dp, int dm)
 101 {
 102         void __iomem *usb2_base = ch->base;
 103         u32 val = readl(usb2_base + USB2_LINECTRL1);
 104
 105         dev_vdbg(&ch->phy->dev, "%s: %08x, %d, %d\n", __func__, val, dp, dm);
 106         val &= ~(USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD);
 107         if (dp)
 108                 val |= USB2_LINECTRL1_DP_RPD;
 109         if (dm)
 110                 val |= USB2_LINECTRL1_DM_RPD;
 111         writel(val, usb2_base + USB2_LINECTRL1);
 112 }
 113
 114 static void rcar_gen3_enable_vbus_ctrl(struct rcar_gen3_chan *ch, int vbus)
 115 {
 116         void __iomem *usb2_base = ch->base;
 117         u32 val = readl(usb2_base + USB2_ADPCTRL);
 118
 119         dev_vdbg(&ch->phy->dev, "%s: %08x, %d\n", __func__, val, vbus);
 120         if (vbus)
 121                 val |= USB2_ADPCTRL_DRVVBUS;
 122         else
 123                 val &= ~USB2_ADPCTRL_DRVVBUS;
 124         writel(val, usb2_base + USB2_ADPCTRL);
 125 }
 126
 127 static void rcar_gen3_init_for_host(struct rcar_gen3_chan *ch)
 128 {
 129         rcar_gen3_set_linectrl(ch, 1, 1);
 130         rcar_gen3_set_host_mode(ch, 1);
 131         rcar_gen3_enable_vbus_ctrl(ch, 1);
 132
 133         extcon_set_cable_state_(ch->extcon, EXTCON_USB_HOST, true);
 134         extcon_set_cable_state_(ch->extcon, EXTCON_USB, false);
 135 }
 136
 137 static void rcar_gen3_init_for_peri(struct rcar_gen3_chan *ch)
 138 {
 139         rcar_gen3_set_linectrl(ch, 0, 1);
 140         rcar_gen3_set_host_mode(ch, 0);
 141         rcar_gen3_enable_vbus_ctrl(ch, 0);
 142
 143         extcon_set_cable_state_(ch->extcon, EXTCON_USB_HOST, false);
 144         extcon_set_cable_state_(ch->extcon, EXTCON_USB, true);
 145 }
 146
 147 static bool rcar_gen3_check_id(struct rcar_gen3_chan *ch)
 148 {
 149         return !!(readl(ch->base + USB2_ADPCTRL) & USB2_ADPCTRL_IDDIG);
 150 }
 151
 152 static void rcar_gen3_device_recognition(struct rcar_gen3_chan *ch)
 153 {
 154         if (!rcar_gen3_check_id(ch))
 155                 rcar_gen3_init_for_host(ch);
 156         else
 157                 rcar_gen3_init_for_peri(ch);
 158 }
 159
 160 static void rcar_gen3_init_otg(struct rcar_gen3_chan *ch)
 161 {
 162         void __iomem *usb2_base = ch->base;
 163         u32 val;
 164
 165         val = readl(usb2_base + USB2_VBCTRL);
 166         writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL);
 167         writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTSTA);
 168         val = readl(usb2_base + USB2_OBINTEN);
 169         writel(val | USB2_OBINT_BITS, usb2_base + USB2_OBINTEN);
 170         val = readl(usb2_base + USB2_ADPCTRL);
 171         writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL);
 172         val = readl(usb2_base + USB2_LINECTRL1);
 173         rcar_gen3_set_linectrl(ch, 0, 0);
 174         writel(val | USB2_LINECTRL1_DPRPD_EN | USB2_LINECTRL1_DMRPD_EN,
 175                usb2_base + USB2_LINECTRL1);
 176
 177         rcar_gen3_device_recognition(ch);
 178 }
 179
 180 static int rcar_gen3_phy_usb2_init(struct phy *p)
 181 {
 182         struct rcar_gen3_chan *channel = phy_get_drvdata(p);
 183         void __iomem *usb2_base = channel->base;
 184
 185         /* Initialize USB2 part */
 186         writel(USB2_INT_ENABLE_INIT, usb2_base + USB2_INT_ENABLE);
 187         writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET);
 188         writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET);
 189
 190         /* Initialize otg part */
 191         if (channel->has_otg)
 192                 rcar_gen3_init_otg(channel);
 193
 194         return 0;
 195 }
 196
 197 static int rcar_gen3_phy_usb2_exit(struct phy *p)
 198 {
 199         struct rcar_gen3_chan *channel = phy_get_drvdata(p);
 200
 201         writel(0, channel->base + USB2_INT_ENABLE);
 202
 203         return 0;
 204 }
 205
 206 static int rcar_gen3_phy_usb2_power_on(struct phy *p)
 207 {
 208         struct rcar_gen3_chan *channel = phy_get_drvdata(p);
 209         void __iomem *usb2_base = channel->base;
 210         u32 val;
 211         int ret;
 212
 213         if (channel->vbus) {
 214                 ret = regulator_enable(channel->vbus);
 215                 if (ret)
 216                         return ret;
 217         }
 218
 219         val = readl(usb2_base + USB2_USBCTR);
 220         val |= USB2_USBCTR_PLL_RST;
 221         writel(val, usb2_base + USB2_USBCTR);
 222         val &= ~USB2_USBCTR_PLL_RST;
 223         writel(val, usb2_base + USB2_USBCTR);
 224
 225         return 0;
 226 }
 227
 228 static int rcar_gen3_phy_usb2_power_off(struct phy *p)
 229 {
 230         struct rcar_gen3_chan *channel = phy_get_drvdata(p);
 231         int ret = 0;
 232
 233         if (channel->vbus)
 234                 ret = regulator_disable(channel->vbus);
 235
 236         return ret;
 237 }
 238
 239 static struct phy_ops rcar_gen3_phy_usb2_ops = {
 240         .init           = rcar_gen3_phy_usb2_init,
 241         .exit           = rcar_gen3_phy_usb2_exit,
 242         .power_on       = rcar_gen3_phy_usb2_power_on,
 243         .power_off      = rcar_gen3_phy_usb2_power_off,
 244         .owner          = THIS_MODULE,
 245 };
 246
 247 static irqreturn_t rcar_gen3_phy_usb2_irq(int irq, void *_ch)
 248 {
 249         struct rcar_gen3_chan *ch = _ch;
 250         void __iomem *usb2_base = ch->base;
 251         u32 status = readl(usb2_base + USB2_OBINTSTA);
 252         irqreturn_t ret = IRQ_NONE;
 253
 254         if (status & USB2_OBINT_BITS) {
 255                 dev_vdbg(&ch->phy->dev, "%s: %08x\n", __func__, status);
 256                 writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTSTA);
 257                 rcar_gen3_device_recognition(ch);
 258                 ret = IRQ_HANDLED;
 259         }
 260
 261         return ret;
 262 }
 263
 264 static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
 265         { .compatible = "renesas,usb2-phy-r8a7795" },
 266         { .compatible = "renesas,rcar-gen3-usb2-phy" },
 267         { }
 268 };
 269 MODULE_DEVICE_TABLE(of, rcar_gen3_phy_usb2_match_table);
 270
 271 static const unsigned int rcar_gen3_phy_cable[] = {
 272         EXTCON_USB,
 273         EXTCON_USB_HOST,
 274         EXTCON_NONE,
 275 };
 276
 277 static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
 278 {
 279         struct device *dev = &pdev->dev;
 280         struct rcar_gen3_chan *channel;
 281         struct phy_provider *provider;
 282         struct resource *res;
 283         int irq;
 284
 285         if (!dev->of_node) {
 286                 dev_err(dev, "This driver needs device tree\n");
 287                 return -EINVAL;
 288         }
 289
 290         channel = devm_kzalloc(dev, sizeof(*channel), GFP_KERNEL);
 291         if (!channel)
 292                 return -ENOMEM;
 293
 294         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 295         channel->base = devm_ioremap_resource(dev, res);
 296         if (IS_ERR(channel->base))
 297                 return PTR_ERR(channel->base);
 298
 299         /* call request_irq for OTG */
 300         irq = platform_get_irq(pdev, 0);
 301         if (irq >= 0) {
 302                 int ret;
 303
 304                 irq = devm_request_irq(dev, irq, rcar_gen3_phy_usb2_irq,
 305                                        IRQF_SHARED, dev_name(dev), channel);
 306                 if (irq < 0)
 307                         dev_err(dev, "No irq handler (%d)\n", irq);
 308                 channel->has_otg = true;
 309                 channel->extcon = devm_extcon_dev_allocate(dev,
 310                                                         rcar_gen3_phy_cable);
 311                 if (IS_ERR(channel->extcon))
 312                         return PTR_ERR(channel->extcon);
 313
 314                 ret = devm_extcon_dev_register(dev, channel->extcon);
 315                 if (ret < 0) {
 316                         dev_err(dev, "Failed to register extcon\n");
 317                         return ret;
 318                 }
 319         }
 320
 321         /* devm_phy_create() will call pm_runtime_enable(dev); */
 322         channel->phy = devm_phy_create(dev, NULL, &rcar_gen3_phy_usb2_ops);
 323         if (IS_ERR(channel->phy)) {
 324                 dev_err(dev, "Failed to create USB2 PHY\n");
 325                 return PTR_ERR(channel->phy);
 326         }
 327
 328         channel->vbus = devm_regulator_get_optional(dev, "vbus");
 329         if (IS_ERR(channel->vbus)) {
 330                 if (PTR_ERR(channel->vbus) == -EPROBE_DEFER)
 331                         return PTR_ERR(channel->vbus);
 332                 channel->vbus = NULL;
 333         }
 334
 335         phy_set_drvdata(channel->phy, channel);
 336
 337         provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 338         if (IS_ERR(provider))
 339                 dev_err(dev, "Failed to register PHY provider\n");
 340
 341         return PTR_ERR_OR_ZERO(provider);
 342 }
 343
 344 static struct platform_driver rcar_gen3_phy_usb2_driver = {
 345         .driver = {
 346                 .name           = "phy_rcar_gen3_usb2",
 347                 .of_match_table = rcar_gen3_phy_usb2_match_table,
 348         },
 349         .probe  = rcar_gen3_phy_usb2_probe,
 350 };
 351 module_platform_driver(rcar_gen3_phy_usb2_driver);
 352
 353 MODULE_LICENSE("GPL v2");
 354 MODULE_DESCRIPTION("Renesas R-Car Gen3 USB 2.0 PHY");
 355 MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");