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Merge branch 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm
[deliverable/linux.git] / drivers / phy / phy-twl4030-usb.c
1 /*
2 * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller
3 *
4 * Copyright (C) 2004-2007 Texas Instruments
5 * Copyright (C) 2008 Nokia Corporation
6 * Contact: Felipe Balbi <felipe.balbi@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Current status:
23 * - HS USB ULPI mode works.
24 * - 3-pin mode support may be added in future.
25 */
26
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/platform_device.h>
31 #include <linux/workqueue.h>
32 #include <linux/io.h>
33 #include <linux/delay.h>
34 #include <linux/usb/otg.h>
35 #include <linux/phy/phy.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/usb/musb-omap.h>
38 #include <linux/usb/ulpi.h>
39 #include <linux/i2c/twl.h>
40 #include <linux/regulator/consumer.h>
41 #include <linux/err.h>
42 #include <linux/slab.h>
43
44 /* Register defines */
45
46 #define MCPC_CTRL 0x30
47 #define MCPC_CTRL_RTSOL (1 << 7)
48 #define MCPC_CTRL_EXTSWR (1 << 6)
49 #define MCPC_CTRL_EXTSWC (1 << 5)
50 #define MCPC_CTRL_VOICESW (1 << 4)
51 #define MCPC_CTRL_OUT64K (1 << 3)
52 #define MCPC_CTRL_RTSCTSSW (1 << 2)
53 #define MCPC_CTRL_HS_UART (1 << 0)
54
55 #define MCPC_IO_CTRL 0x33
56 #define MCPC_IO_CTRL_MICBIASEN (1 << 5)
57 #define MCPC_IO_CTRL_CTS_NPU (1 << 4)
58 #define MCPC_IO_CTRL_RXD_PU (1 << 3)
59 #define MCPC_IO_CTRL_TXDTYP (1 << 2)
60 #define MCPC_IO_CTRL_CTSTYP (1 << 1)
61 #define MCPC_IO_CTRL_RTSTYP (1 << 0)
62
63 #define MCPC_CTRL2 0x36
64 #define MCPC_CTRL2_MCPC_CK_EN (1 << 0)
65
66 #define OTHER_FUNC_CTRL 0x80
67 #define OTHER_FUNC_CTRL_BDIS_ACON_EN (1 << 4)
68 #define OTHER_FUNC_CTRL_FIVEWIRE_MODE (1 << 2)
69
70 #define OTHER_IFC_CTRL 0x83
71 #define OTHER_IFC_CTRL_OE_INT_EN (1 << 6)
72 #define OTHER_IFC_CTRL_CEA2011_MODE (1 << 5)
73 #define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN (1 << 4)
74 #define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT (1 << 3)
75 #define OTHER_IFC_CTRL_HIZ_ULPI (1 << 2)
76 #define OTHER_IFC_CTRL_ALT_INT_REROUTE (1 << 0)
77
78 #define OTHER_INT_EN_RISE 0x86
79 #define OTHER_INT_EN_FALL 0x89
80 #define OTHER_INT_STS 0x8C
81 #define OTHER_INT_LATCH 0x8D
82 #define OTHER_INT_VB_SESS_VLD (1 << 7)
83 #define OTHER_INT_DM_HI (1 << 6) /* not valid for "latch" reg */
84 #define OTHER_INT_DP_HI (1 << 5) /* not valid for "latch" reg */
85 #define OTHER_INT_BDIS_ACON (1 << 3) /* not valid for "fall" regs */
86 #define OTHER_INT_MANU (1 << 1)
87 #define OTHER_INT_ABNORMAL_STRESS (1 << 0)
88
89 #define ID_STATUS 0x96
90 #define ID_RES_FLOAT (1 << 4)
91 #define ID_RES_440K (1 << 3)
92 #define ID_RES_200K (1 << 2)
93 #define ID_RES_102K (1 << 1)
94 #define ID_RES_GND (1 << 0)
95
96 #define POWER_CTRL 0xAC
97 #define POWER_CTRL_OTG_ENAB (1 << 5)
98
99 #define OTHER_IFC_CTRL2 0xAF
100 #define OTHER_IFC_CTRL2_ULPI_STP_LOW (1 << 4)
101 #define OTHER_IFC_CTRL2_ULPI_TXEN_POL (1 << 3)
102 #define OTHER_IFC_CTRL2_ULPI_4PIN_2430 (1 << 2)
103 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK (3 << 0) /* bits 0 and 1 */
104 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N (0 << 0)
105 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N (1 << 0)
106
107 #define REG_CTRL_EN 0xB2
108 #define REG_CTRL_ERROR 0xB5
109 #define ULPI_I2C_CONFLICT_INTEN (1 << 0)
110
111 #define OTHER_FUNC_CTRL2 0xB8
112 #define OTHER_FUNC_CTRL2_VBAT_TIMER_EN (1 << 0)
113
114 /* following registers do not have separate _clr and _set registers */
115 #define VBUS_DEBOUNCE 0xC0
116 #define ID_DEBOUNCE 0xC1
117 #define VBAT_TIMER 0xD3
118 #define PHY_PWR_CTRL 0xFD
119 #define PHY_PWR_PHYPWD (1 << 0)
120 #define PHY_CLK_CTRL 0xFE
121 #define PHY_CLK_CTRL_CLOCKGATING_EN (1 << 2)
122 #define PHY_CLK_CTRL_CLK32K_EN (1 << 1)
123 #define REQ_PHY_DPLL_CLK (1 << 0)
124 #define PHY_CLK_CTRL_STS 0xFF
125 #define PHY_DPLL_CLK (1 << 0)
126
127 /* In module TWL_MODULE_PM_MASTER */
128 #define STS_HW_CONDITIONS 0x0F
129
130 /* In module TWL_MODULE_PM_RECEIVER */
131 #define VUSB_DEDICATED1 0x7D
132 #define VUSB_DEDICATED2 0x7E
133 #define VUSB1V5_DEV_GRP 0x71
134 #define VUSB1V5_TYPE 0x72
135 #define VUSB1V5_REMAP 0x73
136 #define VUSB1V8_DEV_GRP 0x74
137 #define VUSB1V8_TYPE 0x75
138 #define VUSB1V8_REMAP 0x76
139 #define VUSB3V1_DEV_GRP 0x77
140 #define VUSB3V1_TYPE 0x78
141 #define VUSB3V1_REMAP 0x79
142
143 /* In module TWL4030_MODULE_INTBR */
144 #define PMBR1 0x0D
145 #define GPIO_USB_4PIN_ULPI_2430C (3 << 0)
146
147 struct twl4030_usb {
148 struct usb_phy phy;
149 struct device *dev;
150
151 /* TWL4030 internal USB regulator supplies */
152 struct regulator *usb1v5;
153 struct regulator *usb1v8;
154 struct regulator *usb3v1;
155
156 /* for vbus reporting with irqs disabled */
157 struct mutex lock;
158
159 /* pin configuration */
160 enum twl4030_usb_mode usb_mode;
161
162 int irq;
163 enum omap_musb_vbus_id_status linkstat;
164 bool vbus_supplied;
165
166 struct delayed_work id_workaround_work;
167 };
168
169 /* internal define on top of container_of */
170 #define phy_to_twl(x) container_of((x), struct twl4030_usb, phy)
171
172 /*-------------------------------------------------------------------------*/
173
174 static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl,
175 u8 module, u8 data, u8 address)
176 {
177 u8 check;
178
179 if ((twl_i2c_write_u8(module, data, address) >= 0) &&
180 (twl_i2c_read_u8(module, &check, address) >= 0) &&
181 (check == data))
182 return 0;
183 dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
184 1, module, address, check, data);
185
186 /* Failed once: Try again */
187 if ((twl_i2c_write_u8(module, data, address) >= 0) &&
188 (twl_i2c_read_u8(module, &check, address) >= 0) &&
189 (check == data))
190 return 0;
191 dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
192 2, module, address, check, data);
193
194 /* Failed again: Return error */
195 return -EBUSY;
196 }
197
198 #define twl4030_usb_write_verify(twl, address, data) \
199 twl4030_i2c_write_u8_verify(twl, TWL_MODULE_USB, (data), (address))
200
201 static inline int twl4030_usb_write(struct twl4030_usb *twl,
202 u8 address, u8 data)
203 {
204 int ret = 0;
205
206 ret = twl_i2c_write_u8(TWL_MODULE_USB, data, address);
207 if (ret < 0)
208 dev_dbg(twl->dev,
209 "TWL4030:USB:Write[0x%x] Error %d\n", address, ret);
210 return ret;
211 }
212
213 static inline int twl4030_readb(struct twl4030_usb *twl, u8 module, u8 address)
214 {
215 u8 data;
216 int ret = 0;
217
218 ret = twl_i2c_read_u8(module, &data, address);
219 if (ret >= 0)
220 ret = data;
221 else
222 dev_dbg(twl->dev,
223 "TWL4030:readb[0x%x,0x%x] Error %d\n",
224 module, address, ret);
225
226 return ret;
227 }
228
229 static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address)
230 {
231 return twl4030_readb(twl, TWL_MODULE_USB, address);
232 }
233
234 /*-------------------------------------------------------------------------*/
235
236 static inline int
237 twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
238 {
239 return twl4030_usb_write(twl, ULPI_SET(reg), bits);
240 }
241
242 static inline int
243 twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
244 {
245 return twl4030_usb_write(twl, ULPI_CLR(reg), bits);
246 }
247
248 /*-------------------------------------------------------------------------*/
249
250 static bool twl4030_is_driving_vbus(struct twl4030_usb *twl)
251 {
252 int ret;
253
254 ret = twl4030_usb_read(twl, PHY_CLK_CTRL_STS);
255 if (ret < 0 || !(ret & PHY_DPLL_CLK))
256 /*
257 * if clocks are off, registers are not updated,
258 * but we can assume we don't drive VBUS in this case
259 */
260 return false;
261
262 ret = twl4030_usb_read(twl, ULPI_OTG_CTRL);
263 if (ret < 0)
264 return false;
265
266 return (ret & (ULPI_OTG_DRVVBUS | ULPI_OTG_CHRGVBUS)) ? true : false;
267 }
268
269 static enum omap_musb_vbus_id_status
270 twl4030_usb_linkstat(struct twl4030_usb *twl)
271 {
272 int status;
273 enum omap_musb_vbus_id_status linkstat = OMAP_MUSB_UNKNOWN;
274
275 twl->vbus_supplied = false;
276
277 /*
278 * For ID/VBUS sensing, see manual section 15.4.8 ...
279 * except when using only battery backup power, two
280 * comparators produce VBUS_PRES and ID_PRES signals,
281 * which don't match docs elsewhere. But ... BIT(7)
282 * and BIT(2) of STS_HW_CONDITIONS, respectively, do
283 * seem to match up. If either is true the USB_PRES
284 * signal is active, the OTG module is activated, and
285 * its interrupt may be raised (may wake the system).
286 */
287 status = twl4030_readb(twl, TWL_MODULE_PM_MASTER, STS_HW_CONDITIONS);
288 if (status < 0)
289 dev_err(twl->dev, "USB link status err %d\n", status);
290 else if (status & (BIT(7) | BIT(2))) {
291 if (status & BIT(7)) {
292 if (twl4030_is_driving_vbus(twl))
293 status &= ~BIT(7);
294 else
295 twl->vbus_supplied = true;
296 }
297
298 if (status & BIT(2))
299 linkstat = OMAP_MUSB_ID_GROUND;
300 else if (status & BIT(7))
301 linkstat = OMAP_MUSB_VBUS_VALID;
302 else
303 linkstat = OMAP_MUSB_VBUS_OFF;
304 } else {
305 if (twl->linkstat != OMAP_MUSB_UNKNOWN)
306 linkstat = OMAP_MUSB_VBUS_OFF;
307 }
308
309 dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n",
310 status, status, linkstat);
311
312 /* REVISIT this assumes host and peripheral controllers
313 * are registered, and that both are active...
314 */
315
316 return linkstat;
317 }
318
319 static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode)
320 {
321 twl->usb_mode = mode;
322
323 switch (mode) {
324 case T2_USB_MODE_ULPI:
325 twl4030_usb_clear_bits(twl, ULPI_IFC_CTRL,
326 ULPI_IFC_CTRL_CARKITMODE);
327 twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
328 twl4030_usb_clear_bits(twl, ULPI_FUNC_CTRL,
329 ULPI_FUNC_CTRL_XCVRSEL_MASK |
330 ULPI_FUNC_CTRL_OPMODE_MASK);
331 break;
332 case -1:
333 /* FIXME: power on defaults */
334 break;
335 default:
336 dev_err(twl->dev, "unsupported T2 transceiver mode %d\n",
337 mode);
338 break;
339 }
340 }
341
342 static void twl4030_i2c_access(struct twl4030_usb *twl, int on)
343 {
344 unsigned long timeout;
345 int val = twl4030_usb_read(twl, PHY_CLK_CTRL);
346
347 if (val >= 0) {
348 if (on) {
349 /* enable DPLL to access PHY registers over I2C */
350 val |= REQ_PHY_DPLL_CLK;
351 WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
352 (u8)val) < 0);
353
354 timeout = jiffies + HZ;
355 while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
356 PHY_DPLL_CLK)
357 && time_before(jiffies, timeout))
358 udelay(10);
359 if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
360 PHY_DPLL_CLK))
361 dev_err(twl->dev, "Timeout setting T2 HSUSB "
362 "PHY DPLL clock\n");
363 } else {
364 /* let ULPI control the DPLL clock */
365 val &= ~REQ_PHY_DPLL_CLK;
366 WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
367 (u8)val) < 0);
368 }
369 }
370 }
371
372 static void __twl4030_phy_power(struct twl4030_usb *twl, int on)
373 {
374 u8 pwr = twl4030_usb_read(twl, PHY_PWR_CTRL);
375
376 if (on)
377 pwr &= ~PHY_PWR_PHYPWD;
378 else
379 pwr |= PHY_PWR_PHYPWD;
380
381 WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0);
382 }
383
384 static int twl4030_usb_runtime_suspend(struct device *dev)
385 {
386 struct twl4030_usb *twl = dev_get_drvdata(dev);
387
388 dev_dbg(twl->dev, "%s\n", __func__);
389 if (pm_runtime_suspended(dev))
390 return 0;
391
392 __twl4030_phy_power(twl, 0);
393 regulator_disable(twl->usb1v5);
394 regulator_disable(twl->usb1v8);
395 regulator_disable(twl->usb3v1);
396
397 return 0;
398 }
399
400 static int twl4030_usb_runtime_resume(struct device *dev)
401 {
402 struct twl4030_usb *twl = dev_get_drvdata(dev);
403 int res;
404
405 dev_dbg(twl->dev, "%s\n", __func__);
406 if (pm_runtime_active(dev))
407 return 0;
408
409 res = regulator_enable(twl->usb3v1);
410 if (res)
411 dev_err(twl->dev, "Failed to enable usb3v1\n");
412
413 res = regulator_enable(twl->usb1v8);
414 if (res)
415 dev_err(twl->dev, "Failed to enable usb1v8\n");
416
417 /*
418 * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP
419 * in twl4030) resets the VUSB_DEDICATED2 register. This reset
420 * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to
421 * SLEEP. We work around this by clearing the bit after usv3v1
422 * is re-activated. This ensures that VUSB3V1 is really active.
423 */
424 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);
425
426 res = regulator_enable(twl->usb1v5);
427 if (res)
428 dev_err(twl->dev, "Failed to enable usb1v5\n");
429
430 __twl4030_phy_power(twl, 1);
431 twl4030_usb_write(twl, PHY_CLK_CTRL,
432 twl4030_usb_read(twl, PHY_CLK_CTRL) |
433 (PHY_CLK_CTRL_CLOCKGATING_EN |
434 PHY_CLK_CTRL_CLK32K_EN));
435
436 return 0;
437 }
438
439 static int twl4030_phy_power_off(struct phy *phy)
440 {
441 struct twl4030_usb *twl = phy_get_drvdata(phy);
442
443 dev_dbg(twl->dev, "%s\n", __func__);
444 pm_runtime_mark_last_busy(twl->dev);
445 pm_runtime_put_autosuspend(twl->dev);
446
447 return 0;
448 }
449
450 static int twl4030_phy_power_on(struct phy *phy)
451 {
452 struct twl4030_usb *twl = phy_get_drvdata(phy);
453
454 dev_dbg(twl->dev, "%s\n", __func__);
455 pm_runtime_get_sync(twl->dev);
456 twl4030_i2c_access(twl, 1);
457 twl4030_usb_set_mode(twl, twl->usb_mode);
458 if (twl->usb_mode == T2_USB_MODE_ULPI)
459 twl4030_i2c_access(twl, 0);
460 schedule_delayed_work(&twl->id_workaround_work, 0);
461
462 return 0;
463 }
464
465 static int twl4030_usb_ldo_init(struct twl4030_usb *twl)
466 {
467 /* Enable writing to power configuration registers */
468 twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
469 TWL4030_PM_MASTER_PROTECT_KEY);
470
471 twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
472 TWL4030_PM_MASTER_PROTECT_KEY);
473
474 /* Keep VUSB3V1 LDO in sleep state until VBUS/ID change detected*/
475 /*twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);*/
476
477 /* input to VUSB3V1 LDO is from VBAT, not VBUS */
478 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1);
479
480 /* Initialize 3.1V regulator */
481 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_DEV_GRP);
482
483 twl->usb3v1 = devm_regulator_get(twl->dev, "usb3v1");
484 if (IS_ERR(twl->usb3v1))
485 return -ENODEV;
486
487 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE);
488
489 /* Initialize 1.5V regulator */
490 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_DEV_GRP);
491
492 twl->usb1v5 = devm_regulator_get(twl->dev, "usb1v5");
493 if (IS_ERR(twl->usb1v5))
494 return -ENODEV;
495
496 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE);
497
498 /* Initialize 1.8V regulator */
499 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_DEV_GRP);
500
501 twl->usb1v8 = devm_regulator_get(twl->dev, "usb1v8");
502 if (IS_ERR(twl->usb1v8))
503 return -ENODEV;
504
505 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE);
506
507 /* disable access to power configuration registers */
508 twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
509 TWL4030_PM_MASTER_PROTECT_KEY);
510
511 return 0;
512 }
513
514 static ssize_t twl4030_usb_vbus_show(struct device *dev,
515 struct device_attribute *attr, char *buf)
516 {
517 struct twl4030_usb *twl = dev_get_drvdata(dev);
518 int ret = -EINVAL;
519
520 mutex_lock(&twl->lock);
521 ret = sprintf(buf, "%s\n",
522 twl->vbus_supplied ? "on" : "off");
523 mutex_unlock(&twl->lock);
524
525 return ret;
526 }
527 static DEVICE_ATTR(vbus, 0444, twl4030_usb_vbus_show, NULL);
528
529 static irqreturn_t twl4030_usb_irq(int irq, void *_twl)
530 {
531 struct twl4030_usb *twl = _twl;
532 enum omap_musb_vbus_id_status status;
533 bool status_changed = false;
534
535 status = twl4030_usb_linkstat(twl);
536
537 mutex_lock(&twl->lock);
538 if (status >= 0 && status != twl->linkstat) {
539 twl->linkstat = status;
540 status_changed = true;
541 }
542 mutex_unlock(&twl->lock);
543
544 if (status_changed) {
545 /* FIXME add a set_power() method so that B-devices can
546 * configure the charger appropriately. It's not always
547 * correct to consume VBUS power, and how much current to
548 * consume is a function of the USB configuration chosen
549 * by the host.
550 *
551 * REVISIT usb_gadget_vbus_connect(...) as needed, ditto
552 * its disconnect() sibling, when changing to/from the
553 * USB_LINK_VBUS state. musb_hdrc won't care until it
554 * starts to handle softconnect right.
555 */
556 if ((status == OMAP_MUSB_VBUS_VALID) ||
557 (status == OMAP_MUSB_ID_GROUND)) {
558 if (pm_runtime_suspended(twl->dev))
559 pm_runtime_get_sync(twl->dev);
560 } else {
561 if (pm_runtime_active(twl->dev)) {
562 pm_runtime_mark_last_busy(twl->dev);
563 pm_runtime_put_autosuspend(twl->dev);
564 }
565 }
566 omap_musb_mailbox(status);
567 }
568
569 /* don't schedule during sleep - irq works right then */
570 if (status == OMAP_MUSB_ID_GROUND && pm_runtime_active(twl->dev)) {
571 cancel_delayed_work(&twl->id_workaround_work);
572 schedule_delayed_work(&twl->id_workaround_work, HZ);
573 }
574
575 if (irq)
576 sysfs_notify(&twl->dev->kobj, NULL, "vbus");
577
578 return IRQ_HANDLED;
579 }
580
581 static void twl4030_id_workaround_work(struct work_struct *work)
582 {
583 struct twl4030_usb *twl = container_of(work, struct twl4030_usb,
584 id_workaround_work.work);
585
586 twl4030_usb_irq(0, twl);
587 }
588
589 static int twl4030_phy_init(struct phy *phy)
590 {
591 struct twl4030_usb *twl = phy_get_drvdata(phy);
592
593 pm_runtime_get_sync(twl->dev);
594 schedule_delayed_work(&twl->id_workaround_work, 0);
595 pm_runtime_mark_last_busy(twl->dev);
596 pm_runtime_put_autosuspend(twl->dev);
597
598 return 0;
599 }
600
601 static int twl4030_set_peripheral(struct usb_otg *otg,
602 struct usb_gadget *gadget)
603 {
604 if (!otg)
605 return -ENODEV;
606
607 otg->gadget = gadget;
608 if (!gadget)
609 otg->phy->state = OTG_STATE_UNDEFINED;
610
611 return 0;
612 }
613
614 static int twl4030_set_host(struct usb_otg *otg, struct usb_bus *host)
615 {
616 if (!otg)
617 return -ENODEV;
618
619 otg->host = host;
620 if (!host)
621 otg->phy->state = OTG_STATE_UNDEFINED;
622
623 return 0;
624 }
625
626 static const struct phy_ops ops = {
627 .init = twl4030_phy_init,
628 .power_on = twl4030_phy_power_on,
629 .power_off = twl4030_phy_power_off,
630 .owner = THIS_MODULE,
631 };
632
633 static const struct dev_pm_ops twl4030_usb_pm_ops = {
634 SET_RUNTIME_PM_OPS(twl4030_usb_runtime_suspend,
635 twl4030_usb_runtime_resume, NULL)
636 };
637
638 static int twl4030_usb_probe(struct platform_device *pdev)
639 {
640 struct twl4030_usb_data *pdata = dev_get_platdata(&pdev->dev);
641 struct twl4030_usb *twl;
642 struct phy *phy;
643 int status, err;
644 struct usb_otg *otg;
645 struct device_node *np = pdev->dev.of_node;
646 struct phy_provider *phy_provider;
647 struct phy_init_data *init_data = NULL;
648
649 twl = devm_kzalloc(&pdev->dev, sizeof(*twl), GFP_KERNEL);
650 if (!twl)
651 return -ENOMEM;
652
653 if (np)
654 of_property_read_u32(np, "usb_mode",
655 (enum twl4030_usb_mode *)&twl->usb_mode);
656 else if (pdata) {
657 twl->usb_mode = pdata->usb_mode;
658 init_data = pdata->init_data;
659 } else {
660 dev_err(&pdev->dev, "twl4030 initialized without pdata\n");
661 return -EINVAL;
662 }
663
664 otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL);
665 if (!otg)
666 return -ENOMEM;
667
668 twl->dev = &pdev->dev;
669 twl->irq = platform_get_irq(pdev, 0);
670 twl->vbus_supplied = false;
671 twl->linkstat = -EINVAL;
672 twl->linkstat = OMAP_MUSB_UNKNOWN;
673
674 twl->phy.dev = twl->dev;
675 twl->phy.label = "twl4030";
676 twl->phy.otg = otg;
677 twl->phy.type = USB_PHY_TYPE_USB2;
678
679 otg->phy = &twl->phy;
680 otg->set_host = twl4030_set_host;
681 otg->set_peripheral = twl4030_set_peripheral;
682
683 phy = devm_phy_create(twl->dev, NULL, &ops, init_data);
684 if (IS_ERR(phy)) {
685 dev_dbg(&pdev->dev, "Failed to create PHY\n");
686 return PTR_ERR(phy);
687 }
688
689 phy_set_drvdata(phy, twl);
690
691 phy_provider = devm_of_phy_provider_register(twl->dev,
692 of_phy_simple_xlate);
693 if (IS_ERR(phy_provider))
694 return PTR_ERR(phy_provider);
695
696 /* init mutex for workqueue */
697 mutex_init(&twl->lock);
698
699 INIT_DELAYED_WORK(&twl->id_workaround_work, twl4030_id_workaround_work);
700
701 err = twl4030_usb_ldo_init(twl);
702 if (err) {
703 dev_err(&pdev->dev, "ldo init failed\n");
704 return err;
705 }
706 usb_add_phy_dev(&twl->phy);
707
708 platform_set_drvdata(pdev, twl);
709 if (device_create_file(&pdev->dev, &dev_attr_vbus))
710 dev_warn(&pdev->dev, "could not create sysfs file\n");
711
712 ATOMIC_INIT_NOTIFIER_HEAD(&twl->phy.notifier);
713
714 pm_runtime_use_autosuspend(&pdev->dev);
715 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
716 pm_runtime_enable(&pdev->dev);
717 pm_runtime_get_sync(&pdev->dev);
718
719 /* Our job is to use irqs and status from the power module
720 * to keep the transceiver disabled when nothing's connected.
721 *
722 * FIXME we actually shouldn't start enabling it until the
723 * USB controller drivers have said they're ready, by calling
724 * set_host() and/or set_peripheral() ... OTG_capable boards
725 * need both handles, otherwise just one suffices.
726 */
727 status = devm_request_threaded_irq(twl->dev, twl->irq, NULL,
728 twl4030_usb_irq, IRQF_TRIGGER_FALLING |
729 IRQF_TRIGGER_RISING | IRQF_ONESHOT, "twl4030_usb", twl);
730 if (status < 0) {
731 dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n",
732 twl->irq, status);
733 return status;
734 }
735
736 pm_runtime_mark_last_busy(&pdev->dev);
737 pm_runtime_put_autosuspend(twl->dev);
738
739 dev_info(&pdev->dev, "Initialized TWL4030 USB module\n");
740 return 0;
741 }
742
743 static int twl4030_usb_remove(struct platform_device *pdev)
744 {
745 struct twl4030_usb *twl = platform_get_drvdata(pdev);
746 int val;
747
748 pm_runtime_get_sync(twl->dev);
749 cancel_delayed_work(&twl->id_workaround_work);
750 device_remove_file(twl->dev, &dev_attr_vbus);
751
752 /* set transceiver mode to power on defaults */
753 twl4030_usb_set_mode(twl, -1);
754
755 /* autogate 60MHz ULPI clock,
756 * clear dpll clock request for i2c access,
757 * disable 32KHz
758 */
759 val = twl4030_usb_read(twl, PHY_CLK_CTRL);
760 if (val >= 0) {
761 val |= PHY_CLK_CTRL_CLOCKGATING_EN;
762 val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK);
763 twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val);
764 }
765
766 /* disable complete OTG block */
767 twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
768 pm_runtime_mark_last_busy(twl->dev);
769 pm_runtime_put(twl->dev);
770
771 return 0;
772 }
773
774 #ifdef CONFIG_OF
775 static const struct of_device_id twl4030_usb_id_table[] = {
776 { .compatible = "ti,twl4030-usb" },
777 {}
778 };
779 MODULE_DEVICE_TABLE(of, twl4030_usb_id_table);
780 #endif
781
782 static struct platform_driver twl4030_usb_driver = {
783 .probe = twl4030_usb_probe,
784 .remove = twl4030_usb_remove,
785 .driver = {
786 .name = "twl4030_usb",
787 .pm = &twl4030_usb_pm_ops,
788 .of_match_table = of_match_ptr(twl4030_usb_id_table),
789 },
790 };
791
792 static int __init twl4030_usb_init(void)
793 {
794 return platform_driver_register(&twl4030_usb_driver);
795 }
796 subsys_initcall(twl4030_usb_init);
797
798 static void __exit twl4030_usb_exit(void)
799 {
800 platform_driver_unregister(&twl4030_usb_driver);
801 }
802 module_exit(twl4030_usb_exit);
803
804 MODULE_ALIAS("platform:twl4030_usb");
805 MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation");
806 MODULE_DESCRIPTION("TWL4030 USB transceiver driver");
807 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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