bbf14dc67ad2059e7e81dd7bb10eab7651547554
[deliverable/linux.git] / drivers / pinctrl / Kconfig
1 #
2 # PINCTRL infrastructure and drivers
3 #
4
5 config PINCTRL
6 bool
7
8 if PINCTRL
9
10 menu "Pin controllers"
11 depends on PINCTRL
12
13 config PINMUX
14 bool "Support pin multiplexing controllers"
15
16 config PINCONF
17 bool "Support pin configuration controllers"
18
19 config GENERIC_PINCONF
20 bool
21 select PINCONF
22
23 config DEBUG_PINCTRL
24 bool "Debug PINCTRL calls"
25 depends on DEBUG_KERNEL
26 help
27 Say Y here to add some extra checks and diagnostics to PINCTRL calls.
28
29 config PINCTRL_PXA3xx
30 bool
31 select PINMUX
32
33 config PINCTRL_MMP2
34 bool "MMP2 pin controller driver"
35 depends on ARCH_MMP
36 select PINCTRL_PXA3xx
37 select PINCONF
38
39 config PINCTRL_NOMADIK
40 bool "Nomadik pin controller driver"
41 depends on ARCH_U8500
42 select PINMUX
43
44 config PINCTRL_DB8500
45 bool "DB8500 pin controller driver"
46 depends on PINCTRL_NOMADIK && ARCH_U8500
47
48 config PINCTRL_PXA168
49 bool "PXA168 pin controller driver"
50 depends on ARCH_MMP
51 select PINCTRL_PXA3xx
52 select PINCONF
53
54 config PINCTRL_PXA910
55 bool "PXA910 pin controller driver"
56 depends on ARCH_MMP
57 select PINCTRL_PXA3xx
58 select PINCONF
59
60 config PINCTRL_SIRF
61 bool "CSR SiRFprimaII pin controller driver"
62 depends on ARCH_PRIMA2
63 select PINMUX
64
65 config PINCTRL_TEGRA
66 bool
67
68 config PINCTRL_TEGRA20
69 bool
70 select PINMUX
71 select PINCONF
72 select PINCTRL_TEGRA
73
74 config PINCTRL_TEGRA30
75 bool
76 select PINMUX
77 select PINCONF
78 select PINCTRL_TEGRA
79
80 config PINCTRL_U300
81 bool "U300 pin controller driver"
82 depends on ARCH_U300
83 select PINMUX
84 select GENERIC_PINCONF
85
86 config PINCTRL_COH901
87 bool "ST-Ericsson U300 COH 901 335/571 GPIO"
88 depends on GPIOLIB && ARCH_U300 && PINMUX_U300
89 help
90 Say yes here to support GPIO interface on ST-Ericsson U300.
91 The names of the two IP block variants supported are
92 COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
93 ports of 8 GPIO pins each.
94
95 endmenu
96
97 endif
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