drivers/pinctrl/freescale/pinctrl-imx.c

   1 /*
   2  * Core driver for the imx pin controller
   3  *
   4  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   5  * Copyright (C) 2012 Linaro Ltd.
   6  *
   7  * Author: Dong Aisheng <dong.aisheng@linaro.org>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  */
  14
  15 #include <linux/err.h>
  16 #include <linux/init.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/of_address.h>
  22 #include <linux/pinctrl/machine.h>
  23 #include <linux/pinctrl/pinconf.h>
  24 #include <linux/pinctrl/pinctrl.h>
  25 #include <linux/pinctrl/pinmux.h>
  26 #include <linux/slab.h>
  27
  28 #include "../core.h"
  29 #include "pinctrl-imx.h"
  30
  31 /* The bits in CONFIG cell defined in binding doc*/
  32 #define IMX_NO_PAD_CTL  0x80000000      /* no pin config need */
  33 #define IMX_PAD_SION 0x40000000         /* set SION */
  34
  35 /**
  36  * @dev: a pointer back to containing device
  37  * @base: the offset to the controller in virtual memory
  38  */
  39 struct imx_pinctrl {
  40         struct device *dev;
  41         struct pinctrl_dev *pctl;
  42         void __iomem *base;
  43         void __iomem *input_sel_base;
  44         const struct imx_pinctrl_soc_info *info;
  45 };
  46
  47 static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name(
  48                                 const struct imx_pinctrl_soc_info *info,
  49                                 const char *name)
  50 {
  51         const struct imx_pin_group *grp = NULL;
  52         int i;
  53
  54         for (i = 0; i < info->ngroups; i++) {
  55                 if (!strcmp(info->groups[i].name, name)) {
  56                         grp = &info->groups[i];
  57                         break;
  58                 }
  59         }
  60
  61         return grp;
  62 }
  63
  64 static int imx_get_groups_count(struct pinctrl_dev *pctldev)
  65 {
  66         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  67         const struct imx_pinctrl_soc_info *info = ipctl->info;
  68
  69         return info->ngroups;
  70 }
  71
  72 static const char *imx_get_group_name(struct pinctrl_dev *pctldev,
  73                                        unsigned selector)
  74 {
  75         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  76         const struct imx_pinctrl_soc_info *info = ipctl->info;
  77
  78         return info->groups[selector].name;
  79 }
  80
  81 static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
  82                                const unsigned **pins,
  83                                unsigned *npins)
  84 {
  85         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  86         const struct imx_pinctrl_soc_info *info = ipctl->info;
  87
  88         if (selector >= info->ngroups)
  89                 return -EINVAL;
  90
  91         *pins = info->groups[selector].pin_ids;
  92         *npins = info->groups[selector].npins;
  93
  94         return 0;
  95 }
  96
  97 static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
  98                    unsigned offset)
  99 {
 100         seq_printf(s, "%s", dev_name(pctldev->dev));
 101 }
 102
 103 static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
 104                         struct device_node *np,
 105                         struct pinctrl_map **map, unsigned *num_maps)
 106 {
 107         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 108         const struct imx_pinctrl_soc_info *info = ipctl->info;
 109         const struct imx_pin_group *grp;
 110         struct pinctrl_map *new_map;
 111         struct device_node *parent;
 112         int map_num = 1;
 113         int i, j;
 114
 115         /*
 116          * first find the group of this node and check if we need create
 117          * config maps for pins
 118          */
 119         grp = imx_pinctrl_find_group_by_name(info, np->name);
 120         if (!grp) {
 121                 dev_err(info->dev, "unable to find group for node %s\n",
 122                         np->name);
 123                 return -EINVAL;
 124         }
 125
 126         for (i = 0; i < grp->npins; i++) {
 127                 if (!(grp->pins[i].config & IMX_NO_PAD_CTL))
 128                         map_num++;
 129         }
 130
 131         new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
 132         if (!new_map)
 133                 return -ENOMEM;
 134
 135         *map = new_map;
 136         *num_maps = map_num;
 137
 138         /* create mux map */
 139         parent = of_get_parent(np);
 140         if (!parent) {
 141                 kfree(new_map);
 142                 return -EINVAL;
 143         }
 144         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 145         new_map[0].data.mux.function = parent->name;
 146         new_map[0].data.mux.group = np->name;
 147         of_node_put(parent);
 148
 149         /* create config map */
 150         new_map++;
 151         for (i = j = 0; i < grp->npins; i++) {
 152                 if (!(grp->pins[i].config & IMX_NO_PAD_CTL)) {
 153                         new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
 154                         new_map[j].data.configs.group_or_pin =
 155                                         pin_get_name(pctldev, grp->pins[i].pin);
 156                         new_map[j].data.configs.configs = &grp->pins[i].config;
 157                         new_map[j].data.configs.num_configs = 1;
 158                         j++;
 159                 }
 160         }
 161
 162         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 163                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 164
 165         return 0;
 166 }
 167
 168 static void imx_dt_free_map(struct pinctrl_dev *pctldev,
 169                                 struct pinctrl_map *map, unsigned num_maps)
 170 {
 171         kfree(map);
 172 }
 173
 174 static const struct pinctrl_ops imx_pctrl_ops = {
 175         .get_groups_count = imx_get_groups_count,
 176         .get_group_name = imx_get_group_name,
 177         .get_group_pins = imx_get_group_pins,
 178         .pin_dbg_show = imx_pin_dbg_show,
 179         .dt_node_to_map = imx_dt_node_to_map,
 180         .dt_free_map = imx_dt_free_map,
 181
 182 };
 183
 184 static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
 185                        unsigned group)
 186 {
 187         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 188         const struct imx_pinctrl_soc_info *info = ipctl->info;
 189         const struct imx_pin_reg *pin_reg;
 190         unsigned int npins, pin_id;
 191         int i;
 192         struct imx_pin_group *grp;
 193
 194         /*
 195          * Configure the mux mode for each pin in the group for a specific
 196          * function.
 197          */
 198         grp = &info->groups[group];
 199         npins = grp->npins;
 200
 201         dev_dbg(ipctl->dev, "enable function %s group %s\n",
 202                 info->functions[selector].name, grp->name);
 203
 204         for (i = 0; i < npins; i++) {
 205                 struct imx_pin *pin = &grp->pins[i];
 206                 pin_id = pin->pin;
 207                 pin_reg = &info->pin_regs[pin_id];
 208
 209                 if (pin_reg->mux_reg == -1) {
 210                         dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
 211                                 info->pins[pin_id].name);
 212                         return -EINVAL;
 213                 }
 214
 215                 if (info->flags & SHARE_MUX_CONF_REG) {
 216                         u32 reg;
 217                         reg = readl(ipctl->base + pin_reg->mux_reg);
 218                         reg &= ~(0x7 << 20);
 219                         reg |= (pin->mux_mode << 20);
 220                         writel(reg, ipctl->base + pin_reg->mux_reg);
 221                 } else {
 222                         writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
 223                 }
 224                 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
 225                         pin_reg->mux_reg, pin->mux_mode);
 226
 227                 /*
 228                  * If the select input value begins with 0xff, it's a quirky
 229                  * select input and the value should be interpreted as below.
 230                  *     31     23      15      7        0
 231                  *     | 0xff | shift | width | select |
 232                  * It's used to work around the problem that the select
 233                  * input for some pin is not implemented in the select
 234                  * input register but in some general purpose register.
 235                  * We encode the select input value, width and shift of
 236                  * the bit field into input_val cell of pin function ID
 237                  * in device tree, and then decode them here for setting
 238                  * up the select input bits in general purpose register.
 239                  */
 240                 if (pin->input_val >> 24 == 0xff) {
 241                         u32 val = pin->input_val;
 242                         u8 select = val & 0xff;
 243                         u8 width = (val >> 8) & 0xff;
 244                         u8 shift = (val >> 16) & 0xff;
 245                         u32 mask = ((1 << width) - 1) << shift;
 246                         /*
 247                          * The input_reg[i] here is actually some IOMUXC general
 248                          * purpose register, not regular select input register.
 249                          */
 250                         val = readl(ipctl->base + pin->input_reg);
 251                         val &= ~mask;
 252                         val |= select << shift;
 253                         writel(val, ipctl->base + pin->input_reg);
 254                 } else if (pin->input_reg) {
 255                         /*
 256                          * Regular select input register can never be at offset
 257                          * 0, and we only print register value for regular case.
 258                          */
 259                         if (ipctl->input_sel_base)
 260                                 writel(pin->input_val, ipctl->input_sel_base +
 261                                                 pin->input_reg);
 262                         else
 263                                 writel(pin->input_val, ipctl->base +
 264                                                 pin->input_reg);
 265                         dev_dbg(ipctl->dev,
 266                                 "==>select_input: offset 0x%x val 0x%x\n",
 267                                 pin->input_reg, pin->input_val);
 268                 }
 269         }
 270
 271         return 0;
 272 }
 273
 274 static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 275 {
 276         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 277         const struct imx_pinctrl_soc_info *info = ipctl->info;
 278
 279         return info->nfunctions;
 280 }
 281
 282 static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev,
 283                                           unsigned selector)
 284 {
 285         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 286         const struct imx_pinctrl_soc_info *info = ipctl->info;
 287
 288         return info->functions[selector].name;
 289 }
 290
 291 static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
 292                                const char * const **groups,
 293                                unsigned * const num_groups)
 294 {
 295         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 296         const struct imx_pinctrl_soc_info *info = ipctl->info;
 297
 298         *groups = info->functions[selector].groups;
 299         *num_groups = info->functions[selector].num_groups;
 300
 301         return 0;
 302 }
 303
 304 static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
 305                         struct pinctrl_gpio_range *range, unsigned offset)
 306 {
 307         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 308         const struct imx_pinctrl_soc_info *info = ipctl->info;
 309         const struct imx_pin_reg *pin_reg;
 310         struct imx_pin_group *grp;
 311         struct imx_pin *imx_pin;
 312         unsigned int pin, group;
 313         u32 reg;
 314
 315         /* Currently implementation only for shared mux/conf register */
 316         if (!(info->flags & SHARE_MUX_CONF_REG))
 317                 return -EINVAL;
 318
 319         pin_reg = &info->pin_regs[offset];
 320         if (pin_reg->mux_reg == -1)
 321                 return -EINVAL;
 322
 323         /* Find the pinctrl config with GPIO mux mode for the requested pin */
 324         for (group = 0; group < info->ngroups; group++) {
 325                 grp = &info->groups[group];
 326                 for (pin = 0; pin < grp->npins; pin++) {
 327                         imx_pin = &grp->pins[pin];
 328                         if (imx_pin->pin == offset && !imx_pin->mux_mode)
 329                                 goto mux_pin;
 330                 }
 331         }
 332
 333         return -EINVAL;
 334
 335 mux_pin:
 336         reg = readl(ipctl->base + pin_reg->mux_reg);
 337         reg &= ~(0x7 << 20);
 338         reg |= imx_pin->config;
 339         writel(reg, ipctl->base + pin_reg->mux_reg);
 340
 341         return 0;
 342 }
 343
 344 static void imx_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
 345                         struct pinctrl_gpio_range *range, unsigned offset)
 346 {
 347         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 348         const struct imx_pinctrl_soc_info *info = ipctl->info;
 349         const struct imx_pin_reg *pin_reg;
 350         u32 reg;
 351
 352         /*
 353          * Only Vybrid has the input/output buffer enable flags (IBE/OBE)
 354          * They are part of the shared mux/conf register.
 355          */
 356         if (!(info->flags & SHARE_MUX_CONF_REG))
 357                 return;
 358
 359         pin_reg = &info->pin_regs[offset];
 360         if (pin_reg->mux_reg == -1)
 361                 return;
 362
 363         /* Clear IBE/OBE/PUE to disable the pin (Hi-Z) */
 364         reg = readl(ipctl->base + pin_reg->mux_reg);
 365         reg &= ~0x7;
 366         writel(reg, ipctl->base + pin_reg->mux_reg);
 367 }
 368
 369 static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 370            struct pinctrl_gpio_range *range, unsigned offset, bool input)
 371 {
 372         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 373         const struct imx_pinctrl_soc_info *info = ipctl->info;
 374         const struct imx_pin_reg *pin_reg;
 375         u32 reg;
 376
 377         /*
 378          * Only Vybrid has the input/output buffer enable flags (IBE/OBE)
 379          * They are part of the shared mux/conf register.
 380          */
 381         if (!(info->flags & SHARE_MUX_CONF_REG))
 382                 return -EINVAL;
 383
 384         pin_reg = &info->pin_regs[offset];
 385         if (pin_reg->mux_reg == -1)
 386                 return -EINVAL;
 387
 388         /* IBE always enabled allows us to read the value "on the wire" */
 389         reg = readl(ipctl->base + pin_reg->mux_reg);
 390         if (input)
 391                 reg &= ~0x2;
 392         else
 393                 reg |= 0x2;
 394         writel(reg, ipctl->base + pin_reg->mux_reg);
 395
 396         return 0;
 397 }
 398
 399 static const struct pinmux_ops imx_pmx_ops = {
 400         .get_functions_count = imx_pmx_get_funcs_count,
 401         .get_function_name = imx_pmx_get_func_name,
 402         .get_function_groups = imx_pmx_get_groups,
 403         .set_mux = imx_pmx_set,
 404         .gpio_request_enable = imx_pmx_gpio_request_enable,
 405         .gpio_disable_free = imx_pmx_gpio_disable_free,
 406         .gpio_set_direction = imx_pmx_gpio_set_direction,
 407 };
 408
 409 static int imx_pinconf_get(struct pinctrl_dev *pctldev,
 410                              unsigned pin_id, unsigned long *config)
 411 {
 412         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 413         const struct imx_pinctrl_soc_info *info = ipctl->info;
 414         const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
 415
 416         if (pin_reg->conf_reg == -1) {
 417                 dev_err(info->dev, "Pin(%s) does not support config function\n",
 418                         info->pins[pin_id].name);
 419                 return -EINVAL;
 420         }
 421
 422         *config = readl(ipctl->base + pin_reg->conf_reg);
 423
 424         if (info->flags & SHARE_MUX_CONF_REG)
 425                 *config &= 0xffff;
 426
 427         return 0;
 428 }
 429
 430 static int imx_pinconf_set(struct pinctrl_dev *pctldev,
 431                              unsigned pin_id, unsigned long *configs,
 432                              unsigned num_configs)
 433 {
 434         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 435         const struct imx_pinctrl_soc_info *info = ipctl->info;
 436         const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
 437         int i;
 438
 439         if (pin_reg->conf_reg == -1) {
 440                 dev_err(info->dev, "Pin(%s) does not support config function\n",
 441                         info->pins[pin_id].name);
 442                 return -EINVAL;
 443         }
 444
 445         dev_dbg(ipctl->dev, "pinconf set pin %s\n",
 446                 info->pins[pin_id].name);
 447
 448         for (i = 0; i < num_configs; i++) {
 449                 if (info->flags & SHARE_MUX_CONF_REG) {
 450                         u32 reg;
 451                         reg = readl(ipctl->base + pin_reg->conf_reg);
 452                         reg &= ~0xffff;
 453                         reg |= configs[i];
 454                         writel(reg, ipctl->base + pin_reg->conf_reg);
 455                 } else {
 456                         writel(configs[i], ipctl->base + pin_reg->conf_reg);
 457                 }
 458                 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
 459                         pin_reg->conf_reg, configs[i]);
 460         } /* for each config */
 461
 462         return 0;
 463 }
 464
 465 static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 466                                    struct seq_file *s, unsigned pin_id)
 467 {
 468         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 469         const struct imx_pinctrl_soc_info *info = ipctl->info;
 470         const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
 471         unsigned long config;
 472
 473         if (!pin_reg || pin_reg->conf_reg == -1) {
 474                 seq_printf(s, "N/A");
 475                 return;
 476         }
 477
 478         config = readl(ipctl->base + pin_reg->conf_reg);
 479         seq_printf(s, "0x%lx", config);
 480 }
 481
 482 static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 483                                          struct seq_file *s, unsigned group)
 484 {
 485         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 486         const struct imx_pinctrl_soc_info *info = ipctl->info;
 487         struct imx_pin_group *grp;
 488         unsigned long config;
 489         const char *name;
 490         int i, ret;
 491
 492         if (group > info->ngroups)
 493                 return;
 494
 495         seq_printf(s, "\n");
 496         grp = &info->groups[group];
 497         for (i = 0; i < grp->npins; i++) {
 498                 struct imx_pin *pin = &grp->pins[i];
 499                 name = pin_get_name(pctldev, pin->pin);
 500                 ret = imx_pinconf_get(pctldev, pin->pin, &config);
 501                 if (ret)
 502                         return;
 503                 seq_printf(s, "%s: 0x%lx", name, config);
 504         }
 505 }
 506
 507 static const struct pinconf_ops imx_pinconf_ops = {
 508         .pin_config_get = imx_pinconf_get,
 509         .pin_config_set = imx_pinconf_set,
 510         .pin_config_dbg_show = imx_pinconf_dbg_show,
 511         .pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
 512 };
 513
 514 static struct pinctrl_desc imx_pinctrl_desc = {
 515         .pctlops = &imx_pctrl_ops,
 516         .pmxops = &imx_pmx_ops,
 517         .confops = &imx_pinconf_ops,
 518         .owner = THIS_MODULE,
 519 };
 520
 521 /*
 522  * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
 523  * 1 u32 CONFIG, so 24 types in total for each pin.
 524  */
 525 #define FSL_PIN_SIZE 24
 526 #define SHARE_FSL_PIN_SIZE 20
 527
 528 static int imx_pinctrl_parse_groups(struct device_node *np,
 529                                     struct imx_pin_group *grp,
 530                                     struct imx_pinctrl_soc_info *info,
 531                                     u32 index)
 532 {
 533         int size, pin_size;
 534         const __be32 *list;
 535         int i;
 536         u32 config;
 537
 538         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
 539
 540         if (info->flags & SHARE_MUX_CONF_REG)
 541                 pin_size = SHARE_FSL_PIN_SIZE;
 542         else
 543                 pin_size = FSL_PIN_SIZE;
 544         /* Initialise group */
 545         grp->name = np->name;
 546
 547         /*
 548          * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
 549          * do sanity check and calculate pins number
 550          */
 551         list = of_get_property(np, "fsl,pins", &size);
 552         if (!list) {
 553                 dev_err(info->dev, "no fsl,pins property in node %s\n", np->full_name);
 554                 return -EINVAL;
 555         }
 556
 557         /* we do not check return since it's safe node passed down */
 558         if (!size || size % pin_size) {
 559                 dev_err(info->dev, "Invalid fsl,pins property in node %s\n", np->full_name);
 560                 return -EINVAL;
 561         }
 562
 563         grp->npins = size / pin_size;
 564         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(struct imx_pin),
 565                                 GFP_KERNEL);
 566         grp->pin_ids = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
 567                                 GFP_KERNEL);
 568         if (!grp->pins || ! grp->pin_ids)
 569                 return -ENOMEM;
 570
 571         for (i = 0; i < grp->npins; i++) {
 572                 u32 mux_reg = be32_to_cpu(*list++);
 573                 u32 conf_reg;
 574                 unsigned int pin_id;
 575                 struct imx_pin_reg *pin_reg;
 576                 struct imx_pin *pin = &grp->pins[i];
 577
 578                 if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
 579                         mux_reg = -1;
 580
 581                 if (info->flags & SHARE_MUX_CONF_REG) {
 582                         conf_reg = mux_reg;
 583                 } else {
 584                         conf_reg = be32_to_cpu(*list++);
 585                         if (!conf_reg)
 586                                 conf_reg = -1;
 587                 }
 588
 589                 pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
 590                 pin_reg = &info->pin_regs[pin_id];
 591                 pin->pin = pin_id;
 592                 grp->pin_ids[i] = pin_id;
 593                 pin_reg->mux_reg = mux_reg;
 594                 pin_reg->conf_reg = conf_reg;
 595                 pin->input_reg = be32_to_cpu(*list++);
 596                 pin->mux_mode = be32_to_cpu(*list++);
 597                 pin->input_val = be32_to_cpu(*list++);
 598
 599                 /* SION bit is in mux register */
 600                 config = be32_to_cpu(*list++);
 601                 if (config & IMX_PAD_SION)
 602                         pin->mux_mode |= IOMUXC_CONFIG_SION;
 603                 pin->config = config & ~IMX_PAD_SION;
 604
 605                 dev_dbg(info->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name,
 606                                 pin->mux_mode, pin->config);
 607         }
 608
 609         return 0;
 610 }
 611
 612 static int imx_pinctrl_parse_functions(struct device_node *np,
 613                                        struct imx_pinctrl_soc_info *info,
 614                                        u32 index)
 615 {
 616         struct device_node *child;
 617         struct imx_pmx_func *func;
 618         struct imx_pin_group *grp;
 619         u32 i = 0;
 620
 621         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
 622
 623         func = &info->functions[index];
 624
 625         /* Initialise function */
 626         func->name = np->name;
 627         func->num_groups = of_get_child_count(np);
 628         if (func->num_groups == 0) {
 629                 dev_err(info->dev, "no groups defined in %s\n", np->full_name);
 630                 return -EINVAL;
 631         }
 632         func->groups = devm_kzalloc(info->dev,
 633                         func->num_groups * sizeof(char *), GFP_KERNEL);
 634
 635         for_each_child_of_node(np, child) {
 636                 func->groups[i] = child->name;
 637                 grp = &info->groups[info->group_index++];
 638                 imx_pinctrl_parse_groups(child, grp, info, i++);
 639         }
 640
 641         return 0;
 642 }
 643
 644 /*
 645  * Check if the DT contains pins in the direct child nodes. This indicates the
 646  * newer DT format to store pins. This function returns true if the first found
 647  * fsl,pins property is in a child of np. Otherwise false is returned.
 648  */
 649 static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np)
 650 {
 651         struct device_node *function_np;
 652         struct device_node *pinctrl_np;
 653
 654         for_each_child_of_node(np, function_np) {
 655                 if (of_property_read_bool(function_np, "fsl,pins"))
 656                         return true;
 657
 658                 for_each_child_of_node(function_np, pinctrl_np) {
 659                         if (of_property_read_bool(pinctrl_np, "fsl,pins"))
 660                                 return false;
 661                 }
 662         }
 663
 664         return true;
 665 }
 666
 667 static int imx_pinctrl_probe_dt(struct platform_device *pdev,
 668                                 struct imx_pinctrl_soc_info *info)
 669 {
 670         struct device_node *np = pdev->dev.of_node;
 671         struct device_node *child;
 672         u32 nfuncs = 0;
 673         u32 i = 0;
 674         bool flat_funcs;
 675
 676         if (!np)
 677                 return -ENODEV;
 678
 679         flat_funcs = imx_pinctrl_dt_is_flat_functions(np);
 680         if (flat_funcs) {
 681                 nfuncs = 1;
 682         } else {
 683                 nfuncs = of_get_child_count(np);
 684                 if (nfuncs <= 0) {
 685                         dev_err(&pdev->dev, "no functions defined\n");
 686                         return -EINVAL;
 687                 }
 688         }
 689
 690         info->nfunctions = nfuncs;
 691         info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func),
 692                                         GFP_KERNEL);
 693         if (!info->functions)
 694                 return -ENOMEM;
 695
 696         if (flat_funcs) {
 697                 info->ngroups = of_get_child_count(np);
 698         } else {
 699                 info->ngroups = 0;
 700                 for_each_child_of_node(np, child)
 701                         info->ngroups += of_get_child_count(child);
 702         }
 703         info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group),
 704                                         GFP_KERNEL);
 705         if (!info->groups)
 706                 return -ENOMEM;
 707
 708         if (flat_funcs) {
 709                 imx_pinctrl_parse_functions(np, info, 0);
 710         } else {
 711                 for_each_child_of_node(np, child)
 712                         imx_pinctrl_parse_functions(child, info, i++);
 713         }
 714
 715         return 0;
 716 }
 717
 718 int imx_pinctrl_probe(struct platform_device *pdev,
 719                       struct imx_pinctrl_soc_info *info)
 720 {
 721         struct device_node *dev_np = pdev->dev.of_node;
 722         struct device_node *np;
 723         struct imx_pinctrl *ipctl;
 724         struct resource *res;
 725         int ret, i;
 726
 727         if (!info || !info->pins || !info->npins) {
 728                 dev_err(&pdev->dev, "wrong pinctrl info\n");
 729                 return -EINVAL;
 730         }
 731         info->dev = &pdev->dev;
 732
 733         /* Create state holders etc for this driver */
 734         ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
 735         if (!ipctl)
 736                 return -ENOMEM;
 737
 738         info->pin_regs = devm_kmalloc(&pdev->dev, sizeof(*info->pin_regs) *
 739                                       info->npins, GFP_KERNEL);
 740         if (!info->pin_regs)
 741                 return -ENOMEM;
 742
 743         for (i = 0; i < info->npins; i++) {
 744                 info->pin_regs[i].mux_reg = -1;
 745                 info->pin_regs[i].conf_reg = -1;
 746         }
 747
 748         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 749         ipctl->base = devm_ioremap_resource(&pdev->dev, res);
 750         if (IS_ERR(ipctl->base))
 751                 return PTR_ERR(ipctl->base);
 752
 753         if (of_property_read_bool(dev_np, "fsl,input-sel")) {
 754                 np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
 755                 if (np) {
 756                         ipctl->input_sel_base = of_iomap(np, 0);
 757                         if (IS_ERR(ipctl->input_sel_base)) {
 758                                 of_node_put(np);
 759                                 dev_err(&pdev->dev,
 760                                         "iomuxc input select base address not found\n");
 761                                 return PTR_ERR(ipctl->input_sel_base);
 762                         }
 763                 } else {
 764                         dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
 765                         return -EINVAL;
 766                 }
 767                 of_node_put(np);
 768         }
 769
 770         imx_pinctrl_desc.name = dev_name(&pdev->dev);
 771         imx_pinctrl_desc.pins = info->pins;
 772         imx_pinctrl_desc.npins = info->npins;
 773
 774         ret = imx_pinctrl_probe_dt(pdev, info);
 775         if (ret) {
 776                 dev_err(&pdev->dev, "fail to probe dt properties\n");
 777                 return ret;
 778         }
 779
 780         ipctl->info = info;
 781         ipctl->dev = info->dev;
 782         platform_set_drvdata(pdev, ipctl);
 783         ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl);
 784         if (IS_ERR(ipctl->pctl)) {
 785                 dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
 786                 return PTR_ERR(ipctl->pctl);
 787         }
 788
 789         dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
 790
 791         return 0;
 792 }
 793
 794 int imx_pinctrl_remove(struct platform_device *pdev)
 795 {
 796         struct imx_pinctrl *ipctl = platform_get_drvdata(pdev);
 797
 798         pinctrl_unregister(ipctl->pctl);
 799
 800         return 0;
 801 }