drivers/pinctrl/pinctrl-abx500.h

   1 #ifndef PINCTRL_PINCTRL_ABx500_H
   2 #define PINCTRL_PINCTRL_ABx500_H
   3
   4 /* Package definitions */
   5 #define PINCTRL_AB8500  0
   6 #define PINCTRL_AB8540  1
   7 #define PINCTRL_AB9540  2
   8 #define PINCTRL_AB8505  3
   9
  10 /* pins alternate function */
  11 enum abx500_pin_func {
  12         ABX500_DEFAULT,
  13         ABX500_ALT_A,
  14         ABX500_ALT_B,
  15         ABX500_ALT_C,
  16 };
  17
  18 enum abx500_gpio_pull_updown {
  19         ABX500_GPIO_PULL_DOWN = 0x0,
  20         ABX500_GPIO_PULL_NONE = 0x1,
  21         ABX500_GPIO_PULL_UP = 0x3,
  22 };
  23
  24 enum abx500_gpio_vinsel {
  25         ABX500_GPIO_VINSEL_VBAT = 0x0,
  26         ABX500_GPIO_VINSEL_VIN_1V8 = 0x1,
  27         ABX500_GPIO_VINSEL_VDD_BIF = 0x2,
  28 };
  29
  30 /**
  31  * struct abx500_function - ABx500 pinctrl mux function
  32  * @name: The name of the function, exported to pinctrl core.
  33  * @groups: An array of pin groups that may select this function.
  34  * @ngroups: The number of entries in @groups.
  35  */
  36 struct abx500_function {
  37         const char *name;
  38         const char * const *groups;
  39         unsigned ngroups;
  40 };
  41
  42 /**
  43  * struct abx500_pingroup - describes a ABx500 pin group
  44  * @name: the name of this specific pin group
  45  * @pins: an array of discrete physical pins used in this group, taken
  46  *      from the driver-local pin enumeration space
  47  * @num_pins: the number of pins in this group array, i.e. the number of
  48  *      elements in .pins so we can iterate over that array
  49  * @altsetting: the altsetting to apply to all pins in this group to
  50  *      configure them to be used by a function
  51  */
  52 struct abx500_pingroup {
  53         const char *name;
  54         const unsigned int *pins;
  55         const unsigned npins;
  56         int altsetting;
  57 };
  58
  59 #define ALTERNATE_FUNCTIONS(pin, sel_bit, alt1, alt2, alta, altb, altc) \
  60 {                                                                       \
  61         .pin_number = pin,                                              \
  62         .gpiosel_bit = sel_bit,                                         \
  63         .alt_bit1 = alt1,                                               \
  64         .alt_bit2 = alt2,                                               \
  65         .alta_val = alta,                                               \
  66         .altb_val = altb,                                               \
  67         .altc_val = altc,                                               \
  68 }
  69
  70 #define UNUSED -1
  71 /**
  72  * struct alternate_functions
  73  * @pin_number:         The pin number
  74  * @gpiosel_bit:        Control bit in GPIOSEL register,
  75  * @alt_bit1:           First AlternateFunction bit used to select the
  76  *                      alternate function
  77  * @alt_bit2:           Second AlternateFunction bit used to select the
  78  *                      alternate function
  79  *
  80  *                      these 3 following fields are necessary due to none
  81  *                      coherency on how to select the altA, altB and altC
  82  *                      function between the ABx500 SOC family when using
  83  *                      alternatfunc register.
  84  * @alta_val:           value to write in alternatfunc to select altA function
  85  * @altb_val:           value to write in alternatfunc to select altB function
  86  * @altc_val:           value to write in alternatfunc to select altC function
  87  */
  88 struct alternate_functions {
  89         unsigned pin_number;
  90         s8 gpiosel_bit;
  91         s8 alt_bit1;
  92         s8 alt_bit2;
  93         u8 alta_val;
  94         u8 altb_val;
  95         u8 altc_val;
  96 };
  97
  98 /**
  99  * struct pullud - specific pull up/down feature
 100  * @first_pin:          The pin number of the first pins which support
 101  *                      specific pull up/down
 102  * @last_pin:           The pin number of the last pins
 103  */
 104 struct pullud {
 105         unsigned first_pin;
 106         unsigned last_pin;
 107 };
 108
 109 #define GPIO_IRQ_CLUSTER(a, b, c)       \
 110 {                                       \
 111         .start = a,                     \
 112         .end = b,                       \
 113         .to_irq = c,                    \
 114 }
 115
 116 /**
 117  * struct abx500_gpio_irq_cluster - indicates GPIOs which are interrupt
 118  *                      capable
 119  * @start:              The pin number of the first pin interrupt capable
 120  * @end:                The pin number of the last pin interrupt capable
 121  * @to_irq:             The ABx500 GPIO's associated IRQs are clustered
 122  *                      together throughout the interrupt numbers at irregular
 123  *                      intervals. To solve this quandary, we will place the
 124  *                      read-in values into the cluster information table
 125  */
 126
 127 struct abx500_gpio_irq_cluster {
 128         int start;
 129         int end;
 130         int to_irq;
 131 };
 132
 133 /**
 134  * struct abx500_pinrange - map pin numbers to GPIO offsets
 135  * @offset:             offset into the GPIO local numberspace, incidentally
 136  *                      identical to the offset into the local pin numberspace
 137  * @npins:              number of pins to map from both offsets
 138  * @altfunc:            altfunc setting to be used to enable GPIO on a pin in
 139  *                      this range (may vary)
 140  */
 141 struct abx500_pinrange {
 142         unsigned int offset;
 143         unsigned int npins;
 144         int altfunc;
 145 };
 146
 147 #define ABX500_PINRANGE(a, b, c) { .offset = a, .npins = b, .altfunc = c }
 148
 149 /**
 150  * struct abx500_pinctrl_soc_data - ABx500 pin controller per-SoC configuration
 151  * @gpio_ranges:        An array of GPIO ranges for this SoC
 152  * @gpio_num_ranges:    The number of GPIO ranges for this SoC
 153  * @pins:               An array describing all pins the pin controller affects.
 154  *                      All pins which are also GPIOs must be listed first within the
 155  *                      array, and be numbered identically to the GPIO controller's
 156  *                      numbering.
 157  * @npins:              The number of entries in @pins.
 158  * @functions:          The functions supported on this SoC.
 159  * @nfunction:          The number of entries in @functions.
 160  * @groups:             An array describing all pin groups the pin SoC supports.
 161  * @ngroups:            The number of entries in @groups.
 162  * @alternate_functions: array describing pins which supports alternate and
 163  *                      how to set it.
 164  * @pullud:             array describing pins which supports pull up/down
 165  *                      specific registers.
 166  * @gpio_irq_cluster:   An array of GPIO interrupt capable for this SoC
 167  * @ngpio_irq_cluster:  The number of GPIO inetrrupt capable for this SoC
 168  * @irq_gpio_rising_offset: Interrupt offset used as base to compute specific
 169  *                      setting strategy of the rising interrupt line
 170  * @irq_gpio_falling_offset: Interrupt offset used as base to compute specific
 171  *                      setting strategy of the falling interrupt line
 172  * @irq_gpio_factor:    Factor used to compute specific setting strategy of
 173  *                      the interrupt line
 174  */
 175
 176 struct abx500_pinctrl_soc_data {
 177         const struct abx500_pinrange *gpio_ranges;
 178         unsigned gpio_num_ranges;
 179         const struct pinctrl_pin_desc *pins;
 180         unsigned npins;
 181         const struct abx500_function *functions;
 182         unsigned nfunctions;
 183         const struct abx500_pingroup *groups;
 184         unsigned ngroups;
 185         struct alternate_functions *alternate_functions;
 186         struct pullud *pullud;
 187         struct abx500_gpio_irq_cluster *gpio_irq_cluster;
 188         unsigned ngpio_irq_cluster;
 189         int irq_gpio_rising_offset;
 190         int irq_gpio_falling_offset;
 191         int irq_gpio_factor;
 192 };
 193
 194 #ifdef CONFIG_PINCTRL_AB8500
 195
 196 void abx500_pinctrl_ab8500_init(struct abx500_pinctrl_soc_data **soc);
 197
 198 #else
 199
 200 static inline void
 201 abx500_pinctrl_ab8500_init(struct abx500_pinctrl_soc_data **soc)
 202 {
 203 }
 204
 205 #endif
 206
 207 #ifdef CONFIG_PINCTRL_AB8540
 208
 209 void abx500_pinctrl_ab8540_init(struct abx500_pinctrl_soc_data **soc);
 210
 211 #else
 212
 213 static inline void
 214 abx500_pinctrl_ab8540_init(struct abx500_pinctrl_soc_data **soc)
 215 {
 216 }
 217
 218 #endif
 219
 220 #ifdef CONFIG_PINCTRL_AB9540
 221
 222 void abx500_pinctrl_ab9540_init(struct abx500_pinctrl_soc_data **soc);
 223
 224 #else
 225
 226 static inline void
 227 abx500_pinctrl_ab9540_init(struct abx500_pinctrl_soc_data **soc)
 228 {
 229 }
 230
 231 #endif
 232
 233 #ifdef CONFIG_PINCTRL_AB8505
 234
 235 void abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data **soc);
 236
 237 #else
 238
 239 static inline void
 240 abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data **soc)
 241 {
 242 }
 243
 244 #endif
 245
 246 #endif /* PINCTRL_PINCTRL_ABx500_H */