2 * Pinctrl Driver for ADI GPIO2 controller
4 * Copyright 2007-2013 Analog Devices Inc.
6 * Licensed under the GPLv2 or later
9 #include <linux/bitops.h>
10 #include <linux/delay.h>
11 #include <linux/module.h>
12 #include <linux/err.h>
13 #include <linux/debugfs.h>
14 #include <linux/seq_file.h>
15 #include <linux/irq.h>
16 #include <linux/platform_data/pinctrl-adi2.h>
17 #include <linux/irqdomain.h>
18 #include <linux/irqchip/chained_irq.h>
19 #include <linux/pinctrl/pinctrl.h>
20 #include <linux/pinctrl/pinmux.h>
21 #include <linux/pinctrl/consumer.h>
22 #include <linux/pinctrl/machine.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/gpio.h>
25 #include <asm/portmux.h>
26 #include "pinctrl-adi2.h"
30 According to the BF54x HRM, pint means "pin interrupt".
31 http://www.analog.com/static/imported-files/processor_manuals/ADSP-BF54x_hwr_rev1.2.pdf
33 ADSP-BF54x processor Blackfin processors have four SIC interrupt chan-
34 nels dedicated to pin interrupt purposes. These channels are managed by
35 four hardware blocks, called PINT0, PINT1, PINT2, and PINT3. Every PINTx
36 block can sense to up to 32 pins. While PINT0 and PINT1 can sense the
37 pins of port A and port B, PINT2 and PINT3 manage all the pins from port
38 C to port J as shown in Figure 9-2.
41 The ten GPIO ports are subdivided into 8-bit half ports, resulting in lower and
42 upper half 8-bit units. The PINTx_ASSIGN registers control the 8-bit multi-
43 plexers shown in Figure 9-3. Lower half units of eight pins can be
44 forwarded to either byte 0 or byte 2 of either associated PINTx block.
45 Upper half units can be forwarded to either byte 1 or byte 3 of the pin
46 interrupt blocks, without further restrictions.
48 All MMR registers in the pin interrupt module are 32 bits wide. To simply the
49 mapping logic, this driver only maps a 16-bit gpio port to the upper or lower
50 16 bits of a PINTx block. You can find the Figure 9-3 on page 583.
52 Each IRQ domain is binding to a GPIO bank device. 2 GPIO bank devices can map
53 to one PINT device. Two in "struct gpio_pint" are used to ease the PINT
56 The GPIO bank mapping to the lower 16 bits of the PINT device set its IRQ
57 domain pointer in domain[0]. The IRQ domain pointer of the other bank is set
58 to domain[1]. PINT interrupt handler adi_gpio_handle_pint_irq() finds out
59 the current domain pointer according to whether the interrupt request mask
60 is in lower 16 bits (domain[0]) or upper 16bits (domain[1]).
62 A PINT device is not part of a GPIO port device in Blackfin. Multiple GPIO
63 port devices can be mapped to the same PINT device.
67 static LIST_HEAD(adi_pint_list
);
68 static LIST_HEAD(adi_gpio_port_list
);
70 #define DRIVER_NAME "pinctrl-adi2"
72 #define PINT_HI_OFFSET 16
75 * struct gpio_port_saved - GPIO port registers that should be saved between
76 * power suspend and resume operations.
78 * @fer: PORTx_FER register
79 * @data: PORTx_DATA register
80 * @dir: PORTx_DIR register
81 * @inen: PORTx_INEN register
82 * @mux: PORTx_MUX register
84 struct gpio_port_saved
{
93 * struct gpio_pint_saved - PINT registers saved in PM operations
95 * @assign: ASSIGN register
96 * @edge_set: EDGE_SET register
97 * @invert_set: INVERT_SET register
99 struct gpio_pint_saved
{
106 * struct gpio_pint - Pin interrupt controller device. Multiple ADI GPIO
107 * banks can be mapped into one Pin interrupt controller.
109 * @node: All gpio_pint instances are added to a global list.
110 * @base: PINT device register base address
111 * @irq: IRQ of the PINT device, it is the parent IRQ of all
112 * GPIO IRQs mapping to this device.
113 * @domain: [0] irq domain of the gpio port, whose hardware interrupts are
114 * mapping to the low 16-bit of the pint registers.
115 * [1] irq domain of the gpio port, whose hardware interrupts are
116 * mapping to the high 16-bit of the pint registers.
117 * @regs: address pointer to the PINT device
118 * @map_count: No more than 2 GPIO banks can be mapped to this PINT device.
119 * @lock: This lock make sure the irq_chip operations to one PINT device
120 * for different GPIO interrrupts are atomic.
121 * @pint_map_port: Set up the mapping between one PINT device and
122 * multiple GPIO banks.
125 struct list_head node
;
128 struct irq_domain
*domain
[2];
129 struct gpio_pint_regs
*regs
;
130 struct gpio_pint_saved saved_data
;
134 int (*pint_map_port
)(struct gpio_pint
*pint
, bool assign
,
135 u8 map
, struct irq_domain
*domain
);
141 * @dev: a pointer back to containing device
142 * @pctl: the pinctrl device
143 * @soc: SoC data for this specific chip
147 struct pinctrl_dev
*pctl
;
148 const struct adi_pinctrl_soc_data
*soc
;
152 * struct gpio_port - GPIO bank device. Multiple ADI GPIO banks can be mapped
153 * into one pin interrupt controller.
155 * @node: All gpio_port instances are added to a list.
156 * @base: GPIO bank device register base address
157 * @irq_base: base IRQ of the GPIO bank device
158 * @width: PIN number of the GPIO bank device
159 * @regs: address pointer to the GPIO bank device
160 * @saved_data: registers that should be saved between PM operations.
161 * @dev: device structure of this GPIO bank
162 * @pint: GPIO PINT device that this GPIO bank mapped to
163 * @pint_map: GIOP bank mapping code in PINT device
164 * @pint_assign: The 32-bit PINT registers can be divided into 2 parts. A
165 * GPIO bank can be mapped into either low 16 bits[0] or high 16
166 * bits[1] of each PINT register.
167 * @lock: This lock make sure the irq_chip operations to one PINT device
168 * for different GPIO interrrupts are atomic.
169 * @chip: abstract a GPIO controller
170 * @domain: The irq domain owned by the GPIO port.
171 * @rsvmap: Reservation map array for each pin in the GPIO bank
174 struct list_head node
;
178 struct gpio_port_t
*regs
;
179 struct gpio_port_saved saved_data
;
182 struct gpio_pint
*pint
;
187 struct gpio_chip chip
;
188 struct irq_domain
*domain
;
191 static inline u8
pin_to_offset(struct pinctrl_gpio_range
*range
, unsigned pin
)
193 return pin
- range
->pin_base
;
196 static inline u32
hwirq_to_pintbit(struct gpio_port
*port
, int hwirq
)
198 return port
->pint_assign
? BIT(hwirq
) << PINT_HI_OFFSET
: BIT(hwirq
);
201 static struct gpio_pint
*find_gpio_pint(unsigned id
)
203 struct gpio_pint
*pint
;
206 list_for_each_entry(pint
, &adi_pint_list
, node
) {
215 static inline void port_setup(struct gpio_port
*port
, unsigned offset
,
218 struct gpio_port_t
*regs
= port
->regs
;
221 writew(readw(®s
->port_fer
) & ~BIT(offset
),
224 writew(readw(®s
->port_fer
) | BIT(offset
), ®s
->port_fer
);
227 static inline void portmux_setup(struct gpio_port
*port
, unsigned offset
,
228 unsigned short function
)
230 struct gpio_port_t
*regs
= port
->regs
;
233 pmux
= readl(®s
->port_mux
);
235 /* The function field of each pin has 2 consecutive bits in
238 pmux
&= ~(0x3 << (2 * offset
));
239 pmux
|= (function
& 0x3) << (2 * offset
);
241 writel(pmux
, ®s
->port_mux
);
244 static inline u16
get_portmux(struct gpio_port
*port
, unsigned offset
)
246 struct gpio_port_t
*regs
= port
->regs
;
247 u32 pmux
= readl(®s
->port_mux
);
249 /* The function field of each pin has 2 consecutive bits in
252 return pmux
>> (2 * offset
) & 0x3;
255 static void adi_gpio_ack_irq(struct irq_data
*d
)
258 struct gpio_port
*port
= irq_data_get_irq_chip_data(d
);
259 struct gpio_pint_regs
*regs
= port
->pint
->regs
;
260 unsigned pintbit
= hwirq_to_pintbit(port
, d
->hwirq
);
262 spin_lock_irqsave(&port
->lock
, flags
);
263 spin_lock(&port
->pint
->lock
);
265 if (irqd_get_trigger_type(d
) == IRQ_TYPE_EDGE_BOTH
) {
266 if (readl(®s
->invert_set
) & pintbit
)
267 writel(pintbit
, ®s
->invert_clear
);
269 writel(pintbit
, ®s
->invert_set
);
272 writel(pintbit
, ®s
->request
);
274 spin_unlock(&port
->pint
->lock
);
275 spin_unlock_irqrestore(&port
->lock
, flags
);
278 static void adi_gpio_mask_ack_irq(struct irq_data
*d
)
281 struct gpio_port
*port
= irq_data_get_irq_chip_data(d
);
282 struct gpio_pint_regs
*regs
= port
->pint
->regs
;
283 unsigned pintbit
= hwirq_to_pintbit(port
, d
->hwirq
);
285 spin_lock_irqsave(&port
->lock
, flags
);
286 spin_lock(&port
->pint
->lock
);
288 if (irqd_get_trigger_type(d
) == IRQ_TYPE_EDGE_BOTH
) {
289 if (readl(®s
->invert_set
) & pintbit
)
290 writel(pintbit
, ®s
->invert_clear
);
292 writel(pintbit
, ®s
->invert_set
);
295 writel(pintbit
, ®s
->request
);
296 writel(pintbit
, ®s
->mask_clear
);
298 spin_unlock(&port
->pint
->lock
);
299 spin_unlock_irqrestore(&port
->lock
, flags
);
302 static void adi_gpio_mask_irq(struct irq_data
*d
)
305 struct gpio_port
*port
= irq_data_get_irq_chip_data(d
);
306 struct gpio_pint_regs
*regs
= port
->pint
->regs
;
308 spin_lock_irqsave(&port
->lock
, flags
);
309 spin_lock(&port
->pint
->lock
);
311 writel(hwirq_to_pintbit(port
, d
->hwirq
), ®s
->mask_clear
);
313 spin_unlock(&port
->pint
->lock
);
314 spin_unlock_irqrestore(&port
->lock
, flags
);
317 static void adi_gpio_unmask_irq(struct irq_data
*d
)
320 struct gpio_port
*port
= irq_data_get_irq_chip_data(d
);
321 struct gpio_pint_regs
*regs
= port
->pint
->regs
;
323 spin_lock_irqsave(&port
->lock
, flags
);
324 spin_lock(&port
->pint
->lock
);
326 writel(hwirq_to_pintbit(port
, d
->hwirq
), ®s
->mask_set
);
328 spin_unlock(&port
->pint
->lock
);
329 spin_unlock_irqrestore(&port
->lock
, flags
);
332 static unsigned int adi_gpio_irq_startup(struct irq_data
*d
)
335 struct gpio_port
*port
= irq_data_get_irq_chip_data(d
);
336 struct gpio_pint_regs
*regs
;
339 pr_err("GPIO IRQ %d :Not exist\n", d
->irq
);
343 regs
= port
->pint
->regs
;
345 spin_lock_irqsave(&port
->lock
, flags
);
346 spin_lock(&port
->pint
->lock
);
348 port_setup(port
, d
->hwirq
, true);
349 writew(BIT(d
->hwirq
), &port
->regs
->dir_clear
);
350 writew(readw(&port
->regs
->inen
) | BIT(d
->hwirq
), &port
->regs
->inen
);
352 writel(hwirq_to_pintbit(port
, d
->hwirq
), ®s
->mask_set
);
354 spin_unlock(&port
->pint
->lock
);
355 spin_unlock_irqrestore(&port
->lock
, flags
);
360 static void adi_gpio_irq_shutdown(struct irq_data
*d
)
363 struct gpio_port
*port
= irq_data_get_irq_chip_data(d
);
364 struct gpio_pint_regs
*regs
= port
->pint
->regs
;
366 spin_lock_irqsave(&port
->lock
, flags
);
367 spin_lock(&port
->pint
->lock
);
369 writel(hwirq_to_pintbit(port
, d
->hwirq
), ®s
->mask_clear
);
371 spin_unlock(&port
->pint
->lock
);
372 spin_unlock_irqrestore(&port
->lock
, flags
);
375 static int adi_gpio_irq_type(struct irq_data
*d
, unsigned int type
)
378 struct gpio_port
*port
= irq_data_get_irq_chip_data(d
);
379 struct gpio_pint_regs
*pint_regs
;
381 unsigned int irq
= d
->irq
;
386 pr_err("GPIO IRQ %d :Not exist\n", d
->irq
);
390 pint_regs
= port
->pint
->regs
;
392 pintmask
= hwirq_to_pintbit(port
, d
->hwirq
);
394 spin_lock_irqsave(&port
->lock
, flags
);
395 spin_lock(&port
->pint
->lock
);
397 /* In case of interrupt autodetect, set irq type to edge sensitive. */
398 if (type
== IRQ_TYPE_PROBE
)
399 type
= IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
;
401 if (type
& (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
|
402 IRQ_TYPE_LEVEL_HIGH
| IRQ_TYPE_LEVEL_LOW
)) {
403 snprintf(buf
, 16, "gpio-irq%d", irq
);
404 port_setup(port
, d
->hwirq
, true);
408 /* The GPIO interrupt is triggered only when its input value
409 * transfer from 0 to 1. So, invert the input value if the
410 * irq type is low or falling
412 if ((type
& (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_LEVEL_LOW
)))
413 writel(pintmask
, &pint_regs
->invert_set
);
415 writel(pintmask
, &pint_regs
->invert_clear
);
417 /* In edge sensitive case, if the input value of the requested irq
418 * is already 1, invert it.
420 if ((type
& IRQ_TYPE_EDGE_BOTH
) == IRQ_TYPE_EDGE_BOTH
) {
421 if (gpio_get_value(port
->chip
.base
+ d
->hwirq
))
422 writel(pintmask
, &pint_regs
->invert_set
);
424 writel(pintmask
, &pint_regs
->invert_clear
);
427 if (type
& (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
)) {
428 writel(pintmask
, &pint_regs
->edge_set
);
429 __irq_set_handler_locked(irq
, handle_edge_irq
);
431 writel(pintmask
, &pint_regs
->edge_clear
);
432 __irq_set_handler_locked(irq
, handle_level_irq
);
436 spin_unlock(&port
->pint
->lock
);
437 spin_unlock_irqrestore(&port
->lock
, flags
);
443 static int adi_gpio_set_wake(struct irq_data
*d
, unsigned int state
)
445 struct gpio_port
*port
= irq_data_get_irq_chip_data(d
);
447 if (!port
|| !port
->pint
|| port
->pint
->irq
!= d
->irq
)
451 adi_internal_set_wake(port
->pint
->irq
, state
);
457 static int adi_pint_suspend(void)
459 struct gpio_pint
*pint
;
461 list_for_each_entry(pint
, &adi_pint_list
, node
) {
462 writel(0xffffffff, &pint
->regs
->mask_clear
);
463 pint
->saved_data
.assign
= readl(&pint
->regs
->assign
);
464 pint
->saved_data
.edge_set
= readl(&pint
->regs
->edge_set
);
465 pint
->saved_data
.invert_set
= readl(&pint
->regs
->invert_set
);
471 static void adi_pint_resume(void)
473 struct gpio_pint
*pint
;
475 list_for_each_entry(pint
, &adi_pint_list
, node
) {
476 writel(pint
->saved_data
.assign
, &pint
->regs
->assign
);
477 writel(pint
->saved_data
.edge_set
, &pint
->regs
->edge_set
);
478 writel(pint
->saved_data
.invert_set
, &pint
->regs
->invert_set
);
482 static int adi_gpio_suspend(void)
484 struct gpio_port
*port
;
486 list_for_each_entry(port
, &adi_gpio_port_list
, node
) {
487 port
->saved_data
.fer
= readw(&port
->regs
->port_fer
);
488 port
->saved_data
.mux
= readl(&port
->regs
->port_mux
);
489 port
->saved_data
.data
= readw(&port
->regs
->data
);
490 port
->saved_data
.inen
= readw(&port
->regs
->inen
);
491 port
->saved_data
.dir
= readw(&port
->regs
->dir_set
);
494 return adi_pint_suspend();
497 static void adi_gpio_resume(void)
499 struct gpio_port
*port
;
503 list_for_each_entry(port
, &adi_gpio_port_list
, node
) {
504 writel(port
->saved_data
.mux
, &port
->regs
->port_mux
);
505 writew(port
->saved_data
.fer
, &port
->regs
->port_fer
);
506 writew(port
->saved_data
.inen
, &port
->regs
->inen
);
507 writew(port
->saved_data
.data
& port
->saved_data
.dir
,
508 &port
->regs
->data_set
);
509 writew(port
->saved_data
.dir
, &port
->regs
->dir_set
);
514 static struct syscore_ops gpio_pm_syscore_ops
= {
515 .suspend
= adi_gpio_suspend
,
516 .resume
= adi_gpio_resume
,
518 #else /* CONFIG_PM */
519 #define adi_gpio_set_wake NULL
520 #endif /* CONFIG_PM */
522 #ifdef CONFIG_IRQ_PREFLOW_FASTEOI
523 static inline void preflow_handler(struct irq_desc
*desc
)
525 if (desc
->preflow_handler
)
526 desc
->preflow_handler(&desc
->irq_data
);
529 static inline void preflow_handler(struct irq_desc
*desc
) { }
532 static void adi_gpio_handle_pint_irq(unsigned int inta_irq
,
533 struct irq_desc
*desc
)
536 u32 level_mask
, hwirq
;
538 struct gpio_pint
*pint
= irq_desc_get_handler_data(desc
);
539 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
540 struct gpio_pint_regs
*regs
= pint
->regs
;
541 struct irq_domain
*domain
;
543 preflow_handler(desc
);
544 chained_irq_enter(chip
, desc
);
546 request
= readl(®s
->request
);
547 level_mask
= readl(®s
->edge_set
) & request
;
550 domain
= pint
->domain
[0];
552 /* domain pointer need to be changed only once at IRQ 16 when
553 * we go through IRQ requests from bit 0 to bit 31.
555 if (hwirq
== PINT_HI_OFFSET
)
556 domain
= pint
->domain
[1];
559 if (level_mask
& BIT(hwirq
)) {
561 chained_irq_exit(chip
, desc
);
563 generic_handle_irq(irq_find_mapping(domain
,
564 hwirq
% PINT_HI_OFFSET
));
572 chained_irq_exit(chip
, desc
);
575 static struct irq_chip adi_gpio_irqchip
= {
577 .irq_ack
= adi_gpio_ack_irq
,
578 .irq_mask
= adi_gpio_mask_irq
,
579 .irq_mask_ack
= adi_gpio_mask_ack_irq
,
580 .irq_unmask
= adi_gpio_unmask_irq
,
581 .irq_disable
= adi_gpio_mask_irq
,
582 .irq_enable
= adi_gpio_unmask_irq
,
583 .irq_set_type
= adi_gpio_irq_type
,
584 .irq_startup
= adi_gpio_irq_startup
,
585 .irq_shutdown
= adi_gpio_irq_shutdown
,
586 .irq_set_wake
= adi_gpio_set_wake
,
589 static int adi_get_groups_count(struct pinctrl_dev
*pctldev
)
591 struct adi_pinctrl
*pinctrl
= pinctrl_dev_get_drvdata(pctldev
);
593 return pinctrl
->soc
->ngroups
;
596 static const char *adi_get_group_name(struct pinctrl_dev
*pctldev
,
599 struct adi_pinctrl
*pinctrl
= pinctrl_dev_get_drvdata(pctldev
);
601 return pinctrl
->soc
->groups
[selector
].name
;
604 static int adi_get_group_pins(struct pinctrl_dev
*pctldev
, unsigned selector
,
605 const unsigned **pins
,
608 struct adi_pinctrl
*pinctrl
= pinctrl_dev_get_drvdata(pctldev
);
610 *pins
= pinctrl
->soc
->groups
[selector
].pins
;
611 *num_pins
= pinctrl
->soc
->groups
[selector
].num
;
615 static struct pinctrl_ops adi_pctrl_ops
= {
616 .get_groups_count
= adi_get_groups_count
,
617 .get_group_name
= adi_get_group_name
,
618 .get_group_pins
= adi_get_group_pins
,
621 static int adi_pinmux_enable(struct pinctrl_dev
*pctldev
, unsigned selector
,
624 struct adi_pinctrl
*pinctrl
= pinctrl_dev_get_drvdata(pctldev
);
625 struct gpio_port
*port
;
626 struct pinctrl_gpio_range
*range
;
628 unsigned short *mux
, pin
;
630 mux
= (unsigned short *)pinctrl
->soc
->functions
[selector
].mux
;
635 range
= pinctrl_find_gpio_range_from_pin(pctldev
, pin
);
636 if (range
== NULL
) /* should not happen */
639 port
= container_of(range
->gc
, struct gpio_port
, chip
);
641 spin_lock_irqsave(&port
->lock
, flags
);
643 portmux_setup(port
, pin_to_offset(range
, pin
),
645 port_setup(port
, pin_to_offset(range
, pin
), false);
648 spin_unlock_irqrestore(&port
->lock
, flags
);
654 static void adi_pinmux_disable(struct pinctrl_dev
*pctldev
, unsigned selector
,
657 struct adi_pinctrl
*pinctrl
= pinctrl_dev_get_drvdata(pctldev
);
658 struct gpio_port
*port
;
659 struct pinctrl_gpio_range
*range
;
661 unsigned short *mux
, pin
;
663 mux
= (unsigned short *)pinctrl
->soc
->functions
[selector
].mux
;
668 range
= pinctrl_find_gpio_range_from_pin(pctldev
, pin
);
669 if (range
== NULL
) /* should not happen */
672 port
= container_of(range
->gc
, struct gpio_port
, chip
);
674 spin_lock_irqsave(&port
->lock
, flags
);
676 port_setup(port
, pin_to_offset(range
, pin
), true);
679 spin_unlock_irqrestore(&port
->lock
, flags
);
683 static int adi_pinmux_get_funcs_count(struct pinctrl_dev
*pctldev
)
685 struct adi_pinctrl
*pinctrl
= pinctrl_dev_get_drvdata(pctldev
);
687 return pinctrl
->soc
->nfunctions
;
690 static const char *adi_pinmux_get_func_name(struct pinctrl_dev
*pctldev
,
693 struct adi_pinctrl
*pinctrl
= pinctrl_dev_get_drvdata(pctldev
);
695 return pinctrl
->soc
->functions
[selector
].name
;
698 static int adi_pinmux_get_groups(struct pinctrl_dev
*pctldev
, unsigned selector
,
699 const char * const **groups
,
700 unsigned * const num_groups
)
702 struct adi_pinctrl
*pinctrl
= pinctrl_dev_get_drvdata(pctldev
);
704 *groups
= pinctrl
->soc
->functions
[selector
].groups
;
705 *num_groups
= pinctrl
->soc
->functions
[selector
].num_groups
;
709 static int adi_pinmux_request_gpio(struct pinctrl_dev
*pctldev
,
710 struct pinctrl_gpio_range
*range
, unsigned pin
)
712 struct gpio_port
*port
;
716 port
= container_of(range
->gc
, struct gpio_port
, chip
);
717 offset
= pin_to_offset(range
, pin
);
719 spin_lock_irqsave(&port
->lock
, flags
);
721 port_setup(port
, offset
, true);
723 spin_unlock_irqrestore(&port
->lock
, flags
);
728 static struct pinmux_ops adi_pinmux_ops
= {
729 .enable
= adi_pinmux_enable
,
730 .disable
= adi_pinmux_disable
,
731 .get_functions_count
= adi_pinmux_get_funcs_count
,
732 .get_function_name
= adi_pinmux_get_func_name
,
733 .get_function_groups
= adi_pinmux_get_groups
,
734 .gpio_request_enable
= adi_pinmux_request_gpio
,
738 static struct pinctrl_desc adi_pinmux_desc
= {
740 .pctlops
= &adi_pctrl_ops
,
741 .pmxops
= &adi_pinmux_ops
,
742 .owner
= THIS_MODULE
,
745 static int adi_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
747 return pinctrl_request_gpio(chip
->base
+ offset
);
750 static void adi_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
752 pinctrl_free_gpio(chip
->base
+ offset
);
755 static int adi_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
757 struct gpio_port
*port
;
760 port
= container_of(chip
, struct gpio_port
, chip
);
762 spin_lock_irqsave(&port
->lock
, flags
);
764 writew(BIT(offset
), &port
->regs
->dir_clear
);
765 writew(readw(&port
->regs
->inen
) | BIT(offset
), &port
->regs
->inen
);
767 spin_unlock_irqrestore(&port
->lock
, flags
);
772 static void adi_gpio_set_value(struct gpio_chip
*chip
, unsigned offset
,
775 struct gpio_port
*port
= container_of(chip
, struct gpio_port
, chip
);
776 struct gpio_port_t
*regs
= port
->regs
;
779 spin_lock_irqsave(&port
->lock
, flags
);
782 writew(BIT(offset
), ®s
->data_set
);
784 writew(BIT(offset
), ®s
->data_clear
);
786 spin_unlock_irqrestore(&port
->lock
, flags
);
789 static int adi_gpio_direction_output(struct gpio_chip
*chip
, unsigned offset
,
792 struct gpio_port
*port
= container_of(chip
, struct gpio_port
, chip
);
793 struct gpio_port_t
*regs
= port
->regs
;
796 spin_lock_irqsave(&port
->lock
, flags
);
798 writew(readw(®s
->inen
) & ~BIT(offset
), ®s
->inen
);
800 writew(BIT(offset
), ®s
->data_set
);
802 writew(BIT(offset
), ®s
->data_clear
);
803 writew(BIT(offset
), ®s
->dir_set
);
805 spin_unlock_irqrestore(&port
->lock
, flags
);
810 static int adi_gpio_get_value(struct gpio_chip
*chip
, unsigned offset
)
812 struct gpio_port
*port
= container_of(chip
, struct gpio_port
, chip
);
813 struct gpio_port_t
*regs
= port
->regs
;
817 spin_lock_irqsave(&port
->lock
, flags
);
819 ret
= !!(readw(®s
->data
) & BIT(offset
));
821 spin_unlock_irqrestore(&port
->lock
, flags
);
826 static int adi_gpio_to_irq(struct gpio_chip
*chip
, unsigned offset
)
828 struct gpio_port
*port
= container_of(chip
, struct gpio_port
, chip
);
830 if (port
->irq_base
>= 0)
831 return irq_find_mapping(port
->domain
, offset
);
833 return irq_create_mapping(port
->domain
, offset
);
836 static int adi_pint_map_port(struct gpio_pint
*pint
, bool assign
, u8 map
,
837 struct irq_domain
*domain
)
839 struct gpio_pint_regs
*regs
= pint
->regs
;
842 if (pint
->map_count
> 1)
847 /* The map_mask of each gpio port is a 16-bit duplicate
848 * of the 8-bit map. It can be set to either high 16 bits or low
849 * 16 bits of the pint assignment register.
851 map_mask
= (map
<< 8) | map
;
853 map_mask
<<= PINT_HI_OFFSET
;
854 writel((readl(®s
->assign
) & 0xFFFF) | map_mask
,
857 writel((readl(®s
->assign
) & 0xFFFF0000) | map_mask
,
860 pint
->domain
[assign
] = domain
;
865 static int adi_gpio_pint_probe(struct platform_device
*pdev
)
867 struct device
*dev
= &pdev
->dev
;
868 struct resource
*res
;
869 struct gpio_pint
*pint
;
871 pint
= devm_kzalloc(dev
, sizeof(struct gpio_pint
), GFP_KERNEL
);
873 dev_err(dev
, "Memory alloc failed\n");
877 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
878 pint
->base
= devm_ioremap_resource(dev
, res
);
879 if (IS_ERR(pint
->base
))
880 return PTR_ERR(pint
->base
);
882 pint
->regs
= (struct gpio_pint_regs
*)pint
->base
;
884 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
886 dev_err(dev
, "Invalid IRQ resource\n");
890 spin_lock_init(&pint
->lock
);
892 pint
->irq
= res
->start
;
893 pint
->pint_map_port
= adi_pint_map_port
;
894 platform_set_drvdata(pdev
, pint
);
896 irq_set_chained_handler(pint
->irq
, adi_gpio_handle_pint_irq
);
897 irq_set_handler_data(pint
->irq
, pint
);
899 list_add_tail(&pint
->node
, &adi_pint_list
);
904 static int adi_gpio_pint_remove(struct platform_device
*pdev
)
906 struct gpio_pint
*pint
= platform_get_drvdata(pdev
);
908 list_del(&pint
->node
);
909 irq_set_handler(pint
->irq
, handle_simple_irq
);
914 static int adi_gpio_irq_map(struct irq_domain
*d
, unsigned int irq
,
915 irq_hw_number_t hwirq
)
917 struct gpio_port
*port
= d
->host_data
;
922 irq_set_chip_data(irq
, port
);
923 irq_set_chip_and_handler(irq
, &adi_gpio_irqchip
,
929 const struct irq_domain_ops adi_gpio_irq_domain_ops
= {
930 .map
= adi_gpio_irq_map
,
931 .xlate
= irq_domain_xlate_onecell
,
934 static int adi_gpio_init_int(struct gpio_port
*port
)
936 struct device_node
*node
= port
->dev
->of_node
;
937 struct gpio_pint
*pint
= port
->pint
;
940 port
->domain
= irq_domain_add_linear(node
, port
->width
,
941 &adi_gpio_irq_domain_ops
, port
);
943 dev_err(port
->dev
, "Failed to create irqdomain\n");
947 /* According to BF54x and BF60x HRM, pin interrupt devices are not
948 * part of the GPIO port device. in GPIO interrupt mode, the GPIO
949 * pins of multiple port devices can be routed into one pin interrupt
950 * device. The mapping can be configured by setting pint assignment
951 * register with the mapping value of different GPIO port. This is
952 * done via function pint_map_port().
954 ret
= pint
->pint_map_port(port
->pint
, port
->pint_assign
,
955 port
->pint_map
, port
->domain
);
959 if (port
->irq_base
>= 0) {
960 ret
= irq_create_strict_mappings(port
->domain
, port
->irq_base
,
963 dev_err(port
->dev
, "Couldn't associate to domain\n");
971 #define DEVNAME_SIZE 16
973 static int adi_gpio_probe(struct platform_device
*pdev
)
975 struct device
*dev
= &pdev
->dev
;
976 const struct adi_pinctrl_gpio_platform_data
*pdata
;
977 struct resource
*res
;
978 struct gpio_port
*port
;
979 char pinctrl_devname
[DEVNAME_SIZE
];
983 pdata
= dev
->platform_data
;
987 port
= devm_kzalloc(dev
, sizeof(struct gpio_port
), GFP_KERNEL
);
989 dev_err(dev
, "Memory alloc failed\n");
993 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
994 port
->base
= devm_ioremap_resource(dev
, res
);
995 if (IS_ERR(port
->base
))
996 return PTR_ERR(port
->base
);
998 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1000 port
->irq_base
= -1;
1002 port
->irq_base
= res
->start
;
1004 port
->width
= pdata
->port_width
;
1006 port
->regs
= (struct gpio_port_t
*)port
->base
;
1007 port
->pint_assign
= pdata
->pint_assign
;
1008 port
->pint_map
= pdata
->pint_map
;
1010 port
->pint
= find_gpio_pint(pdata
->pint_id
);
1012 ret
= adi_gpio_init_int(port
);
1017 spin_lock_init(&port
->lock
);
1019 platform_set_drvdata(pdev
, port
);
1021 port
->chip
.label
= "adi-gpio";
1022 port
->chip
.direction_input
= adi_gpio_direction_input
;
1023 port
->chip
.get
= adi_gpio_get_value
;
1024 port
->chip
.direction_output
= adi_gpio_direction_output
;
1025 port
->chip
.set
= adi_gpio_set_value
;
1026 port
->chip
.request
= adi_gpio_request
;
1027 port
->chip
.free
= adi_gpio_free
;
1028 port
->chip
.to_irq
= adi_gpio_to_irq
;
1029 if (pdata
->port_gpio_base
> 0)
1030 port
->chip
.base
= pdata
->port_gpio_base
;
1032 port
->chip
.base
= gpio
;
1033 port
->chip
.ngpio
= port
->width
;
1034 gpio
= port
->chip
.base
+ port
->width
;
1036 ret
= gpiochip_add(&port
->chip
);
1038 dev_err(&pdev
->dev
, "Fail to add GPIO chip.\n");
1039 goto out_remove_domain
;
1042 /* Add gpio pin range */
1043 snprintf(pinctrl_devname
, DEVNAME_SIZE
, "pinctrl-adi2.%d",
1045 pinctrl_devname
[DEVNAME_SIZE
- 1] = 0;
1046 ret
= gpiochip_add_pin_range(&port
->chip
, pinctrl_devname
,
1047 0, pdata
->port_pin_base
, port
->width
);
1049 dev_err(&pdev
->dev
, "Fail to add pin range to %s.\n",
1051 goto out_remove_gpiochip
;
1054 list_add_tail(&port
->node
, &adi_gpio_port_list
);
1058 out_remove_gpiochip
:
1059 ret1
= gpiochip_remove(&port
->chip
);
1062 irq_domain_remove(port
->domain
);
1067 static int adi_gpio_remove(struct platform_device
*pdev
)
1069 struct gpio_port
*port
= platform_get_drvdata(pdev
);
1073 list_del(&port
->node
);
1074 gpiochip_remove_pin_ranges(&port
->chip
);
1075 ret
= gpiochip_remove(&port
->chip
);
1077 for (offset
= 0; offset
< port
->width
; offset
++)
1078 irq_dispose_mapping(irq_find_mapping(port
->domain
,
1080 irq_domain_remove(port
->domain
);
1086 static int adi_pinctrl_probe(struct platform_device
*pdev
)
1088 struct adi_pinctrl
*pinctrl
;
1090 pinctrl
= devm_kzalloc(&pdev
->dev
, sizeof(*pinctrl
), GFP_KERNEL
);
1094 pinctrl
->dev
= &pdev
->dev
;
1096 adi_pinctrl_soc_init(&pinctrl
->soc
);
1098 adi_pinmux_desc
.pins
= pinctrl
->soc
->pins
;
1099 adi_pinmux_desc
.npins
= pinctrl
->soc
->npins
;
1101 /* Now register the pin controller and all pins it handles */
1102 pinctrl
->pctl
= pinctrl_register(&adi_pinmux_desc
, &pdev
->dev
, pinctrl
);
1103 if (!pinctrl
->pctl
) {
1104 dev_err(&pdev
->dev
, "could not register pinctrl ADI2 driver\n");
1108 platform_set_drvdata(pdev
, pinctrl
);
1113 static int adi_pinctrl_remove(struct platform_device
*pdev
)
1115 struct adi_pinctrl
*pinctrl
= platform_get_drvdata(pdev
);
1117 pinctrl_unregister(pinctrl
->pctl
);
1122 static struct platform_driver adi_pinctrl_driver
= {
1123 .probe
= adi_pinctrl_probe
,
1124 .remove
= adi_pinctrl_remove
,
1126 .name
= DRIVER_NAME
,
1130 static struct platform_driver adi_gpio_pint_driver
= {
1131 .probe
= adi_gpio_pint_probe
,
1132 .remove
= adi_gpio_pint_remove
,
1134 .name
= "adi-gpio-pint",
1138 static struct platform_driver adi_gpio_driver
= {
1139 .probe
= adi_gpio_probe
,
1140 .remove
= adi_gpio_remove
,
1146 static int __init
adi_pinctrl_setup(void)
1150 ret
= platform_driver_register(&adi_pinctrl_driver
);
1154 ret
= platform_driver_register(&adi_gpio_pint_driver
);
1158 ret
= platform_driver_register(&adi_gpio_driver
);
1163 register_syscore_ops(&gpio_pm_syscore_ops
);
1167 platform_driver_unregister(&adi_gpio_pint_driver
);
1169 platform_driver_unregister(&adi_pinctrl_driver
);
1173 arch_initcall(adi_pinctrl_setup
);
1175 MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>");
1176 MODULE_DESCRIPTION("ADI gpio2 pin control driver");
1177 MODULE_LICENSE("GPL");