2 * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2012 Linaro Ltd
7 * http://www.linaro.org
9 * Author: Thomas Abraham <thomas.ab@samsung.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This file contains the Samsung Exynos specific information required by the
17 * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
18 * external gpio and wakeup interrupt support.
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/irqdomain.h>
25 #include <linux/irq.h>
26 #include <linux/irqchip/chained_irq.h>
27 #include <linux/of_irq.h>
29 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31 #include <linux/err.h>
33 #include "pinctrl-samsung.h"
34 #include "pinctrl-exynos.h"
37 static struct samsung_pin_bank_type bank_type_off
= {
38 .fld_width
= { 4, 1, 2, 2, 2, 2, },
39 .reg_offset
= { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
42 static struct samsung_pin_bank_type bank_type_alive
= {
43 .fld_width
= { 4, 1, 2, 2, },
44 .reg_offset
= { 0x00, 0x04, 0x08, 0x0c, },
47 /* list of external wakeup controllers supported */
48 static const struct of_device_id exynos_wkup_irq_ids
[] = {
49 { .compatible
= "samsung,exynos4210-wakeup-eint", },
53 static void exynos_gpio_irq_mask(struct irq_data
*irqd
)
55 struct samsung_pin_bank
*bank
= irq_data_get_irq_chip_data(irqd
);
56 struct samsung_pinctrl_drv_data
*d
= bank
->drvdata
;
57 unsigned long reg_mask
= d
->ctrl
->geint_mask
+ bank
->eint_offset
;
61 spin_lock_irqsave(&bank
->slock
, flags
);
63 mask
= readl(d
->virt_base
+ reg_mask
);
64 mask
|= 1 << irqd
->hwirq
;
65 writel(mask
, d
->virt_base
+ reg_mask
);
67 spin_unlock_irqrestore(&bank
->slock
, flags
);
70 static void exynos_gpio_irq_ack(struct irq_data
*irqd
)
72 struct samsung_pin_bank
*bank
= irq_data_get_irq_chip_data(irqd
);
73 struct samsung_pinctrl_drv_data
*d
= bank
->drvdata
;
74 unsigned long reg_pend
= d
->ctrl
->geint_pend
+ bank
->eint_offset
;
76 writel(1 << irqd
->hwirq
, d
->virt_base
+ reg_pend
);
79 static void exynos_gpio_irq_unmask(struct irq_data
*irqd
)
81 struct samsung_pin_bank
*bank
= irq_data_get_irq_chip_data(irqd
);
82 struct samsung_pinctrl_drv_data
*d
= bank
->drvdata
;
83 unsigned long reg_mask
= d
->ctrl
->geint_mask
+ bank
->eint_offset
;
88 * Ack level interrupts right before unmask
90 * If we don't do this we'll get a double-interrupt. Level triggered
91 * interrupts must not fire an interrupt if the level is not
92 * _currently_ active, even if it was active while the interrupt was
95 if (irqd_get_trigger_type(irqd
) & IRQ_TYPE_LEVEL_MASK
)
96 exynos_gpio_irq_ack(irqd
);
98 spin_lock_irqsave(&bank
->slock
, flags
);
100 mask
= readl(d
->virt_base
+ reg_mask
);
101 mask
&= ~(1 << irqd
->hwirq
);
102 writel(mask
, d
->virt_base
+ reg_mask
);
104 spin_unlock_irqrestore(&bank
->slock
, flags
);
107 static int exynos_gpio_irq_set_type(struct irq_data
*irqd
, unsigned int type
)
109 struct samsung_pin_bank
*bank
= irq_data_get_irq_chip_data(irqd
);
110 struct samsung_pin_bank_type
*bank_type
= bank
->type
;
111 struct samsung_pinctrl_drv_data
*d
= bank
->drvdata
;
112 struct samsung_pin_ctrl
*ctrl
= d
->ctrl
;
113 unsigned int pin
= irqd
->hwirq
;
114 unsigned int shift
= EXYNOS_EINT_CON_LEN
* pin
;
115 unsigned int con
, trig_type
;
116 unsigned long reg_con
= ctrl
->geint_con
+ bank
->eint_offset
;
121 case IRQ_TYPE_EDGE_RISING
:
122 trig_type
= EXYNOS_EINT_EDGE_RISING
;
124 case IRQ_TYPE_EDGE_FALLING
:
125 trig_type
= EXYNOS_EINT_EDGE_FALLING
;
127 case IRQ_TYPE_EDGE_BOTH
:
128 trig_type
= EXYNOS_EINT_EDGE_BOTH
;
130 case IRQ_TYPE_LEVEL_HIGH
:
131 trig_type
= EXYNOS_EINT_LEVEL_HIGH
;
133 case IRQ_TYPE_LEVEL_LOW
:
134 trig_type
= EXYNOS_EINT_LEVEL_LOW
;
137 pr_err("unsupported external interrupt type\n");
141 if (type
& IRQ_TYPE_EDGE_BOTH
)
142 __irq_set_handler_locked(irqd
->irq
, handle_edge_irq
);
144 __irq_set_handler_locked(irqd
->irq
, handle_level_irq
);
146 con
= readl(d
->virt_base
+ reg_con
);
147 con
&= ~(EXYNOS_EINT_CON_MASK
<< shift
);
148 con
|= trig_type
<< shift
;
149 writel(con
, d
->virt_base
+ reg_con
);
151 reg_con
= bank
->pctl_offset
+ bank_type
->reg_offset
[PINCFG_TYPE_FUNC
];
152 shift
= pin
* bank_type
->fld_width
[PINCFG_TYPE_FUNC
];
153 mask
= (1 << bank_type
->fld_width
[PINCFG_TYPE_FUNC
]) - 1;
155 spin_lock_irqsave(&bank
->slock
, flags
);
157 con
= readl(d
->virt_base
+ reg_con
);
158 con
&= ~(mask
<< shift
);
159 con
|= EXYNOS_EINT_FUNC
<< shift
;
160 writel(con
, d
->virt_base
+ reg_con
);
162 spin_unlock_irqrestore(&bank
->slock
, flags
);
168 * irq_chip for gpio interrupts.
170 static struct irq_chip exynos_gpio_irq_chip
= {
171 .name
= "exynos_gpio_irq_chip",
172 .irq_unmask
= exynos_gpio_irq_unmask
,
173 .irq_mask
= exynos_gpio_irq_mask
,
174 .irq_ack
= exynos_gpio_irq_ack
,
175 .irq_set_type
= exynos_gpio_irq_set_type
,
178 static int exynos_gpio_irq_map(struct irq_domain
*h
, unsigned int virq
,
181 struct samsung_pin_bank
*b
= h
->host_data
;
183 irq_set_chip_data(virq
, b
);
184 irq_set_chip_and_handler(virq
, &exynos_gpio_irq_chip
,
186 set_irq_flags(virq
, IRQF_VALID
);
191 * irq domain callbacks for external gpio interrupt controller.
193 static const struct irq_domain_ops exynos_gpio_irqd_ops
= {
194 .map
= exynos_gpio_irq_map
,
195 .xlate
= irq_domain_xlate_twocell
,
198 static irqreturn_t
exynos_eint_gpio_irq(int irq
, void *data
)
200 struct samsung_pinctrl_drv_data
*d
= data
;
201 struct samsung_pin_ctrl
*ctrl
= d
->ctrl
;
202 struct samsung_pin_bank
*bank
= ctrl
->pin_banks
;
203 unsigned int svc
, group
, pin
, virq
;
205 svc
= readl(d
->virt_base
+ ctrl
->svc
);
206 group
= EXYNOS_SVC_GROUP(svc
);
207 pin
= svc
& EXYNOS_SVC_NUM_MASK
;
213 virq
= irq_linear_revmap(bank
->irq_domain
, pin
);
216 generic_handle_irq(virq
);
220 struct exynos_eint_gpio_save
{
227 * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
228 * @d: driver data of samsung pinctrl driver.
230 static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data
*d
)
232 struct samsung_pin_bank
*bank
;
233 struct device
*dev
= d
->dev
;
238 dev_err(dev
, "irq number not available\n");
242 ret
= devm_request_irq(dev
, d
->irq
, exynos_eint_gpio_irq
,
243 0, dev_name(dev
), d
);
245 dev_err(dev
, "irq request failed\n");
249 bank
= d
->ctrl
->pin_banks
;
250 for (i
= 0; i
< d
->ctrl
->nr_banks
; ++i
, ++bank
) {
251 if (bank
->eint_type
!= EINT_TYPE_GPIO
)
253 bank
->irq_domain
= irq_domain_add_linear(bank
->of_node
,
254 bank
->nr_pins
, &exynos_gpio_irqd_ops
, bank
);
255 if (!bank
->irq_domain
) {
256 dev_err(dev
, "gpio irq domain add failed\n");
261 bank
->soc_priv
= devm_kzalloc(d
->dev
,
262 sizeof(struct exynos_eint_gpio_save
), GFP_KERNEL
);
263 if (!bank
->soc_priv
) {
264 irq_domain_remove(bank
->irq_domain
);
273 for (--i
, --bank
; i
>= 0; --i
, --bank
) {
274 if (bank
->eint_type
!= EINT_TYPE_GPIO
)
276 irq_domain_remove(bank
->irq_domain
);
282 static void exynos_wkup_irq_mask(struct irq_data
*irqd
)
284 struct samsung_pin_bank
*b
= irq_data_get_irq_chip_data(irqd
);
285 struct samsung_pinctrl_drv_data
*d
= b
->drvdata
;
286 unsigned long reg_mask
= d
->ctrl
->weint_mask
+ b
->eint_offset
;
290 spin_lock_irqsave(&b
->slock
, flags
);
292 mask
= readl(d
->virt_base
+ reg_mask
);
293 mask
|= 1 << irqd
->hwirq
;
294 writel(mask
, d
->virt_base
+ reg_mask
);
296 spin_unlock_irqrestore(&b
->slock
, flags
);
299 static void exynos_wkup_irq_ack(struct irq_data
*irqd
)
301 struct samsung_pin_bank
*b
= irq_data_get_irq_chip_data(irqd
);
302 struct samsung_pinctrl_drv_data
*d
= b
->drvdata
;
303 unsigned long pend
= d
->ctrl
->weint_pend
+ b
->eint_offset
;
305 writel(1 << irqd
->hwirq
, d
->virt_base
+ pend
);
308 static void exynos_wkup_irq_unmask(struct irq_data
*irqd
)
310 struct samsung_pin_bank
*b
= irq_data_get_irq_chip_data(irqd
);
311 struct samsung_pinctrl_drv_data
*d
= b
->drvdata
;
312 unsigned long reg_mask
= d
->ctrl
->weint_mask
+ b
->eint_offset
;
317 * Ack level interrupts right before unmask
319 * If we don't do this we'll get a double-interrupt. Level triggered
320 * interrupts must not fire an interrupt if the level is not
321 * _currently_ active, even if it was active while the interrupt was
324 if (irqd_get_trigger_type(irqd
) & IRQ_TYPE_LEVEL_MASK
)
325 exynos_wkup_irq_ack(irqd
);
327 spin_lock_irqsave(&b
->slock
, flags
);
329 mask
= readl(d
->virt_base
+ reg_mask
);
330 mask
&= ~(1 << irqd
->hwirq
);
331 writel(mask
, d
->virt_base
+ reg_mask
);
333 spin_unlock_irqrestore(&b
->slock
, flags
);
336 static int exynos_wkup_irq_set_type(struct irq_data
*irqd
, unsigned int type
)
338 struct samsung_pin_bank
*bank
= irq_data_get_irq_chip_data(irqd
);
339 struct samsung_pin_bank_type
*bank_type
= bank
->type
;
340 struct samsung_pinctrl_drv_data
*d
= bank
->drvdata
;
341 unsigned int pin
= irqd
->hwirq
;
342 unsigned long reg_con
= d
->ctrl
->weint_con
+ bank
->eint_offset
;
343 unsigned long shift
= EXYNOS_EINT_CON_LEN
* pin
;
344 unsigned long con
, trig_type
;
349 case IRQ_TYPE_EDGE_RISING
:
350 trig_type
= EXYNOS_EINT_EDGE_RISING
;
352 case IRQ_TYPE_EDGE_FALLING
:
353 trig_type
= EXYNOS_EINT_EDGE_FALLING
;
355 case IRQ_TYPE_EDGE_BOTH
:
356 trig_type
= EXYNOS_EINT_EDGE_BOTH
;
358 case IRQ_TYPE_LEVEL_HIGH
:
359 trig_type
= EXYNOS_EINT_LEVEL_HIGH
;
361 case IRQ_TYPE_LEVEL_LOW
:
362 trig_type
= EXYNOS_EINT_LEVEL_LOW
;
365 pr_err("unsupported external interrupt type\n");
369 if (type
& IRQ_TYPE_EDGE_BOTH
)
370 __irq_set_handler_locked(irqd
->irq
, handle_edge_irq
);
372 __irq_set_handler_locked(irqd
->irq
, handle_level_irq
);
374 con
= readl(d
->virt_base
+ reg_con
);
375 con
&= ~(EXYNOS_EINT_CON_MASK
<< shift
);
376 con
|= trig_type
<< shift
;
377 writel(con
, d
->virt_base
+ reg_con
);
379 reg_con
= bank
->pctl_offset
+ bank_type
->reg_offset
[PINCFG_TYPE_FUNC
];
380 shift
= pin
* bank_type
->fld_width
[PINCFG_TYPE_FUNC
];
381 mask
= (1 << bank_type
->fld_width
[PINCFG_TYPE_FUNC
]) - 1;
383 spin_lock_irqsave(&bank
->slock
, flags
);
385 con
= readl(d
->virt_base
+ reg_con
);
386 con
&= ~(mask
<< shift
);
387 con
|= EXYNOS_EINT_FUNC
<< shift
;
388 writel(con
, d
->virt_base
+ reg_con
);
390 spin_unlock_irqrestore(&bank
->slock
, flags
);
395 static u32 exynos_eint_wake_mask
= 0xffffffff;
397 u32
exynos_get_eint_wake_mask(void)
399 return exynos_eint_wake_mask
;
402 static int exynos_wkup_irq_set_wake(struct irq_data
*irqd
, unsigned int on
)
404 struct samsung_pin_bank
*bank
= irq_data_get_irq_chip_data(irqd
);
405 unsigned long bit
= 1UL << (2 * bank
->eint_offset
+ irqd
->hwirq
);
407 pr_info("wake %s for irq %d\n", on
? "enabled" : "disabled", irqd
->irq
);
410 exynos_eint_wake_mask
|= bit
;
412 exynos_eint_wake_mask
&= ~bit
;
418 * irq_chip for wakeup interrupts
420 static struct irq_chip exynos_wkup_irq_chip
= {
421 .name
= "exynos_wkup_irq_chip",
422 .irq_unmask
= exynos_wkup_irq_unmask
,
423 .irq_mask
= exynos_wkup_irq_mask
,
424 .irq_ack
= exynos_wkup_irq_ack
,
425 .irq_set_type
= exynos_wkup_irq_set_type
,
426 .irq_set_wake
= exynos_wkup_irq_set_wake
,
429 /* interrupt handler for wakeup interrupts 0..15 */
430 static void exynos_irq_eint0_15(unsigned int irq
, struct irq_desc
*desc
)
432 struct exynos_weint_data
*eintd
= irq_get_handler_data(irq
);
433 struct samsung_pin_bank
*bank
= eintd
->bank
;
434 struct irq_chip
*chip
= irq_get_chip(irq
);
437 chained_irq_enter(chip
, desc
);
438 chip
->irq_mask(&desc
->irq_data
);
441 chip
->irq_ack(&desc
->irq_data
);
443 eint_irq
= irq_linear_revmap(bank
->irq_domain
, eintd
->irq
);
444 generic_handle_irq(eint_irq
);
445 chip
->irq_unmask(&desc
->irq_data
);
446 chained_irq_exit(chip
, desc
);
449 static inline void exynos_irq_demux_eint(unsigned long pend
,
450 struct irq_domain
*domain
)
456 generic_handle_irq(irq_find_mapping(domain
, irq
));
461 /* interrupt handler for wakeup interrupt 16 */
462 static void exynos_irq_demux_eint16_31(unsigned int irq
, struct irq_desc
*desc
)
464 struct irq_chip
*chip
= irq_get_chip(irq
);
465 struct exynos_muxed_weint_data
*eintd
= irq_get_handler_data(irq
);
466 struct samsung_pinctrl_drv_data
*d
= eintd
->banks
[0]->drvdata
;
467 struct samsung_pin_ctrl
*ctrl
= d
->ctrl
;
472 chained_irq_enter(chip
, desc
);
474 for (i
= 0; i
< eintd
->nr_banks
; ++i
) {
475 struct samsung_pin_bank
*b
= eintd
->banks
[i
];
476 pend
= readl(d
->virt_base
+ ctrl
->weint_pend
+ b
->eint_offset
);
477 mask
= readl(d
->virt_base
+ ctrl
->weint_mask
+ b
->eint_offset
);
478 exynos_irq_demux_eint(pend
& ~mask
, b
->irq_domain
);
481 chained_irq_exit(chip
, desc
);
484 static int exynos_wkup_irq_map(struct irq_domain
*h
, unsigned int virq
,
487 irq_set_chip_and_handler(virq
, &exynos_wkup_irq_chip
, handle_level_irq
);
488 irq_set_chip_data(virq
, h
->host_data
);
489 set_irq_flags(virq
, IRQF_VALID
);
494 * irq domain callbacks for external wakeup interrupt controller.
496 static const struct irq_domain_ops exynos_wkup_irqd_ops
= {
497 .map
= exynos_wkup_irq_map
,
498 .xlate
= irq_domain_xlate_twocell
,
502 * exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
503 * @d: driver data of samsung pinctrl driver.
505 static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data
*d
)
507 struct device
*dev
= d
->dev
;
508 struct device_node
*wkup_np
= NULL
;
509 struct device_node
*np
;
510 struct samsung_pin_bank
*bank
;
511 struct exynos_weint_data
*weint_data
;
512 struct exynos_muxed_weint_data
*muxed_data
;
513 unsigned int muxed_banks
= 0;
517 for_each_child_of_node(dev
->of_node
, np
) {
518 if (of_match_node(exynos_wkup_irq_ids
, np
)) {
526 bank
= d
->ctrl
->pin_banks
;
527 for (i
= 0; i
< d
->ctrl
->nr_banks
; ++i
, ++bank
) {
528 if (bank
->eint_type
!= EINT_TYPE_WKUP
)
531 bank
->irq_domain
= irq_domain_add_linear(bank
->of_node
,
532 bank
->nr_pins
, &exynos_wkup_irqd_ops
, bank
);
533 if (!bank
->irq_domain
) {
534 dev_err(dev
, "wkup irq domain add failed\n");
538 if (!of_find_property(bank
->of_node
, "interrupts", NULL
)) {
539 bank
->eint_type
= EINT_TYPE_WKUP_MUX
;
544 weint_data
= devm_kzalloc(dev
, bank
->nr_pins
545 * sizeof(*weint_data
), GFP_KERNEL
);
547 dev_err(dev
, "could not allocate memory for weint_data\n");
551 for (idx
= 0; idx
< bank
->nr_pins
; ++idx
) {
552 irq
= irq_of_parse_and_map(bank
->of_node
, idx
);
554 dev_err(dev
, "irq number for eint-%s-%d not found\n",
558 weint_data
[idx
].irq
= idx
;
559 weint_data
[idx
].bank
= bank
;
560 irq_set_handler_data(irq
, &weint_data
[idx
]);
561 irq_set_chained_handler(irq
, exynos_irq_eint0_15
);
568 irq
= irq_of_parse_and_map(wkup_np
, 0);
570 dev_err(dev
, "irq number for muxed EINTs not found\n");
574 muxed_data
= devm_kzalloc(dev
, sizeof(*muxed_data
)
575 + muxed_banks
*sizeof(struct samsung_pin_bank
*), GFP_KERNEL
);
577 dev_err(dev
, "could not allocate memory for muxed_data\n");
581 irq_set_chained_handler(irq
, exynos_irq_demux_eint16_31
);
582 irq_set_handler_data(irq
, muxed_data
);
584 bank
= d
->ctrl
->pin_banks
;
586 for (i
= 0; i
< d
->ctrl
->nr_banks
; ++i
, ++bank
) {
587 if (bank
->eint_type
!= EINT_TYPE_WKUP_MUX
)
590 muxed_data
->banks
[idx
++] = bank
;
592 muxed_data
->nr_banks
= muxed_banks
;
597 static void exynos_pinctrl_suspend_bank(
598 struct samsung_pinctrl_drv_data
*drvdata
,
599 struct samsung_pin_bank
*bank
)
601 struct exynos_eint_gpio_save
*save
= bank
->soc_priv
;
602 void __iomem
*regs
= drvdata
->virt_base
;
604 save
->eint_con
= readl(regs
+ EXYNOS_GPIO_ECON_OFFSET
605 + bank
->eint_offset
);
606 save
->eint_fltcon0
= readl(regs
+ EXYNOS_GPIO_EFLTCON_OFFSET
607 + 2 * bank
->eint_offset
);
608 save
->eint_fltcon1
= readl(regs
+ EXYNOS_GPIO_EFLTCON_OFFSET
609 + 2 * bank
->eint_offset
+ 4);
611 pr_debug("%s: save con %#010x\n", bank
->name
, save
->eint_con
);
612 pr_debug("%s: save fltcon0 %#010x\n", bank
->name
, save
->eint_fltcon0
);
613 pr_debug("%s: save fltcon1 %#010x\n", bank
->name
, save
->eint_fltcon1
);
616 static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data
*drvdata
)
618 struct samsung_pin_ctrl
*ctrl
= drvdata
->ctrl
;
619 struct samsung_pin_bank
*bank
= ctrl
->pin_banks
;
622 for (i
= 0; i
< ctrl
->nr_banks
; ++i
, ++bank
)
623 if (bank
->eint_type
== EINT_TYPE_GPIO
)
624 exynos_pinctrl_suspend_bank(drvdata
, bank
);
627 static void exynos_pinctrl_resume_bank(
628 struct samsung_pinctrl_drv_data
*drvdata
,
629 struct samsung_pin_bank
*bank
)
631 struct exynos_eint_gpio_save
*save
= bank
->soc_priv
;
632 void __iomem
*regs
= drvdata
->virt_base
;
634 pr_debug("%s: con %#010x => %#010x\n", bank
->name
,
635 readl(regs
+ EXYNOS_GPIO_ECON_OFFSET
636 + bank
->eint_offset
), save
->eint_con
);
637 pr_debug("%s: fltcon0 %#010x => %#010x\n", bank
->name
,
638 readl(regs
+ EXYNOS_GPIO_EFLTCON_OFFSET
639 + 2 * bank
->eint_offset
), save
->eint_fltcon0
);
640 pr_debug("%s: fltcon1 %#010x => %#010x\n", bank
->name
,
641 readl(regs
+ EXYNOS_GPIO_EFLTCON_OFFSET
642 + 2 * bank
->eint_offset
+ 4), save
->eint_fltcon1
);
644 writel(save
->eint_con
, regs
+ EXYNOS_GPIO_ECON_OFFSET
645 + bank
->eint_offset
);
646 writel(save
->eint_fltcon0
, regs
+ EXYNOS_GPIO_EFLTCON_OFFSET
647 + 2 * bank
->eint_offset
);
648 writel(save
->eint_fltcon1
, regs
+ EXYNOS_GPIO_EFLTCON_OFFSET
649 + 2 * bank
->eint_offset
+ 4);
652 static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data
*drvdata
)
654 struct samsung_pin_ctrl
*ctrl
= drvdata
->ctrl
;
655 struct samsung_pin_bank
*bank
= ctrl
->pin_banks
;
658 for (i
= 0; i
< ctrl
->nr_banks
; ++i
, ++bank
)
659 if (bank
->eint_type
== EINT_TYPE_GPIO
)
660 exynos_pinctrl_resume_bank(drvdata
, bank
);
663 /* pin banks of exynos4210 pin-controller 0 */
664 static struct samsung_pin_bank exynos4210_pin_banks0
[] = {
665 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
666 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
667 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
668 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
669 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
670 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
671 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
672 EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c),
673 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),
674 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24),
675 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28),
676 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c),
677 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
678 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
679 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
680 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
683 /* pin banks of exynos4210 pin-controller 1 */
684 static struct samsung_pin_bank exynos4210_pin_banks1
[] = {
685 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),
686 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),
687 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
688 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
689 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
690 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
691 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18),
692 EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c),
693 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
694 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
695 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
696 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
697 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
698 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
699 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
700 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
701 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
702 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
703 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
704 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
707 /* pin banks of exynos4210 pin-controller 2 */
708 static struct samsung_pin_bank exynos4210_pin_banks2
[] = {
709 EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
713 * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
714 * three gpio/pin-mux/pinconfig controllers.
716 struct samsung_pin_ctrl exynos4210_pin_ctrl
[] = {
718 /* pin-controller instance 0 data */
719 .pin_banks
= exynos4210_pin_banks0
,
720 .nr_banks
= ARRAY_SIZE(exynos4210_pin_banks0
),
721 .geint_con
= EXYNOS_GPIO_ECON_OFFSET
,
722 .geint_mask
= EXYNOS_GPIO_EMASK_OFFSET
,
723 .geint_pend
= EXYNOS_GPIO_EPEND_OFFSET
,
724 .svc
= EXYNOS_SVC_OFFSET
,
725 .eint_gpio_init
= exynos_eint_gpio_init
,
726 .suspend
= exynos_pinctrl_suspend
,
727 .resume
= exynos_pinctrl_resume
,
728 .label
= "exynos4210-gpio-ctrl0",
730 /* pin-controller instance 1 data */
731 .pin_banks
= exynos4210_pin_banks1
,
732 .nr_banks
= ARRAY_SIZE(exynos4210_pin_banks1
),
733 .geint_con
= EXYNOS_GPIO_ECON_OFFSET
,
734 .geint_mask
= EXYNOS_GPIO_EMASK_OFFSET
,
735 .geint_pend
= EXYNOS_GPIO_EPEND_OFFSET
,
736 .weint_con
= EXYNOS_WKUP_ECON_OFFSET
,
737 .weint_mask
= EXYNOS_WKUP_EMASK_OFFSET
,
738 .weint_pend
= EXYNOS_WKUP_EPEND_OFFSET
,
739 .svc
= EXYNOS_SVC_OFFSET
,
740 .eint_gpio_init
= exynos_eint_gpio_init
,
741 .eint_wkup_init
= exynos_eint_wkup_init
,
742 .suspend
= exynos_pinctrl_suspend
,
743 .resume
= exynos_pinctrl_resume
,
744 .label
= "exynos4210-gpio-ctrl1",
746 /* pin-controller instance 2 data */
747 .pin_banks
= exynos4210_pin_banks2
,
748 .nr_banks
= ARRAY_SIZE(exynos4210_pin_banks2
),
749 .label
= "exynos4210-gpio-ctrl2",
753 /* pin banks of exynos4x12 pin-controller 0 */
754 static struct samsung_pin_bank exynos4x12_pin_banks0
[] = {
755 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
756 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
757 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
758 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
759 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
760 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
761 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
762 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
763 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
764 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
765 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
766 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40),
767 EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44),
770 /* pin banks of exynos4x12 pin-controller 1 */
771 static struct samsung_pin_bank exynos4x12_pin_banks1
[] = {
772 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
773 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
774 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
775 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
776 EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18),
777 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c),
778 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
779 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
780 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
781 EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
782 EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
783 EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
784 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
785 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
786 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
787 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
788 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
789 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
790 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
791 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
792 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
793 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
794 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
797 /* pin banks of exynos4x12 pin-controller 2 */
798 static struct samsung_pin_bank exynos4x12_pin_banks2
[] = {
799 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
802 /* pin banks of exynos4x12 pin-controller 3 */
803 static struct samsung_pin_bank exynos4x12_pin_banks3
[] = {
804 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
805 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
806 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
807 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c),
808 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10),
812 * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes
813 * four gpio/pin-mux/pinconfig controllers.
815 struct samsung_pin_ctrl exynos4x12_pin_ctrl
[] = {
817 /* pin-controller instance 0 data */
818 .pin_banks
= exynos4x12_pin_banks0
,
819 .nr_banks
= ARRAY_SIZE(exynos4x12_pin_banks0
),
820 .geint_con
= EXYNOS_GPIO_ECON_OFFSET
,
821 .geint_mask
= EXYNOS_GPIO_EMASK_OFFSET
,
822 .geint_pend
= EXYNOS_GPIO_EPEND_OFFSET
,
823 .svc
= EXYNOS_SVC_OFFSET
,
824 .eint_gpio_init
= exynos_eint_gpio_init
,
825 .suspend
= exynos_pinctrl_suspend
,
826 .resume
= exynos_pinctrl_resume
,
827 .label
= "exynos4x12-gpio-ctrl0",
829 /* pin-controller instance 1 data */
830 .pin_banks
= exynos4x12_pin_banks1
,
831 .nr_banks
= ARRAY_SIZE(exynos4x12_pin_banks1
),
832 .geint_con
= EXYNOS_GPIO_ECON_OFFSET
,
833 .geint_mask
= EXYNOS_GPIO_EMASK_OFFSET
,
834 .geint_pend
= EXYNOS_GPIO_EPEND_OFFSET
,
835 .weint_con
= EXYNOS_WKUP_ECON_OFFSET
,
836 .weint_mask
= EXYNOS_WKUP_EMASK_OFFSET
,
837 .weint_pend
= EXYNOS_WKUP_EPEND_OFFSET
,
838 .svc
= EXYNOS_SVC_OFFSET
,
839 .eint_gpio_init
= exynos_eint_gpio_init
,
840 .eint_wkup_init
= exynos_eint_wkup_init
,
841 .suspend
= exynos_pinctrl_suspend
,
842 .resume
= exynos_pinctrl_resume
,
843 .label
= "exynos4x12-gpio-ctrl1",
845 /* pin-controller instance 2 data */
846 .pin_banks
= exynos4x12_pin_banks2
,
847 .nr_banks
= ARRAY_SIZE(exynos4x12_pin_banks2
),
848 .geint_con
= EXYNOS_GPIO_ECON_OFFSET
,
849 .geint_mask
= EXYNOS_GPIO_EMASK_OFFSET
,
850 .geint_pend
= EXYNOS_GPIO_EPEND_OFFSET
,
851 .svc
= EXYNOS_SVC_OFFSET
,
852 .eint_gpio_init
= exynos_eint_gpio_init
,
853 .suspend
= exynos_pinctrl_suspend
,
854 .resume
= exynos_pinctrl_resume
,
855 .label
= "exynos4x12-gpio-ctrl2",
857 /* pin-controller instance 3 data */
858 .pin_banks
= exynos4x12_pin_banks3
,
859 .nr_banks
= ARRAY_SIZE(exynos4x12_pin_banks3
),
860 .geint_con
= EXYNOS_GPIO_ECON_OFFSET
,
861 .geint_mask
= EXYNOS_GPIO_EMASK_OFFSET
,
862 .geint_pend
= EXYNOS_GPIO_EPEND_OFFSET
,
863 .svc
= EXYNOS_SVC_OFFSET
,
864 .eint_gpio_init
= exynos_eint_gpio_init
,
865 .suspend
= exynos_pinctrl_suspend
,
866 .resume
= exynos_pinctrl_resume
,
867 .label
= "exynos4x12-gpio-ctrl3",
871 /* pin banks of exynos5250 pin-controller 0 */
872 static struct samsung_pin_bank exynos5250_pin_banks0
[] = {
873 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
874 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
875 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
876 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
877 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
878 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
879 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
880 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
881 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),
882 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),
883 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),
884 EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),
885 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),
886 EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),
887 EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),
888 EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),
889 EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),
890 EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),
891 EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),
892 EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),
893 EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),
894 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
895 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
896 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
897 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
900 /* pin banks of exynos5250 pin-controller 1 */
901 static struct samsung_pin_bank exynos5250_pin_banks1
[] = {
902 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
903 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
904 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
905 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),
906 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
907 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
908 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
909 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),
910 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),
913 /* pin banks of exynos5250 pin-controller 2 */
914 static struct samsung_pin_bank exynos5250_pin_banks2
[] = {
915 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
916 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
917 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
918 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
919 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
922 /* pin banks of exynos5250 pin-controller 3 */
923 static struct samsung_pin_bank exynos5250_pin_banks3
[] = {
924 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
928 * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
929 * four gpio/pin-mux/pinconfig controllers.
931 struct samsung_pin_ctrl exynos5250_pin_ctrl
[] = {
933 /* pin-controller instance 0 data */
934 .pin_banks
= exynos5250_pin_banks0
,
935 .nr_banks
= ARRAY_SIZE(exynos5250_pin_banks0
),
936 .geint_con
= EXYNOS_GPIO_ECON_OFFSET
,
937 .geint_mask
= EXYNOS_GPIO_EMASK_OFFSET
,
938 .geint_pend
= EXYNOS_GPIO_EPEND_OFFSET
,
939 .weint_con
= EXYNOS_WKUP_ECON_OFFSET
,
940 .weint_mask
= EXYNOS_WKUP_EMASK_OFFSET
,
941 .weint_pend
= EXYNOS_WKUP_EPEND_OFFSET
,
942 .svc
= EXYNOS_SVC_OFFSET
,
943 .eint_gpio_init
= exynos_eint_gpio_init
,
944 .eint_wkup_init
= exynos_eint_wkup_init
,
945 .suspend
= exynos_pinctrl_suspend
,
946 .resume
= exynos_pinctrl_resume
,
947 .label
= "exynos5250-gpio-ctrl0",
949 /* pin-controller instance 1 data */
950 .pin_banks
= exynos5250_pin_banks1
,
951 .nr_banks
= ARRAY_SIZE(exynos5250_pin_banks1
),
952 .geint_con
= EXYNOS_GPIO_ECON_OFFSET
,
953 .geint_mask
= EXYNOS_GPIO_EMASK_OFFSET
,
954 .geint_pend
= EXYNOS_GPIO_EPEND_OFFSET
,
955 .svc
= EXYNOS_SVC_OFFSET
,
956 .eint_gpio_init
= exynos_eint_gpio_init
,
957 .suspend
= exynos_pinctrl_suspend
,
958 .resume
= exynos_pinctrl_resume
,
959 .label
= "exynos5250-gpio-ctrl1",
961 /* pin-controller instance 2 data */
962 .pin_banks
= exynos5250_pin_banks2
,
963 .nr_banks
= ARRAY_SIZE(exynos5250_pin_banks2
),
964 .geint_con
= EXYNOS_GPIO_ECON_OFFSET
,
965 .geint_mask
= EXYNOS_GPIO_EMASK_OFFSET
,
966 .geint_pend
= EXYNOS_GPIO_EPEND_OFFSET
,
967 .svc
= EXYNOS_SVC_OFFSET
,
968 .eint_gpio_init
= exynos_eint_gpio_init
,
969 .suspend
= exynos_pinctrl_suspend
,
970 .resume
= exynos_pinctrl_resume
,
971 .label
= "exynos5250-gpio-ctrl2",
973 /* pin-controller instance 3 data */
974 .pin_banks
= exynos5250_pin_banks3
,
975 .nr_banks
= ARRAY_SIZE(exynos5250_pin_banks3
),
976 .geint_con
= EXYNOS_GPIO_ECON_OFFSET
,
977 .geint_mask
= EXYNOS_GPIO_EMASK_OFFSET
,
978 .geint_pend
= EXYNOS_GPIO_EPEND_OFFSET
,
979 .svc
= EXYNOS_SVC_OFFSET
,
980 .eint_gpio_init
= exynos_eint_gpio_init
,
981 .suspend
= exynos_pinctrl_suspend
,
982 .resume
= exynos_pinctrl_resume
,
983 .label
= "exynos5250-gpio-ctrl3",
987 /* pin banks of exynos5420 pin-controller 0 */
988 static struct samsung_pin_bank exynos5420_pin_banks0
[] = {
989 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
990 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
991 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
992 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
993 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
996 /* pin banks of exynos5420 pin-controller 1 */
997 static struct samsung_pin_bank exynos5420_pin_banks1
[] = {
998 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00),
999 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04),
1000 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
1001 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
1002 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10),
1003 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14),
1004 EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"),
1005 EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"),
1006 EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"),
1007 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"),
1008 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"),
1009 EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"),
1010 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"),
1013 /* pin banks of exynos5420 pin-controller 2 */
1014 static struct samsung_pin_bank exynos5420_pin_banks2
[] = {
1015 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
1016 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
1017 EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08),
1018 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c),
1019 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
1020 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
1021 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
1022 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c),
1025 /* pin banks of exynos5420 pin-controller 3 */
1026 static struct samsung_pin_bank exynos5420_pin_banks3
[] = {
1027 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
1028 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
1029 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
1030 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
1031 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
1032 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
1033 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18),
1034 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c),
1035 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20),
1038 /* pin banks of exynos5420 pin-controller 4 */
1039 static struct samsung_pin_bank exynos5420_pin_banks4
[] = {
1040 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
1044 * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes
1045 * four gpio/pin-mux/pinconfig controllers.
1047 struct samsung_pin_ctrl exynos5420_pin_ctrl
[] = {
1049 /* pin-controller instance 0 data */
1050 .pin_banks
= exynos5420_pin_banks0
,
1051 .nr_banks
= ARRAY_SIZE(exynos5420_pin_banks0
),
1052 .geint_con
= EXYNOS_GPIO_ECON_OFFSET
,
1053 .geint_mask
= EXYNOS_GPIO_EMASK_OFFSET
,
1054 .geint_pend
= EXYNOS_GPIO_EPEND_OFFSET
,
1055 .weint_con
= EXYNOS_WKUP_ECON_OFFSET
,
1056 .weint_mask
= EXYNOS_WKUP_EMASK_OFFSET
,
1057 .weint_pend
= EXYNOS_WKUP_EPEND_OFFSET
,
1058 .svc
= EXYNOS_SVC_OFFSET
,
1059 .eint_gpio_init
= exynos_eint_gpio_init
,
1060 .eint_wkup_init
= exynos_eint_wkup_init
,
1061 .label
= "exynos5420-gpio-ctrl0",
1063 /* pin-controller instance 1 data */
1064 .pin_banks
= exynos5420_pin_banks1
,
1065 .nr_banks
= ARRAY_SIZE(exynos5420_pin_banks1
),
1066 .geint_con
= EXYNOS_GPIO_ECON_OFFSET
,
1067 .geint_mask
= EXYNOS_GPIO_EMASK_OFFSET
,
1068 .geint_pend
= EXYNOS_GPIO_EPEND_OFFSET
,
1069 .svc
= EXYNOS_SVC_OFFSET
,
1070 .eint_gpio_init
= exynos_eint_gpio_init
,
1071 .label
= "exynos5420-gpio-ctrl1",
1073 /* pin-controller instance 2 data */
1074 .pin_banks
= exynos5420_pin_banks2
,
1075 .nr_banks
= ARRAY_SIZE(exynos5420_pin_banks2
),
1076 .geint_con
= EXYNOS_GPIO_ECON_OFFSET
,
1077 .geint_mask
= EXYNOS_GPIO_EMASK_OFFSET
,
1078 .geint_pend
= EXYNOS_GPIO_EPEND_OFFSET
,
1079 .svc
= EXYNOS_SVC_OFFSET
,
1080 .eint_gpio_init
= exynos_eint_gpio_init
,
1081 .label
= "exynos5420-gpio-ctrl2",
1083 /* pin-controller instance 3 data */
1084 .pin_banks
= exynos5420_pin_banks3
,
1085 .nr_banks
= ARRAY_SIZE(exynos5420_pin_banks3
),
1086 .geint_con
= EXYNOS_GPIO_ECON_OFFSET
,
1087 .geint_mask
= EXYNOS_GPIO_EMASK_OFFSET
,
1088 .geint_pend
= EXYNOS_GPIO_EPEND_OFFSET
,
1089 .svc
= EXYNOS_SVC_OFFSET
,
1090 .eint_gpio_init
= exynos_eint_gpio_init
,
1091 .label
= "exynos5420-gpio-ctrl3",
1093 /* pin-controller instance 4 data */
1094 .pin_banks
= exynos5420_pin_banks4
,
1095 .nr_banks
= ARRAY_SIZE(exynos5420_pin_banks4
),
1096 .geint_con
= EXYNOS_GPIO_ECON_OFFSET
,
1097 .geint_mask
= EXYNOS_GPIO_EMASK_OFFSET
,
1098 .geint_pend
= EXYNOS_GPIO_EPEND_OFFSET
,
1099 .svc
= EXYNOS_SVC_OFFSET
,
1100 .eint_gpio_init
= exynos_eint_gpio_init
,
1101 .label
= "exynos5420-gpio-ctrl4",