2 * Core driver for the imx pin controller
4 * Copyright (C) 2012 Freescale Semiconductor, Inc.
5 * Copyright (C) 2012 Linaro Ltd.
7 * Author: Dong Aisheng <dong.aisheng@linaro.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #include <linux/err.h>
16 #include <linux/init.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/pinctrl/pinctrl.h>
24 #include <linux/pinctrl/pinmux.h>
25 #include <linux/slab.h>
28 #include "pinctrl-imx.h"
30 /* The bits in CONFIG cell defined in binding doc*/
31 #define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */
32 #define IMX_PAD_SION 0x40000000 /* set SION */
35 * @dev: a pointer back to containing device
36 * @base: the offset to the controller in virtual memory
40 struct pinctrl_dev
*pctl
;
42 const struct imx_pinctrl_soc_info
*info
;
45 static const inline struct imx_pin_group
*imx_pinctrl_find_group_by_name(
46 const struct imx_pinctrl_soc_info
*info
,
49 const struct imx_pin_group
*grp
= NULL
;
52 for (i
= 0; i
< info
->ngroups
; i
++) {
53 if (!strcmp(info
->groups
[i
].name
, name
)) {
54 grp
= &info
->groups
[i
];
62 static int imx_get_groups_count(struct pinctrl_dev
*pctldev
)
64 struct imx_pinctrl
*ipctl
= pinctrl_dev_get_drvdata(pctldev
);
65 const struct imx_pinctrl_soc_info
*info
= ipctl
->info
;
70 static const char *imx_get_group_name(struct pinctrl_dev
*pctldev
,
73 struct imx_pinctrl
*ipctl
= pinctrl_dev_get_drvdata(pctldev
);
74 const struct imx_pinctrl_soc_info
*info
= ipctl
->info
;
76 return info
->groups
[selector
].name
;
79 static int imx_get_group_pins(struct pinctrl_dev
*pctldev
, unsigned selector
,
80 const unsigned **pins
,
83 struct imx_pinctrl
*ipctl
= pinctrl_dev_get_drvdata(pctldev
);
84 const struct imx_pinctrl_soc_info
*info
= ipctl
->info
;
86 if (selector
>= info
->ngroups
)
89 *pins
= info
->groups
[selector
].pin_ids
;
90 *npins
= info
->groups
[selector
].npins
;
95 static void imx_pin_dbg_show(struct pinctrl_dev
*pctldev
, struct seq_file
*s
,
98 seq_printf(s
, "%s", dev_name(pctldev
->dev
));
101 static int imx_dt_node_to_map(struct pinctrl_dev
*pctldev
,
102 struct device_node
*np
,
103 struct pinctrl_map
**map
, unsigned *num_maps
)
105 struct imx_pinctrl
*ipctl
= pinctrl_dev_get_drvdata(pctldev
);
106 const struct imx_pinctrl_soc_info
*info
= ipctl
->info
;
107 const struct imx_pin_group
*grp
;
108 struct pinctrl_map
*new_map
;
109 struct device_node
*parent
;
114 * first find the group of this node and check if we need create
115 * config maps for pins
117 grp
= imx_pinctrl_find_group_by_name(info
, np
->name
);
119 dev_err(info
->dev
, "unable to find group for node %s\n",
124 for (i
= 0; i
< grp
->npins
; i
++) {
125 if (!(grp
->pins
[i
].config
& IMX_NO_PAD_CTL
))
129 new_map
= kmalloc(sizeof(struct pinctrl_map
) * map_num
, GFP_KERNEL
);
137 parent
= of_get_parent(np
);
142 new_map
[0].type
= PIN_MAP_TYPE_MUX_GROUP
;
143 new_map
[0].data
.mux
.function
= parent
->name
;
144 new_map
[0].data
.mux
.group
= np
->name
;
147 /* create config map */
149 for (i
= j
= 0; i
< grp
->npins
; i
++) {
150 if (!(grp
->pins
[i
].config
& IMX_NO_PAD_CTL
)) {
151 new_map
[j
].type
= PIN_MAP_TYPE_CONFIGS_PIN
;
152 new_map
[j
].data
.configs
.group_or_pin
=
153 pin_get_name(pctldev
, grp
->pins
[i
].pin
);
154 new_map
[j
].data
.configs
.configs
= &grp
->pins
[i
].config
;
155 new_map
[j
].data
.configs
.num_configs
= 1;
160 dev_dbg(pctldev
->dev
, "maps: function %s group %s num %d\n",
161 (*map
)->data
.mux
.function
, (*map
)->data
.mux
.group
, map_num
);
166 static void imx_dt_free_map(struct pinctrl_dev
*pctldev
,
167 struct pinctrl_map
*map
, unsigned num_maps
)
172 static const struct pinctrl_ops imx_pctrl_ops
= {
173 .get_groups_count
= imx_get_groups_count
,
174 .get_group_name
= imx_get_group_name
,
175 .get_group_pins
= imx_get_group_pins
,
176 .pin_dbg_show
= imx_pin_dbg_show
,
177 .dt_node_to_map
= imx_dt_node_to_map
,
178 .dt_free_map
= imx_dt_free_map
,
182 static int imx_pmx_enable(struct pinctrl_dev
*pctldev
, unsigned selector
,
185 struct imx_pinctrl
*ipctl
= pinctrl_dev_get_drvdata(pctldev
);
186 const struct imx_pinctrl_soc_info
*info
= ipctl
->info
;
187 const struct imx_pin_reg
*pin_reg
;
188 unsigned int npins
, pin_id
;
190 struct imx_pin_group
*grp
;
193 * Configure the mux mode for each pin in the group for a specific
196 grp
= &info
->groups
[group
];
199 dev_dbg(ipctl
->dev
, "enable function %s group %s\n",
200 info
->functions
[selector
].name
, grp
->name
);
202 for (i
= 0; i
< npins
; i
++) {
203 struct imx_pin
*pin
= &grp
->pins
[i
];
205 pin_reg
= &info
->pin_regs
[pin_id
];
207 if (!(info
->flags
& ZERO_OFFSET_VALID
) && !pin_reg
->mux_reg
) {
208 dev_err(ipctl
->dev
, "Pin(%s) does not support mux function\n",
209 info
->pins
[pin_id
].name
);
213 if (info
->flags
& SHARE_MUX_CONF_REG
) {
215 reg
= readl(ipctl
->base
+ pin_reg
->mux_reg
);
217 reg
|= (pin
->mux_mode
<< 20);
218 writel(reg
, ipctl
->base
+ pin_reg
->mux_reg
);
220 writel(pin
->mux_mode
, ipctl
->base
+ pin_reg
->mux_reg
);
222 dev_dbg(ipctl
->dev
, "write: offset 0x%x val 0x%x\n",
223 pin_reg
->mux_reg
, pin
->mux_mode
);
226 * If the select input value begins with 0xff, it's a quirky
227 * select input and the value should be interpreted as below.
229 * | 0xff | shift | width | select |
230 * It's used to work around the problem that the select
231 * input for some pin is not implemented in the select
232 * input register but in some general purpose register.
233 * We encode the select input value, width and shift of
234 * the bit field into input_val cell of pin function ID
235 * in device tree, and then decode them here for setting
236 * up the select input bits in general purpose register.
238 if (pin
->input_val
>> 24 == 0xff) {
239 u32 val
= pin
->input_val
;
240 u8 select
= val
& 0xff;
241 u8 width
= (val
>> 8) & 0xff;
242 u8 shift
= (val
>> 16) & 0xff;
243 u32 mask
= ((1 << width
) - 1) << shift
;
245 * The input_reg[i] here is actually some IOMUXC general
246 * purpose register, not regular select input register.
248 val
= readl(ipctl
->base
+ pin
->input_val
);
250 val
|= select
<< shift
;
251 writel(val
, ipctl
->base
+ pin
->input_val
);
252 } else if (pin
->input_val
) {
254 * Regular select input register can never be at offset
255 * 0, and we only print register value for regular case.
257 writel(pin
->input_val
, ipctl
->base
+ pin
->input_reg
);
259 "==>select_input: offset 0x%x val 0x%x\n",
260 pin
->input_reg
, pin
->input_val
);
267 static int imx_pmx_get_funcs_count(struct pinctrl_dev
*pctldev
)
269 struct imx_pinctrl
*ipctl
= pinctrl_dev_get_drvdata(pctldev
);
270 const struct imx_pinctrl_soc_info
*info
= ipctl
->info
;
272 return info
->nfunctions
;
275 static const char *imx_pmx_get_func_name(struct pinctrl_dev
*pctldev
,
278 struct imx_pinctrl
*ipctl
= pinctrl_dev_get_drvdata(pctldev
);
279 const struct imx_pinctrl_soc_info
*info
= ipctl
->info
;
281 return info
->functions
[selector
].name
;
284 static int imx_pmx_get_groups(struct pinctrl_dev
*pctldev
, unsigned selector
,
285 const char * const **groups
,
286 unsigned * const num_groups
)
288 struct imx_pinctrl
*ipctl
= pinctrl_dev_get_drvdata(pctldev
);
289 const struct imx_pinctrl_soc_info
*info
= ipctl
->info
;
291 *groups
= info
->functions
[selector
].groups
;
292 *num_groups
= info
->functions
[selector
].num_groups
;
297 static const struct pinmux_ops imx_pmx_ops
= {
298 .get_functions_count
= imx_pmx_get_funcs_count
,
299 .get_function_name
= imx_pmx_get_func_name
,
300 .get_function_groups
= imx_pmx_get_groups
,
301 .enable
= imx_pmx_enable
,
304 static int imx_pinconf_get(struct pinctrl_dev
*pctldev
,
305 unsigned pin_id
, unsigned long *config
)
307 struct imx_pinctrl
*ipctl
= pinctrl_dev_get_drvdata(pctldev
);
308 const struct imx_pinctrl_soc_info
*info
= ipctl
->info
;
309 const struct imx_pin_reg
*pin_reg
= &info
->pin_regs
[pin_id
];
311 if (!(info
->flags
& ZERO_OFFSET_VALID
) && !pin_reg
->conf_reg
) {
312 dev_err(info
->dev
, "Pin(%s) does not support config function\n",
313 info
->pins
[pin_id
].name
);
317 *config
= readl(ipctl
->base
+ pin_reg
->conf_reg
);
319 if (info
->flags
& SHARE_MUX_CONF_REG
)
325 static int imx_pinconf_set(struct pinctrl_dev
*pctldev
,
326 unsigned pin_id
, unsigned long config
)
328 struct imx_pinctrl
*ipctl
= pinctrl_dev_get_drvdata(pctldev
);
329 const struct imx_pinctrl_soc_info
*info
= ipctl
->info
;
330 const struct imx_pin_reg
*pin_reg
= &info
->pin_regs
[pin_id
];
332 if (!(info
->flags
& ZERO_OFFSET_VALID
) && !pin_reg
->conf_reg
) {
333 dev_err(info
->dev
, "Pin(%s) does not support config function\n",
334 info
->pins
[pin_id
].name
);
338 dev_dbg(ipctl
->dev
, "pinconf set pin %s\n",
339 info
->pins
[pin_id
].name
);
341 if (info
->flags
& SHARE_MUX_CONF_REG
) {
343 reg
= readl(ipctl
->base
+ pin_reg
->conf_reg
);
346 writel(reg
, ipctl
->base
+ pin_reg
->conf_reg
);
348 writel(config
, ipctl
->base
+ pin_reg
->conf_reg
);
350 dev_dbg(ipctl
->dev
, "write: offset 0x%x val 0x%lx\n",
351 pin_reg
->conf_reg
, config
);
356 static void imx_pinconf_dbg_show(struct pinctrl_dev
*pctldev
,
357 struct seq_file
*s
, unsigned pin_id
)
359 struct imx_pinctrl
*ipctl
= pinctrl_dev_get_drvdata(pctldev
);
360 const struct imx_pinctrl_soc_info
*info
= ipctl
->info
;
361 const struct imx_pin_reg
*pin_reg
= &info
->pin_regs
[pin_id
];
362 unsigned long config
;
364 if (!pin_reg
|| !pin_reg
->conf_reg
) {
365 seq_printf(s
, "N/A");
369 config
= readl(ipctl
->base
+ pin_reg
->conf_reg
);
370 seq_printf(s
, "0x%lx", config
);
373 static void imx_pinconf_group_dbg_show(struct pinctrl_dev
*pctldev
,
374 struct seq_file
*s
, unsigned group
)
376 struct imx_pinctrl
*ipctl
= pinctrl_dev_get_drvdata(pctldev
);
377 const struct imx_pinctrl_soc_info
*info
= ipctl
->info
;
378 struct imx_pin_group
*grp
;
379 unsigned long config
;
383 if (group
> info
->ngroups
)
387 grp
= &info
->groups
[group
];
388 for (i
= 0; i
< grp
->npins
; i
++) {
389 struct imx_pin
*pin
= &grp
->pins
[i
];
390 name
= pin_get_name(pctldev
, pin
->pin
);
391 ret
= imx_pinconf_get(pctldev
, pin
->pin
, &config
);
394 seq_printf(s
, "%s: 0x%lx", name
, config
);
398 static const struct pinconf_ops imx_pinconf_ops
= {
399 .pin_config_get
= imx_pinconf_get
,
400 .pin_config_set
= imx_pinconf_set
,
401 .pin_config_dbg_show
= imx_pinconf_dbg_show
,
402 .pin_config_group_dbg_show
= imx_pinconf_group_dbg_show
,
405 static struct pinctrl_desc imx_pinctrl_desc
= {
406 .pctlops
= &imx_pctrl_ops
,
407 .pmxops
= &imx_pmx_ops
,
408 .confops
= &imx_pinconf_ops
,
409 .owner
= THIS_MODULE
,
413 * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
414 * 1 u32 CONFIG, so 24 types in total for each pin.
416 #define FSL_PIN_SIZE 24
417 #define SHARE_FSL_PIN_SIZE 20
419 static int imx_pinctrl_parse_groups(struct device_node
*np
,
420 struct imx_pin_group
*grp
,
421 struct imx_pinctrl_soc_info
*info
,
429 dev_dbg(info
->dev
, "group(%d): %s\n", index
, np
->name
);
431 if (info
->flags
& SHARE_MUX_CONF_REG
)
432 pin_size
= SHARE_FSL_PIN_SIZE
;
434 pin_size
= FSL_PIN_SIZE
;
435 /* Initialise group */
436 grp
->name
= np
->name
;
439 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
440 * do sanity check and calculate pins number
442 list
= of_get_property(np
, "fsl,pins", &size
);
444 dev_err(info
->dev
, "no fsl,pins property in node %s\n", np
->full_name
);
448 /* we do not check return since it's safe node passed down */
449 if (!size
|| size
% pin_size
) {
450 dev_err(info
->dev
, "Invalid fsl,pins property in node %s\n", np
->full_name
);
454 grp
->npins
= size
/ pin_size
;
455 grp
->pins
= devm_kzalloc(info
->dev
, grp
->npins
* sizeof(struct imx_pin
),
457 grp
->pin_ids
= devm_kzalloc(info
->dev
, grp
->npins
* sizeof(unsigned int),
459 if (!grp
->pins
|| ! grp
->pin_ids
)
462 for (i
= 0; i
< grp
->npins
; i
++) {
463 u32 mux_reg
= be32_to_cpu(*list
++);
466 struct imx_pin_reg
*pin_reg
;
467 struct imx_pin
*pin
= &grp
->pins
[i
];
469 if (info
->flags
& SHARE_MUX_CONF_REG
)
472 conf_reg
= be32_to_cpu(*list
++);
474 pin_id
= mux_reg
? mux_reg
/ 4 : conf_reg
/ 4;
475 pin_reg
= &info
->pin_regs
[pin_id
];
477 grp
->pin_ids
[i
] = pin_id
;
478 pin_reg
->mux_reg
= mux_reg
;
479 pin_reg
->conf_reg
= conf_reg
;
480 pin
->input_reg
= be32_to_cpu(*list
++);
481 pin
->mux_mode
= be32_to_cpu(*list
++);
482 pin
->input_val
= be32_to_cpu(*list
++);
484 /* SION bit is in mux register */
485 config
= be32_to_cpu(*list
++);
486 if (config
& IMX_PAD_SION
)
487 pin
->mux_mode
|= IOMUXC_CONFIG_SION
;
488 pin
->config
= config
& ~IMX_PAD_SION
;
490 dev_dbg(info
->dev
, "%s: %d 0x%08lx", info
->pins
[i
].name
,
491 pin
->mux_mode
, pin
->config
);
497 static int imx_pinctrl_parse_functions(struct device_node
*np
,
498 struct imx_pinctrl_soc_info
*info
,
501 struct device_node
*child
;
502 struct imx_pmx_func
*func
;
503 struct imx_pin_group
*grp
;
504 static u32 grp_index
;
507 dev_dbg(info
->dev
, "parse function(%d): %s\n", index
, np
->name
);
509 func
= &info
->functions
[index
];
511 /* Initialise function */
512 func
->name
= np
->name
;
513 func
->num_groups
= of_get_child_count(np
);
514 if (func
->num_groups
<= 0) {
515 dev_err(info
->dev
, "no groups defined in %s\n", np
->full_name
);
518 func
->groups
= devm_kzalloc(info
->dev
,
519 func
->num_groups
* sizeof(char *), GFP_KERNEL
);
521 for_each_child_of_node(np
, child
) {
522 func
->groups
[i
] = child
->name
;
523 grp
= &info
->groups
[grp_index
++];
524 imx_pinctrl_parse_groups(child
, grp
, info
, i
++);
530 static int imx_pinctrl_probe_dt(struct platform_device
*pdev
,
531 struct imx_pinctrl_soc_info
*info
)
533 struct device_node
*np
= pdev
->dev
.of_node
;
534 struct device_node
*child
;
541 nfuncs
= of_get_child_count(np
);
543 dev_err(&pdev
->dev
, "no functions defined\n");
547 info
->nfunctions
= nfuncs
;
548 info
->functions
= devm_kzalloc(&pdev
->dev
, nfuncs
* sizeof(struct imx_pmx_func
),
550 if (!info
->functions
)
554 for_each_child_of_node(np
, child
)
555 info
->ngroups
+= of_get_child_count(child
);
556 info
->groups
= devm_kzalloc(&pdev
->dev
, info
->ngroups
* sizeof(struct imx_pin_group
),
561 for_each_child_of_node(np
, child
)
562 imx_pinctrl_parse_functions(child
, info
, i
++);
567 int imx_pinctrl_probe(struct platform_device
*pdev
,
568 struct imx_pinctrl_soc_info
*info
)
570 struct imx_pinctrl
*ipctl
;
571 struct resource
*res
;
574 if (!info
|| !info
->pins
|| !info
->npins
) {
575 dev_err(&pdev
->dev
, "wrong pinctrl info\n");
578 info
->dev
= &pdev
->dev
;
580 /* Create state holders etc for this driver */
581 ipctl
= devm_kzalloc(&pdev
->dev
, sizeof(*ipctl
), GFP_KERNEL
);
585 info
->pin_regs
= devm_kzalloc(&pdev
->dev
, sizeof(*info
->pin_regs
) *
586 info
->npins
, GFP_KERNEL
);
590 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
591 ipctl
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
592 if (IS_ERR(ipctl
->base
))
593 return PTR_ERR(ipctl
->base
);
595 imx_pinctrl_desc
.name
= dev_name(&pdev
->dev
);
596 imx_pinctrl_desc
.pins
= info
->pins
;
597 imx_pinctrl_desc
.npins
= info
->npins
;
599 ret
= imx_pinctrl_probe_dt(pdev
, info
);
601 dev_err(&pdev
->dev
, "fail to probe dt properties\n");
606 ipctl
->dev
= info
->dev
;
607 platform_set_drvdata(pdev
, ipctl
);
608 ipctl
->pctl
= pinctrl_register(&imx_pinctrl_desc
, &pdev
->dev
, ipctl
);
610 dev_err(&pdev
->dev
, "could not register IMX pinctrl driver\n");
614 dev_info(&pdev
->dev
, "initialized IMX pinctrl driver\n");
619 int imx_pinctrl_remove(struct platform_device
*pdev
)
621 struct imx_pinctrl
*ipctl
= platform_get_drvdata(pdev
);
623 pinctrl_unregister(ipctl
->pctl
);