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pinctrl/nomadik: !CONFIG_OF build error
[deliverable/linux.git] / drivers / pinctrl / pinctrl-nomadik.c
1 /*
2 * Generic GPIO driver for logic cells found in the Nomadik SoC
3 *
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/device.h>
17 #include <linux/platform_device.h>
18 #include <linux/io.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/irqdomain.h>
26 #include <linux/slab.h>
27
28 #include <asm/mach/irq.h>
29
30 #include <plat/pincfg.h>
31 #include <plat/gpio-nomadik.h>
32
33 /*
34 * The GPIO module in the Nomadik family of Systems-on-Chip is an
35 * AMBA device, managing 32 pins and alternate functions. The logic block
36 * is currently used in the Nomadik and ux500.
37 *
38 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
39 */
40
41 #define NMK_GPIO_PER_CHIP 32
42
43 struct nmk_gpio_chip {
44 struct gpio_chip chip;
45 struct irq_domain *domain;
46 void __iomem *addr;
47 struct clk *clk;
48 unsigned int bank;
49 unsigned int parent_irq;
50 int secondary_parent_irq;
51 u32 (*get_secondary_status)(unsigned int bank);
52 void (*set_ioforce)(bool enable);
53 spinlock_t lock;
54 bool sleepmode;
55 /* Keep track of configured edges */
56 u32 edge_rising;
57 u32 edge_falling;
58 u32 real_wake;
59 u32 rwimsc;
60 u32 fwimsc;
61 u32 rimsc;
62 u32 fimsc;
63 u32 pull_up;
64 u32 lowemi;
65 };
66
67 static struct nmk_gpio_chip *
68 nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
69
70 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
71
72 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
73
74 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
75 unsigned offset, int gpio_mode)
76 {
77 u32 bit = 1 << offset;
78 u32 afunc, bfunc;
79
80 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
81 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
82 if (gpio_mode & NMK_GPIO_ALT_A)
83 afunc |= bit;
84 if (gpio_mode & NMK_GPIO_ALT_B)
85 bfunc |= bit;
86 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
87 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
88 }
89
90 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
91 unsigned offset, enum nmk_gpio_slpm mode)
92 {
93 u32 bit = 1 << offset;
94 u32 slpm;
95
96 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
97 if (mode == NMK_GPIO_SLPM_NOCHANGE)
98 slpm |= bit;
99 else
100 slpm &= ~bit;
101 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
102 }
103
104 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
105 unsigned offset, enum nmk_gpio_pull pull)
106 {
107 u32 bit = 1 << offset;
108 u32 pdis;
109
110 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
111 if (pull == NMK_GPIO_PULL_NONE) {
112 pdis |= bit;
113 nmk_chip->pull_up &= ~bit;
114 } else {
115 pdis &= ~bit;
116 }
117
118 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
119
120 if (pull == NMK_GPIO_PULL_UP) {
121 nmk_chip->pull_up |= bit;
122 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
123 } else if (pull == NMK_GPIO_PULL_DOWN) {
124 nmk_chip->pull_up &= ~bit;
125 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
126 }
127 }
128
129 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
130 unsigned offset, bool lowemi)
131 {
132 u32 bit = BIT(offset);
133 bool enabled = nmk_chip->lowemi & bit;
134
135 if (lowemi == enabled)
136 return;
137
138 if (lowemi)
139 nmk_chip->lowemi |= bit;
140 else
141 nmk_chip->lowemi &= ~bit;
142
143 writel_relaxed(nmk_chip->lowemi,
144 nmk_chip->addr + NMK_GPIO_LOWEMI);
145 }
146
147 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
148 unsigned offset)
149 {
150 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
151 }
152
153 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
154 unsigned offset, int val)
155 {
156 if (val)
157 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
158 else
159 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
160 }
161
162 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
163 unsigned offset, int val)
164 {
165 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
166 __nmk_gpio_set_output(nmk_chip, offset, val);
167 }
168
169 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
170 unsigned offset, int gpio_mode,
171 bool glitch)
172 {
173 u32 rwimsc = nmk_chip->rwimsc;
174 u32 fwimsc = nmk_chip->fwimsc;
175
176 if (glitch && nmk_chip->set_ioforce) {
177 u32 bit = BIT(offset);
178
179 /* Prevent spurious wakeups */
180 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
181 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
182
183 nmk_chip->set_ioforce(true);
184 }
185
186 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
187
188 if (glitch && nmk_chip->set_ioforce) {
189 nmk_chip->set_ioforce(false);
190
191 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
192 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
193 }
194 }
195
196 static void
197 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
198 {
199 u32 falling = nmk_chip->fimsc & BIT(offset);
200 u32 rising = nmk_chip->rimsc & BIT(offset);
201 int gpio = nmk_chip->chip.base + offset;
202 int irq = NOMADIK_GPIO_TO_IRQ(gpio);
203 struct irq_data *d = irq_get_irq_data(irq);
204
205 if (!rising && !falling)
206 return;
207
208 if (!d || !irqd_irq_disabled(d))
209 return;
210
211 if (rising) {
212 nmk_chip->rimsc &= ~BIT(offset);
213 writel_relaxed(nmk_chip->rimsc,
214 nmk_chip->addr + NMK_GPIO_RIMSC);
215 }
216
217 if (falling) {
218 nmk_chip->fimsc &= ~BIT(offset);
219 writel_relaxed(nmk_chip->fimsc,
220 nmk_chip->addr + NMK_GPIO_FIMSC);
221 }
222
223 dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
224 }
225
226 static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
227 pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
228 {
229 static const char *afnames[] = {
230 [NMK_GPIO_ALT_GPIO] = "GPIO",
231 [NMK_GPIO_ALT_A] = "A",
232 [NMK_GPIO_ALT_B] = "B",
233 [NMK_GPIO_ALT_C] = "C"
234 };
235 static const char *pullnames[] = {
236 [NMK_GPIO_PULL_NONE] = "none",
237 [NMK_GPIO_PULL_UP] = "up",
238 [NMK_GPIO_PULL_DOWN] = "down",
239 [3] /* illegal */ = "??"
240 };
241 static const char *slpmnames[] = {
242 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
243 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
244 };
245
246 int pin = PIN_NUM(cfg);
247 int pull = PIN_PULL(cfg);
248 int af = PIN_ALT(cfg);
249 int slpm = PIN_SLPM(cfg);
250 int output = PIN_DIR(cfg);
251 int val = PIN_VAL(cfg);
252 bool glitch = af == NMK_GPIO_ALT_C;
253
254 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
255 pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
256 output ? "output " : "input",
257 output ? (val ? "high" : "low") : "");
258
259 if (sleep) {
260 int slpm_pull = PIN_SLPM_PULL(cfg);
261 int slpm_output = PIN_SLPM_DIR(cfg);
262 int slpm_val = PIN_SLPM_VAL(cfg);
263
264 af = NMK_GPIO_ALT_GPIO;
265
266 /*
267 * The SLPM_* values are normal values + 1 to allow zero to
268 * mean "same as normal".
269 */
270 if (slpm_pull)
271 pull = slpm_pull - 1;
272 if (slpm_output)
273 output = slpm_output - 1;
274 if (slpm_val)
275 val = slpm_val - 1;
276
277 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
278 pin,
279 slpm_pull ? pullnames[pull] : "same",
280 slpm_output ? (output ? "output" : "input") : "same",
281 slpm_val ? (val ? "high" : "low") : "same");
282 }
283
284 if (output)
285 __nmk_gpio_make_output(nmk_chip, offset, val);
286 else {
287 __nmk_gpio_make_input(nmk_chip, offset);
288 __nmk_gpio_set_pull(nmk_chip, offset, pull);
289 }
290
291 __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg));
292
293 /*
294 * If the pin is switching to altfunc, and there was an interrupt
295 * installed on it which has been lazy disabled, actually mask the
296 * interrupt to prevent spurious interrupts that would occur while the
297 * pin is under control of the peripheral. Only SKE does this.
298 */
299 if (af != NMK_GPIO_ALT_GPIO)
300 nmk_gpio_disable_lazy_irq(nmk_chip, offset);
301
302 /*
303 * If we've backed up the SLPM registers (glitch workaround), modify
304 * the backups since they will be restored.
305 */
306 if (slpmregs) {
307 if (slpm == NMK_GPIO_SLPM_NOCHANGE)
308 slpmregs[nmk_chip->bank] |= BIT(offset);
309 else
310 slpmregs[nmk_chip->bank] &= ~BIT(offset);
311 } else
312 __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
313
314 __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
315 }
316
317 /*
318 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
319 * - Save SLPM registers
320 * - Set SLPM=0 for the IOs you want to switch and others to 1
321 * - Configure the GPIO registers for the IOs that are being switched
322 * - Set IOFORCE=1
323 * - Modify the AFLSA/B registers for the IOs that are being switched
324 * - Set IOFORCE=0
325 * - Restore SLPM registers
326 * - Any spurious wake up event during switch sequence to be ignored and
327 * cleared
328 */
329 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
330 {
331 int i;
332
333 for (i = 0; i < NUM_BANKS; i++) {
334 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
335 unsigned int temp = slpm[i];
336
337 if (!chip)
338 break;
339
340 clk_enable(chip->clk);
341
342 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
343 writel(temp, chip->addr + NMK_GPIO_SLPC);
344 }
345 }
346
347 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
348 {
349 int i;
350
351 for (i = 0; i < NUM_BANKS; i++) {
352 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
353
354 if (!chip)
355 break;
356
357 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
358
359 clk_disable(chip->clk);
360 }
361 }
362
363 static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
364 {
365 static unsigned int slpm[NUM_BANKS];
366 unsigned long flags;
367 bool glitch = false;
368 int ret = 0;
369 int i;
370
371 for (i = 0; i < num; i++) {
372 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
373 glitch = true;
374 break;
375 }
376 }
377
378 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
379
380 if (glitch) {
381 memset(slpm, 0xff, sizeof(slpm));
382
383 for (i = 0; i < num; i++) {
384 int pin = PIN_NUM(cfgs[i]);
385 int offset = pin % NMK_GPIO_PER_CHIP;
386
387 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
388 slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
389 }
390
391 nmk_gpio_glitch_slpm_init(slpm);
392 }
393
394 for (i = 0; i < num; i++) {
395 struct nmk_gpio_chip *nmk_chip;
396 int pin = PIN_NUM(cfgs[i]);
397
398 nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP];
399 if (!nmk_chip) {
400 ret = -EINVAL;
401 break;
402 }
403
404 clk_enable(nmk_chip->clk);
405 spin_lock(&nmk_chip->lock);
406 __nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP,
407 cfgs[i], sleep, glitch ? slpm : NULL);
408 spin_unlock(&nmk_chip->lock);
409 clk_disable(nmk_chip->clk);
410 }
411
412 if (glitch)
413 nmk_gpio_glitch_slpm_restore(slpm);
414
415 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
416
417 return ret;
418 }
419
420 /**
421 * nmk_config_pin - configure a pin's mux attributes
422 * @cfg: pin confguration
423 *
424 * Configures a pin's mode (alternate function or GPIO), its pull up status,
425 * and its sleep mode based on the specified configuration. The @cfg is
426 * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
427 * are constructed using, and can be further enhanced with, the macros in
428 * plat/pincfg.h.
429 *
430 * If a pin's mode is set to GPIO, it is configured as an input to avoid
431 * side-effects. The gpio can be manipulated later using standard GPIO API
432 * calls.
433 */
434 int nmk_config_pin(pin_cfg_t cfg, bool sleep)
435 {
436 return __nmk_config_pins(&cfg, 1, sleep);
437 }
438 EXPORT_SYMBOL(nmk_config_pin);
439
440 /**
441 * nmk_config_pins - configure several pins at once
442 * @cfgs: array of pin configurations
443 * @num: number of elments in the array
444 *
445 * Configures several pins using nmk_config_pin(). Refer to that function for
446 * further information.
447 */
448 int nmk_config_pins(pin_cfg_t *cfgs, int num)
449 {
450 return __nmk_config_pins(cfgs, num, false);
451 }
452 EXPORT_SYMBOL(nmk_config_pins);
453
454 int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
455 {
456 return __nmk_config_pins(cfgs, num, true);
457 }
458 EXPORT_SYMBOL(nmk_config_pins_sleep);
459
460 /**
461 * nmk_gpio_set_slpm() - configure the sleep mode of a pin
462 * @gpio: pin number
463 * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
464 *
465 * This register is actually in the pinmux layer, not the GPIO block itself.
466 * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP
467 * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code).
468 * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is
469 * HIGH, overriding the normal setting defined by GPIO_AFSELx registers.
470 * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit),
471 * the GPIOs return to the normal setting defined by GPIO_AFSELx registers.
472 *
473 * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO
474 * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is
475 * entered) regardless of the altfunction selected. Also wake-up detection is
476 * ENABLED.
477 *
478 * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains
479 * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS
480 * (for altfunction GPIO) or respective on-chip peripherals (for other
481 * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED.
482 *
483 * Note that enable_irq_wake() will automatically enable wakeup detection.
484 */
485 int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
486 {
487 struct nmk_gpio_chip *nmk_chip;
488 unsigned long flags;
489
490 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
491 if (!nmk_chip)
492 return -EINVAL;
493
494 clk_enable(nmk_chip->clk);
495 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
496 spin_lock(&nmk_chip->lock);
497
498 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode);
499
500 spin_unlock(&nmk_chip->lock);
501 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
502 clk_disable(nmk_chip->clk);
503
504 return 0;
505 }
506
507 /**
508 * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
509 * @gpio: pin number
510 * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
511 *
512 * Enables/disables pull up/down on a specified pin. This only takes effect if
513 * the pin is configured as an input (either explicitly or by the alternate
514 * function).
515 *
516 * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
517 * configured as an input. Otherwise, due to the way the controller registers
518 * work, this function will change the value output on the pin.
519 */
520 int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
521 {
522 struct nmk_gpio_chip *nmk_chip;
523 unsigned long flags;
524
525 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
526 if (!nmk_chip)
527 return -EINVAL;
528
529 clk_enable(nmk_chip->clk);
530 spin_lock_irqsave(&nmk_chip->lock, flags);
531 __nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull);
532 spin_unlock_irqrestore(&nmk_chip->lock, flags);
533 clk_disable(nmk_chip->clk);
534
535 return 0;
536 }
537
538 /* Mode functions */
539 /**
540 * nmk_gpio_set_mode() - set the mux mode of a gpio pin
541 * @gpio: pin number
542 * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
543 * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
544 *
545 * Sets the mode of the specified pin to one of the alternate functions or
546 * plain GPIO.
547 */
548 int nmk_gpio_set_mode(int gpio, int gpio_mode)
549 {
550 struct nmk_gpio_chip *nmk_chip;
551 unsigned long flags;
552
553 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
554 if (!nmk_chip)
555 return -EINVAL;
556
557 clk_enable(nmk_chip->clk);
558 spin_lock_irqsave(&nmk_chip->lock, flags);
559 __nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode);
560 spin_unlock_irqrestore(&nmk_chip->lock, flags);
561 clk_disable(nmk_chip->clk);
562
563 return 0;
564 }
565 EXPORT_SYMBOL(nmk_gpio_set_mode);
566
567 int nmk_gpio_get_mode(int gpio)
568 {
569 struct nmk_gpio_chip *nmk_chip;
570 u32 afunc, bfunc, bit;
571
572 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
573 if (!nmk_chip)
574 return -EINVAL;
575
576 bit = 1 << (gpio % NMK_GPIO_PER_CHIP);
577
578 clk_enable(nmk_chip->clk);
579
580 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
581 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
582
583 clk_disable(nmk_chip->clk);
584
585 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
586 }
587 EXPORT_SYMBOL(nmk_gpio_get_mode);
588
589
590 /* IRQ functions */
591 static inline int nmk_gpio_get_bitmask(int gpio)
592 {
593 return 1 << (gpio % NMK_GPIO_PER_CHIP);
594 }
595
596 static void nmk_gpio_irq_ack(struct irq_data *d)
597 {
598 struct nmk_gpio_chip *nmk_chip;
599
600 nmk_chip = irq_data_get_irq_chip_data(d);
601 if (!nmk_chip)
602 return;
603
604 clk_enable(nmk_chip->clk);
605 writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
606 clk_disable(nmk_chip->clk);
607 }
608
609 enum nmk_gpio_irq_type {
610 NORMAL,
611 WAKE,
612 };
613
614 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
615 int gpio, enum nmk_gpio_irq_type which,
616 bool enable)
617 {
618 u32 bitmask = nmk_gpio_get_bitmask(gpio);
619 u32 *rimscval;
620 u32 *fimscval;
621 u32 rimscreg;
622 u32 fimscreg;
623
624 if (which == NORMAL) {
625 rimscreg = NMK_GPIO_RIMSC;
626 fimscreg = NMK_GPIO_FIMSC;
627 rimscval = &nmk_chip->rimsc;
628 fimscval = &nmk_chip->fimsc;
629 } else {
630 rimscreg = NMK_GPIO_RWIMSC;
631 fimscreg = NMK_GPIO_FWIMSC;
632 rimscval = &nmk_chip->rwimsc;
633 fimscval = &nmk_chip->fwimsc;
634 }
635
636 /* we must individually set/clear the two edges */
637 if (nmk_chip->edge_rising & bitmask) {
638 if (enable)
639 *rimscval |= bitmask;
640 else
641 *rimscval &= ~bitmask;
642 writel(*rimscval, nmk_chip->addr + rimscreg);
643 }
644 if (nmk_chip->edge_falling & bitmask) {
645 if (enable)
646 *fimscval |= bitmask;
647 else
648 *fimscval &= ~bitmask;
649 writel(*fimscval, nmk_chip->addr + fimscreg);
650 }
651 }
652
653 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
654 int gpio, bool on)
655 {
656 /*
657 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
658 * disabled, since setting SLPM to 1 increases power consumption, and
659 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
660 */
661 if (nmk_chip->sleepmode && on) {
662 __nmk_gpio_set_slpm(nmk_chip, gpio % nmk_chip->chip.base,
663 NMK_GPIO_SLPM_WAKEUP_ENABLE);
664 }
665
666 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
667 }
668
669 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
670 {
671 struct nmk_gpio_chip *nmk_chip;
672 unsigned long flags;
673 u32 bitmask;
674
675 nmk_chip = irq_data_get_irq_chip_data(d);
676 bitmask = nmk_gpio_get_bitmask(d->hwirq);
677 if (!nmk_chip)
678 return -EINVAL;
679
680 clk_enable(nmk_chip->clk);
681 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
682 spin_lock(&nmk_chip->lock);
683
684 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
685
686 if (!(nmk_chip->real_wake & bitmask))
687 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
688
689 spin_unlock(&nmk_chip->lock);
690 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
691 clk_disable(nmk_chip->clk);
692
693 return 0;
694 }
695
696 static void nmk_gpio_irq_mask(struct irq_data *d)
697 {
698 nmk_gpio_irq_maskunmask(d, false);
699 }
700
701 static void nmk_gpio_irq_unmask(struct irq_data *d)
702 {
703 nmk_gpio_irq_maskunmask(d, true);
704 }
705
706 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
707 {
708 struct nmk_gpio_chip *nmk_chip;
709 unsigned long flags;
710 u32 bitmask;
711
712 nmk_chip = irq_data_get_irq_chip_data(d);
713 if (!nmk_chip)
714 return -EINVAL;
715 bitmask = nmk_gpio_get_bitmask(d->hwirq);
716
717 clk_enable(nmk_chip->clk);
718 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
719 spin_lock(&nmk_chip->lock);
720
721 if (irqd_irq_disabled(d))
722 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
723
724 if (on)
725 nmk_chip->real_wake |= bitmask;
726 else
727 nmk_chip->real_wake &= ~bitmask;
728
729 spin_unlock(&nmk_chip->lock);
730 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
731 clk_disable(nmk_chip->clk);
732
733 return 0;
734 }
735
736 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
737 {
738 bool enabled = !irqd_irq_disabled(d);
739 bool wake = irqd_is_wakeup_set(d);
740 struct nmk_gpio_chip *nmk_chip;
741 unsigned long flags;
742 u32 bitmask;
743
744 nmk_chip = irq_data_get_irq_chip_data(d);
745 bitmask = nmk_gpio_get_bitmask(d->hwirq);
746 if (!nmk_chip)
747 return -EINVAL;
748 if (type & IRQ_TYPE_LEVEL_HIGH)
749 return -EINVAL;
750 if (type & IRQ_TYPE_LEVEL_LOW)
751 return -EINVAL;
752
753 clk_enable(nmk_chip->clk);
754 spin_lock_irqsave(&nmk_chip->lock, flags);
755
756 if (enabled)
757 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
758
759 if (enabled || wake)
760 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
761
762 nmk_chip->edge_rising &= ~bitmask;
763 if (type & IRQ_TYPE_EDGE_RISING)
764 nmk_chip->edge_rising |= bitmask;
765
766 nmk_chip->edge_falling &= ~bitmask;
767 if (type & IRQ_TYPE_EDGE_FALLING)
768 nmk_chip->edge_falling |= bitmask;
769
770 if (enabled)
771 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
772
773 if (enabled || wake)
774 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
775
776 spin_unlock_irqrestore(&nmk_chip->lock, flags);
777 clk_disable(nmk_chip->clk);
778
779 return 0;
780 }
781
782 static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
783 {
784 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
785
786 clk_enable(nmk_chip->clk);
787 nmk_gpio_irq_unmask(d);
788 return 0;
789 }
790
791 static void nmk_gpio_irq_shutdown(struct irq_data *d)
792 {
793 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
794
795 nmk_gpio_irq_mask(d);
796 clk_disable(nmk_chip->clk);
797 }
798
799 static struct irq_chip nmk_gpio_irq_chip = {
800 .name = "Nomadik-GPIO",
801 .irq_ack = nmk_gpio_irq_ack,
802 .irq_mask = nmk_gpio_irq_mask,
803 .irq_unmask = nmk_gpio_irq_unmask,
804 .irq_set_type = nmk_gpio_irq_set_type,
805 .irq_set_wake = nmk_gpio_irq_set_wake,
806 .irq_startup = nmk_gpio_irq_startup,
807 .irq_shutdown = nmk_gpio_irq_shutdown,
808 };
809
810 static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
811 u32 status)
812 {
813 struct nmk_gpio_chip *nmk_chip;
814 struct irq_chip *host_chip = irq_get_chip(irq);
815 unsigned int first_irq;
816
817 chained_irq_enter(host_chip, desc);
818
819 nmk_chip = irq_get_handler_data(irq);
820 first_irq = nmk_chip->domain->revmap_data.legacy.first_irq;
821 while (status) {
822 int bit = __ffs(status);
823
824 generic_handle_irq(first_irq + bit);
825 status &= ~BIT(bit);
826 }
827
828 chained_irq_exit(host_chip, desc);
829 }
830
831 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
832 {
833 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
834 u32 status;
835
836 clk_enable(nmk_chip->clk);
837 status = readl(nmk_chip->addr + NMK_GPIO_IS);
838 clk_disable(nmk_chip->clk);
839
840 __nmk_gpio_irq_handler(irq, desc, status);
841 }
842
843 static void nmk_gpio_secondary_irq_handler(unsigned int irq,
844 struct irq_desc *desc)
845 {
846 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
847 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
848
849 __nmk_gpio_irq_handler(irq, desc, status);
850 }
851
852 static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
853 {
854 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
855 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
856
857 if (nmk_chip->secondary_parent_irq >= 0) {
858 irq_set_chained_handler(nmk_chip->secondary_parent_irq,
859 nmk_gpio_secondary_irq_handler);
860 irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
861 }
862
863 return 0;
864 }
865
866 /* I/O Functions */
867 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
868 {
869 struct nmk_gpio_chip *nmk_chip =
870 container_of(chip, struct nmk_gpio_chip, chip);
871
872 clk_enable(nmk_chip->clk);
873
874 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
875
876 clk_disable(nmk_chip->clk);
877
878 return 0;
879 }
880
881 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
882 {
883 struct nmk_gpio_chip *nmk_chip =
884 container_of(chip, struct nmk_gpio_chip, chip);
885 u32 bit = 1 << offset;
886 int value;
887
888 clk_enable(nmk_chip->clk);
889
890 value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
891
892 clk_disable(nmk_chip->clk);
893
894 return value;
895 }
896
897 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
898 int val)
899 {
900 struct nmk_gpio_chip *nmk_chip =
901 container_of(chip, struct nmk_gpio_chip, chip);
902
903 clk_enable(nmk_chip->clk);
904
905 __nmk_gpio_set_output(nmk_chip, offset, val);
906
907 clk_disable(nmk_chip->clk);
908 }
909
910 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
911 int val)
912 {
913 struct nmk_gpio_chip *nmk_chip =
914 container_of(chip, struct nmk_gpio_chip, chip);
915
916 clk_enable(nmk_chip->clk);
917
918 __nmk_gpio_make_output(nmk_chip, offset, val);
919
920 clk_disable(nmk_chip->clk);
921
922 return 0;
923 }
924
925 static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
926 {
927 struct nmk_gpio_chip *nmk_chip =
928 container_of(chip, struct nmk_gpio_chip, chip);
929
930 return irq_find_mapping(nmk_chip->domain, offset);
931 }
932
933 #ifdef CONFIG_DEBUG_FS
934
935 #include <linux/seq_file.h>
936
937 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
938 {
939 int mode;
940 unsigned i;
941 unsigned gpio = chip->base;
942 int is_out;
943 struct nmk_gpio_chip *nmk_chip =
944 container_of(chip, struct nmk_gpio_chip, chip);
945 const char *modes[] = {
946 [NMK_GPIO_ALT_GPIO] = "gpio",
947 [NMK_GPIO_ALT_A] = "altA",
948 [NMK_GPIO_ALT_B] = "altB",
949 [NMK_GPIO_ALT_C] = "altC",
950 };
951
952 clk_enable(nmk_chip->clk);
953
954 for (i = 0; i < chip->ngpio; i++, gpio++) {
955 const char *label = gpiochip_is_requested(chip, i);
956 bool pull;
957 u32 bit = 1 << i;
958
959 is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit;
960 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
961 mode = nmk_gpio_get_mode(gpio);
962 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
963 gpio, label ?: "(none)",
964 is_out ? "out" : "in ",
965 chip->get
966 ? (chip->get(chip, i) ? "hi" : "lo")
967 : "? ",
968 (mode < 0) ? "unknown" : modes[mode],
969 pull ? "pull" : "none");
970
971 if (label && !is_out) {
972 int irq = gpio_to_irq(gpio);
973 struct irq_desc *desc = irq_to_desc(irq);
974
975 /* This races with request_irq(), set_irq_type(),
976 * and set_irq_wake() ... but those are "rare".
977 */
978 if (irq >= 0 && desc->action) {
979 char *trigger;
980 u32 bitmask = nmk_gpio_get_bitmask(gpio);
981
982 if (nmk_chip->edge_rising & bitmask)
983 trigger = "edge-rising";
984 else if (nmk_chip->edge_falling & bitmask)
985 trigger = "edge-falling";
986 else
987 trigger = "edge-undefined";
988
989 seq_printf(s, " irq-%d %s%s",
990 irq, trigger,
991 irqd_is_wakeup_set(&desc->irq_data)
992 ? " wakeup" : "");
993 }
994 }
995
996 seq_printf(s, "\n");
997 }
998
999 clk_disable(nmk_chip->clk);
1000 }
1001
1002 #else
1003 #define nmk_gpio_dbg_show NULL
1004 #endif
1005
1006 /* This structure is replicated for each GPIO block allocated at probe time */
1007 static struct gpio_chip nmk_gpio_template = {
1008 .direction_input = nmk_gpio_make_input,
1009 .get = nmk_gpio_get_input,
1010 .direction_output = nmk_gpio_make_output,
1011 .set = nmk_gpio_set_output,
1012 .to_irq = nmk_gpio_to_irq,
1013 .dbg_show = nmk_gpio_dbg_show,
1014 .can_sleep = 0,
1015 };
1016
1017 void nmk_gpio_clocks_enable(void)
1018 {
1019 int i;
1020
1021 for (i = 0; i < NUM_BANKS; i++) {
1022 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1023
1024 if (!chip)
1025 continue;
1026
1027 clk_enable(chip->clk);
1028 }
1029 }
1030
1031 void nmk_gpio_clocks_disable(void)
1032 {
1033 int i;
1034
1035 for (i = 0; i < NUM_BANKS; i++) {
1036 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1037
1038 if (!chip)
1039 continue;
1040
1041 clk_disable(chip->clk);
1042 }
1043 }
1044
1045 /*
1046 * Called from the suspend/resume path to only keep the real wakeup interrupts
1047 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
1048 * and not the rest of the interrupts which we needed to have as wakeups for
1049 * cpuidle.
1050 *
1051 * PM ops are not used since this needs to be done at the end, after all the
1052 * other drivers are done with their suspend callbacks.
1053 */
1054 void nmk_gpio_wakeups_suspend(void)
1055 {
1056 int i;
1057
1058 for (i = 0; i < NUM_BANKS; i++) {
1059 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1060
1061 if (!chip)
1062 break;
1063
1064 clk_enable(chip->clk);
1065
1066 writel(chip->rwimsc & chip->real_wake,
1067 chip->addr + NMK_GPIO_RWIMSC);
1068 writel(chip->fwimsc & chip->real_wake,
1069 chip->addr + NMK_GPIO_FWIMSC);
1070
1071 clk_disable(chip->clk);
1072 }
1073 }
1074
1075 void nmk_gpio_wakeups_resume(void)
1076 {
1077 int i;
1078
1079 for (i = 0; i < NUM_BANKS; i++) {
1080 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1081
1082 if (!chip)
1083 break;
1084
1085 clk_enable(chip->clk);
1086
1087 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
1088 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
1089
1090 clk_disable(chip->clk);
1091 }
1092 }
1093
1094 /*
1095 * Read the pull up/pull down status.
1096 * A bit set in 'pull_up' means that pull up
1097 * is selected if pull is enabled in PDIS register.
1098 * Note: only pull up/down set via this driver can
1099 * be detected due to HW limitations.
1100 */
1101 void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
1102 {
1103 if (gpio_bank < NUM_BANKS) {
1104 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
1105
1106 if (!chip)
1107 return;
1108
1109 *pull_up = chip->pull_up;
1110 }
1111 }
1112
1113 int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1114 irq_hw_number_t hwirq)
1115 {
1116 struct nmk_gpio_chip *nmk_chip = d->host_data;
1117
1118 if (!nmk_chip)
1119 return -EINVAL;
1120
1121 irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq);
1122 set_irq_flags(irq, IRQF_VALID);
1123 irq_set_chip_data(irq, nmk_chip);
1124 irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING);
1125
1126 return 0;
1127 }
1128
1129 const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
1130 .map = nmk_gpio_irq_map,
1131 .xlate = irq_domain_xlate_twocell,
1132 };
1133
1134 static int __devinit nmk_gpio_probe(struct platform_device *dev)
1135 {
1136 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
1137 struct device_node *np = dev->dev.of_node;
1138 struct nmk_gpio_chip *nmk_chip;
1139 struct gpio_chip *chip;
1140 struct resource *res;
1141 struct clk *clk;
1142 int secondary_irq;
1143 void __iomem *base;
1144 int irq;
1145 int ret;
1146
1147 if (!pdata && !np) {
1148 dev_err(&dev->dev, "No platform data or device tree found\n");
1149 return -ENODEV;
1150 }
1151
1152 if (np) {
1153 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
1154 if (!pdata)
1155 return -ENOMEM;
1156
1157 if (of_get_property(np, "supports-sleepmode", NULL))
1158 pdata->supports_sleepmode = true;
1159
1160 if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
1161 dev_err(&dev->dev, "gpio-bank property not found\n");
1162 ret = -EINVAL;
1163 goto out;
1164 }
1165
1166 pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
1167 pdata->num_gpio = NMK_GPIO_PER_CHIP;
1168 }
1169
1170 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1171 if (!res) {
1172 ret = -ENOENT;
1173 goto out;
1174 }
1175
1176 irq = platform_get_irq(dev, 0);
1177 if (irq < 0) {
1178 ret = irq;
1179 goto out;
1180 }
1181
1182 secondary_irq = platform_get_irq(dev, 1);
1183 if (secondary_irq >= 0 && !pdata->get_secondary_status) {
1184 ret = -EINVAL;
1185 goto out;
1186 }
1187
1188 if (request_mem_region(res->start, resource_size(res),
1189 dev_name(&dev->dev)) == NULL) {
1190 ret = -EBUSY;
1191 goto out;
1192 }
1193
1194 base = ioremap(res->start, resource_size(res));
1195 if (!base) {
1196 ret = -ENOMEM;
1197 goto out_release;
1198 }
1199
1200 clk = clk_get(&dev->dev, NULL);
1201 if (IS_ERR(clk)) {
1202 ret = PTR_ERR(clk);
1203 goto out_unmap;
1204 }
1205
1206 nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL);
1207 if (!nmk_chip) {
1208 ret = -ENOMEM;
1209 goto out_clk;
1210 }
1211
1212 /*
1213 * The virt address in nmk_chip->addr is in the nomadik register space,
1214 * so we can simply convert the resource address, without remapping
1215 */
1216 nmk_chip->bank = dev->id;
1217 nmk_chip->clk = clk;
1218 nmk_chip->addr = base;
1219 nmk_chip->chip = nmk_gpio_template;
1220 nmk_chip->parent_irq = irq;
1221 nmk_chip->secondary_parent_irq = secondary_irq;
1222 nmk_chip->get_secondary_status = pdata->get_secondary_status;
1223 nmk_chip->set_ioforce = pdata->set_ioforce;
1224 nmk_chip->sleepmode = pdata->supports_sleepmode;
1225 spin_lock_init(&nmk_chip->lock);
1226
1227 chip = &nmk_chip->chip;
1228 chip->base = pdata->first_gpio;
1229 chip->ngpio = pdata->num_gpio;
1230 chip->label = pdata->name ?: dev_name(&dev->dev);
1231 chip->dev = &dev->dev;
1232 chip->owner = THIS_MODULE;
1233
1234 clk_enable(nmk_chip->clk);
1235 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1236 clk_disable(nmk_chip->clk);
1237
1238 #ifdef CONFIG_OF_GPIO
1239 chip->of_node = np;
1240 #endif
1241
1242 ret = gpiochip_add(&nmk_chip->chip);
1243 if (ret)
1244 goto out_free;
1245
1246 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1247
1248 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1249
1250 platform_set_drvdata(dev, nmk_chip);
1251
1252 nmk_chip->domain = irq_domain_add_legacy(np, NMK_GPIO_PER_CHIP,
1253 NOMADIK_GPIO_TO_IRQ(pdata->first_gpio),
1254 0, &nmk_gpio_irq_simple_ops, nmk_chip);
1255 if (!nmk_chip->domain) {
1256 pr_err("%s: Failed to create irqdomain\n", np->full_name);
1257 ret = -ENOSYS;
1258 goto out_free;
1259 }
1260
1261 nmk_gpio_init_irq(nmk_chip);
1262
1263 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1264
1265 return 0;
1266
1267 out_free:
1268 kfree(nmk_chip);
1269 out_clk:
1270 clk_disable(clk);
1271 clk_put(clk);
1272 out_unmap:
1273 iounmap(base);
1274 out_release:
1275 release_mem_region(res->start, resource_size(res));
1276 out:
1277 dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
1278 pdata->first_gpio, pdata->first_gpio+31);
1279 if (np)
1280 kfree(pdata);
1281
1282 return ret;
1283 }
1284
1285 static const struct of_device_id nmk_gpio_match[] = {
1286 { .compatible = "st,nomadik-gpio", },
1287 {}
1288 };
1289
1290 static struct platform_driver nmk_gpio_driver = {
1291 .driver = {
1292 .owner = THIS_MODULE,
1293 .name = "gpio",
1294 .of_match_table = nmk_gpio_match,
1295 },
1296 .probe = nmk_gpio_probe,
1297 };
1298
1299 static int __init nmk_gpio_init(void)
1300 {
1301 return platform_driver_register(&nmk_gpio_driver);
1302 }
1303
1304 core_initcall(nmk_gpio_init);
1305
1306 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
1307 MODULE_DESCRIPTION("Nomadik GPIO Driver");
1308 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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