2 * Generic GPIO driver for logic cells found in the Nomadik SoC
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/device.h>
17 #include <linux/platform_device.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/irqdomain.h>
26 #include <linux/slab.h>
28 #include <asm/mach/irq.h>
30 #include <plat/pincfg.h>
31 #include <plat/gpio-nomadik.h>
34 * The GPIO module in the Nomadik family of Systems-on-Chip is an
35 * AMBA device, managing 32 pins and alternate functions. The logic block
36 * is currently used in the Nomadik and ux500.
38 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
41 #define NMK_GPIO_PER_CHIP 32
43 struct nmk_gpio_chip
{
44 struct gpio_chip chip
;
45 struct irq_domain
*domain
;
49 unsigned int parent_irq
;
50 int secondary_parent_irq
;
51 u32 (*get_secondary_status
)(unsigned int bank
);
52 void (*set_ioforce
)(bool enable
);
55 /* Keep track of configured edges */
67 static struct nmk_gpio_chip
*
68 nmk_gpio_chips
[DIV_ROUND_UP(ARCH_NR_GPIOS
, NMK_GPIO_PER_CHIP
)];
70 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock
);
72 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
74 static void __nmk_gpio_set_mode(struct nmk_gpio_chip
*nmk_chip
,
75 unsigned offset
, int gpio_mode
)
77 u32 bit
= 1 << offset
;
80 afunc
= readl(nmk_chip
->addr
+ NMK_GPIO_AFSLA
) & ~bit
;
81 bfunc
= readl(nmk_chip
->addr
+ NMK_GPIO_AFSLB
) & ~bit
;
82 if (gpio_mode
& NMK_GPIO_ALT_A
)
84 if (gpio_mode
& NMK_GPIO_ALT_B
)
86 writel(afunc
, nmk_chip
->addr
+ NMK_GPIO_AFSLA
);
87 writel(bfunc
, nmk_chip
->addr
+ NMK_GPIO_AFSLB
);
90 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip
*nmk_chip
,
91 unsigned offset
, enum nmk_gpio_slpm mode
)
93 u32 bit
= 1 << offset
;
96 slpm
= readl(nmk_chip
->addr
+ NMK_GPIO_SLPC
);
97 if (mode
== NMK_GPIO_SLPM_NOCHANGE
)
101 writel(slpm
, nmk_chip
->addr
+ NMK_GPIO_SLPC
);
104 static void __nmk_gpio_set_pull(struct nmk_gpio_chip
*nmk_chip
,
105 unsigned offset
, enum nmk_gpio_pull pull
)
107 u32 bit
= 1 << offset
;
110 pdis
= readl(nmk_chip
->addr
+ NMK_GPIO_PDIS
);
111 if (pull
== NMK_GPIO_PULL_NONE
) {
113 nmk_chip
->pull_up
&= ~bit
;
118 writel(pdis
, nmk_chip
->addr
+ NMK_GPIO_PDIS
);
120 if (pull
== NMK_GPIO_PULL_UP
) {
121 nmk_chip
->pull_up
|= bit
;
122 writel(bit
, nmk_chip
->addr
+ NMK_GPIO_DATS
);
123 } else if (pull
== NMK_GPIO_PULL_DOWN
) {
124 nmk_chip
->pull_up
&= ~bit
;
125 writel(bit
, nmk_chip
->addr
+ NMK_GPIO_DATC
);
129 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip
*nmk_chip
,
130 unsigned offset
, bool lowemi
)
132 u32 bit
= BIT(offset
);
133 bool enabled
= nmk_chip
->lowemi
& bit
;
135 if (lowemi
== enabled
)
139 nmk_chip
->lowemi
|= bit
;
141 nmk_chip
->lowemi
&= ~bit
;
143 writel_relaxed(nmk_chip
->lowemi
,
144 nmk_chip
->addr
+ NMK_GPIO_LOWEMI
);
147 static void __nmk_gpio_make_input(struct nmk_gpio_chip
*nmk_chip
,
150 writel(1 << offset
, nmk_chip
->addr
+ NMK_GPIO_DIRC
);
153 static void __nmk_gpio_set_output(struct nmk_gpio_chip
*nmk_chip
,
154 unsigned offset
, int val
)
157 writel(1 << offset
, nmk_chip
->addr
+ NMK_GPIO_DATS
);
159 writel(1 << offset
, nmk_chip
->addr
+ NMK_GPIO_DATC
);
162 static void __nmk_gpio_make_output(struct nmk_gpio_chip
*nmk_chip
,
163 unsigned offset
, int val
)
165 writel(1 << offset
, nmk_chip
->addr
+ NMK_GPIO_DIRS
);
166 __nmk_gpio_set_output(nmk_chip
, offset
, val
);
169 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip
*nmk_chip
,
170 unsigned offset
, int gpio_mode
,
173 u32 rwimsc
= nmk_chip
->rwimsc
;
174 u32 fwimsc
= nmk_chip
->fwimsc
;
176 if (glitch
&& nmk_chip
->set_ioforce
) {
177 u32 bit
= BIT(offset
);
179 /* Prevent spurious wakeups */
180 writel(rwimsc
& ~bit
, nmk_chip
->addr
+ NMK_GPIO_RWIMSC
);
181 writel(fwimsc
& ~bit
, nmk_chip
->addr
+ NMK_GPIO_FWIMSC
);
183 nmk_chip
->set_ioforce(true);
186 __nmk_gpio_set_mode(nmk_chip
, offset
, gpio_mode
);
188 if (glitch
&& nmk_chip
->set_ioforce
) {
189 nmk_chip
->set_ioforce(false);
191 writel(rwimsc
, nmk_chip
->addr
+ NMK_GPIO_RWIMSC
);
192 writel(fwimsc
, nmk_chip
->addr
+ NMK_GPIO_FWIMSC
);
197 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip
*nmk_chip
, unsigned offset
)
199 u32 falling
= nmk_chip
->fimsc
& BIT(offset
);
200 u32 rising
= nmk_chip
->rimsc
& BIT(offset
);
201 int gpio
= nmk_chip
->chip
.base
+ offset
;
202 int irq
= NOMADIK_GPIO_TO_IRQ(gpio
);
203 struct irq_data
*d
= irq_get_irq_data(irq
);
205 if (!rising
&& !falling
)
208 if (!d
|| !irqd_irq_disabled(d
))
212 nmk_chip
->rimsc
&= ~BIT(offset
);
213 writel_relaxed(nmk_chip
->rimsc
,
214 nmk_chip
->addr
+ NMK_GPIO_RIMSC
);
218 nmk_chip
->fimsc
&= ~BIT(offset
);
219 writel_relaxed(nmk_chip
->fimsc
,
220 nmk_chip
->addr
+ NMK_GPIO_FIMSC
);
223 dev_dbg(nmk_chip
->chip
.dev
, "%d: clearing interrupt mask\n", gpio
);
226 static void __nmk_config_pin(struct nmk_gpio_chip
*nmk_chip
, unsigned offset
,
227 pin_cfg_t cfg
, bool sleep
, unsigned int *slpmregs
)
229 static const char *afnames
[] = {
230 [NMK_GPIO_ALT_GPIO
] = "GPIO",
231 [NMK_GPIO_ALT_A
] = "A",
232 [NMK_GPIO_ALT_B
] = "B",
233 [NMK_GPIO_ALT_C
] = "C"
235 static const char *pullnames
[] = {
236 [NMK_GPIO_PULL_NONE
] = "none",
237 [NMK_GPIO_PULL_UP
] = "up",
238 [NMK_GPIO_PULL_DOWN
] = "down",
239 [3] /* illegal */ = "??"
241 static const char *slpmnames
[] = {
242 [NMK_GPIO_SLPM_INPUT
] = "input/wakeup",
243 [NMK_GPIO_SLPM_NOCHANGE
] = "no-change/no-wakeup",
246 int pin
= PIN_NUM(cfg
);
247 int pull
= PIN_PULL(cfg
);
248 int af
= PIN_ALT(cfg
);
249 int slpm
= PIN_SLPM(cfg
);
250 int output
= PIN_DIR(cfg
);
251 int val
= PIN_VAL(cfg
);
252 bool glitch
= af
== NMK_GPIO_ALT_C
;
254 dev_dbg(nmk_chip
->chip
.dev
, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
255 pin
, cfg
, afnames
[af
], pullnames
[pull
], slpmnames
[slpm
],
256 output
? "output " : "input",
257 output
? (val
? "high" : "low") : "");
260 int slpm_pull
= PIN_SLPM_PULL(cfg
);
261 int slpm_output
= PIN_SLPM_DIR(cfg
);
262 int slpm_val
= PIN_SLPM_VAL(cfg
);
264 af
= NMK_GPIO_ALT_GPIO
;
267 * The SLPM_* values are normal values + 1 to allow zero to
268 * mean "same as normal".
271 pull
= slpm_pull
- 1;
273 output
= slpm_output
- 1;
277 dev_dbg(nmk_chip
->chip
.dev
, "pin %d: sleep pull %s, dir %s, val %s\n",
279 slpm_pull
? pullnames
[pull
] : "same",
280 slpm_output
? (output
? "output" : "input") : "same",
281 slpm_val
? (val
? "high" : "low") : "same");
285 __nmk_gpio_make_output(nmk_chip
, offset
, val
);
287 __nmk_gpio_make_input(nmk_chip
, offset
);
288 __nmk_gpio_set_pull(nmk_chip
, offset
, pull
);
291 __nmk_gpio_set_lowemi(nmk_chip
, offset
, PIN_LOWEMI(cfg
));
294 * If the pin is switching to altfunc, and there was an interrupt
295 * installed on it which has been lazy disabled, actually mask the
296 * interrupt to prevent spurious interrupts that would occur while the
297 * pin is under control of the peripheral. Only SKE does this.
299 if (af
!= NMK_GPIO_ALT_GPIO
)
300 nmk_gpio_disable_lazy_irq(nmk_chip
, offset
);
303 * If we've backed up the SLPM registers (glitch workaround), modify
304 * the backups since they will be restored.
307 if (slpm
== NMK_GPIO_SLPM_NOCHANGE
)
308 slpmregs
[nmk_chip
->bank
] |= BIT(offset
);
310 slpmregs
[nmk_chip
->bank
] &= ~BIT(offset
);
312 __nmk_gpio_set_slpm(nmk_chip
, offset
, slpm
);
314 __nmk_gpio_set_mode_safe(nmk_chip
, offset
, af
, glitch
);
318 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
319 * - Save SLPM registers
320 * - Set SLPM=0 for the IOs you want to switch and others to 1
321 * - Configure the GPIO registers for the IOs that are being switched
323 * - Modify the AFLSA/B registers for the IOs that are being switched
325 * - Restore SLPM registers
326 * - Any spurious wake up event during switch sequence to be ignored and
329 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm
)
333 for (i
= 0; i
< NUM_BANKS
; i
++) {
334 struct nmk_gpio_chip
*chip
= nmk_gpio_chips
[i
];
335 unsigned int temp
= slpm
[i
];
340 clk_enable(chip
->clk
);
342 slpm
[i
] = readl(chip
->addr
+ NMK_GPIO_SLPC
);
343 writel(temp
, chip
->addr
+ NMK_GPIO_SLPC
);
347 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm
)
351 for (i
= 0; i
< NUM_BANKS
; i
++) {
352 struct nmk_gpio_chip
*chip
= nmk_gpio_chips
[i
];
357 writel(slpm
[i
], chip
->addr
+ NMK_GPIO_SLPC
);
359 clk_disable(chip
->clk
);
363 static int __nmk_config_pins(pin_cfg_t
*cfgs
, int num
, bool sleep
)
365 static unsigned int slpm
[NUM_BANKS
];
371 for (i
= 0; i
< num
; i
++) {
372 if (PIN_ALT(cfgs
[i
]) == NMK_GPIO_ALT_C
) {
378 spin_lock_irqsave(&nmk_gpio_slpm_lock
, flags
);
381 memset(slpm
, 0xff, sizeof(slpm
));
383 for (i
= 0; i
< num
; i
++) {
384 int pin
= PIN_NUM(cfgs
[i
]);
385 int offset
= pin
% NMK_GPIO_PER_CHIP
;
387 if (PIN_ALT(cfgs
[i
]) == NMK_GPIO_ALT_C
)
388 slpm
[pin
/ NMK_GPIO_PER_CHIP
] &= ~BIT(offset
);
391 nmk_gpio_glitch_slpm_init(slpm
);
394 for (i
= 0; i
< num
; i
++) {
395 struct nmk_gpio_chip
*nmk_chip
;
396 int pin
= PIN_NUM(cfgs
[i
]);
398 nmk_chip
= nmk_gpio_chips
[pin
/ NMK_GPIO_PER_CHIP
];
404 clk_enable(nmk_chip
->clk
);
405 spin_lock(&nmk_chip
->lock
);
406 __nmk_config_pin(nmk_chip
, pin
% NMK_GPIO_PER_CHIP
,
407 cfgs
[i
], sleep
, glitch
? slpm
: NULL
);
408 spin_unlock(&nmk_chip
->lock
);
409 clk_disable(nmk_chip
->clk
);
413 nmk_gpio_glitch_slpm_restore(slpm
);
415 spin_unlock_irqrestore(&nmk_gpio_slpm_lock
, flags
);
421 * nmk_config_pin - configure a pin's mux attributes
422 * @cfg: pin confguration
424 * Configures a pin's mode (alternate function or GPIO), its pull up status,
425 * and its sleep mode based on the specified configuration. The @cfg is
426 * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
427 * are constructed using, and can be further enhanced with, the macros in
430 * If a pin's mode is set to GPIO, it is configured as an input to avoid
431 * side-effects. The gpio can be manipulated later using standard GPIO API
434 int nmk_config_pin(pin_cfg_t cfg
, bool sleep
)
436 return __nmk_config_pins(&cfg
, 1, sleep
);
438 EXPORT_SYMBOL(nmk_config_pin
);
441 * nmk_config_pins - configure several pins at once
442 * @cfgs: array of pin configurations
443 * @num: number of elments in the array
445 * Configures several pins using nmk_config_pin(). Refer to that function for
446 * further information.
448 int nmk_config_pins(pin_cfg_t
*cfgs
, int num
)
450 return __nmk_config_pins(cfgs
, num
, false);
452 EXPORT_SYMBOL(nmk_config_pins
);
454 int nmk_config_pins_sleep(pin_cfg_t
*cfgs
, int num
)
456 return __nmk_config_pins(cfgs
, num
, true);
458 EXPORT_SYMBOL(nmk_config_pins_sleep
);
461 * nmk_gpio_set_slpm() - configure the sleep mode of a pin
463 * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
465 * This register is actually in the pinmux layer, not the GPIO block itself.
466 * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP
467 * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code).
468 * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is
469 * HIGH, overriding the normal setting defined by GPIO_AFSELx registers.
470 * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit),
471 * the GPIOs return to the normal setting defined by GPIO_AFSELx registers.
473 * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO
474 * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is
475 * entered) regardless of the altfunction selected. Also wake-up detection is
478 * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains
479 * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS
480 * (for altfunction GPIO) or respective on-chip peripherals (for other
481 * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED.
483 * Note that enable_irq_wake() will automatically enable wakeup detection.
485 int nmk_gpio_set_slpm(int gpio
, enum nmk_gpio_slpm mode
)
487 struct nmk_gpio_chip
*nmk_chip
;
490 nmk_chip
= nmk_gpio_chips
[gpio
/ NMK_GPIO_PER_CHIP
];
494 clk_enable(nmk_chip
->clk
);
495 spin_lock_irqsave(&nmk_gpio_slpm_lock
, flags
);
496 spin_lock(&nmk_chip
->lock
);
498 __nmk_gpio_set_slpm(nmk_chip
, gpio
% NMK_GPIO_PER_CHIP
, mode
);
500 spin_unlock(&nmk_chip
->lock
);
501 spin_unlock_irqrestore(&nmk_gpio_slpm_lock
, flags
);
502 clk_disable(nmk_chip
->clk
);
508 * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
510 * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
512 * Enables/disables pull up/down on a specified pin. This only takes effect if
513 * the pin is configured as an input (either explicitly or by the alternate
516 * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
517 * configured as an input. Otherwise, due to the way the controller registers
518 * work, this function will change the value output on the pin.
520 int nmk_gpio_set_pull(int gpio
, enum nmk_gpio_pull pull
)
522 struct nmk_gpio_chip
*nmk_chip
;
525 nmk_chip
= nmk_gpio_chips
[gpio
/ NMK_GPIO_PER_CHIP
];
529 clk_enable(nmk_chip
->clk
);
530 spin_lock_irqsave(&nmk_chip
->lock
, flags
);
531 __nmk_gpio_set_pull(nmk_chip
, gpio
% NMK_GPIO_PER_CHIP
, pull
);
532 spin_unlock_irqrestore(&nmk_chip
->lock
, flags
);
533 clk_disable(nmk_chip
->clk
);
540 * nmk_gpio_set_mode() - set the mux mode of a gpio pin
542 * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
543 * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
545 * Sets the mode of the specified pin to one of the alternate functions or
548 int nmk_gpio_set_mode(int gpio
, int gpio_mode
)
550 struct nmk_gpio_chip
*nmk_chip
;
553 nmk_chip
= nmk_gpio_chips
[gpio
/ NMK_GPIO_PER_CHIP
];
557 clk_enable(nmk_chip
->clk
);
558 spin_lock_irqsave(&nmk_chip
->lock
, flags
);
559 __nmk_gpio_set_mode(nmk_chip
, gpio
% NMK_GPIO_PER_CHIP
, gpio_mode
);
560 spin_unlock_irqrestore(&nmk_chip
->lock
, flags
);
561 clk_disable(nmk_chip
->clk
);
565 EXPORT_SYMBOL(nmk_gpio_set_mode
);
567 int nmk_gpio_get_mode(int gpio
)
569 struct nmk_gpio_chip
*nmk_chip
;
570 u32 afunc
, bfunc
, bit
;
572 nmk_chip
= nmk_gpio_chips
[gpio
/ NMK_GPIO_PER_CHIP
];
576 bit
= 1 << (gpio
% NMK_GPIO_PER_CHIP
);
578 clk_enable(nmk_chip
->clk
);
580 afunc
= readl(nmk_chip
->addr
+ NMK_GPIO_AFSLA
) & bit
;
581 bfunc
= readl(nmk_chip
->addr
+ NMK_GPIO_AFSLB
) & bit
;
583 clk_disable(nmk_chip
->clk
);
585 return (afunc
? NMK_GPIO_ALT_A
: 0) | (bfunc
? NMK_GPIO_ALT_B
: 0);
587 EXPORT_SYMBOL(nmk_gpio_get_mode
);
591 static inline int nmk_gpio_get_bitmask(int gpio
)
593 return 1 << (gpio
% NMK_GPIO_PER_CHIP
);
596 static void nmk_gpio_irq_ack(struct irq_data
*d
)
598 struct nmk_gpio_chip
*nmk_chip
;
600 nmk_chip
= irq_data_get_irq_chip_data(d
);
604 clk_enable(nmk_chip
->clk
);
605 writel(nmk_gpio_get_bitmask(d
->hwirq
), nmk_chip
->addr
+ NMK_GPIO_IC
);
606 clk_disable(nmk_chip
->clk
);
609 enum nmk_gpio_irq_type
{
614 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip
*nmk_chip
,
615 int gpio
, enum nmk_gpio_irq_type which
,
618 u32 bitmask
= nmk_gpio_get_bitmask(gpio
);
624 if (which
== NORMAL
) {
625 rimscreg
= NMK_GPIO_RIMSC
;
626 fimscreg
= NMK_GPIO_FIMSC
;
627 rimscval
= &nmk_chip
->rimsc
;
628 fimscval
= &nmk_chip
->fimsc
;
630 rimscreg
= NMK_GPIO_RWIMSC
;
631 fimscreg
= NMK_GPIO_FWIMSC
;
632 rimscval
= &nmk_chip
->rwimsc
;
633 fimscval
= &nmk_chip
->fwimsc
;
636 /* we must individually set/clear the two edges */
637 if (nmk_chip
->edge_rising
& bitmask
) {
639 *rimscval
|= bitmask
;
641 *rimscval
&= ~bitmask
;
642 writel(*rimscval
, nmk_chip
->addr
+ rimscreg
);
644 if (nmk_chip
->edge_falling
& bitmask
) {
646 *fimscval
|= bitmask
;
648 *fimscval
&= ~bitmask
;
649 writel(*fimscval
, nmk_chip
->addr
+ fimscreg
);
653 static void __nmk_gpio_set_wake(struct nmk_gpio_chip
*nmk_chip
,
657 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
658 * disabled, since setting SLPM to 1 increases power consumption, and
659 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
661 if (nmk_chip
->sleepmode
&& on
) {
662 __nmk_gpio_set_slpm(nmk_chip
, gpio
% nmk_chip
->chip
.base
,
663 NMK_GPIO_SLPM_WAKEUP_ENABLE
);
666 __nmk_gpio_irq_modify(nmk_chip
, gpio
, WAKE
, on
);
669 static int nmk_gpio_irq_maskunmask(struct irq_data
*d
, bool enable
)
671 struct nmk_gpio_chip
*nmk_chip
;
675 nmk_chip
= irq_data_get_irq_chip_data(d
);
676 bitmask
= nmk_gpio_get_bitmask(d
->hwirq
);
680 clk_enable(nmk_chip
->clk
);
681 spin_lock_irqsave(&nmk_gpio_slpm_lock
, flags
);
682 spin_lock(&nmk_chip
->lock
);
684 __nmk_gpio_irq_modify(nmk_chip
, d
->hwirq
, NORMAL
, enable
);
686 if (!(nmk_chip
->real_wake
& bitmask
))
687 __nmk_gpio_set_wake(nmk_chip
, d
->hwirq
, enable
);
689 spin_unlock(&nmk_chip
->lock
);
690 spin_unlock_irqrestore(&nmk_gpio_slpm_lock
, flags
);
691 clk_disable(nmk_chip
->clk
);
696 static void nmk_gpio_irq_mask(struct irq_data
*d
)
698 nmk_gpio_irq_maskunmask(d
, false);
701 static void nmk_gpio_irq_unmask(struct irq_data
*d
)
703 nmk_gpio_irq_maskunmask(d
, true);
706 static int nmk_gpio_irq_set_wake(struct irq_data
*d
, unsigned int on
)
708 struct nmk_gpio_chip
*nmk_chip
;
712 nmk_chip
= irq_data_get_irq_chip_data(d
);
715 bitmask
= nmk_gpio_get_bitmask(d
->hwirq
);
717 clk_enable(nmk_chip
->clk
);
718 spin_lock_irqsave(&nmk_gpio_slpm_lock
, flags
);
719 spin_lock(&nmk_chip
->lock
);
721 if (irqd_irq_disabled(d
))
722 __nmk_gpio_set_wake(nmk_chip
, d
->hwirq
, on
);
725 nmk_chip
->real_wake
|= bitmask
;
727 nmk_chip
->real_wake
&= ~bitmask
;
729 spin_unlock(&nmk_chip
->lock
);
730 spin_unlock_irqrestore(&nmk_gpio_slpm_lock
, flags
);
731 clk_disable(nmk_chip
->clk
);
736 static int nmk_gpio_irq_set_type(struct irq_data
*d
, unsigned int type
)
738 bool enabled
= !irqd_irq_disabled(d
);
739 bool wake
= irqd_is_wakeup_set(d
);
740 struct nmk_gpio_chip
*nmk_chip
;
744 nmk_chip
= irq_data_get_irq_chip_data(d
);
745 bitmask
= nmk_gpio_get_bitmask(d
->hwirq
);
748 if (type
& IRQ_TYPE_LEVEL_HIGH
)
750 if (type
& IRQ_TYPE_LEVEL_LOW
)
753 clk_enable(nmk_chip
->clk
);
754 spin_lock_irqsave(&nmk_chip
->lock
, flags
);
757 __nmk_gpio_irq_modify(nmk_chip
, d
->hwirq
, NORMAL
, false);
760 __nmk_gpio_irq_modify(nmk_chip
, d
->hwirq
, WAKE
, false);
762 nmk_chip
->edge_rising
&= ~bitmask
;
763 if (type
& IRQ_TYPE_EDGE_RISING
)
764 nmk_chip
->edge_rising
|= bitmask
;
766 nmk_chip
->edge_falling
&= ~bitmask
;
767 if (type
& IRQ_TYPE_EDGE_FALLING
)
768 nmk_chip
->edge_falling
|= bitmask
;
771 __nmk_gpio_irq_modify(nmk_chip
, d
->hwirq
, NORMAL
, true);
774 __nmk_gpio_irq_modify(nmk_chip
, d
->hwirq
, WAKE
, true);
776 spin_unlock_irqrestore(&nmk_chip
->lock
, flags
);
777 clk_disable(nmk_chip
->clk
);
782 static unsigned int nmk_gpio_irq_startup(struct irq_data
*d
)
784 struct nmk_gpio_chip
*nmk_chip
= irq_data_get_irq_chip_data(d
);
786 clk_enable(nmk_chip
->clk
);
787 nmk_gpio_irq_unmask(d
);
791 static void nmk_gpio_irq_shutdown(struct irq_data
*d
)
793 struct nmk_gpio_chip
*nmk_chip
= irq_data_get_irq_chip_data(d
);
795 nmk_gpio_irq_mask(d
);
796 clk_disable(nmk_chip
->clk
);
799 static struct irq_chip nmk_gpio_irq_chip
= {
800 .name
= "Nomadik-GPIO",
801 .irq_ack
= nmk_gpio_irq_ack
,
802 .irq_mask
= nmk_gpio_irq_mask
,
803 .irq_unmask
= nmk_gpio_irq_unmask
,
804 .irq_set_type
= nmk_gpio_irq_set_type
,
805 .irq_set_wake
= nmk_gpio_irq_set_wake
,
806 .irq_startup
= nmk_gpio_irq_startup
,
807 .irq_shutdown
= nmk_gpio_irq_shutdown
,
810 static void __nmk_gpio_irq_handler(unsigned int irq
, struct irq_desc
*desc
,
813 struct nmk_gpio_chip
*nmk_chip
;
814 struct irq_chip
*host_chip
= irq_get_chip(irq
);
815 unsigned int first_irq
;
817 chained_irq_enter(host_chip
, desc
);
819 nmk_chip
= irq_get_handler_data(irq
);
820 first_irq
= nmk_chip
->domain
->revmap_data
.legacy
.first_irq
;
822 int bit
= __ffs(status
);
824 generic_handle_irq(first_irq
+ bit
);
828 chained_irq_exit(host_chip
, desc
);
831 static void nmk_gpio_irq_handler(unsigned int irq
, struct irq_desc
*desc
)
833 struct nmk_gpio_chip
*nmk_chip
= irq_get_handler_data(irq
);
836 clk_enable(nmk_chip
->clk
);
837 status
= readl(nmk_chip
->addr
+ NMK_GPIO_IS
);
838 clk_disable(nmk_chip
->clk
);
840 __nmk_gpio_irq_handler(irq
, desc
, status
);
843 static void nmk_gpio_secondary_irq_handler(unsigned int irq
,
844 struct irq_desc
*desc
)
846 struct nmk_gpio_chip
*nmk_chip
= irq_get_handler_data(irq
);
847 u32 status
= nmk_chip
->get_secondary_status(nmk_chip
->bank
);
849 __nmk_gpio_irq_handler(irq
, desc
, status
);
852 static int nmk_gpio_init_irq(struct nmk_gpio_chip
*nmk_chip
)
854 irq_set_chained_handler(nmk_chip
->parent_irq
, nmk_gpio_irq_handler
);
855 irq_set_handler_data(nmk_chip
->parent_irq
, nmk_chip
);
857 if (nmk_chip
->secondary_parent_irq
>= 0) {
858 irq_set_chained_handler(nmk_chip
->secondary_parent_irq
,
859 nmk_gpio_secondary_irq_handler
);
860 irq_set_handler_data(nmk_chip
->secondary_parent_irq
, nmk_chip
);
867 static int nmk_gpio_make_input(struct gpio_chip
*chip
, unsigned offset
)
869 struct nmk_gpio_chip
*nmk_chip
=
870 container_of(chip
, struct nmk_gpio_chip
, chip
);
872 clk_enable(nmk_chip
->clk
);
874 writel(1 << offset
, nmk_chip
->addr
+ NMK_GPIO_DIRC
);
876 clk_disable(nmk_chip
->clk
);
881 static int nmk_gpio_get_input(struct gpio_chip
*chip
, unsigned offset
)
883 struct nmk_gpio_chip
*nmk_chip
=
884 container_of(chip
, struct nmk_gpio_chip
, chip
);
885 u32 bit
= 1 << offset
;
888 clk_enable(nmk_chip
->clk
);
890 value
= (readl(nmk_chip
->addr
+ NMK_GPIO_DAT
) & bit
) != 0;
892 clk_disable(nmk_chip
->clk
);
897 static void nmk_gpio_set_output(struct gpio_chip
*chip
, unsigned offset
,
900 struct nmk_gpio_chip
*nmk_chip
=
901 container_of(chip
, struct nmk_gpio_chip
, chip
);
903 clk_enable(nmk_chip
->clk
);
905 __nmk_gpio_set_output(nmk_chip
, offset
, val
);
907 clk_disable(nmk_chip
->clk
);
910 static int nmk_gpio_make_output(struct gpio_chip
*chip
, unsigned offset
,
913 struct nmk_gpio_chip
*nmk_chip
=
914 container_of(chip
, struct nmk_gpio_chip
, chip
);
916 clk_enable(nmk_chip
->clk
);
918 __nmk_gpio_make_output(nmk_chip
, offset
, val
);
920 clk_disable(nmk_chip
->clk
);
925 static int nmk_gpio_to_irq(struct gpio_chip
*chip
, unsigned offset
)
927 struct nmk_gpio_chip
*nmk_chip
=
928 container_of(chip
, struct nmk_gpio_chip
, chip
);
930 return irq_find_mapping(nmk_chip
->domain
, offset
);
933 #ifdef CONFIG_DEBUG_FS
935 #include <linux/seq_file.h>
937 static void nmk_gpio_dbg_show(struct seq_file
*s
, struct gpio_chip
*chip
)
941 unsigned gpio
= chip
->base
;
943 struct nmk_gpio_chip
*nmk_chip
=
944 container_of(chip
, struct nmk_gpio_chip
, chip
);
945 const char *modes
[] = {
946 [NMK_GPIO_ALT_GPIO
] = "gpio",
947 [NMK_GPIO_ALT_A
] = "altA",
948 [NMK_GPIO_ALT_B
] = "altB",
949 [NMK_GPIO_ALT_C
] = "altC",
952 clk_enable(nmk_chip
->clk
);
954 for (i
= 0; i
< chip
->ngpio
; i
++, gpio
++) {
955 const char *label
= gpiochip_is_requested(chip
, i
);
959 is_out
= readl(nmk_chip
->addr
+ NMK_GPIO_DIR
) & bit
;
960 pull
= !(readl(nmk_chip
->addr
+ NMK_GPIO_PDIS
) & bit
);
961 mode
= nmk_gpio_get_mode(gpio
);
962 seq_printf(s
, " gpio-%-3d (%-20.20s) %s %s %s %s",
963 gpio
, label
?: "(none)",
964 is_out
? "out" : "in ",
966 ? (chip
->get(chip
, i
) ? "hi" : "lo")
968 (mode
< 0) ? "unknown" : modes
[mode
],
969 pull
? "pull" : "none");
971 if (label
&& !is_out
) {
972 int irq
= gpio_to_irq(gpio
);
973 struct irq_desc
*desc
= irq_to_desc(irq
);
975 /* This races with request_irq(), set_irq_type(),
976 * and set_irq_wake() ... but those are "rare".
978 if (irq
>= 0 && desc
->action
) {
980 u32 bitmask
= nmk_gpio_get_bitmask(gpio
);
982 if (nmk_chip
->edge_rising
& bitmask
)
983 trigger
= "edge-rising";
984 else if (nmk_chip
->edge_falling
& bitmask
)
985 trigger
= "edge-falling";
987 trigger
= "edge-undefined";
989 seq_printf(s
, " irq-%d %s%s",
991 irqd_is_wakeup_set(&desc
->irq_data
)
999 clk_disable(nmk_chip
->clk
);
1003 #define nmk_gpio_dbg_show NULL
1006 /* This structure is replicated for each GPIO block allocated at probe time */
1007 static struct gpio_chip nmk_gpio_template
= {
1008 .direction_input
= nmk_gpio_make_input
,
1009 .get
= nmk_gpio_get_input
,
1010 .direction_output
= nmk_gpio_make_output
,
1011 .set
= nmk_gpio_set_output
,
1012 .to_irq
= nmk_gpio_to_irq
,
1013 .dbg_show
= nmk_gpio_dbg_show
,
1017 void nmk_gpio_clocks_enable(void)
1021 for (i
= 0; i
< NUM_BANKS
; i
++) {
1022 struct nmk_gpio_chip
*chip
= nmk_gpio_chips
[i
];
1027 clk_enable(chip
->clk
);
1031 void nmk_gpio_clocks_disable(void)
1035 for (i
= 0; i
< NUM_BANKS
; i
++) {
1036 struct nmk_gpio_chip
*chip
= nmk_gpio_chips
[i
];
1041 clk_disable(chip
->clk
);
1046 * Called from the suspend/resume path to only keep the real wakeup interrupts
1047 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
1048 * and not the rest of the interrupts which we needed to have as wakeups for
1051 * PM ops are not used since this needs to be done at the end, after all the
1052 * other drivers are done with their suspend callbacks.
1054 void nmk_gpio_wakeups_suspend(void)
1058 for (i
= 0; i
< NUM_BANKS
; i
++) {
1059 struct nmk_gpio_chip
*chip
= nmk_gpio_chips
[i
];
1064 clk_enable(chip
->clk
);
1066 writel(chip
->rwimsc
& chip
->real_wake
,
1067 chip
->addr
+ NMK_GPIO_RWIMSC
);
1068 writel(chip
->fwimsc
& chip
->real_wake
,
1069 chip
->addr
+ NMK_GPIO_FWIMSC
);
1071 clk_disable(chip
->clk
);
1075 void nmk_gpio_wakeups_resume(void)
1079 for (i
= 0; i
< NUM_BANKS
; i
++) {
1080 struct nmk_gpio_chip
*chip
= nmk_gpio_chips
[i
];
1085 clk_enable(chip
->clk
);
1087 writel(chip
->rwimsc
, chip
->addr
+ NMK_GPIO_RWIMSC
);
1088 writel(chip
->fwimsc
, chip
->addr
+ NMK_GPIO_FWIMSC
);
1090 clk_disable(chip
->clk
);
1095 * Read the pull up/pull down status.
1096 * A bit set in 'pull_up' means that pull up
1097 * is selected if pull is enabled in PDIS register.
1098 * Note: only pull up/down set via this driver can
1099 * be detected due to HW limitations.
1101 void nmk_gpio_read_pull(int gpio_bank
, u32
*pull_up
)
1103 if (gpio_bank
< NUM_BANKS
) {
1104 struct nmk_gpio_chip
*chip
= nmk_gpio_chips
[gpio_bank
];
1109 *pull_up
= chip
->pull_up
;
1113 int nmk_gpio_irq_map(struct irq_domain
*d
, unsigned int irq
,
1114 irq_hw_number_t hwirq
)
1116 struct nmk_gpio_chip
*nmk_chip
= d
->host_data
;
1121 irq_set_chip_and_handler(irq
, &nmk_gpio_irq_chip
, handle_edge_irq
);
1122 set_irq_flags(irq
, IRQF_VALID
);
1123 irq_set_chip_data(irq
, nmk_chip
);
1124 irq_set_irq_type(irq
, IRQ_TYPE_EDGE_FALLING
);
1129 const struct irq_domain_ops nmk_gpio_irq_simple_ops
= {
1130 .map
= nmk_gpio_irq_map
,
1131 .xlate
= irq_domain_xlate_twocell
,
1134 static int __devinit
nmk_gpio_probe(struct platform_device
*dev
)
1136 struct nmk_gpio_platform_data
*pdata
= dev
->dev
.platform_data
;
1137 struct device_node
*np
= dev
->dev
.of_node
;
1138 struct nmk_gpio_chip
*nmk_chip
;
1139 struct gpio_chip
*chip
;
1140 struct resource
*res
;
1147 if (!pdata
&& !np
) {
1148 dev_err(&dev
->dev
, "No platform data or device tree found\n");
1153 pdata
= kzalloc(sizeof(*pdata
), GFP_KERNEL
);
1157 if (of_get_property(np
, "supports-sleepmode", NULL
))
1158 pdata
->supports_sleepmode
= true;
1160 if (of_property_read_u32(np
, "gpio-bank", &dev
->id
)) {
1161 dev_err(&dev
->dev
, "gpio-bank property not found\n");
1166 pdata
->first_gpio
= dev
->id
* NMK_GPIO_PER_CHIP
;
1167 pdata
->num_gpio
= NMK_GPIO_PER_CHIP
;
1170 res
= platform_get_resource(dev
, IORESOURCE_MEM
, 0);
1176 irq
= platform_get_irq(dev
, 0);
1182 secondary_irq
= platform_get_irq(dev
, 1);
1183 if (secondary_irq
>= 0 && !pdata
->get_secondary_status
) {
1188 if (request_mem_region(res
->start
, resource_size(res
),
1189 dev_name(&dev
->dev
)) == NULL
) {
1194 base
= ioremap(res
->start
, resource_size(res
));
1200 clk
= clk_get(&dev
->dev
, NULL
);
1206 nmk_chip
= kzalloc(sizeof(*nmk_chip
), GFP_KERNEL
);
1213 * The virt address in nmk_chip->addr is in the nomadik register space,
1214 * so we can simply convert the resource address, without remapping
1216 nmk_chip
->bank
= dev
->id
;
1217 nmk_chip
->clk
= clk
;
1218 nmk_chip
->addr
= base
;
1219 nmk_chip
->chip
= nmk_gpio_template
;
1220 nmk_chip
->parent_irq
= irq
;
1221 nmk_chip
->secondary_parent_irq
= secondary_irq
;
1222 nmk_chip
->get_secondary_status
= pdata
->get_secondary_status
;
1223 nmk_chip
->set_ioforce
= pdata
->set_ioforce
;
1224 nmk_chip
->sleepmode
= pdata
->supports_sleepmode
;
1225 spin_lock_init(&nmk_chip
->lock
);
1227 chip
= &nmk_chip
->chip
;
1228 chip
->base
= pdata
->first_gpio
;
1229 chip
->ngpio
= pdata
->num_gpio
;
1230 chip
->label
= pdata
->name
?: dev_name(&dev
->dev
);
1231 chip
->dev
= &dev
->dev
;
1232 chip
->owner
= THIS_MODULE
;
1234 clk_enable(nmk_chip
->clk
);
1235 nmk_chip
->lowemi
= readl_relaxed(nmk_chip
->addr
+ NMK_GPIO_LOWEMI
);
1236 clk_disable(nmk_chip
->clk
);
1240 ret
= gpiochip_add(&nmk_chip
->chip
);
1244 BUG_ON(nmk_chip
->bank
>= ARRAY_SIZE(nmk_gpio_chips
));
1246 nmk_gpio_chips
[nmk_chip
->bank
] = nmk_chip
;
1248 platform_set_drvdata(dev
, nmk_chip
);
1250 nmk_chip
->domain
= irq_domain_add_legacy(np
, NMK_GPIO_PER_CHIP
,
1251 NOMADIK_GPIO_TO_IRQ(pdata
->first_gpio
),
1252 0, &nmk_gpio_irq_simple_ops
, nmk_chip
);
1253 if (!nmk_chip
->domain
) {
1254 pr_err("%s: Failed to create irqdomain\n", np
->full_name
);
1259 nmk_gpio_init_irq(nmk_chip
);
1261 dev_info(&dev
->dev
, "at address %p\n", nmk_chip
->addr
);
1273 release_mem_region(res
->start
, resource_size(res
));
1275 dev_err(&dev
->dev
, "Failure %i for GPIO %i-%i\n", ret
,
1276 pdata
->first_gpio
, pdata
->first_gpio
+31);
1283 static const struct of_device_id nmk_gpio_match
[] = {
1284 { .compatible
= "st,nomadik-gpio", },
1288 static struct platform_driver nmk_gpio_driver
= {
1290 .owner
= THIS_MODULE
,
1292 .of_match_table
= nmk_gpio_match
,
1294 .probe
= nmk_gpio_probe
,
1297 static int __init
nmk_gpio_init(void)
1299 return platform_driver_register(&nmk_gpio_driver
);
1302 core_initcall(nmk_gpio_init
);
1304 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
1305 MODULE_DESCRIPTION("Nomadik GPIO Driver");
1306 MODULE_LICENSE("GPL");