2 * Pinctrl driver for Rockchip SoCs
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
26 #include <linux/module.h>
27 #include <linux/platform_device.h>
29 #include <linux/bitops.h>
30 #include <linux/gpio.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/pinctrl/machine.h>
34 #include <linux/pinctrl/pinconf.h>
35 #include <linux/pinctrl/pinctrl.h>
36 #include <linux/pinctrl/pinmux.h>
37 #include <linux/pinctrl/pinconf-generic.h>
38 #include <linux/irqchip/chained_irq.h>
39 #include <linux/clk.h>
40 #include <dt-bindings/pinctrl/rockchip.h>
45 /* GPIO control registers */
46 #define GPIO_SWPORT_DR 0x00
47 #define GPIO_SWPORT_DDR 0x04
48 #define GPIO_INTEN 0x30
49 #define GPIO_INTMASK 0x34
50 #define GPIO_INTTYPE_LEVEL 0x38
51 #define GPIO_INT_POLARITY 0x3c
52 #define GPIO_INT_STATUS 0x40
53 #define GPIO_INT_RAWSTATUS 0x44
54 #define GPIO_DEBOUNCE 0x48
55 #define GPIO_PORTS_EOI 0x4c
56 #define GPIO_EXT_PORT 0x50
57 #define GPIO_LS_SYNC 0x60
59 enum rockchip_pinctrl_type
{
65 enum rockchip_pin_bank_type
{
71 * @reg_base: register base of the gpio bank
72 * @reg_pull: optional separate register for additional pull settings
73 * @clk: clock of the gpio bank
74 * @irq: interrupt of the gpio bank
75 * @pin_base: first pin number
76 * @nr_pins: number of pins in this bank
77 * @name: name of the bank
78 * @bank_num: number of the bank, to account for holes
79 * @valid: are all necessary informations present
80 * @of_node: dt node of this bank
81 * @drvdata: common pinctrl basedata
82 * @domain: irqdomain of the gpio bank
83 * @gpio_chip: gpiolib chip
85 * @slock: spinlock for the gpio bank
87 struct rockchip_pin_bank
{
88 void __iomem
*reg_base
;
89 void __iomem
*reg_pull
;
96 enum rockchip_pin_bank_type bank_type
;
98 struct device_node
*of_node
;
99 struct rockchip_pinctrl
*drvdata
;
100 struct irq_domain
*domain
;
101 struct gpio_chip gpio_chip
;
102 struct pinctrl_gpio_range grange
;
104 u32 toggle_edge_mode
;
107 #define PIN_BANK(id, pins, label) \
116 struct rockchip_pin_ctrl
{
117 struct rockchip_pin_bank
*pin_banks
;
121 enum rockchip_pinctrl_type type
;
123 void (*pull_calc_reg
)(struct rockchip_pin_bank
*bank
, int pin_num
,
124 void __iomem
**reg
, u8
*bit
);
127 struct rockchip_pin_config
{
129 unsigned long *configs
;
130 unsigned int nconfigs
;
134 * struct rockchip_pin_group: represent group of pins of a pinmux function.
135 * @name: name of the pin group, used to lookup the group.
136 * @pins: the pins included in this group.
137 * @npins: number of pins included in this group.
138 * @func: the mux function number to be programmed when selected.
139 * @configs: the config values to be set for each pin
140 * @nconfigs: number of configs for each pin
142 struct rockchip_pin_group
{
146 struct rockchip_pin_config
*data
;
150 * struct rockchip_pmx_func: represent a pin function.
151 * @name: name of the pin function, used to lookup the function.
152 * @groups: one or more names of pin groups that provide this function.
153 * @num_groups: number of groups included in @groups.
155 struct rockchip_pmx_func
{
161 struct rockchip_pinctrl
{
162 void __iomem
*reg_base
;
163 void __iomem
*reg_pull
;
165 struct rockchip_pin_ctrl
*ctrl
;
166 struct pinctrl_desc pctl
;
167 struct pinctrl_dev
*pctl_dev
;
168 struct rockchip_pin_group
*groups
;
169 unsigned int ngroups
;
170 struct rockchip_pmx_func
*functions
;
171 unsigned int nfunctions
;
174 static inline struct rockchip_pin_bank
*gc_to_pin_bank(struct gpio_chip
*gc
)
176 return container_of(gc
, struct rockchip_pin_bank
, gpio_chip
);
179 static const inline struct rockchip_pin_group
*pinctrl_name_to_group(
180 const struct rockchip_pinctrl
*info
,
185 for (i
= 0; i
< info
->ngroups
; i
++) {
186 if (!strcmp(info
->groups
[i
].name
, name
))
187 return &info
->groups
[i
];
194 * given a pin number that is local to a pin controller, find out the pin bank
195 * and the register base of the pin bank.
197 static struct rockchip_pin_bank
*pin_to_bank(struct rockchip_pinctrl
*info
,
200 struct rockchip_pin_bank
*b
= info
->ctrl
->pin_banks
;
202 while (pin
>= (b
->pin_base
+ b
->nr_pins
))
208 static struct rockchip_pin_bank
*bank_num_to_bank(
209 struct rockchip_pinctrl
*info
,
212 struct rockchip_pin_bank
*b
= info
->ctrl
->pin_banks
;
215 for (i
= 0; i
< info
->ctrl
->nr_banks
; i
++, b
++) {
216 if (b
->bank_num
== num
)
220 return ERR_PTR(-EINVAL
);
224 * Pinctrl_ops handling
227 static int rockchip_get_groups_count(struct pinctrl_dev
*pctldev
)
229 struct rockchip_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
231 return info
->ngroups
;
234 static const char *rockchip_get_group_name(struct pinctrl_dev
*pctldev
,
237 struct rockchip_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
239 return info
->groups
[selector
].name
;
242 static int rockchip_get_group_pins(struct pinctrl_dev
*pctldev
,
243 unsigned selector
, const unsigned **pins
,
246 struct rockchip_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
248 if (selector
>= info
->ngroups
)
251 *pins
= info
->groups
[selector
].pins
;
252 *npins
= info
->groups
[selector
].npins
;
257 static int rockchip_dt_node_to_map(struct pinctrl_dev
*pctldev
,
258 struct device_node
*np
,
259 struct pinctrl_map
**map
, unsigned *num_maps
)
261 struct rockchip_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
262 const struct rockchip_pin_group
*grp
;
263 struct pinctrl_map
*new_map
;
264 struct device_node
*parent
;
269 * first find the group of this node and check if we need to create
270 * config maps for pins
272 grp
= pinctrl_name_to_group(info
, np
->name
);
274 dev_err(info
->dev
, "unable to find group for node %s\n",
279 map_num
+= grp
->npins
;
280 new_map
= devm_kzalloc(pctldev
->dev
, sizeof(*new_map
) * map_num
,
289 parent
= of_get_parent(np
);
291 devm_kfree(pctldev
->dev
, new_map
);
294 new_map
[0].type
= PIN_MAP_TYPE_MUX_GROUP
;
295 new_map
[0].data
.mux
.function
= parent
->name
;
296 new_map
[0].data
.mux
.group
= np
->name
;
299 /* create config map */
301 for (i
= 0; i
< grp
->npins
; i
++) {
302 new_map
[i
].type
= PIN_MAP_TYPE_CONFIGS_PIN
;
303 new_map
[i
].data
.configs
.group_or_pin
=
304 pin_get_name(pctldev
, grp
->pins
[i
]);
305 new_map
[i
].data
.configs
.configs
= grp
->data
[i
].configs
;
306 new_map
[i
].data
.configs
.num_configs
= grp
->data
[i
].nconfigs
;
309 dev_dbg(pctldev
->dev
, "maps: function %s group %s num %d\n",
310 (*map
)->data
.mux
.function
, (*map
)->data
.mux
.group
, map_num
);
315 static void rockchip_dt_free_map(struct pinctrl_dev
*pctldev
,
316 struct pinctrl_map
*map
, unsigned num_maps
)
320 static const struct pinctrl_ops rockchip_pctrl_ops
= {
321 .get_groups_count
= rockchip_get_groups_count
,
322 .get_group_name
= rockchip_get_group_name
,
323 .get_group_pins
= rockchip_get_group_pins
,
324 .dt_node_to_map
= rockchip_dt_node_to_map
,
325 .dt_free_map
= rockchip_dt_free_map
,
332 static int rockchip_get_mux(struct rockchip_pin_bank
*bank
, int pin
)
334 struct rockchip_pinctrl
*info
= bank
->drvdata
;
335 void __iomem
*reg
= info
->reg_base
+ info
->ctrl
->mux_offset
;
338 if (bank
->bank_type
== RK3188_BANK0
&& pin
< 16)
341 /* get basic quadrupel of mux registers and the correct reg inside */
342 reg
+= bank
->bank_num
* 0x10;
343 reg
+= (pin
/ 8) * 4;
346 return ((readl(reg
) >> bit
) & 3);
350 * Set a new mux function for a pin.
352 * The register is divided into the upper and lower 16 bit. When changing
353 * a value, the previous register value is not read and changed. Instead
354 * it seems the changed bits are marked in the upper 16 bit, while the
355 * changed value gets set in the same offset in the lower 16 bit.
356 * All pin settings seem to be 2 bit wide in both the upper and lower
358 * @bank: pin bank to change
359 * @pin: pin to change
360 * @mux: new mux function to set
362 static int rockchip_set_mux(struct rockchip_pin_bank
*bank
, int pin
, int mux
)
364 struct rockchip_pinctrl
*info
= bank
->drvdata
;
365 void __iomem
*reg
= info
->reg_base
+ info
->ctrl
->mux_offset
;
371 * The first 16 pins of rk3188_bank0 are always gpios and do not have
372 * a mux register at all.
374 if (bank
->bank_type
== RK3188_BANK0
&& pin
< 16) {
375 if (mux
!= RK_FUNC_GPIO
) {
377 "pin %d only supports a gpio mux\n", pin
);
384 dev_dbg(info
->dev
, "setting mux of GPIO%d-%d to %d\n",
385 bank
->bank_num
, pin
, mux
);
387 /* get basic quadrupel of mux registers and the correct reg inside */
388 reg
+= bank
->bank_num
* 0x10;
389 reg
+= (pin
/ 8) * 4;
392 spin_lock_irqsave(&bank
->slock
, flags
);
394 data
= (3 << (bit
+ 16));
395 data
|= (mux
& 3) << bit
;
398 spin_unlock_irqrestore(&bank
->slock
, flags
);
403 #define RK2928_PULL_OFFSET 0x118
404 #define RK2928_PULL_PINS_PER_REG 16
405 #define RK2928_PULL_BANK_STRIDE 8
407 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank
*bank
,
408 int pin_num
, void __iomem
**reg
, u8
*bit
)
410 struct rockchip_pinctrl
*info
= bank
->drvdata
;
412 *reg
= info
->reg_base
+ RK2928_PULL_OFFSET
;
413 *reg
+= bank
->bank_num
* RK2928_PULL_BANK_STRIDE
;
414 *reg
+= (pin_num
/ RK2928_PULL_PINS_PER_REG
) * 4;
416 *bit
= pin_num
% RK2928_PULL_PINS_PER_REG
;
419 #define RK3188_PULL_BITS_PER_PIN 2
420 #define RK3188_PULL_PINS_PER_REG 8
421 #define RK3188_PULL_BANK_STRIDE 16
423 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank
*bank
,
424 int pin_num
, void __iomem
**reg
, u8
*bit
)
426 struct rockchip_pinctrl
*info
= bank
->drvdata
;
428 /* The first 12 pins of the first bank are located elsewhere */
429 if (bank
->bank_type
== RK3188_BANK0
&& pin_num
< 12) {
430 *reg
= bank
->reg_pull
+
431 ((pin_num
/ RK3188_PULL_PINS_PER_REG
) * 4);
432 *bit
= pin_num
% RK3188_PULL_PINS_PER_REG
;
433 *bit
*= RK3188_PULL_BITS_PER_PIN
;
435 *reg
= info
->reg_pull
- 4;
436 *reg
+= bank
->bank_num
* RK3188_PULL_BANK_STRIDE
;
437 *reg
+= ((pin_num
/ RK3188_PULL_PINS_PER_REG
) * 4);
440 * The bits in these registers have an inverse ordering
441 * with the lowest pin being in bits 15:14 and the highest
444 *bit
= 7 - (pin_num
% RK3188_PULL_PINS_PER_REG
);
445 *bit
*= RK3188_PULL_BITS_PER_PIN
;
449 static int rockchip_get_pull(struct rockchip_pin_bank
*bank
, int pin_num
)
451 struct rockchip_pinctrl
*info
= bank
->drvdata
;
452 struct rockchip_pin_ctrl
*ctrl
= info
->ctrl
;
457 /* rk3066b does support any pulls */
458 if (ctrl
->type
== RK3066B
)
459 return PIN_CONFIG_BIAS_DISABLE
;
461 ctrl
->pull_calc_reg(bank
, pin_num
, ®
, &bit
);
463 switch (ctrl
->type
) {
465 return !(readl_relaxed(reg
) & BIT(bit
))
466 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
467 : PIN_CONFIG_BIAS_DISABLE
;
469 data
= readl_relaxed(reg
) >> bit
;
470 data
&= (1 << RK3188_PULL_BITS_PER_PIN
) - 1;
474 return PIN_CONFIG_BIAS_DISABLE
;
476 return PIN_CONFIG_BIAS_PULL_UP
;
478 return PIN_CONFIG_BIAS_PULL_DOWN
;
480 return PIN_CONFIG_BIAS_BUS_HOLD
;
483 dev_err(info
->dev
, "unknown pull setting\n");
486 dev_err(info
->dev
, "unsupported pinctrl type\n");
491 static int rockchip_set_pull(struct rockchip_pin_bank
*bank
,
492 int pin_num
, int pull
)
494 struct rockchip_pinctrl
*info
= bank
->drvdata
;
495 struct rockchip_pin_ctrl
*ctrl
= info
->ctrl
;
501 dev_dbg(info
->dev
, "setting pull of GPIO%d-%d to %d\n",
502 bank
->bank_num
, pin_num
, pull
);
504 /* rk3066b does support any pulls */
505 if (ctrl
->type
== RK3066B
)
506 return pull
? -EINVAL
: 0;
508 ctrl
->pull_calc_reg(bank
, pin_num
, ®
, &bit
);
510 switch (ctrl
->type
) {
512 spin_lock_irqsave(&bank
->slock
, flags
);
514 data
= BIT(bit
+ 16);
515 if (pull
== PIN_CONFIG_BIAS_DISABLE
)
519 spin_unlock_irqrestore(&bank
->slock
, flags
);
522 spin_lock_irqsave(&bank
->slock
, flags
);
524 /* enable the write to the equivalent lower bits */
525 data
= ((1 << RK3188_PULL_BITS_PER_PIN
) - 1) << (bit
+ 16);
528 case PIN_CONFIG_BIAS_DISABLE
:
530 case PIN_CONFIG_BIAS_PULL_UP
:
533 case PIN_CONFIG_BIAS_PULL_DOWN
:
536 case PIN_CONFIG_BIAS_BUS_HOLD
:
540 spin_unlock_irqrestore(&bank
->slock
, flags
);
541 dev_err(info
->dev
, "unsupported pull setting %d\n",
548 spin_unlock_irqrestore(&bank
->slock
, flags
);
551 dev_err(info
->dev
, "unsupported pinctrl type\n");
559 * Pinmux_ops handling
562 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev
*pctldev
)
564 struct rockchip_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
566 return info
->nfunctions
;
569 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev
*pctldev
,
572 struct rockchip_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
574 return info
->functions
[selector
].name
;
577 static int rockchip_pmx_get_groups(struct pinctrl_dev
*pctldev
,
578 unsigned selector
, const char * const **groups
,
579 unsigned * const num_groups
)
581 struct rockchip_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
583 *groups
= info
->functions
[selector
].groups
;
584 *num_groups
= info
->functions
[selector
].ngroups
;
589 static int rockchip_pmx_enable(struct pinctrl_dev
*pctldev
, unsigned selector
,
592 struct rockchip_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
593 const unsigned int *pins
= info
->groups
[group
].pins
;
594 const struct rockchip_pin_config
*data
= info
->groups
[group
].data
;
595 struct rockchip_pin_bank
*bank
;
598 dev_dbg(info
->dev
, "enable function %s group %s\n",
599 info
->functions
[selector
].name
, info
->groups
[group
].name
);
602 * for each pin in the pin group selected, program the correspoding pin
603 * pin function number in the config register.
605 for (cnt
= 0; cnt
< info
->groups
[group
].npins
; cnt
++) {
606 bank
= pin_to_bank(info
, pins
[cnt
]);
607 ret
= rockchip_set_mux(bank
, pins
[cnt
] - bank
->pin_base
,
614 /* revert the already done pin settings */
615 for (cnt
--; cnt
>= 0; cnt
--)
616 rockchip_set_mux(bank
, pins
[cnt
] - bank
->pin_base
, 0);
624 static void rockchip_pmx_disable(struct pinctrl_dev
*pctldev
,
625 unsigned selector
, unsigned group
)
627 struct rockchip_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
628 const unsigned int *pins
= info
->groups
[group
].pins
;
629 struct rockchip_pin_bank
*bank
;
632 dev_dbg(info
->dev
, "disable function %s group %s\n",
633 info
->functions
[selector
].name
, info
->groups
[group
].name
);
635 for (cnt
= 0; cnt
< info
->groups
[group
].npins
; cnt
++) {
636 bank
= pin_to_bank(info
, pins
[cnt
]);
637 rockchip_set_mux(bank
, pins
[cnt
] - bank
->pin_base
, 0);
642 * The calls to gpio_direction_output() and gpio_direction_input()
643 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
644 * function called from the gpiolib interface).
646 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev
*pctldev
,
647 struct pinctrl_gpio_range
*range
,
648 unsigned offset
, bool input
)
650 struct rockchip_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
651 struct rockchip_pin_bank
*bank
;
652 struct gpio_chip
*chip
;
657 bank
= gc_to_pin_bank(chip
);
658 pin
= offset
- chip
->base
;
660 dev_dbg(info
->dev
, "gpio_direction for pin %u as %s-%d to %s\n",
661 offset
, range
->name
, pin
, input
? "input" : "output");
663 ret
= rockchip_set_mux(bank
, pin
, RK_FUNC_GPIO
);
667 data
= readl_relaxed(bank
->reg_base
+ GPIO_SWPORT_DDR
);
668 /* set bit to 1 for output, 0 for input */
673 writel_relaxed(data
, bank
->reg_base
+ GPIO_SWPORT_DDR
);
678 static const struct pinmux_ops rockchip_pmx_ops
= {
679 .get_functions_count
= rockchip_pmx_get_funcs_count
,
680 .get_function_name
= rockchip_pmx_get_func_name
,
681 .get_function_groups
= rockchip_pmx_get_groups
,
682 .enable
= rockchip_pmx_enable
,
683 .disable
= rockchip_pmx_disable
,
684 .gpio_set_direction
= rockchip_pmx_gpio_set_direction
,
688 * Pinconf_ops handling
691 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl
*ctrl
,
692 enum pin_config_param pull
)
694 switch (ctrl
->type
) {
696 return (pull
== PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
||
697 pull
== PIN_CONFIG_BIAS_DISABLE
);
699 return pull
? false : true;
701 return (pull
!= PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
);
707 static int rockchip_gpio_direction_output(struct gpio_chip
*gc
,
708 unsigned offset
, int value
);
709 static int rockchip_gpio_get(struct gpio_chip
*gc
, unsigned offset
);
711 /* set the pin config settings for a specified pin */
712 static int rockchip_pinconf_set(struct pinctrl_dev
*pctldev
, unsigned int pin
,
713 unsigned long *configs
, unsigned num_configs
)
715 struct rockchip_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
716 struct rockchip_pin_bank
*bank
= pin_to_bank(info
, pin
);
717 enum pin_config_param param
;
722 for (i
= 0; i
< num_configs
; i
++) {
723 param
= pinconf_to_config_param(configs
[i
]);
724 arg
= pinconf_to_config_argument(configs
[i
]);
727 case PIN_CONFIG_BIAS_DISABLE
:
728 rc
= rockchip_set_pull(bank
, pin
- bank
->pin_base
,
733 case PIN_CONFIG_BIAS_PULL_UP
:
734 case PIN_CONFIG_BIAS_PULL_DOWN
:
735 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
:
736 case PIN_CONFIG_BIAS_BUS_HOLD
:
737 if (!rockchip_pinconf_pull_valid(info
->ctrl
, param
))
743 rc
= rockchip_set_pull(bank
, pin
- bank
->pin_base
,
748 case PIN_CONFIG_OUTPUT
:
749 rc
= rockchip_gpio_direction_output(&bank
->gpio_chip
,
750 pin
- bank
->pin_base
,
759 } /* for each config */
764 /* get the pin config settings for a specified pin */
765 static int rockchip_pinconf_get(struct pinctrl_dev
*pctldev
, unsigned int pin
,
766 unsigned long *config
)
768 struct rockchip_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
769 struct rockchip_pin_bank
*bank
= pin_to_bank(info
, pin
);
770 enum pin_config_param param
= pinconf_to_config_param(*config
);
775 case PIN_CONFIG_BIAS_DISABLE
:
776 if (rockchip_get_pull(bank
, pin
- bank
->pin_base
) != param
)
781 case PIN_CONFIG_BIAS_PULL_UP
:
782 case PIN_CONFIG_BIAS_PULL_DOWN
:
783 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
:
784 case PIN_CONFIG_BIAS_BUS_HOLD
:
785 if (!rockchip_pinconf_pull_valid(info
->ctrl
, param
))
788 if (rockchip_get_pull(bank
, pin
- bank
->pin_base
) != param
)
793 case PIN_CONFIG_OUTPUT
:
794 rc
= rockchip_get_mux(bank
, pin
- bank
->pin_base
);
795 if (rc
!= RK_FUNC_GPIO
)
798 rc
= rockchip_gpio_get(&bank
->gpio_chip
, pin
- bank
->pin_base
);
809 *config
= pinconf_to_config_packed(param
, arg
);
814 static const struct pinconf_ops rockchip_pinconf_ops
= {
815 .pin_config_get
= rockchip_pinconf_get
,
816 .pin_config_set
= rockchip_pinconf_set
,
819 static const struct of_device_id rockchip_bank_match
[] = {
820 { .compatible
= "rockchip,gpio-bank" },
821 { .compatible
= "rockchip,rk3188-gpio-bank0" },
825 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl
*info
,
826 struct device_node
*np
)
828 struct device_node
*child
;
830 for_each_child_of_node(np
, child
) {
831 if (of_match_node(rockchip_bank_match
, child
))
835 info
->ngroups
+= of_get_child_count(child
);
839 static int rockchip_pinctrl_parse_groups(struct device_node
*np
,
840 struct rockchip_pin_group
*grp
,
841 struct rockchip_pinctrl
*info
,
844 struct rockchip_pin_bank
*bank
;
851 dev_dbg(info
->dev
, "group(%d): %s\n", index
, np
->name
);
853 /* Initialise group */
854 grp
->name
= np
->name
;
857 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
858 * do sanity check and calculate pins number
860 list
= of_get_property(np
, "rockchip,pins", &size
);
861 /* we do not check return since it's safe node passed down */
862 size
/= sizeof(*list
);
863 if (!size
|| size
% 4) {
864 dev_err(info
->dev
, "wrong pins number or pins and configs should be by 4\n");
868 grp
->npins
= size
/ 4;
870 grp
->pins
= devm_kzalloc(info
->dev
, grp
->npins
* sizeof(unsigned int),
872 grp
->data
= devm_kzalloc(info
->dev
, grp
->npins
*
873 sizeof(struct rockchip_pin_config
),
875 if (!grp
->pins
|| !grp
->data
)
878 for (i
= 0, j
= 0; i
< size
; i
+= 4, j
++) {
879 const __be32
*phandle
;
880 struct device_node
*np_config
;
882 num
= be32_to_cpu(*list
++);
883 bank
= bank_num_to_bank(info
, num
);
885 return PTR_ERR(bank
);
887 grp
->pins
[j
] = bank
->pin_base
+ be32_to_cpu(*list
++);
888 grp
->data
[j
].func
= be32_to_cpu(*list
++);
894 np_config
= of_find_node_by_phandle(be32_to_cpup(phandle
));
895 ret
= pinconf_generic_parse_dt_config(np_config
,
896 &grp
->data
[j
].configs
, &grp
->data
[j
].nconfigs
);
904 static int rockchip_pinctrl_parse_functions(struct device_node
*np
,
905 struct rockchip_pinctrl
*info
,
908 struct device_node
*child
;
909 struct rockchip_pmx_func
*func
;
910 struct rockchip_pin_group
*grp
;
912 static u32 grp_index
;
915 dev_dbg(info
->dev
, "parse function(%d): %s\n", index
, np
->name
);
917 func
= &info
->functions
[index
];
919 /* Initialise function */
920 func
->name
= np
->name
;
921 func
->ngroups
= of_get_child_count(np
);
922 if (func
->ngroups
<= 0)
925 func
->groups
= devm_kzalloc(info
->dev
,
926 func
->ngroups
* sizeof(char *), GFP_KERNEL
);
930 for_each_child_of_node(np
, child
) {
931 func
->groups
[i
] = child
->name
;
932 grp
= &info
->groups
[grp_index
++];
933 ret
= rockchip_pinctrl_parse_groups(child
, grp
, info
, i
++);
941 static int rockchip_pinctrl_parse_dt(struct platform_device
*pdev
,
942 struct rockchip_pinctrl
*info
)
944 struct device
*dev
= &pdev
->dev
;
945 struct device_node
*np
= dev
->of_node
;
946 struct device_node
*child
;
950 rockchip_pinctrl_child_count(info
, np
);
952 dev_dbg(&pdev
->dev
, "nfunctions = %d\n", info
->nfunctions
);
953 dev_dbg(&pdev
->dev
, "ngroups = %d\n", info
->ngroups
);
955 info
->functions
= devm_kzalloc(dev
, info
->nfunctions
*
956 sizeof(struct rockchip_pmx_func
),
958 if (!info
->functions
) {
959 dev_err(dev
, "failed to allocate memory for function list\n");
963 info
->groups
= devm_kzalloc(dev
, info
->ngroups
*
964 sizeof(struct rockchip_pin_group
),
967 dev_err(dev
, "failed allocate memory for ping group list\n");
973 for_each_child_of_node(np
, child
) {
974 if (of_match_node(rockchip_bank_match
, child
))
977 ret
= rockchip_pinctrl_parse_functions(child
, info
, i
++);
979 dev_err(&pdev
->dev
, "failed to parse function\n");
987 static int rockchip_pinctrl_register(struct platform_device
*pdev
,
988 struct rockchip_pinctrl
*info
)
990 struct pinctrl_desc
*ctrldesc
= &info
->pctl
;
991 struct pinctrl_pin_desc
*pindesc
, *pdesc
;
992 struct rockchip_pin_bank
*pin_bank
;
996 ctrldesc
->name
= "rockchip-pinctrl";
997 ctrldesc
->owner
= THIS_MODULE
;
998 ctrldesc
->pctlops
= &rockchip_pctrl_ops
;
999 ctrldesc
->pmxops
= &rockchip_pmx_ops
;
1000 ctrldesc
->confops
= &rockchip_pinconf_ops
;
1002 pindesc
= devm_kzalloc(&pdev
->dev
, sizeof(*pindesc
) *
1003 info
->ctrl
->nr_pins
, GFP_KERNEL
);
1005 dev_err(&pdev
->dev
, "mem alloc for pin descriptors failed\n");
1008 ctrldesc
->pins
= pindesc
;
1009 ctrldesc
->npins
= info
->ctrl
->nr_pins
;
1012 for (bank
= 0 , k
= 0; bank
< info
->ctrl
->nr_banks
; bank
++) {
1013 pin_bank
= &info
->ctrl
->pin_banks
[bank
];
1014 for (pin
= 0; pin
< pin_bank
->nr_pins
; pin
++, k
++) {
1016 pdesc
->name
= kasprintf(GFP_KERNEL
, "%s-%d",
1017 pin_bank
->name
, pin
);
1022 info
->pctl_dev
= pinctrl_register(ctrldesc
, &pdev
->dev
, info
);
1023 if (!info
->pctl_dev
) {
1024 dev_err(&pdev
->dev
, "could not register pinctrl driver\n");
1028 for (bank
= 0; bank
< info
->ctrl
->nr_banks
; ++bank
) {
1029 pin_bank
= &info
->ctrl
->pin_banks
[bank
];
1030 pin_bank
->grange
.name
= pin_bank
->name
;
1031 pin_bank
->grange
.id
= bank
;
1032 pin_bank
->grange
.pin_base
= pin_bank
->pin_base
;
1033 pin_bank
->grange
.base
= pin_bank
->gpio_chip
.base
;
1034 pin_bank
->grange
.npins
= pin_bank
->gpio_chip
.ngpio
;
1035 pin_bank
->grange
.gc
= &pin_bank
->gpio_chip
;
1036 pinctrl_add_gpio_range(info
->pctl_dev
, &pin_bank
->grange
);
1039 ret
= rockchip_pinctrl_parse_dt(pdev
, info
);
1041 pinctrl_unregister(info
->pctl_dev
);
1052 static int rockchip_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
1054 return pinctrl_request_gpio(chip
->base
+ offset
);
1057 static void rockchip_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
1059 pinctrl_free_gpio(chip
->base
+ offset
);
1062 static void rockchip_gpio_set(struct gpio_chip
*gc
, unsigned offset
, int value
)
1064 struct rockchip_pin_bank
*bank
= gc_to_pin_bank(gc
);
1065 void __iomem
*reg
= bank
->reg_base
+ GPIO_SWPORT_DR
;
1066 unsigned long flags
;
1069 spin_lock_irqsave(&bank
->slock
, flags
);
1072 data
&= ~BIT(offset
);
1074 data
|= BIT(offset
);
1077 spin_unlock_irqrestore(&bank
->slock
, flags
);
1081 * Returns the level of the pin for input direction and setting of the DR
1082 * register for output gpios.
1084 static int rockchip_gpio_get(struct gpio_chip
*gc
, unsigned offset
)
1086 struct rockchip_pin_bank
*bank
= gc_to_pin_bank(gc
);
1089 data
= readl(bank
->reg_base
+ GPIO_EXT_PORT
);
1096 * gpiolib gpio_direction_input callback function. The setting of the pin
1097 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1100 static int rockchip_gpio_direction_input(struct gpio_chip
*gc
, unsigned offset
)
1102 return pinctrl_gpio_direction_input(gc
->base
+ offset
);
1106 * gpiolib gpio_direction_output callback function. The setting of the pin
1107 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1110 static int rockchip_gpio_direction_output(struct gpio_chip
*gc
,
1111 unsigned offset
, int value
)
1113 rockchip_gpio_set(gc
, offset
, value
);
1114 return pinctrl_gpio_direction_output(gc
->base
+ offset
);
1118 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1119 * and a virtual IRQ, if not already present.
1121 static int rockchip_gpio_to_irq(struct gpio_chip
*gc
, unsigned offset
)
1123 struct rockchip_pin_bank
*bank
= gc_to_pin_bank(gc
);
1129 virq
= irq_create_mapping(bank
->domain
, offset
);
1131 return (virq
) ? : -ENXIO
;
1134 static const struct gpio_chip rockchip_gpiolib_chip
= {
1135 .request
= rockchip_gpio_request
,
1136 .free
= rockchip_gpio_free
,
1137 .set
= rockchip_gpio_set
,
1138 .get
= rockchip_gpio_get
,
1139 .direction_input
= rockchip_gpio_direction_input
,
1140 .direction_output
= rockchip_gpio_direction_output
,
1141 .to_irq
= rockchip_gpio_to_irq
,
1142 .owner
= THIS_MODULE
,
1146 * Interrupt handling
1149 static void rockchip_irq_demux(unsigned int irq
, struct irq_desc
*desc
)
1151 struct irq_chip
*chip
= irq_get_chip(irq
);
1152 struct rockchip_pin_bank
*bank
= irq_get_handler_data(irq
);
1153 u32 polarity
= 0, data
= 0;
1155 bool edge_changed
= false;
1157 dev_dbg(bank
->drvdata
->dev
, "got irq for bank %s\n", bank
->name
);
1159 chained_irq_enter(chip
, desc
);
1161 pend
= readl_relaxed(bank
->reg_base
+ GPIO_INT_STATUS
);
1163 if (bank
->toggle_edge_mode
) {
1164 polarity
= readl_relaxed(bank
->reg_base
+
1166 data
= readl_relaxed(bank
->reg_base
+ GPIO_EXT_PORT
);
1174 virq
= irq_linear_revmap(bank
->domain
, irq
);
1177 dev_err(bank
->drvdata
->dev
, "unmapped irq %d\n", irq
);
1181 dev_dbg(bank
->drvdata
->dev
, "handling irq %d\n", irq
);
1184 * Triggering IRQ on both rising and falling edge
1185 * needs manual intervention.
1187 if (bank
->toggle_edge_mode
& BIT(irq
)) {
1188 if (data
& BIT(irq
))
1189 polarity
&= ~BIT(irq
);
1191 polarity
|= BIT(irq
);
1193 edge_changed
= true;
1196 generic_handle_irq(virq
);
1199 if (bank
->toggle_edge_mode
&& edge_changed
) {
1200 /* Interrupt params should only be set with ints disabled */
1201 data
= readl_relaxed(bank
->reg_base
+ GPIO_INTEN
);
1202 writel_relaxed(0, bank
->reg_base
+ GPIO_INTEN
);
1203 writel(polarity
, bank
->reg_base
+ GPIO_INT_POLARITY
);
1204 writel(data
, bank
->reg_base
+ GPIO_INTEN
);
1207 chained_irq_exit(chip
, desc
);
1210 static int rockchip_irq_set_type(struct irq_data
*d
, unsigned int type
)
1212 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
1213 struct rockchip_pin_bank
*bank
= gc
->private;
1214 u32 mask
= BIT(d
->hwirq
);
1220 /* make sure the pin is configured as gpio input */
1221 ret
= rockchip_set_mux(bank
, d
->hwirq
, RK_FUNC_GPIO
);
1225 data
= readl_relaxed(bank
->reg_base
+ GPIO_SWPORT_DDR
);
1227 writel_relaxed(data
, bank
->reg_base
+ GPIO_SWPORT_DDR
);
1229 if (type
& IRQ_TYPE_EDGE_BOTH
)
1230 __irq_set_handler_locked(d
->irq
, handle_edge_irq
);
1232 __irq_set_handler_locked(d
->irq
, handle_level_irq
);
1236 level
= readl_relaxed(gc
->reg_base
+ GPIO_INTTYPE_LEVEL
);
1237 polarity
= readl_relaxed(gc
->reg_base
+ GPIO_INT_POLARITY
);
1240 case IRQ_TYPE_EDGE_BOTH
:
1241 bank
->toggle_edge_mode
|= mask
;
1245 * Determine gpio state. If 1 next interrupt should be falling
1248 data
= readl(bank
->reg_base
+ GPIO_EXT_PORT
);
1254 case IRQ_TYPE_EDGE_RISING
:
1255 bank
->toggle_edge_mode
&= ~mask
;
1259 case IRQ_TYPE_EDGE_FALLING
:
1260 bank
->toggle_edge_mode
&= ~mask
;
1264 case IRQ_TYPE_LEVEL_HIGH
:
1265 bank
->toggle_edge_mode
&= ~mask
;
1269 case IRQ_TYPE_LEVEL_LOW
:
1270 bank
->toggle_edge_mode
&= ~mask
;
1279 writel_relaxed(level
, gc
->reg_base
+ GPIO_INTTYPE_LEVEL
);
1280 writel_relaxed(polarity
, gc
->reg_base
+ GPIO_INT_POLARITY
);
1287 static int rockchip_interrupts_register(struct platform_device
*pdev
,
1288 struct rockchip_pinctrl
*info
)
1290 struct rockchip_pin_ctrl
*ctrl
= info
->ctrl
;
1291 struct rockchip_pin_bank
*bank
= ctrl
->pin_banks
;
1292 unsigned int clr
= IRQ_NOREQUEST
| IRQ_NOPROBE
| IRQ_NOAUTOEN
;
1293 struct irq_chip_generic
*gc
;
1297 for (i
= 0; i
< ctrl
->nr_banks
; ++i
, ++bank
) {
1299 dev_warn(&pdev
->dev
, "bank %s is not valid\n",
1304 bank
->domain
= irq_domain_add_linear(bank
->of_node
, 32,
1305 &irq_generic_chip_ops
, NULL
);
1306 if (!bank
->domain
) {
1307 dev_warn(&pdev
->dev
, "could not initialize irq domain for bank %s\n",
1312 ret
= irq_alloc_domain_generic_chips(bank
->domain
, 32, 1,
1313 "rockchip_gpio_irq", handle_level_irq
,
1314 clr
, 0, IRQ_GC_INIT_MASK_CACHE
);
1316 dev_err(&pdev
->dev
, "could not alloc generic chips for bank %s\n",
1318 irq_domain_remove(bank
->domain
);
1322 gc
= irq_get_domain_generic_chip(bank
->domain
, 0);
1323 gc
->reg_base
= bank
->reg_base
;
1325 gc
->chip_types
[0].regs
.mask
= GPIO_INTEN
;
1326 gc
->chip_types
[0].regs
.ack
= GPIO_PORTS_EOI
;
1327 gc
->chip_types
[0].chip
.irq_ack
= irq_gc_ack_set_bit
;
1328 gc
->chip_types
[0].chip
.irq_mask
= irq_gc_mask_clr_bit
;
1329 gc
->chip_types
[0].chip
.irq_unmask
= irq_gc_mask_set_bit
;
1330 gc
->chip_types
[0].chip
.irq_set_wake
= irq_gc_set_wake
;
1331 gc
->chip_types
[0].chip
.irq_set_type
= rockchip_irq_set_type
;
1333 irq_set_handler_data(bank
->irq
, bank
);
1334 irq_set_chained_handler(bank
->irq
, rockchip_irq_demux
);
1340 static int rockchip_gpiolib_register(struct platform_device
*pdev
,
1341 struct rockchip_pinctrl
*info
)
1343 struct rockchip_pin_ctrl
*ctrl
= info
->ctrl
;
1344 struct rockchip_pin_bank
*bank
= ctrl
->pin_banks
;
1345 struct gpio_chip
*gc
;
1349 for (i
= 0; i
< ctrl
->nr_banks
; ++i
, ++bank
) {
1351 dev_warn(&pdev
->dev
, "bank %s is not valid\n",
1356 bank
->gpio_chip
= rockchip_gpiolib_chip
;
1358 gc
= &bank
->gpio_chip
;
1359 gc
->base
= bank
->pin_base
;
1360 gc
->ngpio
= bank
->nr_pins
;
1361 gc
->dev
= &pdev
->dev
;
1362 gc
->of_node
= bank
->of_node
;
1363 gc
->label
= bank
->name
;
1365 ret
= gpiochip_add(gc
);
1367 dev_err(&pdev
->dev
, "failed to register gpio_chip %s, error code: %d\n",
1373 rockchip_interrupts_register(pdev
, info
);
1378 for (--i
, --bank
; i
>= 0; --i
, --bank
) {
1382 if (gpiochip_remove(&bank
->gpio_chip
))
1383 dev_err(&pdev
->dev
, "gpio chip %s remove failed\n",
1384 bank
->gpio_chip
.label
);
1389 static int rockchip_gpiolib_unregister(struct platform_device
*pdev
,
1390 struct rockchip_pinctrl
*info
)
1392 struct rockchip_pin_ctrl
*ctrl
= info
->ctrl
;
1393 struct rockchip_pin_bank
*bank
= ctrl
->pin_banks
;
1397 for (i
= 0; !ret
&& i
< ctrl
->nr_banks
; ++i
, ++bank
) {
1401 ret
= gpiochip_remove(&bank
->gpio_chip
);
1405 dev_err(&pdev
->dev
, "gpio chip remove failed\n");
1410 static int rockchip_get_bank_data(struct rockchip_pin_bank
*bank
,
1413 struct resource res
;
1415 if (of_address_to_resource(bank
->of_node
, 0, &res
)) {
1416 dev_err(dev
, "cannot find IO resource for bank\n");
1420 bank
->reg_base
= devm_ioremap_resource(dev
, &res
);
1421 if (IS_ERR(bank
->reg_base
))
1422 return PTR_ERR(bank
->reg_base
);
1425 * special case, where parts of the pull setting-registers are
1426 * part of the PMU register space
1428 if (of_device_is_compatible(bank
->of_node
,
1429 "rockchip,rk3188-gpio-bank0")) {
1430 bank
->bank_type
= RK3188_BANK0
;
1432 if (of_address_to_resource(bank
->of_node
, 1, &res
)) {
1433 dev_err(dev
, "cannot find IO resource for bank\n");
1437 bank
->reg_pull
= devm_ioremap_resource(dev
, &res
);
1438 if (IS_ERR(bank
->reg_pull
))
1439 return PTR_ERR(bank
->reg_pull
);
1441 bank
->bank_type
= COMMON_BANK
;
1444 bank
->irq
= irq_of_parse_and_map(bank
->of_node
, 0);
1446 bank
->clk
= of_clk_get(bank
->of_node
, 0);
1447 if (IS_ERR(bank
->clk
))
1448 return PTR_ERR(bank
->clk
);
1450 return clk_prepare_enable(bank
->clk
);
1453 static const struct of_device_id rockchip_pinctrl_dt_match
[];
1455 /* retrieve the soc specific data */
1456 static struct rockchip_pin_ctrl
*rockchip_pinctrl_get_soc_data(
1457 struct rockchip_pinctrl
*d
,
1458 struct platform_device
*pdev
)
1460 const struct of_device_id
*match
;
1461 struct device_node
*node
= pdev
->dev
.of_node
;
1462 struct device_node
*np
;
1463 struct rockchip_pin_ctrl
*ctrl
;
1464 struct rockchip_pin_bank
*bank
;
1467 match
= of_match_node(rockchip_pinctrl_dt_match
, node
);
1468 ctrl
= (struct rockchip_pin_ctrl
*)match
->data
;
1470 for_each_child_of_node(node
, np
) {
1471 if (!of_find_property(np
, "gpio-controller", NULL
))
1474 bank
= ctrl
->pin_banks
;
1475 for (i
= 0; i
< ctrl
->nr_banks
; ++i
, ++bank
) {
1476 if (!strcmp(bank
->name
, np
->name
)) {
1479 if (!rockchip_get_bank_data(bank
, &pdev
->dev
))
1487 bank
= ctrl
->pin_banks
;
1488 for (i
= 0; i
< ctrl
->nr_banks
; ++i
, ++bank
) {
1489 spin_lock_init(&bank
->slock
);
1491 bank
->pin_base
= ctrl
->nr_pins
;
1492 ctrl
->nr_pins
+= bank
->nr_pins
;
1498 static int rockchip_pinctrl_probe(struct platform_device
*pdev
)
1500 struct rockchip_pinctrl
*info
;
1501 struct device
*dev
= &pdev
->dev
;
1502 struct rockchip_pin_ctrl
*ctrl
;
1503 struct resource
*res
;
1506 if (!dev
->of_node
) {
1507 dev_err(dev
, "device tree node not found\n");
1511 info
= devm_kzalloc(dev
, sizeof(struct rockchip_pinctrl
), GFP_KERNEL
);
1515 ctrl
= rockchip_pinctrl_get_soc_data(info
, pdev
);
1517 dev_err(dev
, "driver data not available\n");
1523 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1524 info
->reg_base
= devm_ioremap_resource(&pdev
->dev
, res
);
1525 if (IS_ERR(info
->reg_base
))
1526 return PTR_ERR(info
->reg_base
);
1528 /* The RK3188 has its pull registers in a separate place */
1529 if (ctrl
->type
== RK3188
) {
1530 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1531 info
->reg_pull
= devm_ioremap_resource(&pdev
->dev
, res
);
1532 if (IS_ERR(info
->reg_pull
))
1533 return PTR_ERR(info
->reg_pull
);
1536 ret
= rockchip_gpiolib_register(pdev
, info
);
1540 ret
= rockchip_pinctrl_register(pdev
, info
);
1542 rockchip_gpiolib_unregister(pdev
, info
);
1546 platform_set_drvdata(pdev
, info
);
1551 static struct rockchip_pin_bank rk2928_pin_banks
[] = {
1552 PIN_BANK(0, 32, "gpio0"),
1553 PIN_BANK(1, 32, "gpio1"),
1554 PIN_BANK(2, 32, "gpio2"),
1555 PIN_BANK(3, 32, "gpio3"),
1558 static struct rockchip_pin_ctrl rk2928_pin_ctrl
= {
1559 .pin_banks
= rk2928_pin_banks
,
1560 .nr_banks
= ARRAY_SIZE(rk2928_pin_banks
),
1561 .label
= "RK2928-GPIO",
1564 .pull_calc_reg
= rk2928_calc_pull_reg_and_bit
,
1567 static struct rockchip_pin_bank rk3066a_pin_banks
[] = {
1568 PIN_BANK(0, 32, "gpio0"),
1569 PIN_BANK(1, 32, "gpio1"),
1570 PIN_BANK(2, 32, "gpio2"),
1571 PIN_BANK(3, 32, "gpio3"),
1572 PIN_BANK(4, 32, "gpio4"),
1573 PIN_BANK(6, 16, "gpio6"),
1576 static struct rockchip_pin_ctrl rk3066a_pin_ctrl
= {
1577 .pin_banks
= rk3066a_pin_banks
,
1578 .nr_banks
= ARRAY_SIZE(rk3066a_pin_banks
),
1579 .label
= "RK3066a-GPIO",
1582 .pull_calc_reg
= rk2928_calc_pull_reg_and_bit
,
1585 static struct rockchip_pin_bank rk3066b_pin_banks
[] = {
1586 PIN_BANK(0, 32, "gpio0"),
1587 PIN_BANK(1, 32, "gpio1"),
1588 PIN_BANK(2, 32, "gpio2"),
1589 PIN_BANK(3, 32, "gpio3"),
1592 static struct rockchip_pin_ctrl rk3066b_pin_ctrl
= {
1593 .pin_banks
= rk3066b_pin_banks
,
1594 .nr_banks
= ARRAY_SIZE(rk3066b_pin_banks
),
1595 .label
= "RK3066b-GPIO",
1600 static struct rockchip_pin_bank rk3188_pin_banks
[] = {
1601 PIN_BANK(0, 32, "gpio0"),
1602 PIN_BANK(1, 32, "gpio1"),
1603 PIN_BANK(2, 32, "gpio2"),
1604 PIN_BANK(3, 32, "gpio3"),
1607 static struct rockchip_pin_ctrl rk3188_pin_ctrl
= {
1608 .pin_banks
= rk3188_pin_banks
,
1609 .nr_banks
= ARRAY_SIZE(rk3188_pin_banks
),
1610 .label
= "RK3188-GPIO",
1613 .pull_calc_reg
= rk3188_calc_pull_reg_and_bit
,
1616 static const struct of_device_id rockchip_pinctrl_dt_match
[] = {
1617 { .compatible
= "rockchip,rk2928-pinctrl",
1618 .data
= (void *)&rk2928_pin_ctrl
},
1619 { .compatible
= "rockchip,rk3066a-pinctrl",
1620 .data
= (void *)&rk3066a_pin_ctrl
},
1621 { .compatible
= "rockchip,rk3066b-pinctrl",
1622 .data
= (void *)&rk3066b_pin_ctrl
},
1623 { .compatible
= "rockchip,rk3188-pinctrl",
1624 .data
= (void *)&rk3188_pin_ctrl
},
1627 MODULE_DEVICE_TABLE(of
, rockchip_pinctrl_dt_match
);
1629 static struct platform_driver rockchip_pinctrl_driver
= {
1630 .probe
= rockchip_pinctrl_probe
,
1632 .name
= "rockchip-pinctrl",
1633 .owner
= THIS_MODULE
,
1634 .of_match_table
= rockchip_pinctrl_dt_match
,
1638 static int __init
rockchip_pinctrl_drv_register(void)
1640 return platform_driver_register(&rockchip_pinctrl_driver
);
1642 postcore_initcall(rockchip_pinctrl_drv_register
);
1644 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
1645 MODULE_DESCRIPTION("Rockchip pinctrl driver");
1646 MODULE_LICENSE("GPL v2");