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pinctrl: rockchip: return a complete config in pinconf_get
[deliverable/linux.git] / drivers / pinctrl / pinctrl-rockchip.c
1 /*
2 * Pinctrl driver for Rockchip SoCs
3 *
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
6 *
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
12 *
13 * and pinctrl-at91:
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 */
25
26 #include <linux/module.h>
27 #include <linux/platform_device.h>
28 #include <linux/io.h>
29 #include <linux/bitops.h>
30 #include <linux/gpio.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/pinctrl/machine.h>
34 #include <linux/pinctrl/pinconf.h>
35 #include <linux/pinctrl/pinctrl.h>
36 #include <linux/pinctrl/pinmux.h>
37 #include <linux/pinctrl/pinconf-generic.h>
38 #include <linux/irqchip/chained_irq.h>
39 #include <linux/clk.h>
40 #include <dt-bindings/pinctrl/rockchip.h>
41
42 #include "core.h"
43 #include "pinconf.h"
44
45 /* GPIO control registers */
46 #define GPIO_SWPORT_DR 0x00
47 #define GPIO_SWPORT_DDR 0x04
48 #define GPIO_INTEN 0x30
49 #define GPIO_INTMASK 0x34
50 #define GPIO_INTTYPE_LEVEL 0x38
51 #define GPIO_INT_POLARITY 0x3c
52 #define GPIO_INT_STATUS 0x40
53 #define GPIO_INT_RAWSTATUS 0x44
54 #define GPIO_DEBOUNCE 0x48
55 #define GPIO_PORTS_EOI 0x4c
56 #define GPIO_EXT_PORT 0x50
57 #define GPIO_LS_SYNC 0x60
58
59 enum rockchip_pinctrl_type {
60 RK2928,
61 RK3066B,
62 RK3188,
63 };
64
65 enum rockchip_pin_bank_type {
66 COMMON_BANK,
67 RK3188_BANK0,
68 };
69
70 /**
71 * @reg_base: register base of the gpio bank
72 * @reg_pull: optional separate register for additional pull settings
73 * @clk: clock of the gpio bank
74 * @irq: interrupt of the gpio bank
75 * @pin_base: first pin number
76 * @nr_pins: number of pins in this bank
77 * @name: name of the bank
78 * @bank_num: number of the bank, to account for holes
79 * @valid: are all necessary informations present
80 * @of_node: dt node of this bank
81 * @drvdata: common pinctrl basedata
82 * @domain: irqdomain of the gpio bank
83 * @gpio_chip: gpiolib chip
84 * @grange: gpio range
85 * @slock: spinlock for the gpio bank
86 */
87 struct rockchip_pin_bank {
88 void __iomem *reg_base;
89 void __iomem *reg_pull;
90 struct clk *clk;
91 int irq;
92 u32 pin_base;
93 u8 nr_pins;
94 char *name;
95 u8 bank_num;
96 enum rockchip_pin_bank_type bank_type;
97 bool valid;
98 struct device_node *of_node;
99 struct rockchip_pinctrl *drvdata;
100 struct irq_domain *domain;
101 struct gpio_chip gpio_chip;
102 struct pinctrl_gpio_range grange;
103 spinlock_t slock;
104 u32 toggle_edge_mode;
105 };
106
107 #define PIN_BANK(id, pins, label) \
108 { \
109 .bank_num = id, \
110 .nr_pins = pins, \
111 .name = label, \
112 }
113
114 /**
115 */
116 struct rockchip_pin_ctrl {
117 struct rockchip_pin_bank *pin_banks;
118 u32 nr_banks;
119 u32 nr_pins;
120 char *label;
121 enum rockchip_pinctrl_type type;
122 int mux_offset;
123 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num,
124 void __iomem **reg, u8 *bit);
125 };
126
127 struct rockchip_pin_config {
128 unsigned int func;
129 unsigned long *configs;
130 unsigned int nconfigs;
131 };
132
133 /**
134 * struct rockchip_pin_group: represent group of pins of a pinmux function.
135 * @name: name of the pin group, used to lookup the group.
136 * @pins: the pins included in this group.
137 * @npins: number of pins included in this group.
138 * @func: the mux function number to be programmed when selected.
139 * @configs: the config values to be set for each pin
140 * @nconfigs: number of configs for each pin
141 */
142 struct rockchip_pin_group {
143 const char *name;
144 unsigned int npins;
145 unsigned int *pins;
146 struct rockchip_pin_config *data;
147 };
148
149 /**
150 * struct rockchip_pmx_func: represent a pin function.
151 * @name: name of the pin function, used to lookup the function.
152 * @groups: one or more names of pin groups that provide this function.
153 * @num_groups: number of groups included in @groups.
154 */
155 struct rockchip_pmx_func {
156 const char *name;
157 const char **groups;
158 u8 ngroups;
159 };
160
161 struct rockchip_pinctrl {
162 void __iomem *reg_base;
163 void __iomem *reg_pull;
164 struct device *dev;
165 struct rockchip_pin_ctrl *ctrl;
166 struct pinctrl_desc pctl;
167 struct pinctrl_dev *pctl_dev;
168 struct rockchip_pin_group *groups;
169 unsigned int ngroups;
170 struct rockchip_pmx_func *functions;
171 unsigned int nfunctions;
172 };
173
174 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
175 {
176 return container_of(gc, struct rockchip_pin_bank, gpio_chip);
177 }
178
179 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
180 const struct rockchip_pinctrl *info,
181 const char *name)
182 {
183 int i;
184
185 for (i = 0; i < info->ngroups; i++) {
186 if (!strcmp(info->groups[i].name, name))
187 return &info->groups[i];
188 }
189
190 return NULL;
191 }
192
193 /*
194 * given a pin number that is local to a pin controller, find out the pin bank
195 * and the register base of the pin bank.
196 */
197 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
198 unsigned pin)
199 {
200 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
201
202 while (pin >= (b->pin_base + b->nr_pins))
203 b++;
204
205 return b;
206 }
207
208 static struct rockchip_pin_bank *bank_num_to_bank(
209 struct rockchip_pinctrl *info,
210 unsigned num)
211 {
212 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
213 int i;
214
215 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
216 if (b->bank_num == num)
217 return b;
218 }
219
220 return ERR_PTR(-EINVAL);
221 }
222
223 /*
224 * Pinctrl_ops handling
225 */
226
227 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
228 {
229 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
230
231 return info->ngroups;
232 }
233
234 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
235 unsigned selector)
236 {
237 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
238
239 return info->groups[selector].name;
240 }
241
242 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
243 unsigned selector, const unsigned **pins,
244 unsigned *npins)
245 {
246 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
247
248 if (selector >= info->ngroups)
249 return -EINVAL;
250
251 *pins = info->groups[selector].pins;
252 *npins = info->groups[selector].npins;
253
254 return 0;
255 }
256
257 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
258 struct device_node *np,
259 struct pinctrl_map **map, unsigned *num_maps)
260 {
261 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
262 const struct rockchip_pin_group *grp;
263 struct pinctrl_map *new_map;
264 struct device_node *parent;
265 int map_num = 1;
266 int i;
267
268 /*
269 * first find the group of this node and check if we need to create
270 * config maps for pins
271 */
272 grp = pinctrl_name_to_group(info, np->name);
273 if (!grp) {
274 dev_err(info->dev, "unable to find group for node %s\n",
275 np->name);
276 return -EINVAL;
277 }
278
279 map_num += grp->npins;
280 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
281 GFP_KERNEL);
282 if (!new_map)
283 return -ENOMEM;
284
285 *map = new_map;
286 *num_maps = map_num;
287
288 /* create mux map */
289 parent = of_get_parent(np);
290 if (!parent) {
291 devm_kfree(pctldev->dev, new_map);
292 return -EINVAL;
293 }
294 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
295 new_map[0].data.mux.function = parent->name;
296 new_map[0].data.mux.group = np->name;
297 of_node_put(parent);
298
299 /* create config map */
300 new_map++;
301 for (i = 0; i < grp->npins; i++) {
302 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
303 new_map[i].data.configs.group_or_pin =
304 pin_get_name(pctldev, grp->pins[i]);
305 new_map[i].data.configs.configs = grp->data[i].configs;
306 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
307 }
308
309 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
310 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
311
312 return 0;
313 }
314
315 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
316 struct pinctrl_map *map, unsigned num_maps)
317 {
318 }
319
320 static const struct pinctrl_ops rockchip_pctrl_ops = {
321 .get_groups_count = rockchip_get_groups_count,
322 .get_group_name = rockchip_get_group_name,
323 .get_group_pins = rockchip_get_group_pins,
324 .dt_node_to_map = rockchip_dt_node_to_map,
325 .dt_free_map = rockchip_dt_free_map,
326 };
327
328 /*
329 * Hardware access
330 */
331
332 /*
333 * Set a new mux function for a pin.
334 *
335 * The register is divided into the upper and lower 16 bit. When changing
336 * a value, the previous register value is not read and changed. Instead
337 * it seems the changed bits are marked in the upper 16 bit, while the
338 * changed value gets set in the same offset in the lower 16 bit.
339 * All pin settings seem to be 2 bit wide in both the upper and lower
340 * parts.
341 * @bank: pin bank to change
342 * @pin: pin to change
343 * @mux: new mux function to set
344 */
345 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
346 {
347 struct rockchip_pinctrl *info = bank->drvdata;
348 void __iomem *reg = info->reg_base + info->ctrl->mux_offset;
349 unsigned long flags;
350 u8 bit;
351 u32 data;
352
353 /*
354 * The first 16 pins of rk3188_bank0 are always gpios and do not have
355 * a mux register at all.
356 */
357 if (bank->bank_type == RK3188_BANK0 && pin < 16) {
358 if (mux != RK_FUNC_GPIO) {
359 dev_err(info->dev,
360 "pin %d only supports a gpio mux\n", pin);
361 return -ENOTSUPP;
362 } else {
363 return 0;
364 }
365 }
366
367 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
368 bank->bank_num, pin, mux);
369
370 /* get basic quadrupel of mux registers and the correct reg inside */
371 reg += bank->bank_num * 0x10;
372 reg += (pin / 8) * 4;
373 bit = (pin % 8) * 2;
374
375 spin_lock_irqsave(&bank->slock, flags);
376
377 data = (3 << (bit + 16));
378 data |= (mux & 3) << bit;
379 writel(data, reg);
380
381 spin_unlock_irqrestore(&bank->slock, flags);
382
383 return 0;
384 }
385
386 #define RK2928_PULL_OFFSET 0x118
387 #define RK2928_PULL_PINS_PER_REG 16
388 #define RK2928_PULL_BANK_STRIDE 8
389
390 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
391 int pin_num, void __iomem **reg, u8 *bit)
392 {
393 struct rockchip_pinctrl *info = bank->drvdata;
394
395 *reg = info->reg_base + RK2928_PULL_OFFSET;
396 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
397 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
398
399 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
400 };
401
402 #define RK3188_PULL_BITS_PER_PIN 2
403 #define RK3188_PULL_PINS_PER_REG 8
404 #define RK3188_PULL_BANK_STRIDE 16
405
406 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
407 int pin_num, void __iomem **reg, u8 *bit)
408 {
409 struct rockchip_pinctrl *info = bank->drvdata;
410
411 /* The first 12 pins of the first bank are located elsewhere */
412 if (bank->bank_type == RK3188_BANK0 && pin_num < 12) {
413 *reg = bank->reg_pull +
414 ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
415 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
416 *bit *= RK3188_PULL_BITS_PER_PIN;
417 } else {
418 *reg = info->reg_pull - 4;
419 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
420 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
421
422 /*
423 * The bits in these registers have an inverse ordering
424 * with the lowest pin being in bits 15:14 and the highest
425 * pin in bits 1:0
426 */
427 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
428 *bit *= RK3188_PULL_BITS_PER_PIN;
429 }
430 }
431
432 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
433 {
434 struct rockchip_pinctrl *info = bank->drvdata;
435 struct rockchip_pin_ctrl *ctrl = info->ctrl;
436 void __iomem *reg;
437 u8 bit;
438 u32 data;
439
440 /* rk3066b does support any pulls */
441 if (ctrl->type == RK3066B)
442 return PIN_CONFIG_BIAS_DISABLE;
443
444 ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
445
446 switch (ctrl->type) {
447 case RK2928:
448 return !(readl_relaxed(reg) & BIT(bit))
449 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
450 : PIN_CONFIG_BIAS_DISABLE;
451 case RK3188:
452 data = readl_relaxed(reg) >> bit;
453 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
454
455 switch (data) {
456 case 0:
457 return PIN_CONFIG_BIAS_DISABLE;
458 case 1:
459 return PIN_CONFIG_BIAS_PULL_UP;
460 case 2:
461 return PIN_CONFIG_BIAS_PULL_DOWN;
462 case 3:
463 return PIN_CONFIG_BIAS_BUS_HOLD;
464 }
465
466 dev_err(info->dev, "unknown pull setting\n");
467 return -EIO;
468 default:
469 dev_err(info->dev, "unsupported pinctrl type\n");
470 return -EINVAL;
471 };
472 }
473
474 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
475 int pin_num, int pull)
476 {
477 struct rockchip_pinctrl *info = bank->drvdata;
478 struct rockchip_pin_ctrl *ctrl = info->ctrl;
479 void __iomem *reg;
480 unsigned long flags;
481 u8 bit;
482 u32 data;
483
484 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
485 bank->bank_num, pin_num, pull);
486
487 /* rk3066b does support any pulls */
488 if (ctrl->type == RK3066B)
489 return pull ? -EINVAL : 0;
490
491 ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
492
493 switch (ctrl->type) {
494 case RK2928:
495 spin_lock_irqsave(&bank->slock, flags);
496
497 data = BIT(bit + 16);
498 if (pull == PIN_CONFIG_BIAS_DISABLE)
499 data |= BIT(bit);
500 writel(data, reg);
501
502 spin_unlock_irqrestore(&bank->slock, flags);
503 break;
504 case RK3188:
505 spin_lock_irqsave(&bank->slock, flags);
506
507 /* enable the write to the equivalent lower bits */
508 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
509
510 switch (pull) {
511 case PIN_CONFIG_BIAS_DISABLE:
512 break;
513 case PIN_CONFIG_BIAS_PULL_UP:
514 data |= (1 << bit);
515 break;
516 case PIN_CONFIG_BIAS_PULL_DOWN:
517 data |= (2 << bit);
518 break;
519 case PIN_CONFIG_BIAS_BUS_HOLD:
520 data |= (3 << bit);
521 break;
522 default:
523 spin_unlock_irqrestore(&bank->slock, flags);
524 dev_err(info->dev, "unsupported pull setting %d\n",
525 pull);
526 return -EINVAL;
527 }
528
529 writel(data, reg);
530
531 spin_unlock_irqrestore(&bank->slock, flags);
532 break;
533 default:
534 dev_err(info->dev, "unsupported pinctrl type\n");
535 return -EINVAL;
536 }
537
538 return 0;
539 }
540
541 /*
542 * Pinmux_ops handling
543 */
544
545 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
546 {
547 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
548
549 return info->nfunctions;
550 }
551
552 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
553 unsigned selector)
554 {
555 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
556
557 return info->functions[selector].name;
558 }
559
560 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
561 unsigned selector, const char * const **groups,
562 unsigned * const num_groups)
563 {
564 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
565
566 *groups = info->functions[selector].groups;
567 *num_groups = info->functions[selector].ngroups;
568
569 return 0;
570 }
571
572 static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
573 unsigned group)
574 {
575 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
576 const unsigned int *pins = info->groups[group].pins;
577 const struct rockchip_pin_config *data = info->groups[group].data;
578 struct rockchip_pin_bank *bank;
579 int cnt, ret = 0;
580
581 dev_dbg(info->dev, "enable function %s group %s\n",
582 info->functions[selector].name, info->groups[group].name);
583
584 /*
585 * for each pin in the pin group selected, program the correspoding pin
586 * pin function number in the config register.
587 */
588 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
589 bank = pin_to_bank(info, pins[cnt]);
590 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
591 data[cnt].func);
592 if (ret)
593 break;
594 }
595
596 if (ret) {
597 /* revert the already done pin settings */
598 for (cnt--; cnt >= 0; cnt--)
599 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
600
601 return ret;
602 }
603
604 return 0;
605 }
606
607 static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
608 unsigned selector, unsigned group)
609 {
610 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
611 const unsigned int *pins = info->groups[group].pins;
612 struct rockchip_pin_bank *bank;
613 int cnt;
614
615 dev_dbg(info->dev, "disable function %s group %s\n",
616 info->functions[selector].name, info->groups[group].name);
617
618 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
619 bank = pin_to_bank(info, pins[cnt]);
620 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
621 }
622 }
623
624 /*
625 * The calls to gpio_direction_output() and gpio_direction_input()
626 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
627 * function called from the gpiolib interface).
628 */
629 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
630 struct pinctrl_gpio_range *range,
631 unsigned offset, bool input)
632 {
633 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
634 struct rockchip_pin_bank *bank;
635 struct gpio_chip *chip;
636 int pin, ret;
637 u32 data;
638
639 chip = range->gc;
640 bank = gc_to_pin_bank(chip);
641 pin = offset - chip->base;
642
643 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
644 offset, range->name, pin, input ? "input" : "output");
645
646 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
647 if (ret < 0)
648 return ret;
649
650 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
651 /* set bit to 1 for output, 0 for input */
652 if (!input)
653 data |= BIT(pin);
654 else
655 data &= ~BIT(pin);
656 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
657
658 return 0;
659 }
660
661 static const struct pinmux_ops rockchip_pmx_ops = {
662 .get_functions_count = rockchip_pmx_get_funcs_count,
663 .get_function_name = rockchip_pmx_get_func_name,
664 .get_function_groups = rockchip_pmx_get_groups,
665 .enable = rockchip_pmx_enable,
666 .disable = rockchip_pmx_disable,
667 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
668 };
669
670 /*
671 * Pinconf_ops handling
672 */
673
674 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
675 enum pin_config_param pull)
676 {
677 switch (ctrl->type) {
678 case RK2928:
679 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
680 pull == PIN_CONFIG_BIAS_DISABLE);
681 case RK3066B:
682 return pull ? false : true;
683 case RK3188:
684 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
685 }
686
687 return false;
688 }
689
690 /* set the pin config settings for a specified pin */
691 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
692 unsigned long *configs, unsigned num_configs)
693 {
694 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
695 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
696 enum pin_config_param param;
697 u16 arg;
698 int i;
699 int rc;
700
701 for (i = 0; i < num_configs; i++) {
702 param = pinconf_to_config_param(configs[i]);
703 arg = pinconf_to_config_argument(configs[i]);
704
705 switch (param) {
706 case PIN_CONFIG_BIAS_DISABLE:
707 rc = rockchip_set_pull(bank, pin - bank->pin_base,
708 param);
709 if (rc)
710 return rc;
711 break;
712 case PIN_CONFIG_BIAS_PULL_UP:
713 case PIN_CONFIG_BIAS_PULL_DOWN:
714 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
715 case PIN_CONFIG_BIAS_BUS_HOLD:
716 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
717 return -ENOTSUPP;
718
719 if (!arg)
720 return -EINVAL;
721
722 rc = rockchip_set_pull(bank, pin - bank->pin_base,
723 param);
724 if (rc)
725 return rc;
726 break;
727 default:
728 return -ENOTSUPP;
729 break;
730 }
731 } /* for each config */
732
733 return 0;
734 }
735
736 /* get the pin config settings for a specified pin */
737 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
738 unsigned long *config)
739 {
740 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
741 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
742 enum pin_config_param param = pinconf_to_config_param(*config);
743 u16 arg;
744
745 switch (param) {
746 case PIN_CONFIG_BIAS_DISABLE:
747 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
748 return -EINVAL;
749
750 arg = 0;
751 break;
752 case PIN_CONFIG_BIAS_PULL_UP:
753 case PIN_CONFIG_BIAS_PULL_DOWN:
754 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
755 case PIN_CONFIG_BIAS_BUS_HOLD:
756 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
757 return -ENOTSUPP;
758
759 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
760 return -EINVAL;
761
762 arg = 1;
763 break;
764 default:
765 return -ENOTSUPP;
766 break;
767 }
768
769 *config = pinconf_to_config_packed(param, arg);
770
771 return 0;
772 }
773
774 static const struct pinconf_ops rockchip_pinconf_ops = {
775 .pin_config_get = rockchip_pinconf_get,
776 .pin_config_set = rockchip_pinconf_set,
777 };
778
779 static const struct of_device_id rockchip_bank_match[] = {
780 { .compatible = "rockchip,gpio-bank" },
781 { .compatible = "rockchip,rk3188-gpio-bank0" },
782 {},
783 };
784
785 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
786 struct device_node *np)
787 {
788 struct device_node *child;
789
790 for_each_child_of_node(np, child) {
791 if (of_match_node(rockchip_bank_match, child))
792 continue;
793
794 info->nfunctions++;
795 info->ngroups += of_get_child_count(child);
796 }
797 }
798
799 static int rockchip_pinctrl_parse_groups(struct device_node *np,
800 struct rockchip_pin_group *grp,
801 struct rockchip_pinctrl *info,
802 u32 index)
803 {
804 struct rockchip_pin_bank *bank;
805 int size;
806 const __be32 *list;
807 int num;
808 int i, j;
809 int ret;
810
811 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
812
813 /* Initialise group */
814 grp->name = np->name;
815
816 /*
817 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
818 * do sanity check and calculate pins number
819 */
820 list = of_get_property(np, "rockchip,pins", &size);
821 /* we do not check return since it's safe node passed down */
822 size /= sizeof(*list);
823 if (!size || size % 4) {
824 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
825 return -EINVAL;
826 }
827
828 grp->npins = size / 4;
829
830 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
831 GFP_KERNEL);
832 grp->data = devm_kzalloc(info->dev, grp->npins *
833 sizeof(struct rockchip_pin_config),
834 GFP_KERNEL);
835 if (!grp->pins || !grp->data)
836 return -ENOMEM;
837
838 for (i = 0, j = 0; i < size; i += 4, j++) {
839 const __be32 *phandle;
840 struct device_node *np_config;
841
842 num = be32_to_cpu(*list++);
843 bank = bank_num_to_bank(info, num);
844 if (IS_ERR(bank))
845 return PTR_ERR(bank);
846
847 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
848 grp->data[j].func = be32_to_cpu(*list++);
849
850 phandle = list++;
851 if (!phandle)
852 return -EINVAL;
853
854 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
855 ret = pinconf_generic_parse_dt_config(np_config,
856 &grp->data[j].configs, &grp->data[j].nconfigs);
857 if (ret)
858 return ret;
859 }
860
861 return 0;
862 }
863
864 static int rockchip_pinctrl_parse_functions(struct device_node *np,
865 struct rockchip_pinctrl *info,
866 u32 index)
867 {
868 struct device_node *child;
869 struct rockchip_pmx_func *func;
870 struct rockchip_pin_group *grp;
871 int ret;
872 static u32 grp_index;
873 u32 i = 0;
874
875 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
876
877 func = &info->functions[index];
878
879 /* Initialise function */
880 func->name = np->name;
881 func->ngroups = of_get_child_count(np);
882 if (func->ngroups <= 0)
883 return 0;
884
885 func->groups = devm_kzalloc(info->dev,
886 func->ngroups * sizeof(char *), GFP_KERNEL);
887 if (!func->groups)
888 return -ENOMEM;
889
890 for_each_child_of_node(np, child) {
891 func->groups[i] = child->name;
892 grp = &info->groups[grp_index++];
893 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
894 if (ret)
895 return ret;
896 }
897
898 return 0;
899 }
900
901 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
902 struct rockchip_pinctrl *info)
903 {
904 struct device *dev = &pdev->dev;
905 struct device_node *np = dev->of_node;
906 struct device_node *child;
907 int ret;
908 int i;
909
910 rockchip_pinctrl_child_count(info, np);
911
912 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
913 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
914
915 info->functions = devm_kzalloc(dev, info->nfunctions *
916 sizeof(struct rockchip_pmx_func),
917 GFP_KERNEL);
918 if (!info->functions) {
919 dev_err(dev, "failed to allocate memory for function list\n");
920 return -EINVAL;
921 }
922
923 info->groups = devm_kzalloc(dev, info->ngroups *
924 sizeof(struct rockchip_pin_group),
925 GFP_KERNEL);
926 if (!info->groups) {
927 dev_err(dev, "failed allocate memory for ping group list\n");
928 return -EINVAL;
929 }
930
931 i = 0;
932
933 for_each_child_of_node(np, child) {
934 if (of_match_node(rockchip_bank_match, child))
935 continue;
936
937 ret = rockchip_pinctrl_parse_functions(child, info, i++);
938 if (ret) {
939 dev_err(&pdev->dev, "failed to parse function\n");
940 return ret;
941 }
942 }
943
944 return 0;
945 }
946
947 static int rockchip_pinctrl_register(struct platform_device *pdev,
948 struct rockchip_pinctrl *info)
949 {
950 struct pinctrl_desc *ctrldesc = &info->pctl;
951 struct pinctrl_pin_desc *pindesc, *pdesc;
952 struct rockchip_pin_bank *pin_bank;
953 int pin, bank, ret;
954 int k;
955
956 ctrldesc->name = "rockchip-pinctrl";
957 ctrldesc->owner = THIS_MODULE;
958 ctrldesc->pctlops = &rockchip_pctrl_ops;
959 ctrldesc->pmxops = &rockchip_pmx_ops;
960 ctrldesc->confops = &rockchip_pinconf_ops;
961
962 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
963 info->ctrl->nr_pins, GFP_KERNEL);
964 if (!pindesc) {
965 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
966 return -ENOMEM;
967 }
968 ctrldesc->pins = pindesc;
969 ctrldesc->npins = info->ctrl->nr_pins;
970
971 pdesc = pindesc;
972 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
973 pin_bank = &info->ctrl->pin_banks[bank];
974 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
975 pdesc->number = k;
976 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
977 pin_bank->name, pin);
978 pdesc++;
979 }
980 }
981
982 info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
983 if (!info->pctl_dev) {
984 dev_err(&pdev->dev, "could not register pinctrl driver\n");
985 return -EINVAL;
986 }
987
988 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
989 pin_bank = &info->ctrl->pin_banks[bank];
990 pin_bank->grange.name = pin_bank->name;
991 pin_bank->grange.id = bank;
992 pin_bank->grange.pin_base = pin_bank->pin_base;
993 pin_bank->grange.base = pin_bank->gpio_chip.base;
994 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
995 pin_bank->grange.gc = &pin_bank->gpio_chip;
996 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
997 }
998
999 ret = rockchip_pinctrl_parse_dt(pdev, info);
1000 if (ret) {
1001 pinctrl_unregister(info->pctl_dev);
1002 return ret;
1003 }
1004
1005 return 0;
1006 }
1007
1008 /*
1009 * GPIO handling
1010 */
1011
1012 static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
1013 {
1014 return pinctrl_request_gpio(chip->base + offset);
1015 }
1016
1017 static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
1018 {
1019 pinctrl_free_gpio(chip->base + offset);
1020 }
1021
1022 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1023 {
1024 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1025 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1026 unsigned long flags;
1027 u32 data;
1028
1029 spin_lock_irqsave(&bank->slock, flags);
1030
1031 data = readl(reg);
1032 data &= ~BIT(offset);
1033 if (value)
1034 data |= BIT(offset);
1035 writel(data, reg);
1036
1037 spin_unlock_irqrestore(&bank->slock, flags);
1038 }
1039
1040 /*
1041 * Returns the level of the pin for input direction and setting of the DR
1042 * register for output gpios.
1043 */
1044 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1045 {
1046 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1047 u32 data;
1048
1049 data = readl(bank->reg_base + GPIO_EXT_PORT);
1050 data >>= offset;
1051 data &= 1;
1052 return data;
1053 }
1054
1055 /*
1056 * gpiolib gpio_direction_input callback function. The setting of the pin
1057 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1058 * interface.
1059 */
1060 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1061 {
1062 return pinctrl_gpio_direction_input(gc->base + offset);
1063 }
1064
1065 /*
1066 * gpiolib gpio_direction_output callback function. The setting of the pin
1067 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1068 * interface.
1069 */
1070 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1071 unsigned offset, int value)
1072 {
1073 rockchip_gpio_set(gc, offset, value);
1074 return pinctrl_gpio_direction_output(gc->base + offset);
1075 }
1076
1077 /*
1078 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1079 * and a virtual IRQ, if not already present.
1080 */
1081 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1082 {
1083 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1084 unsigned int virq;
1085
1086 if (!bank->domain)
1087 return -ENXIO;
1088
1089 virq = irq_create_mapping(bank->domain, offset);
1090
1091 return (virq) ? : -ENXIO;
1092 }
1093
1094 static const struct gpio_chip rockchip_gpiolib_chip = {
1095 .request = rockchip_gpio_request,
1096 .free = rockchip_gpio_free,
1097 .set = rockchip_gpio_set,
1098 .get = rockchip_gpio_get,
1099 .direction_input = rockchip_gpio_direction_input,
1100 .direction_output = rockchip_gpio_direction_output,
1101 .to_irq = rockchip_gpio_to_irq,
1102 .owner = THIS_MODULE,
1103 };
1104
1105 /*
1106 * Interrupt handling
1107 */
1108
1109 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
1110 {
1111 struct irq_chip *chip = irq_get_chip(irq);
1112 struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
1113 u32 polarity = 0, data = 0;
1114 u32 pend;
1115 bool edge_changed = false;
1116
1117 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1118
1119 chained_irq_enter(chip, desc);
1120
1121 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1122
1123 if (bank->toggle_edge_mode) {
1124 polarity = readl_relaxed(bank->reg_base +
1125 GPIO_INT_POLARITY);
1126 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1127 }
1128
1129 while (pend) {
1130 unsigned int virq;
1131
1132 irq = __ffs(pend);
1133 pend &= ~BIT(irq);
1134 virq = irq_linear_revmap(bank->domain, irq);
1135
1136 if (!virq) {
1137 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1138 continue;
1139 }
1140
1141 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1142
1143 /*
1144 * Triggering IRQ on both rising and falling edge
1145 * needs manual intervention.
1146 */
1147 if (bank->toggle_edge_mode & BIT(irq)) {
1148 if (data & BIT(irq))
1149 polarity &= ~BIT(irq);
1150 else
1151 polarity |= BIT(irq);
1152
1153 edge_changed = true;
1154 }
1155
1156 generic_handle_irq(virq);
1157 }
1158
1159 if (bank->toggle_edge_mode && edge_changed) {
1160 /* Interrupt params should only be set with ints disabled */
1161 data = readl_relaxed(bank->reg_base + GPIO_INTEN);
1162 writel_relaxed(0, bank->reg_base + GPIO_INTEN);
1163 writel(polarity, bank->reg_base + GPIO_INT_POLARITY);
1164 writel(data, bank->reg_base + GPIO_INTEN);
1165 }
1166
1167 chained_irq_exit(chip, desc);
1168 }
1169
1170 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1171 {
1172 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1173 struct rockchip_pin_bank *bank = gc->private;
1174 u32 mask = BIT(d->hwirq);
1175 u32 polarity;
1176 u32 level;
1177 u32 data;
1178 int ret;
1179
1180 /* make sure the pin is configured as gpio input */
1181 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1182 if (ret < 0)
1183 return ret;
1184
1185 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1186 data &= ~mask;
1187 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1188
1189 if (type & IRQ_TYPE_EDGE_BOTH)
1190 __irq_set_handler_locked(d->irq, handle_edge_irq);
1191 else
1192 __irq_set_handler_locked(d->irq, handle_level_irq);
1193
1194 irq_gc_lock(gc);
1195
1196 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1197 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1198
1199 switch (type) {
1200 case IRQ_TYPE_EDGE_BOTH:
1201 bank->toggle_edge_mode |= mask;
1202 level |= mask;
1203
1204 /*
1205 * Determine gpio state. If 1 next interrupt should be falling
1206 * otherwise rising.
1207 */
1208 data = readl(bank->reg_base + GPIO_EXT_PORT);
1209 if (data & mask)
1210 polarity &= ~mask;
1211 else
1212 polarity |= mask;
1213 break;
1214 case IRQ_TYPE_EDGE_RISING:
1215 bank->toggle_edge_mode &= ~mask;
1216 level |= mask;
1217 polarity |= mask;
1218 break;
1219 case IRQ_TYPE_EDGE_FALLING:
1220 bank->toggle_edge_mode &= ~mask;
1221 level |= mask;
1222 polarity &= ~mask;
1223 break;
1224 case IRQ_TYPE_LEVEL_HIGH:
1225 bank->toggle_edge_mode &= ~mask;
1226 level &= ~mask;
1227 polarity |= mask;
1228 break;
1229 case IRQ_TYPE_LEVEL_LOW:
1230 bank->toggle_edge_mode &= ~mask;
1231 level &= ~mask;
1232 polarity &= ~mask;
1233 break;
1234 default:
1235 irq_gc_unlock(gc);
1236 return -EINVAL;
1237 }
1238
1239 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1240 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1241
1242 irq_gc_unlock(gc);
1243
1244 return 0;
1245 }
1246
1247 static int rockchip_interrupts_register(struct platform_device *pdev,
1248 struct rockchip_pinctrl *info)
1249 {
1250 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1251 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1252 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1253 struct irq_chip_generic *gc;
1254 int ret;
1255 int i;
1256
1257 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1258 if (!bank->valid) {
1259 dev_warn(&pdev->dev, "bank %s is not valid\n",
1260 bank->name);
1261 continue;
1262 }
1263
1264 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1265 &irq_generic_chip_ops, NULL);
1266 if (!bank->domain) {
1267 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1268 bank->name);
1269 continue;
1270 }
1271
1272 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1273 "rockchip_gpio_irq", handle_level_irq,
1274 clr, 0, IRQ_GC_INIT_MASK_CACHE);
1275 if (ret) {
1276 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1277 bank->name);
1278 irq_domain_remove(bank->domain);
1279 continue;
1280 }
1281
1282 gc = irq_get_domain_generic_chip(bank->domain, 0);
1283 gc->reg_base = bank->reg_base;
1284 gc->private = bank;
1285 gc->chip_types[0].regs.mask = GPIO_INTEN;
1286 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1287 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1288 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
1289 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
1290 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1291 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1292
1293 irq_set_handler_data(bank->irq, bank);
1294 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1295 }
1296
1297 return 0;
1298 }
1299
1300 static int rockchip_gpiolib_register(struct platform_device *pdev,
1301 struct rockchip_pinctrl *info)
1302 {
1303 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1304 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1305 struct gpio_chip *gc;
1306 int ret;
1307 int i;
1308
1309 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1310 if (!bank->valid) {
1311 dev_warn(&pdev->dev, "bank %s is not valid\n",
1312 bank->name);
1313 continue;
1314 }
1315
1316 bank->gpio_chip = rockchip_gpiolib_chip;
1317
1318 gc = &bank->gpio_chip;
1319 gc->base = bank->pin_base;
1320 gc->ngpio = bank->nr_pins;
1321 gc->dev = &pdev->dev;
1322 gc->of_node = bank->of_node;
1323 gc->label = bank->name;
1324
1325 ret = gpiochip_add(gc);
1326 if (ret) {
1327 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1328 gc->label, ret);
1329 goto fail;
1330 }
1331 }
1332
1333 rockchip_interrupts_register(pdev, info);
1334
1335 return 0;
1336
1337 fail:
1338 for (--i, --bank; i >= 0; --i, --bank) {
1339 if (!bank->valid)
1340 continue;
1341
1342 if (gpiochip_remove(&bank->gpio_chip))
1343 dev_err(&pdev->dev, "gpio chip %s remove failed\n",
1344 bank->gpio_chip.label);
1345 }
1346 return ret;
1347 }
1348
1349 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1350 struct rockchip_pinctrl *info)
1351 {
1352 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1353 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1354 int ret = 0;
1355 int i;
1356
1357 for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
1358 if (!bank->valid)
1359 continue;
1360
1361 ret = gpiochip_remove(&bank->gpio_chip);
1362 }
1363
1364 if (ret)
1365 dev_err(&pdev->dev, "gpio chip remove failed\n");
1366
1367 return ret;
1368 }
1369
1370 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1371 struct device *dev)
1372 {
1373 struct resource res;
1374
1375 if (of_address_to_resource(bank->of_node, 0, &res)) {
1376 dev_err(dev, "cannot find IO resource for bank\n");
1377 return -ENOENT;
1378 }
1379
1380 bank->reg_base = devm_ioremap_resource(dev, &res);
1381 if (IS_ERR(bank->reg_base))
1382 return PTR_ERR(bank->reg_base);
1383
1384 /*
1385 * special case, where parts of the pull setting-registers are
1386 * part of the PMU register space
1387 */
1388 if (of_device_is_compatible(bank->of_node,
1389 "rockchip,rk3188-gpio-bank0")) {
1390 bank->bank_type = RK3188_BANK0;
1391
1392 if (of_address_to_resource(bank->of_node, 1, &res)) {
1393 dev_err(dev, "cannot find IO resource for bank\n");
1394 return -ENOENT;
1395 }
1396
1397 bank->reg_pull = devm_ioremap_resource(dev, &res);
1398 if (IS_ERR(bank->reg_pull))
1399 return PTR_ERR(bank->reg_pull);
1400 } else {
1401 bank->bank_type = COMMON_BANK;
1402 }
1403
1404 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1405
1406 bank->clk = of_clk_get(bank->of_node, 0);
1407 if (IS_ERR(bank->clk))
1408 return PTR_ERR(bank->clk);
1409
1410 return clk_prepare_enable(bank->clk);
1411 }
1412
1413 static const struct of_device_id rockchip_pinctrl_dt_match[];
1414
1415 /* retrieve the soc specific data */
1416 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1417 struct rockchip_pinctrl *d,
1418 struct platform_device *pdev)
1419 {
1420 const struct of_device_id *match;
1421 struct device_node *node = pdev->dev.of_node;
1422 struct device_node *np;
1423 struct rockchip_pin_ctrl *ctrl;
1424 struct rockchip_pin_bank *bank;
1425 int i;
1426
1427 match = of_match_node(rockchip_pinctrl_dt_match, node);
1428 ctrl = (struct rockchip_pin_ctrl *)match->data;
1429
1430 for_each_child_of_node(node, np) {
1431 if (!of_find_property(np, "gpio-controller", NULL))
1432 continue;
1433
1434 bank = ctrl->pin_banks;
1435 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1436 if (!strcmp(bank->name, np->name)) {
1437 bank->of_node = np;
1438
1439 if (!rockchip_get_bank_data(bank, &pdev->dev))
1440 bank->valid = true;
1441
1442 break;
1443 }
1444 }
1445 }
1446
1447 bank = ctrl->pin_banks;
1448 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1449 spin_lock_init(&bank->slock);
1450 bank->drvdata = d;
1451 bank->pin_base = ctrl->nr_pins;
1452 ctrl->nr_pins += bank->nr_pins;
1453 }
1454
1455 return ctrl;
1456 }
1457
1458 static int rockchip_pinctrl_probe(struct platform_device *pdev)
1459 {
1460 struct rockchip_pinctrl *info;
1461 struct device *dev = &pdev->dev;
1462 struct rockchip_pin_ctrl *ctrl;
1463 struct resource *res;
1464 int ret;
1465
1466 if (!dev->of_node) {
1467 dev_err(dev, "device tree node not found\n");
1468 return -ENODEV;
1469 }
1470
1471 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
1472 if (!info)
1473 return -ENOMEM;
1474
1475 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
1476 if (!ctrl) {
1477 dev_err(dev, "driver data not available\n");
1478 return -EINVAL;
1479 }
1480 info->ctrl = ctrl;
1481 info->dev = dev;
1482
1483 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1484 info->reg_base = devm_ioremap_resource(&pdev->dev, res);
1485 if (IS_ERR(info->reg_base))
1486 return PTR_ERR(info->reg_base);
1487
1488 /* The RK3188 has its pull registers in a separate place */
1489 if (ctrl->type == RK3188) {
1490 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1491 info->reg_pull = devm_ioremap_resource(&pdev->dev, res);
1492 if (IS_ERR(info->reg_pull))
1493 return PTR_ERR(info->reg_pull);
1494 }
1495
1496 ret = rockchip_gpiolib_register(pdev, info);
1497 if (ret)
1498 return ret;
1499
1500 ret = rockchip_pinctrl_register(pdev, info);
1501 if (ret) {
1502 rockchip_gpiolib_unregister(pdev, info);
1503 return ret;
1504 }
1505
1506 platform_set_drvdata(pdev, info);
1507
1508 return 0;
1509 }
1510
1511 static struct rockchip_pin_bank rk2928_pin_banks[] = {
1512 PIN_BANK(0, 32, "gpio0"),
1513 PIN_BANK(1, 32, "gpio1"),
1514 PIN_BANK(2, 32, "gpio2"),
1515 PIN_BANK(3, 32, "gpio3"),
1516 };
1517
1518 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1519 .pin_banks = rk2928_pin_banks,
1520 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
1521 .label = "RK2928-GPIO",
1522 .type = RK2928,
1523 .mux_offset = 0xa8,
1524 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
1525 };
1526
1527 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
1528 PIN_BANK(0, 32, "gpio0"),
1529 PIN_BANK(1, 32, "gpio1"),
1530 PIN_BANK(2, 32, "gpio2"),
1531 PIN_BANK(3, 32, "gpio3"),
1532 PIN_BANK(4, 32, "gpio4"),
1533 PIN_BANK(6, 16, "gpio6"),
1534 };
1535
1536 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
1537 .pin_banks = rk3066a_pin_banks,
1538 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
1539 .label = "RK3066a-GPIO",
1540 .type = RK2928,
1541 .mux_offset = 0xa8,
1542 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
1543 };
1544
1545 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
1546 PIN_BANK(0, 32, "gpio0"),
1547 PIN_BANK(1, 32, "gpio1"),
1548 PIN_BANK(2, 32, "gpio2"),
1549 PIN_BANK(3, 32, "gpio3"),
1550 };
1551
1552 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
1553 .pin_banks = rk3066b_pin_banks,
1554 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
1555 .label = "RK3066b-GPIO",
1556 .type = RK3066B,
1557 .mux_offset = 0x60,
1558 };
1559
1560 static struct rockchip_pin_bank rk3188_pin_banks[] = {
1561 PIN_BANK(0, 32, "gpio0"),
1562 PIN_BANK(1, 32, "gpio1"),
1563 PIN_BANK(2, 32, "gpio2"),
1564 PIN_BANK(3, 32, "gpio3"),
1565 };
1566
1567 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
1568 .pin_banks = rk3188_pin_banks,
1569 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
1570 .label = "RK3188-GPIO",
1571 .type = RK3188,
1572 .mux_offset = 0x60,
1573 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
1574 };
1575
1576 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
1577 { .compatible = "rockchip,rk2928-pinctrl",
1578 .data = (void *)&rk2928_pin_ctrl },
1579 { .compatible = "rockchip,rk3066a-pinctrl",
1580 .data = (void *)&rk3066a_pin_ctrl },
1581 { .compatible = "rockchip,rk3066b-pinctrl",
1582 .data = (void *)&rk3066b_pin_ctrl },
1583 { .compatible = "rockchip,rk3188-pinctrl",
1584 .data = (void *)&rk3188_pin_ctrl },
1585 {},
1586 };
1587 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
1588
1589 static struct platform_driver rockchip_pinctrl_driver = {
1590 .probe = rockchip_pinctrl_probe,
1591 .driver = {
1592 .name = "rockchip-pinctrl",
1593 .owner = THIS_MODULE,
1594 .of_match_table = rockchip_pinctrl_dt_match,
1595 },
1596 };
1597
1598 static int __init rockchip_pinctrl_drv_register(void)
1599 {
1600 return platform_driver_register(&rockchip_pinctrl_driver);
1601 }
1602 postcore_initcall(rockchip_pinctrl_drv_register);
1603
1604 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
1605 MODULE_DESCRIPTION("Rockchip pinctrl driver");
1606 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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