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pinctrl: remove all usage of gpio_remove ret val in driver/pinctl
[deliverable/linux.git] / drivers / pinctrl / pinctrl-rockchip.c
1 /*
2 * Pinctrl driver for Rockchip SoCs
3 *
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
6 *
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
12 *
13 * and pinctrl-at91:
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 */
25
26 #include <linux/module.h>
27 #include <linux/platform_device.h>
28 #include <linux/io.h>
29 #include <linux/bitops.h>
30 #include <linux/gpio.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/pinctrl/machine.h>
34 #include <linux/pinctrl/pinconf.h>
35 #include <linux/pinctrl/pinctrl.h>
36 #include <linux/pinctrl/pinmux.h>
37 #include <linux/pinctrl/pinconf-generic.h>
38 #include <linux/irqchip/chained_irq.h>
39 #include <linux/clk.h>
40 #include <linux/regmap.h>
41 #include <linux/mfd/syscon.h>
42 #include <dt-bindings/pinctrl/rockchip.h>
43
44 #include "core.h"
45 #include "pinconf.h"
46
47 /* GPIO control registers */
48 #define GPIO_SWPORT_DR 0x00
49 #define GPIO_SWPORT_DDR 0x04
50 #define GPIO_INTEN 0x30
51 #define GPIO_INTMASK 0x34
52 #define GPIO_INTTYPE_LEVEL 0x38
53 #define GPIO_INT_POLARITY 0x3c
54 #define GPIO_INT_STATUS 0x40
55 #define GPIO_INT_RAWSTATUS 0x44
56 #define GPIO_DEBOUNCE 0x48
57 #define GPIO_PORTS_EOI 0x4c
58 #define GPIO_EXT_PORT 0x50
59 #define GPIO_LS_SYNC 0x60
60
61 enum rockchip_pinctrl_type {
62 RK2928,
63 RK3066B,
64 RK3188,
65 };
66
67 /**
68 * Encode variants of iomux registers into a type variable
69 */
70 #define IOMUX_GPIO_ONLY BIT(0)
71 #define IOMUX_WIDTH_4BIT BIT(1)
72 #define IOMUX_SOURCE_PMU BIT(2)
73 #define IOMUX_UNROUTED BIT(3)
74
75 /**
76 * @type: iomux variant using IOMUX_* constants
77 * @offset: if initialized to -1 it will be autocalculated, by specifying
78 * an initial offset value the relevant source offset can be reset
79 * to a new value for autocalculating the following iomux registers.
80 */
81 struct rockchip_iomux {
82 int type;
83 int offset;
84 };
85
86 /**
87 * @reg_base: register base of the gpio bank
88 * @reg_pull: optional separate register for additional pull settings
89 * @clk: clock of the gpio bank
90 * @irq: interrupt of the gpio bank
91 * @pin_base: first pin number
92 * @nr_pins: number of pins in this bank
93 * @name: name of the bank
94 * @bank_num: number of the bank, to account for holes
95 * @iomux: array describing the 4 iomux sources of the bank
96 * @valid: are all necessary informations present
97 * @of_node: dt node of this bank
98 * @drvdata: common pinctrl basedata
99 * @domain: irqdomain of the gpio bank
100 * @gpio_chip: gpiolib chip
101 * @grange: gpio range
102 * @slock: spinlock for the gpio bank
103 */
104 struct rockchip_pin_bank {
105 void __iomem *reg_base;
106 struct regmap *regmap_pull;
107 struct clk *clk;
108 int irq;
109 u32 pin_base;
110 u8 nr_pins;
111 char *name;
112 u8 bank_num;
113 struct rockchip_iomux iomux[4];
114 bool valid;
115 struct device_node *of_node;
116 struct rockchip_pinctrl *drvdata;
117 struct irq_domain *domain;
118 struct gpio_chip gpio_chip;
119 struct pinctrl_gpio_range grange;
120 spinlock_t slock;
121 u32 toggle_edge_mode;
122 };
123
124 #define PIN_BANK(id, pins, label) \
125 { \
126 .bank_num = id, \
127 .nr_pins = pins, \
128 .name = label, \
129 .iomux = { \
130 { .offset = -1 }, \
131 { .offset = -1 }, \
132 { .offset = -1 }, \
133 { .offset = -1 }, \
134 }, \
135 }
136
137 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
138 { \
139 .bank_num = id, \
140 .nr_pins = pins, \
141 .name = label, \
142 .iomux = { \
143 { .type = iom0, .offset = -1 }, \
144 { .type = iom1, .offset = -1 }, \
145 { .type = iom2, .offset = -1 }, \
146 { .type = iom3, .offset = -1 }, \
147 }, \
148 }
149
150 /**
151 */
152 struct rockchip_pin_ctrl {
153 struct rockchip_pin_bank *pin_banks;
154 u32 nr_banks;
155 u32 nr_pins;
156 char *label;
157 enum rockchip_pinctrl_type type;
158 int grf_mux_offset;
159 int pmu_mux_offset;
160 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
161 int pin_num, struct regmap **regmap,
162 int *reg, u8 *bit);
163 };
164
165 struct rockchip_pin_config {
166 unsigned int func;
167 unsigned long *configs;
168 unsigned int nconfigs;
169 };
170
171 /**
172 * struct rockchip_pin_group: represent group of pins of a pinmux function.
173 * @name: name of the pin group, used to lookup the group.
174 * @pins: the pins included in this group.
175 * @npins: number of pins included in this group.
176 * @func: the mux function number to be programmed when selected.
177 * @configs: the config values to be set for each pin
178 * @nconfigs: number of configs for each pin
179 */
180 struct rockchip_pin_group {
181 const char *name;
182 unsigned int npins;
183 unsigned int *pins;
184 struct rockchip_pin_config *data;
185 };
186
187 /**
188 * struct rockchip_pmx_func: represent a pin function.
189 * @name: name of the pin function, used to lookup the function.
190 * @groups: one or more names of pin groups that provide this function.
191 * @num_groups: number of groups included in @groups.
192 */
193 struct rockchip_pmx_func {
194 const char *name;
195 const char **groups;
196 u8 ngroups;
197 };
198
199 struct rockchip_pinctrl {
200 struct regmap *regmap_base;
201 int reg_size;
202 struct regmap *regmap_pull;
203 struct regmap *regmap_pmu;
204 struct device *dev;
205 struct rockchip_pin_ctrl *ctrl;
206 struct pinctrl_desc pctl;
207 struct pinctrl_dev *pctl_dev;
208 struct rockchip_pin_group *groups;
209 unsigned int ngroups;
210 struct rockchip_pmx_func *functions;
211 unsigned int nfunctions;
212 };
213
214 static struct regmap_config rockchip_regmap_config = {
215 .reg_bits = 32,
216 .val_bits = 32,
217 .reg_stride = 4,
218 };
219
220 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
221 {
222 return container_of(gc, struct rockchip_pin_bank, gpio_chip);
223 }
224
225 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
226 const struct rockchip_pinctrl *info,
227 const char *name)
228 {
229 int i;
230
231 for (i = 0; i < info->ngroups; i++) {
232 if (!strcmp(info->groups[i].name, name))
233 return &info->groups[i];
234 }
235
236 return NULL;
237 }
238
239 /*
240 * given a pin number that is local to a pin controller, find out the pin bank
241 * and the register base of the pin bank.
242 */
243 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
244 unsigned pin)
245 {
246 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
247
248 while (pin >= (b->pin_base + b->nr_pins))
249 b++;
250
251 return b;
252 }
253
254 static struct rockchip_pin_bank *bank_num_to_bank(
255 struct rockchip_pinctrl *info,
256 unsigned num)
257 {
258 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
259 int i;
260
261 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
262 if (b->bank_num == num)
263 return b;
264 }
265
266 return ERR_PTR(-EINVAL);
267 }
268
269 /*
270 * Pinctrl_ops handling
271 */
272
273 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
274 {
275 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
276
277 return info->ngroups;
278 }
279
280 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
281 unsigned selector)
282 {
283 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
284
285 return info->groups[selector].name;
286 }
287
288 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
289 unsigned selector, const unsigned **pins,
290 unsigned *npins)
291 {
292 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
293
294 if (selector >= info->ngroups)
295 return -EINVAL;
296
297 *pins = info->groups[selector].pins;
298 *npins = info->groups[selector].npins;
299
300 return 0;
301 }
302
303 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
304 struct device_node *np,
305 struct pinctrl_map **map, unsigned *num_maps)
306 {
307 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
308 const struct rockchip_pin_group *grp;
309 struct pinctrl_map *new_map;
310 struct device_node *parent;
311 int map_num = 1;
312 int i;
313
314 /*
315 * first find the group of this node and check if we need to create
316 * config maps for pins
317 */
318 grp = pinctrl_name_to_group(info, np->name);
319 if (!grp) {
320 dev_err(info->dev, "unable to find group for node %s\n",
321 np->name);
322 return -EINVAL;
323 }
324
325 map_num += grp->npins;
326 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
327 GFP_KERNEL);
328 if (!new_map)
329 return -ENOMEM;
330
331 *map = new_map;
332 *num_maps = map_num;
333
334 /* create mux map */
335 parent = of_get_parent(np);
336 if (!parent) {
337 devm_kfree(pctldev->dev, new_map);
338 return -EINVAL;
339 }
340 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
341 new_map[0].data.mux.function = parent->name;
342 new_map[0].data.mux.group = np->name;
343 of_node_put(parent);
344
345 /* create config map */
346 new_map++;
347 for (i = 0; i < grp->npins; i++) {
348 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
349 new_map[i].data.configs.group_or_pin =
350 pin_get_name(pctldev, grp->pins[i]);
351 new_map[i].data.configs.configs = grp->data[i].configs;
352 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
353 }
354
355 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
356 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
357
358 return 0;
359 }
360
361 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
362 struct pinctrl_map *map, unsigned num_maps)
363 {
364 }
365
366 static const struct pinctrl_ops rockchip_pctrl_ops = {
367 .get_groups_count = rockchip_get_groups_count,
368 .get_group_name = rockchip_get_group_name,
369 .get_group_pins = rockchip_get_group_pins,
370 .dt_node_to_map = rockchip_dt_node_to_map,
371 .dt_free_map = rockchip_dt_free_map,
372 };
373
374 /*
375 * Hardware access
376 */
377
378 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
379 {
380 struct rockchip_pinctrl *info = bank->drvdata;
381 int iomux_num = (pin / 8);
382 struct regmap *regmap;
383 unsigned int val;
384 int reg, ret, mask;
385 u8 bit;
386
387 if (iomux_num > 3)
388 return -EINVAL;
389
390 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
391 dev_err(info->dev, "pin %d is unrouted\n", pin);
392 return -EINVAL;
393 }
394
395 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
396 return RK_FUNC_GPIO;
397
398 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
399 ? info->regmap_pmu : info->regmap_base;
400
401 /* get basic quadrupel of mux registers and the correct reg inside */
402 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
403 reg = bank->iomux[iomux_num].offset;
404 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
405 if ((pin % 8) >= 4)
406 reg += 0x4;
407 bit = (pin % 4) * 4;
408 } else {
409 bit = (pin % 8) * 2;
410 }
411
412 ret = regmap_read(regmap, reg, &val);
413 if (ret)
414 return ret;
415
416 return ((val >> bit) & mask);
417 }
418
419 /*
420 * Set a new mux function for a pin.
421 *
422 * The register is divided into the upper and lower 16 bit. When changing
423 * a value, the previous register value is not read and changed. Instead
424 * it seems the changed bits are marked in the upper 16 bit, while the
425 * changed value gets set in the same offset in the lower 16 bit.
426 * All pin settings seem to be 2 bit wide in both the upper and lower
427 * parts.
428 * @bank: pin bank to change
429 * @pin: pin to change
430 * @mux: new mux function to set
431 */
432 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
433 {
434 struct rockchip_pinctrl *info = bank->drvdata;
435 int iomux_num = (pin / 8);
436 struct regmap *regmap;
437 int reg, ret, mask;
438 unsigned long flags;
439 u8 bit;
440 u32 data;
441
442 if (iomux_num > 3)
443 return -EINVAL;
444
445 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
446 dev_err(info->dev, "pin %d is unrouted\n", pin);
447 return -EINVAL;
448 }
449
450 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
451 if (mux != RK_FUNC_GPIO) {
452 dev_err(info->dev,
453 "pin %d only supports a gpio mux\n", pin);
454 return -ENOTSUPP;
455 } else {
456 return 0;
457 }
458 }
459
460 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
461 bank->bank_num, pin, mux);
462
463 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
464 ? info->regmap_pmu : info->regmap_base;
465
466 /* get basic quadrupel of mux registers and the correct reg inside */
467 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
468 reg = bank->iomux[iomux_num].offset;
469 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
470 if ((pin % 8) >= 4)
471 reg += 0x4;
472 bit = (pin % 4) * 4;
473 } else {
474 bit = (pin % 8) * 2;
475 }
476
477 spin_lock_irqsave(&bank->slock, flags);
478
479 data = (mask << (bit + 16));
480 data |= (mux & mask) << bit;
481 ret = regmap_write(regmap, reg, data);
482
483 spin_unlock_irqrestore(&bank->slock, flags);
484
485 return ret;
486 }
487
488 #define RK2928_PULL_OFFSET 0x118
489 #define RK2928_PULL_PINS_PER_REG 16
490 #define RK2928_PULL_BANK_STRIDE 8
491
492 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
493 int pin_num, struct regmap **regmap,
494 int *reg, u8 *bit)
495 {
496 struct rockchip_pinctrl *info = bank->drvdata;
497
498 *regmap = info->regmap_base;
499 *reg = RK2928_PULL_OFFSET;
500 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
501 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
502
503 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
504 };
505
506 #define RK3188_PULL_OFFSET 0x164
507 #define RK3188_PULL_BITS_PER_PIN 2
508 #define RK3188_PULL_PINS_PER_REG 8
509 #define RK3188_PULL_BANK_STRIDE 16
510 #define RK3188_PULL_PMU_OFFSET 0x64
511
512 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
513 int pin_num, struct regmap **regmap,
514 int *reg, u8 *bit)
515 {
516 struct rockchip_pinctrl *info = bank->drvdata;
517
518 /* The first 12 pins of the first bank are located elsewhere */
519 if (bank->bank_num == 0 && pin_num < 12) {
520 *regmap = info->regmap_pmu ? info->regmap_pmu
521 : bank->regmap_pull;
522 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
523 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
524 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
525 *bit *= RK3188_PULL_BITS_PER_PIN;
526 } else {
527 *regmap = info->regmap_pull ? info->regmap_pull
528 : info->regmap_base;
529 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
530
531 /* correct the offset, as it is the 2nd pull register */
532 *reg -= 4;
533 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
534 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
535
536 /*
537 * The bits in these registers have an inverse ordering
538 * with the lowest pin being in bits 15:14 and the highest
539 * pin in bits 1:0
540 */
541 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
542 *bit *= RK3188_PULL_BITS_PER_PIN;
543 }
544 }
545
546 #define RK3288_PULL_OFFSET 0x140
547 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
548 int pin_num, struct regmap **regmap,
549 int *reg, u8 *bit)
550 {
551 struct rockchip_pinctrl *info = bank->drvdata;
552
553 /* The first 24 pins of the first bank are located in PMU */
554 if (bank->bank_num == 0) {
555 *regmap = info->regmap_pmu;
556 *reg = RK3188_PULL_PMU_OFFSET;
557
558 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
559 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
560 *bit *= RK3188_PULL_BITS_PER_PIN;
561 } else {
562 *regmap = info->regmap_base;
563 *reg = RK3288_PULL_OFFSET;
564
565 /* correct the offset, as we're starting with the 2nd bank */
566 *reg -= 0x10;
567 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
568 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
569
570 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
571 *bit *= RK3188_PULL_BITS_PER_PIN;
572 }
573 }
574
575 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
576 {
577 struct rockchip_pinctrl *info = bank->drvdata;
578 struct rockchip_pin_ctrl *ctrl = info->ctrl;
579 struct regmap *regmap;
580 int reg, ret;
581 u8 bit;
582 u32 data;
583
584 /* rk3066b does support any pulls */
585 if (ctrl->type == RK3066B)
586 return PIN_CONFIG_BIAS_DISABLE;
587
588 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
589
590 ret = regmap_read(regmap, reg, &data);
591 if (ret)
592 return ret;
593
594 switch (ctrl->type) {
595 case RK2928:
596 return !(data & BIT(bit))
597 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
598 : PIN_CONFIG_BIAS_DISABLE;
599 case RK3188:
600 data >>= bit;
601 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
602
603 switch (data) {
604 case 0:
605 return PIN_CONFIG_BIAS_DISABLE;
606 case 1:
607 return PIN_CONFIG_BIAS_PULL_UP;
608 case 2:
609 return PIN_CONFIG_BIAS_PULL_DOWN;
610 case 3:
611 return PIN_CONFIG_BIAS_BUS_HOLD;
612 }
613
614 dev_err(info->dev, "unknown pull setting\n");
615 return -EIO;
616 default:
617 dev_err(info->dev, "unsupported pinctrl type\n");
618 return -EINVAL;
619 };
620 }
621
622 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
623 int pin_num, int pull)
624 {
625 struct rockchip_pinctrl *info = bank->drvdata;
626 struct rockchip_pin_ctrl *ctrl = info->ctrl;
627 struct regmap *regmap;
628 int reg, ret;
629 unsigned long flags;
630 u8 bit;
631 u32 data;
632
633 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
634 bank->bank_num, pin_num, pull);
635
636 /* rk3066b does support any pulls */
637 if (ctrl->type == RK3066B)
638 return pull ? -EINVAL : 0;
639
640 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
641
642 switch (ctrl->type) {
643 case RK2928:
644 spin_lock_irqsave(&bank->slock, flags);
645
646 data = BIT(bit + 16);
647 if (pull == PIN_CONFIG_BIAS_DISABLE)
648 data |= BIT(bit);
649 ret = regmap_write(regmap, reg, data);
650
651 spin_unlock_irqrestore(&bank->slock, flags);
652 break;
653 case RK3188:
654 spin_lock_irqsave(&bank->slock, flags);
655
656 /* enable the write to the equivalent lower bits */
657 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
658
659 switch (pull) {
660 case PIN_CONFIG_BIAS_DISABLE:
661 break;
662 case PIN_CONFIG_BIAS_PULL_UP:
663 data |= (1 << bit);
664 break;
665 case PIN_CONFIG_BIAS_PULL_DOWN:
666 data |= (2 << bit);
667 break;
668 case PIN_CONFIG_BIAS_BUS_HOLD:
669 data |= (3 << bit);
670 break;
671 default:
672 spin_unlock_irqrestore(&bank->slock, flags);
673 dev_err(info->dev, "unsupported pull setting %d\n",
674 pull);
675 return -EINVAL;
676 }
677
678 ret = regmap_write(regmap, reg, data);
679
680 spin_unlock_irqrestore(&bank->slock, flags);
681 break;
682 default:
683 dev_err(info->dev, "unsupported pinctrl type\n");
684 return -EINVAL;
685 }
686
687 return ret;
688 }
689
690 /*
691 * Pinmux_ops handling
692 */
693
694 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
695 {
696 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
697
698 return info->nfunctions;
699 }
700
701 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
702 unsigned selector)
703 {
704 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
705
706 return info->functions[selector].name;
707 }
708
709 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
710 unsigned selector, const char * const **groups,
711 unsigned * const num_groups)
712 {
713 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
714
715 *groups = info->functions[selector].groups;
716 *num_groups = info->functions[selector].ngroups;
717
718 return 0;
719 }
720
721 static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
722 unsigned group)
723 {
724 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
725 const unsigned int *pins = info->groups[group].pins;
726 const struct rockchip_pin_config *data = info->groups[group].data;
727 struct rockchip_pin_bank *bank;
728 int cnt, ret = 0;
729
730 dev_dbg(info->dev, "enable function %s group %s\n",
731 info->functions[selector].name, info->groups[group].name);
732
733 /*
734 * for each pin in the pin group selected, program the correspoding pin
735 * pin function number in the config register.
736 */
737 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
738 bank = pin_to_bank(info, pins[cnt]);
739 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
740 data[cnt].func);
741 if (ret)
742 break;
743 }
744
745 if (ret) {
746 /* revert the already done pin settings */
747 for (cnt--; cnt >= 0; cnt--)
748 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
749
750 return ret;
751 }
752
753 return 0;
754 }
755
756 /*
757 * The calls to gpio_direction_output() and gpio_direction_input()
758 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
759 * function called from the gpiolib interface).
760 */
761 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
762 struct pinctrl_gpio_range *range,
763 unsigned offset, bool input)
764 {
765 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
766 struct rockchip_pin_bank *bank;
767 struct gpio_chip *chip;
768 int pin, ret;
769 u32 data;
770
771 chip = range->gc;
772 bank = gc_to_pin_bank(chip);
773 pin = offset - chip->base;
774
775 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
776 offset, range->name, pin, input ? "input" : "output");
777
778 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
779 if (ret < 0)
780 return ret;
781
782 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
783 /* set bit to 1 for output, 0 for input */
784 if (!input)
785 data |= BIT(pin);
786 else
787 data &= ~BIT(pin);
788 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
789
790 return 0;
791 }
792
793 static const struct pinmux_ops rockchip_pmx_ops = {
794 .get_functions_count = rockchip_pmx_get_funcs_count,
795 .get_function_name = rockchip_pmx_get_func_name,
796 .get_function_groups = rockchip_pmx_get_groups,
797 .enable = rockchip_pmx_enable,
798 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
799 };
800
801 /*
802 * Pinconf_ops handling
803 */
804
805 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
806 enum pin_config_param pull)
807 {
808 switch (ctrl->type) {
809 case RK2928:
810 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
811 pull == PIN_CONFIG_BIAS_DISABLE);
812 case RK3066B:
813 return pull ? false : true;
814 case RK3188:
815 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
816 }
817
818 return false;
819 }
820
821 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
822 unsigned offset, int value);
823 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
824
825 /* set the pin config settings for a specified pin */
826 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
827 unsigned long *configs, unsigned num_configs)
828 {
829 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
830 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
831 enum pin_config_param param;
832 u16 arg;
833 int i;
834 int rc;
835
836 for (i = 0; i < num_configs; i++) {
837 param = pinconf_to_config_param(configs[i]);
838 arg = pinconf_to_config_argument(configs[i]);
839
840 switch (param) {
841 case PIN_CONFIG_BIAS_DISABLE:
842 rc = rockchip_set_pull(bank, pin - bank->pin_base,
843 param);
844 if (rc)
845 return rc;
846 break;
847 case PIN_CONFIG_BIAS_PULL_UP:
848 case PIN_CONFIG_BIAS_PULL_DOWN:
849 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
850 case PIN_CONFIG_BIAS_BUS_HOLD:
851 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
852 return -ENOTSUPP;
853
854 if (!arg)
855 return -EINVAL;
856
857 rc = rockchip_set_pull(bank, pin - bank->pin_base,
858 param);
859 if (rc)
860 return rc;
861 break;
862 case PIN_CONFIG_OUTPUT:
863 rc = rockchip_gpio_direction_output(&bank->gpio_chip,
864 pin - bank->pin_base,
865 arg);
866 if (rc)
867 return rc;
868 break;
869 default:
870 return -ENOTSUPP;
871 break;
872 }
873 } /* for each config */
874
875 return 0;
876 }
877
878 /* get the pin config settings for a specified pin */
879 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
880 unsigned long *config)
881 {
882 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
883 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
884 enum pin_config_param param = pinconf_to_config_param(*config);
885 u16 arg;
886 int rc;
887
888 switch (param) {
889 case PIN_CONFIG_BIAS_DISABLE:
890 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
891 return -EINVAL;
892
893 arg = 0;
894 break;
895 case PIN_CONFIG_BIAS_PULL_UP:
896 case PIN_CONFIG_BIAS_PULL_DOWN:
897 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
898 case PIN_CONFIG_BIAS_BUS_HOLD:
899 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
900 return -ENOTSUPP;
901
902 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
903 return -EINVAL;
904
905 arg = 1;
906 break;
907 case PIN_CONFIG_OUTPUT:
908 rc = rockchip_get_mux(bank, pin - bank->pin_base);
909 if (rc != RK_FUNC_GPIO)
910 return -EINVAL;
911
912 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
913 if (rc < 0)
914 return rc;
915
916 arg = rc ? 1 : 0;
917 break;
918 default:
919 return -ENOTSUPP;
920 break;
921 }
922
923 *config = pinconf_to_config_packed(param, arg);
924
925 return 0;
926 }
927
928 static const struct pinconf_ops rockchip_pinconf_ops = {
929 .pin_config_get = rockchip_pinconf_get,
930 .pin_config_set = rockchip_pinconf_set,
931 };
932
933 static const struct of_device_id rockchip_bank_match[] = {
934 { .compatible = "rockchip,gpio-bank" },
935 { .compatible = "rockchip,rk3188-gpio-bank0" },
936 {},
937 };
938
939 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
940 struct device_node *np)
941 {
942 struct device_node *child;
943
944 for_each_child_of_node(np, child) {
945 if (of_match_node(rockchip_bank_match, child))
946 continue;
947
948 info->nfunctions++;
949 info->ngroups += of_get_child_count(child);
950 }
951 }
952
953 static int rockchip_pinctrl_parse_groups(struct device_node *np,
954 struct rockchip_pin_group *grp,
955 struct rockchip_pinctrl *info,
956 u32 index)
957 {
958 struct rockchip_pin_bank *bank;
959 int size;
960 const __be32 *list;
961 int num;
962 int i, j;
963 int ret;
964
965 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
966
967 /* Initialise group */
968 grp->name = np->name;
969
970 /*
971 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
972 * do sanity check and calculate pins number
973 */
974 list = of_get_property(np, "rockchip,pins", &size);
975 /* we do not check return since it's safe node passed down */
976 size /= sizeof(*list);
977 if (!size || size % 4) {
978 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
979 return -EINVAL;
980 }
981
982 grp->npins = size / 4;
983
984 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
985 GFP_KERNEL);
986 grp->data = devm_kzalloc(info->dev, grp->npins *
987 sizeof(struct rockchip_pin_config),
988 GFP_KERNEL);
989 if (!grp->pins || !grp->data)
990 return -ENOMEM;
991
992 for (i = 0, j = 0; i < size; i += 4, j++) {
993 const __be32 *phandle;
994 struct device_node *np_config;
995
996 num = be32_to_cpu(*list++);
997 bank = bank_num_to_bank(info, num);
998 if (IS_ERR(bank))
999 return PTR_ERR(bank);
1000
1001 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
1002 grp->data[j].func = be32_to_cpu(*list++);
1003
1004 phandle = list++;
1005 if (!phandle)
1006 return -EINVAL;
1007
1008 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
1009 ret = pinconf_generic_parse_dt_config(np_config,
1010 &grp->data[j].configs, &grp->data[j].nconfigs);
1011 if (ret)
1012 return ret;
1013 }
1014
1015 return 0;
1016 }
1017
1018 static int rockchip_pinctrl_parse_functions(struct device_node *np,
1019 struct rockchip_pinctrl *info,
1020 u32 index)
1021 {
1022 struct device_node *child;
1023 struct rockchip_pmx_func *func;
1024 struct rockchip_pin_group *grp;
1025 int ret;
1026 static u32 grp_index;
1027 u32 i = 0;
1028
1029 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1030
1031 func = &info->functions[index];
1032
1033 /* Initialise function */
1034 func->name = np->name;
1035 func->ngroups = of_get_child_count(np);
1036 if (func->ngroups <= 0)
1037 return 0;
1038
1039 func->groups = devm_kzalloc(info->dev,
1040 func->ngroups * sizeof(char *), GFP_KERNEL);
1041 if (!func->groups)
1042 return -ENOMEM;
1043
1044 for_each_child_of_node(np, child) {
1045 func->groups[i] = child->name;
1046 grp = &info->groups[grp_index++];
1047 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
1048 if (ret)
1049 return ret;
1050 }
1051
1052 return 0;
1053 }
1054
1055 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
1056 struct rockchip_pinctrl *info)
1057 {
1058 struct device *dev = &pdev->dev;
1059 struct device_node *np = dev->of_node;
1060 struct device_node *child;
1061 int ret;
1062 int i;
1063
1064 rockchip_pinctrl_child_count(info, np);
1065
1066 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1067 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1068
1069 info->functions = devm_kzalloc(dev, info->nfunctions *
1070 sizeof(struct rockchip_pmx_func),
1071 GFP_KERNEL);
1072 if (!info->functions) {
1073 dev_err(dev, "failed to allocate memory for function list\n");
1074 return -EINVAL;
1075 }
1076
1077 info->groups = devm_kzalloc(dev, info->ngroups *
1078 sizeof(struct rockchip_pin_group),
1079 GFP_KERNEL);
1080 if (!info->groups) {
1081 dev_err(dev, "failed allocate memory for ping group list\n");
1082 return -EINVAL;
1083 }
1084
1085 i = 0;
1086
1087 for_each_child_of_node(np, child) {
1088 if (of_match_node(rockchip_bank_match, child))
1089 continue;
1090
1091 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1092 if (ret) {
1093 dev_err(&pdev->dev, "failed to parse function\n");
1094 return ret;
1095 }
1096 }
1097
1098 return 0;
1099 }
1100
1101 static int rockchip_pinctrl_register(struct platform_device *pdev,
1102 struct rockchip_pinctrl *info)
1103 {
1104 struct pinctrl_desc *ctrldesc = &info->pctl;
1105 struct pinctrl_pin_desc *pindesc, *pdesc;
1106 struct rockchip_pin_bank *pin_bank;
1107 int pin, bank, ret;
1108 int k;
1109
1110 ctrldesc->name = "rockchip-pinctrl";
1111 ctrldesc->owner = THIS_MODULE;
1112 ctrldesc->pctlops = &rockchip_pctrl_ops;
1113 ctrldesc->pmxops = &rockchip_pmx_ops;
1114 ctrldesc->confops = &rockchip_pinconf_ops;
1115
1116 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1117 info->ctrl->nr_pins, GFP_KERNEL);
1118 if (!pindesc) {
1119 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1120 return -ENOMEM;
1121 }
1122 ctrldesc->pins = pindesc;
1123 ctrldesc->npins = info->ctrl->nr_pins;
1124
1125 pdesc = pindesc;
1126 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1127 pin_bank = &info->ctrl->pin_banks[bank];
1128 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1129 pdesc->number = k;
1130 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1131 pin_bank->name, pin);
1132 pdesc++;
1133 }
1134 }
1135
1136 info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
1137 if (!info->pctl_dev) {
1138 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1139 return -EINVAL;
1140 }
1141
1142 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1143 pin_bank = &info->ctrl->pin_banks[bank];
1144 pin_bank->grange.name = pin_bank->name;
1145 pin_bank->grange.id = bank;
1146 pin_bank->grange.pin_base = pin_bank->pin_base;
1147 pin_bank->grange.base = pin_bank->gpio_chip.base;
1148 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1149 pin_bank->grange.gc = &pin_bank->gpio_chip;
1150 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
1151 }
1152
1153 ret = rockchip_pinctrl_parse_dt(pdev, info);
1154 if (ret) {
1155 pinctrl_unregister(info->pctl_dev);
1156 return ret;
1157 }
1158
1159 return 0;
1160 }
1161
1162 /*
1163 * GPIO handling
1164 */
1165
1166 static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
1167 {
1168 return pinctrl_request_gpio(chip->base + offset);
1169 }
1170
1171 static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
1172 {
1173 pinctrl_free_gpio(chip->base + offset);
1174 }
1175
1176 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1177 {
1178 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1179 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1180 unsigned long flags;
1181 u32 data;
1182
1183 spin_lock_irqsave(&bank->slock, flags);
1184
1185 data = readl(reg);
1186 data &= ~BIT(offset);
1187 if (value)
1188 data |= BIT(offset);
1189 writel(data, reg);
1190
1191 spin_unlock_irqrestore(&bank->slock, flags);
1192 }
1193
1194 /*
1195 * Returns the level of the pin for input direction and setting of the DR
1196 * register for output gpios.
1197 */
1198 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1199 {
1200 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1201 u32 data;
1202
1203 data = readl(bank->reg_base + GPIO_EXT_PORT);
1204 data >>= offset;
1205 data &= 1;
1206 return data;
1207 }
1208
1209 /*
1210 * gpiolib gpio_direction_input callback function. The setting of the pin
1211 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1212 * interface.
1213 */
1214 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1215 {
1216 return pinctrl_gpio_direction_input(gc->base + offset);
1217 }
1218
1219 /*
1220 * gpiolib gpio_direction_output callback function. The setting of the pin
1221 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1222 * interface.
1223 */
1224 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1225 unsigned offset, int value)
1226 {
1227 rockchip_gpio_set(gc, offset, value);
1228 return pinctrl_gpio_direction_output(gc->base + offset);
1229 }
1230
1231 /*
1232 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1233 * and a virtual IRQ, if not already present.
1234 */
1235 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1236 {
1237 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1238 unsigned int virq;
1239
1240 if (!bank->domain)
1241 return -ENXIO;
1242
1243 virq = irq_create_mapping(bank->domain, offset);
1244
1245 return (virq) ? : -ENXIO;
1246 }
1247
1248 static const struct gpio_chip rockchip_gpiolib_chip = {
1249 .request = rockchip_gpio_request,
1250 .free = rockchip_gpio_free,
1251 .set = rockchip_gpio_set,
1252 .get = rockchip_gpio_get,
1253 .direction_input = rockchip_gpio_direction_input,
1254 .direction_output = rockchip_gpio_direction_output,
1255 .to_irq = rockchip_gpio_to_irq,
1256 .owner = THIS_MODULE,
1257 };
1258
1259 /*
1260 * Interrupt handling
1261 */
1262
1263 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
1264 {
1265 struct irq_chip *chip = irq_get_chip(irq);
1266 struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
1267 u32 polarity = 0, data = 0;
1268 u32 pend;
1269 bool edge_changed = false;
1270
1271 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1272
1273 chained_irq_enter(chip, desc);
1274
1275 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1276
1277 if (bank->toggle_edge_mode) {
1278 polarity = readl_relaxed(bank->reg_base +
1279 GPIO_INT_POLARITY);
1280 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1281 }
1282
1283 while (pend) {
1284 unsigned int virq;
1285
1286 irq = __ffs(pend);
1287 pend &= ~BIT(irq);
1288 virq = irq_linear_revmap(bank->domain, irq);
1289
1290 if (!virq) {
1291 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1292 continue;
1293 }
1294
1295 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1296
1297 /*
1298 * Triggering IRQ on both rising and falling edge
1299 * needs manual intervention.
1300 */
1301 if (bank->toggle_edge_mode & BIT(irq)) {
1302 if (data & BIT(irq))
1303 polarity &= ~BIT(irq);
1304 else
1305 polarity |= BIT(irq);
1306
1307 edge_changed = true;
1308 }
1309
1310 generic_handle_irq(virq);
1311 }
1312
1313 if (bank->toggle_edge_mode && edge_changed) {
1314 /* Interrupt params should only be set with ints disabled */
1315 data = readl_relaxed(bank->reg_base + GPIO_INTEN);
1316 writel_relaxed(0, bank->reg_base + GPIO_INTEN);
1317 writel(polarity, bank->reg_base + GPIO_INT_POLARITY);
1318 writel(data, bank->reg_base + GPIO_INTEN);
1319 }
1320
1321 chained_irq_exit(chip, desc);
1322 }
1323
1324 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1325 {
1326 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1327 struct rockchip_pin_bank *bank = gc->private;
1328 u32 mask = BIT(d->hwirq);
1329 u32 polarity;
1330 u32 level;
1331 u32 data;
1332 int ret;
1333
1334 /* make sure the pin is configured as gpio input */
1335 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1336 if (ret < 0)
1337 return ret;
1338
1339 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1340 data &= ~mask;
1341 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1342
1343 if (type & IRQ_TYPE_EDGE_BOTH)
1344 __irq_set_handler_locked(d->irq, handle_edge_irq);
1345 else
1346 __irq_set_handler_locked(d->irq, handle_level_irq);
1347
1348 irq_gc_lock(gc);
1349
1350 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1351 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1352
1353 switch (type) {
1354 case IRQ_TYPE_EDGE_BOTH:
1355 bank->toggle_edge_mode |= mask;
1356 level |= mask;
1357
1358 /*
1359 * Determine gpio state. If 1 next interrupt should be falling
1360 * otherwise rising.
1361 */
1362 data = readl(bank->reg_base + GPIO_EXT_PORT);
1363 if (data & mask)
1364 polarity &= ~mask;
1365 else
1366 polarity |= mask;
1367 break;
1368 case IRQ_TYPE_EDGE_RISING:
1369 bank->toggle_edge_mode &= ~mask;
1370 level |= mask;
1371 polarity |= mask;
1372 break;
1373 case IRQ_TYPE_EDGE_FALLING:
1374 bank->toggle_edge_mode &= ~mask;
1375 level |= mask;
1376 polarity &= ~mask;
1377 break;
1378 case IRQ_TYPE_LEVEL_HIGH:
1379 bank->toggle_edge_mode &= ~mask;
1380 level &= ~mask;
1381 polarity |= mask;
1382 break;
1383 case IRQ_TYPE_LEVEL_LOW:
1384 bank->toggle_edge_mode &= ~mask;
1385 level &= ~mask;
1386 polarity &= ~mask;
1387 break;
1388 default:
1389 irq_gc_unlock(gc);
1390 return -EINVAL;
1391 }
1392
1393 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1394 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1395
1396 irq_gc_unlock(gc);
1397
1398 return 0;
1399 }
1400
1401 static int rockchip_interrupts_register(struct platform_device *pdev,
1402 struct rockchip_pinctrl *info)
1403 {
1404 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1405 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1406 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1407 struct irq_chip_generic *gc;
1408 int ret;
1409 int i;
1410
1411 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1412 if (!bank->valid) {
1413 dev_warn(&pdev->dev, "bank %s is not valid\n",
1414 bank->name);
1415 continue;
1416 }
1417
1418 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1419 &irq_generic_chip_ops, NULL);
1420 if (!bank->domain) {
1421 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1422 bank->name);
1423 continue;
1424 }
1425
1426 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1427 "rockchip_gpio_irq", handle_level_irq,
1428 clr, 0, IRQ_GC_INIT_MASK_CACHE);
1429 if (ret) {
1430 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1431 bank->name);
1432 irq_domain_remove(bank->domain);
1433 continue;
1434 }
1435
1436 gc = irq_get_domain_generic_chip(bank->domain, 0);
1437 gc->reg_base = bank->reg_base;
1438 gc->private = bank;
1439 gc->chip_types[0].regs.mask = GPIO_INTEN;
1440 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1441 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1442 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
1443 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
1444 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1445 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1446
1447 irq_set_handler_data(bank->irq, bank);
1448 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1449 }
1450
1451 return 0;
1452 }
1453
1454 static int rockchip_gpiolib_register(struct platform_device *pdev,
1455 struct rockchip_pinctrl *info)
1456 {
1457 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1458 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1459 struct gpio_chip *gc;
1460 int ret;
1461 int i;
1462
1463 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1464 if (!bank->valid) {
1465 dev_warn(&pdev->dev, "bank %s is not valid\n",
1466 bank->name);
1467 continue;
1468 }
1469
1470 bank->gpio_chip = rockchip_gpiolib_chip;
1471
1472 gc = &bank->gpio_chip;
1473 gc->base = bank->pin_base;
1474 gc->ngpio = bank->nr_pins;
1475 gc->dev = &pdev->dev;
1476 gc->of_node = bank->of_node;
1477 gc->label = bank->name;
1478
1479 ret = gpiochip_add(gc);
1480 if (ret) {
1481 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1482 gc->label, ret);
1483 goto fail;
1484 }
1485 }
1486
1487 rockchip_interrupts_register(pdev, info);
1488
1489 return 0;
1490
1491 fail:
1492 for (--i, --bank; i >= 0; --i, --bank) {
1493 if (!bank->valid)
1494 continue;
1495 gpiochip_remove(&bank->gpio_chip);
1496 }
1497 return ret;
1498 }
1499
1500 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1501 struct rockchip_pinctrl *info)
1502 {
1503 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1504 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1505 int i;
1506
1507 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1508 if (!bank->valid)
1509 continue;
1510 gpiochip_remove(&bank->gpio_chip);
1511 }
1512
1513 return 0;
1514 }
1515
1516 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1517 struct rockchip_pinctrl *info)
1518 {
1519 struct resource res;
1520 void __iomem *base;
1521
1522 if (of_address_to_resource(bank->of_node, 0, &res)) {
1523 dev_err(info->dev, "cannot find IO resource for bank\n");
1524 return -ENOENT;
1525 }
1526
1527 bank->reg_base = devm_ioremap_resource(info->dev, &res);
1528 if (IS_ERR(bank->reg_base))
1529 return PTR_ERR(bank->reg_base);
1530
1531 /*
1532 * special case, where parts of the pull setting-registers are
1533 * part of the PMU register space
1534 */
1535 if (of_device_is_compatible(bank->of_node,
1536 "rockchip,rk3188-gpio-bank0")) {
1537 struct device_node *node;
1538
1539 node = of_parse_phandle(bank->of_node->parent,
1540 "rockchip,pmu", 0);
1541 if (!node) {
1542 if (of_address_to_resource(bank->of_node, 1, &res)) {
1543 dev_err(info->dev, "cannot find IO resource for bank\n");
1544 return -ENOENT;
1545 }
1546
1547 base = devm_ioremap_resource(info->dev, &res);
1548 if (IS_ERR(base))
1549 return PTR_ERR(base);
1550 rockchip_regmap_config.max_register =
1551 resource_size(&res) - 4;
1552 rockchip_regmap_config.name =
1553 "rockchip,rk3188-gpio-bank0-pull";
1554 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
1555 base,
1556 &rockchip_regmap_config);
1557 }
1558 }
1559
1560 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1561
1562 bank->clk = of_clk_get(bank->of_node, 0);
1563 if (IS_ERR(bank->clk))
1564 return PTR_ERR(bank->clk);
1565
1566 return clk_prepare_enable(bank->clk);
1567 }
1568
1569 static const struct of_device_id rockchip_pinctrl_dt_match[];
1570
1571 /* retrieve the soc specific data */
1572 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1573 struct rockchip_pinctrl *d,
1574 struct platform_device *pdev)
1575 {
1576 const struct of_device_id *match;
1577 struct device_node *node = pdev->dev.of_node;
1578 struct device_node *np;
1579 struct rockchip_pin_ctrl *ctrl;
1580 struct rockchip_pin_bank *bank;
1581 int grf_offs, pmu_offs, i, j;
1582
1583 match = of_match_node(rockchip_pinctrl_dt_match, node);
1584 ctrl = (struct rockchip_pin_ctrl *)match->data;
1585
1586 for_each_child_of_node(node, np) {
1587 if (!of_find_property(np, "gpio-controller", NULL))
1588 continue;
1589
1590 bank = ctrl->pin_banks;
1591 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1592 if (!strcmp(bank->name, np->name)) {
1593 bank->of_node = np;
1594
1595 if (!rockchip_get_bank_data(bank, d))
1596 bank->valid = true;
1597
1598 break;
1599 }
1600 }
1601 }
1602
1603 grf_offs = ctrl->grf_mux_offset;
1604 pmu_offs = ctrl->pmu_mux_offset;
1605 bank = ctrl->pin_banks;
1606 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1607 int bank_pins = 0;
1608
1609 spin_lock_init(&bank->slock);
1610 bank->drvdata = d;
1611 bank->pin_base = ctrl->nr_pins;
1612 ctrl->nr_pins += bank->nr_pins;
1613
1614 /* calculate iomux offsets */
1615 for (j = 0; j < 4; j++) {
1616 struct rockchip_iomux *iom = &bank->iomux[j];
1617 int inc;
1618
1619 if (bank_pins >= bank->nr_pins)
1620 break;
1621
1622 /* preset offset value, set new start value */
1623 if (iom->offset >= 0) {
1624 if (iom->type & IOMUX_SOURCE_PMU)
1625 pmu_offs = iom->offset;
1626 else
1627 grf_offs = iom->offset;
1628 } else { /* set current offset */
1629 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
1630 pmu_offs : grf_offs;
1631 }
1632
1633 dev_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n",
1634 i, j, iom->offset);
1635
1636 /*
1637 * Increase offset according to iomux width.
1638 * 4bit iomux'es are spread over two registers.
1639 */
1640 inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4;
1641 if (iom->type & IOMUX_SOURCE_PMU)
1642 pmu_offs += inc;
1643 else
1644 grf_offs += inc;
1645
1646 bank_pins += 8;
1647 }
1648 }
1649
1650 return ctrl;
1651 }
1652
1653 static int rockchip_pinctrl_probe(struct platform_device *pdev)
1654 {
1655 struct rockchip_pinctrl *info;
1656 struct device *dev = &pdev->dev;
1657 struct rockchip_pin_ctrl *ctrl;
1658 struct device_node *np = pdev->dev.of_node, *node;
1659 struct resource *res;
1660 void __iomem *base;
1661 int ret;
1662
1663 if (!dev->of_node) {
1664 dev_err(dev, "device tree node not found\n");
1665 return -ENODEV;
1666 }
1667
1668 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
1669 if (!info)
1670 return -ENOMEM;
1671
1672 info->dev = dev;
1673
1674 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
1675 if (!ctrl) {
1676 dev_err(dev, "driver data not available\n");
1677 return -EINVAL;
1678 }
1679 info->ctrl = ctrl;
1680
1681 node = of_parse_phandle(np, "rockchip,grf", 0);
1682 if (node) {
1683 info->regmap_base = syscon_node_to_regmap(node);
1684 if (IS_ERR(info->regmap_base))
1685 return PTR_ERR(info->regmap_base);
1686 } else {
1687 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1688 base = devm_ioremap_resource(&pdev->dev, res);
1689 if (IS_ERR(base))
1690 return PTR_ERR(base);
1691
1692 rockchip_regmap_config.max_register = resource_size(res) - 4;
1693 rockchip_regmap_config.name = "rockchip,pinctrl";
1694 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
1695 &rockchip_regmap_config);
1696
1697 /* to check for the old dt-bindings */
1698 info->reg_size = resource_size(res);
1699
1700 /* Honor the old binding, with pull registers as 2nd resource */
1701 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
1702 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1703 base = devm_ioremap_resource(&pdev->dev, res);
1704 if (IS_ERR(base))
1705 return PTR_ERR(base);
1706
1707 rockchip_regmap_config.max_register =
1708 resource_size(res) - 4;
1709 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
1710 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
1711 base,
1712 &rockchip_regmap_config);
1713 }
1714 }
1715
1716 /* try to find the optional reference to the pmu syscon */
1717 node = of_parse_phandle(np, "rockchip,pmu", 0);
1718 if (node) {
1719 info->regmap_pmu = syscon_node_to_regmap(node);
1720 if (IS_ERR(info->regmap_pmu))
1721 return PTR_ERR(info->regmap_pmu);
1722 }
1723
1724 ret = rockchip_gpiolib_register(pdev, info);
1725 if (ret)
1726 return ret;
1727
1728 ret = rockchip_pinctrl_register(pdev, info);
1729 if (ret) {
1730 rockchip_gpiolib_unregister(pdev, info);
1731 return ret;
1732 }
1733
1734 platform_set_drvdata(pdev, info);
1735
1736 return 0;
1737 }
1738
1739 static struct rockchip_pin_bank rk2928_pin_banks[] = {
1740 PIN_BANK(0, 32, "gpio0"),
1741 PIN_BANK(1, 32, "gpio1"),
1742 PIN_BANK(2, 32, "gpio2"),
1743 PIN_BANK(3, 32, "gpio3"),
1744 };
1745
1746 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1747 .pin_banks = rk2928_pin_banks,
1748 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
1749 .label = "RK2928-GPIO",
1750 .type = RK2928,
1751 .grf_mux_offset = 0xa8,
1752 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
1753 };
1754
1755 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
1756 PIN_BANK(0, 32, "gpio0"),
1757 PIN_BANK(1, 32, "gpio1"),
1758 PIN_BANK(2, 32, "gpio2"),
1759 PIN_BANK(3, 32, "gpio3"),
1760 PIN_BANK(4, 32, "gpio4"),
1761 PIN_BANK(6, 16, "gpio6"),
1762 };
1763
1764 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
1765 .pin_banks = rk3066a_pin_banks,
1766 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
1767 .label = "RK3066a-GPIO",
1768 .type = RK2928,
1769 .grf_mux_offset = 0xa8,
1770 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
1771 };
1772
1773 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
1774 PIN_BANK(0, 32, "gpio0"),
1775 PIN_BANK(1, 32, "gpio1"),
1776 PIN_BANK(2, 32, "gpio2"),
1777 PIN_BANK(3, 32, "gpio3"),
1778 };
1779
1780 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
1781 .pin_banks = rk3066b_pin_banks,
1782 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
1783 .label = "RK3066b-GPIO",
1784 .type = RK3066B,
1785 .grf_mux_offset = 0x60,
1786 };
1787
1788 static struct rockchip_pin_bank rk3188_pin_banks[] = {
1789 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
1790 PIN_BANK(1, 32, "gpio1"),
1791 PIN_BANK(2, 32, "gpio2"),
1792 PIN_BANK(3, 32, "gpio3"),
1793 };
1794
1795 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
1796 .pin_banks = rk3188_pin_banks,
1797 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
1798 .label = "RK3188-GPIO",
1799 .type = RK3188,
1800 .grf_mux_offset = 0x60,
1801 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
1802 };
1803
1804 static struct rockchip_pin_bank rk3288_pin_banks[] = {
1805 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
1806 IOMUX_SOURCE_PMU,
1807 IOMUX_SOURCE_PMU,
1808 IOMUX_UNROUTED
1809 ),
1810 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
1811 IOMUX_UNROUTED,
1812 IOMUX_UNROUTED,
1813 0
1814 ),
1815 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
1816 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
1817 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
1818 IOMUX_WIDTH_4BIT,
1819 0,
1820 0
1821 ),
1822 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
1823 0,
1824 0,
1825 IOMUX_UNROUTED
1826 ),
1827 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
1828 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
1829 0,
1830 IOMUX_WIDTH_4BIT,
1831 IOMUX_UNROUTED
1832 ),
1833 PIN_BANK(8, 16, "gpio8"),
1834 };
1835
1836 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
1837 .pin_banks = rk3288_pin_banks,
1838 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
1839 .label = "RK3288-GPIO",
1840 .type = RK3188,
1841 .grf_mux_offset = 0x0,
1842 .pmu_mux_offset = 0x84,
1843 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
1844 };
1845
1846 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
1847 { .compatible = "rockchip,rk2928-pinctrl",
1848 .data = (void *)&rk2928_pin_ctrl },
1849 { .compatible = "rockchip,rk3066a-pinctrl",
1850 .data = (void *)&rk3066a_pin_ctrl },
1851 { .compatible = "rockchip,rk3066b-pinctrl",
1852 .data = (void *)&rk3066b_pin_ctrl },
1853 { .compatible = "rockchip,rk3188-pinctrl",
1854 .data = (void *)&rk3188_pin_ctrl },
1855 { .compatible = "rockchip,rk3288-pinctrl",
1856 .data = (void *)&rk3288_pin_ctrl },
1857 {},
1858 };
1859 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
1860
1861 static struct platform_driver rockchip_pinctrl_driver = {
1862 .probe = rockchip_pinctrl_probe,
1863 .driver = {
1864 .name = "rockchip-pinctrl",
1865 .owner = THIS_MODULE,
1866 .of_match_table = rockchip_pinctrl_dt_match,
1867 },
1868 };
1869
1870 static int __init rockchip_pinctrl_drv_register(void)
1871 {
1872 return platform_driver_register(&rockchip_pinctrl_driver);
1873 }
1874 postcore_initcall(rockchip_pinctrl_drv_register);
1875
1876 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
1877 MODULE_DESCRIPTION("Rockchip pinctrl driver");
1878 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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