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pinctrl: rockchip: Simplify pin_to_bank equation
[deliverable/linux.git] / drivers / pinctrl / pinctrl-rockchip.c
1 /*
2 * Pinctrl driver for Rockchip SoCs
3 *
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
6 *
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
12 *
13 * and pinctrl-at91:
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 */
25
26 #include <linux/module.h>
27 #include <linux/platform_device.h>
28 #include <linux/io.h>
29 #include <linux/bitops.h>
30 #include <linux/gpio.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/pinctrl/machine.h>
34 #include <linux/pinctrl/pinconf.h>
35 #include <linux/pinctrl/pinctrl.h>
36 #include <linux/pinctrl/pinmux.h>
37 #include <linux/pinctrl/pinconf-generic.h>
38 #include <linux/irqchip/chained_irq.h>
39 #include <linux/clk.h>
40 #include <dt-bindings/pinctrl/rockchip.h>
41
42 #include "core.h"
43 #include "pinconf.h"
44
45 /* GPIO control registers */
46 #define GPIO_SWPORT_DR 0x00
47 #define GPIO_SWPORT_DDR 0x04
48 #define GPIO_INTEN 0x30
49 #define GPIO_INTMASK 0x34
50 #define GPIO_INTTYPE_LEVEL 0x38
51 #define GPIO_INT_POLARITY 0x3c
52 #define GPIO_INT_STATUS 0x40
53 #define GPIO_INT_RAWSTATUS 0x44
54 #define GPIO_DEBOUNCE 0x48
55 #define GPIO_PORTS_EOI 0x4c
56 #define GPIO_EXT_PORT 0x50
57 #define GPIO_LS_SYNC 0x60
58
59 /**
60 * @reg_base: register base of the gpio bank
61 * @clk: clock of the gpio bank
62 * @irq: interrupt of the gpio bank
63 * @pin_base: first pin number
64 * @nr_pins: number of pins in this bank
65 * @name: name of the bank
66 * @bank_num: number of the bank, to account for holes
67 * @valid: are all necessary informations present
68 * @of_node: dt node of this bank
69 * @drvdata: common pinctrl basedata
70 * @domain: irqdomain of the gpio bank
71 * @gpio_chip: gpiolib chip
72 * @grange: gpio range
73 * @slock: spinlock for the gpio bank
74 */
75 struct rockchip_pin_bank {
76 void __iomem *reg_base;
77 struct clk *clk;
78 int irq;
79 u32 pin_base;
80 u8 nr_pins;
81 char *name;
82 u8 bank_num;
83 bool valid;
84 struct device_node *of_node;
85 struct rockchip_pinctrl *drvdata;
86 struct irq_domain *domain;
87 struct gpio_chip gpio_chip;
88 struct pinctrl_gpio_range grange;
89 spinlock_t slock;
90
91 };
92
93 #define PIN_BANK(id, pins, label) \
94 { \
95 .bank_num = id, \
96 .nr_pins = pins, \
97 .name = label, \
98 }
99
100 /**
101 * @pull_auto: some SoCs don't allow pulls to be specified as up or down, but
102 * instead decide this automatically based on the pad-type.
103 */
104 struct rockchip_pin_ctrl {
105 struct rockchip_pin_bank *pin_banks;
106 u32 nr_banks;
107 u32 nr_pins;
108 char *label;
109 int mux_offset;
110 int pull_offset;
111 bool pull_auto;
112 int pull_bank_stride;
113 };
114
115 struct rockchip_pin_config {
116 unsigned int func;
117 unsigned long *configs;
118 unsigned int nconfigs;
119 };
120
121 /**
122 * struct rockchip_pin_group: represent group of pins of a pinmux function.
123 * @name: name of the pin group, used to lookup the group.
124 * @pins: the pins included in this group.
125 * @npins: number of pins included in this group.
126 * @func: the mux function number to be programmed when selected.
127 * @configs: the config values to be set for each pin
128 * @nconfigs: number of configs for each pin
129 */
130 struct rockchip_pin_group {
131 const char *name;
132 unsigned int npins;
133 unsigned int *pins;
134 struct rockchip_pin_config *data;
135 };
136
137 /**
138 * struct rockchip_pmx_func: represent a pin function.
139 * @name: name of the pin function, used to lookup the function.
140 * @groups: one or more names of pin groups that provide this function.
141 * @num_groups: number of groups included in @groups.
142 */
143 struct rockchip_pmx_func {
144 const char *name;
145 const char **groups;
146 u8 ngroups;
147 };
148
149 struct rockchip_pinctrl {
150 void __iomem *reg_base;
151 struct device *dev;
152 struct rockchip_pin_ctrl *ctrl;
153 struct pinctrl_desc pctl;
154 struct pinctrl_dev *pctl_dev;
155 struct rockchip_pin_group *groups;
156 unsigned int ngroups;
157 struct rockchip_pmx_func *functions;
158 unsigned int nfunctions;
159 };
160
161 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
162 {
163 return container_of(gc, struct rockchip_pin_bank, gpio_chip);
164 }
165
166 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
167 const struct rockchip_pinctrl *info,
168 const char *name)
169 {
170 int i;
171
172 for (i = 0; i < info->ngroups; i++) {
173 if (!strcmp(info->groups[i].name, name))
174 return &info->groups[i];
175 }
176
177 return NULL;
178 }
179
180 /*
181 * given a pin number that is local to a pin controller, find out the pin bank
182 * and the register base of the pin bank.
183 */
184 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
185 unsigned pin)
186 {
187 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
188
189 while (pin >= (b->pin_base + b->nr_pins))
190 b++;
191
192 return b;
193 }
194
195 static struct rockchip_pin_bank *bank_num_to_bank(
196 struct rockchip_pinctrl *info,
197 unsigned num)
198 {
199 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
200 int i;
201
202 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
203 if (b->bank_num == num)
204 return b;
205 }
206
207 return ERR_PTR(-EINVAL);
208 }
209
210 /*
211 * Pinctrl_ops handling
212 */
213
214 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
215 {
216 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
217
218 return info->ngroups;
219 }
220
221 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
222 unsigned selector)
223 {
224 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
225
226 return info->groups[selector].name;
227 }
228
229 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
230 unsigned selector, const unsigned **pins,
231 unsigned *npins)
232 {
233 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
234
235 if (selector >= info->ngroups)
236 return -EINVAL;
237
238 *pins = info->groups[selector].pins;
239 *npins = info->groups[selector].npins;
240
241 return 0;
242 }
243
244 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
245 struct device_node *np,
246 struct pinctrl_map **map, unsigned *num_maps)
247 {
248 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
249 const struct rockchip_pin_group *grp;
250 struct pinctrl_map *new_map;
251 struct device_node *parent;
252 int map_num = 1;
253 int i;
254
255 /*
256 * first find the group of this node and check if we need to create
257 * config maps for pins
258 */
259 grp = pinctrl_name_to_group(info, np->name);
260 if (!grp) {
261 dev_err(info->dev, "unable to find group for node %s\n",
262 np->name);
263 return -EINVAL;
264 }
265
266 map_num += grp->npins;
267 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
268 GFP_KERNEL);
269 if (!new_map)
270 return -ENOMEM;
271
272 *map = new_map;
273 *num_maps = map_num;
274
275 /* create mux map */
276 parent = of_get_parent(np);
277 if (!parent) {
278 devm_kfree(pctldev->dev, new_map);
279 return -EINVAL;
280 }
281 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
282 new_map[0].data.mux.function = parent->name;
283 new_map[0].data.mux.group = np->name;
284 of_node_put(parent);
285
286 /* create config map */
287 new_map++;
288 for (i = 0; i < grp->npins; i++) {
289 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
290 new_map[i].data.configs.group_or_pin =
291 pin_get_name(pctldev, grp->pins[i]);
292 new_map[i].data.configs.configs = grp->data[i].configs;
293 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
294 }
295
296 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
297 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
298
299 return 0;
300 }
301
302 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
303 struct pinctrl_map *map, unsigned num_maps)
304 {
305 }
306
307 static const struct pinctrl_ops rockchip_pctrl_ops = {
308 .get_groups_count = rockchip_get_groups_count,
309 .get_group_name = rockchip_get_group_name,
310 .get_group_pins = rockchip_get_group_pins,
311 .dt_node_to_map = rockchip_dt_node_to_map,
312 .dt_free_map = rockchip_dt_free_map,
313 };
314
315 /*
316 * Hardware access
317 */
318
319 /*
320 * Set a new mux function for a pin.
321 *
322 * The register is divided into the upper and lower 16 bit. When changing
323 * a value, the previous register value is not read and changed. Instead
324 * it seems the changed bits are marked in the upper 16 bit, while the
325 * changed value gets set in the same offset in the lower 16 bit.
326 * All pin settings seem to be 2 bit wide in both the upper and lower
327 * parts.
328 * @bank: pin bank to change
329 * @pin: pin to change
330 * @mux: new mux function to set
331 */
332 static void rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
333 {
334 struct rockchip_pinctrl *info = bank->drvdata;
335 void __iomem *reg = info->reg_base + info->ctrl->mux_offset;
336 unsigned long flags;
337 u8 bit;
338 u32 data;
339
340 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
341 bank->bank_num, pin, mux);
342
343 /* get basic quadrupel of mux registers and the correct reg inside */
344 reg += bank->bank_num * 0x10;
345 reg += (pin / 8) * 4;
346 bit = (pin % 8) * 2;
347
348 spin_lock_irqsave(&bank->slock, flags);
349
350 data = (3 << (bit + 16));
351 data |= (mux & 3) << bit;
352 writel(data, reg);
353
354 spin_unlock_irqrestore(&bank->slock, flags);
355 }
356
357 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
358 {
359 struct rockchip_pinctrl *info = bank->drvdata;
360 struct rockchip_pin_ctrl *ctrl = info->ctrl;
361 void __iomem *reg;
362 u8 bit;
363
364 /* rk3066b does support any pulls */
365 if (!ctrl->pull_offset)
366 return PIN_CONFIG_BIAS_DISABLE;
367
368 reg = info->reg_base + ctrl->pull_offset;
369
370 if (ctrl->pull_auto) {
371 reg += bank->bank_num * ctrl->pull_bank_stride;
372 reg += (pin_num / 16) * 4;
373 bit = pin_num % 16;
374
375 return !(readl_relaxed(reg) & BIT(bit))
376 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
377 : PIN_CONFIG_BIAS_DISABLE;
378 } else {
379 dev_err(info->dev, "pull support for rk31xx not implemented\n");
380 return -EIO;
381 }
382 }
383
384 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
385 int pin_num, int pull)
386 {
387 struct rockchip_pinctrl *info = bank->drvdata;
388 struct rockchip_pin_ctrl *ctrl = info->ctrl;
389 void __iomem *reg;
390 unsigned long flags;
391 u8 bit;
392 u32 data;
393
394 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
395 bank->bank_num, pin_num, pull);
396
397 /* rk3066b does support any pulls */
398 if (!ctrl->pull_offset)
399 return pull ? -EINVAL : 0;
400
401 reg = info->reg_base + ctrl->pull_offset;
402
403 if (ctrl->pull_auto) {
404 if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
405 pull != PIN_CONFIG_BIAS_DISABLE) {
406 dev_err(info->dev, "only PIN_DEFAULT and DISABLE allowed\n");
407 return -EINVAL;
408 }
409
410 reg += bank->bank_num * ctrl->pull_bank_stride;
411 reg += (pin_num / 16) * 4;
412 bit = pin_num % 16;
413
414 spin_lock_irqsave(&bank->slock, flags);
415
416 data = BIT(bit + 16);
417 if (pull == PIN_CONFIG_BIAS_DISABLE)
418 data |= BIT(bit);
419 writel(data, reg);
420
421 spin_unlock_irqrestore(&bank->slock, flags);
422 } else {
423 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) {
424 dev_err(info->dev, "pull direction (up/down) needs to be specified\n");
425 return -EINVAL;
426 }
427
428 dev_err(info->dev, "pull support for rk31xx not implemented\n");
429 return -EIO;
430 }
431
432 return 0;
433 }
434
435 /*
436 * Pinmux_ops handling
437 */
438
439 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
440 {
441 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
442
443 return info->nfunctions;
444 }
445
446 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
447 unsigned selector)
448 {
449 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
450
451 return info->functions[selector].name;
452 }
453
454 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
455 unsigned selector, const char * const **groups,
456 unsigned * const num_groups)
457 {
458 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
459
460 *groups = info->functions[selector].groups;
461 *num_groups = info->functions[selector].ngroups;
462
463 return 0;
464 }
465
466 static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
467 unsigned group)
468 {
469 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
470 const unsigned int *pins = info->groups[group].pins;
471 const struct rockchip_pin_config *data = info->groups[group].data;
472 struct rockchip_pin_bank *bank;
473 int cnt;
474
475 dev_dbg(info->dev, "enable function %s group %s\n",
476 info->functions[selector].name, info->groups[group].name);
477
478 /*
479 * for each pin in the pin group selected, program the correspoding pin
480 * pin function number in the config register.
481 */
482 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
483 bank = pin_to_bank(info, pins[cnt]);
484 rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
485 data[cnt].func);
486 }
487
488 return 0;
489 }
490
491 static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
492 unsigned selector, unsigned group)
493 {
494 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
495 const unsigned int *pins = info->groups[group].pins;
496 struct rockchip_pin_bank *bank;
497 int cnt;
498
499 dev_dbg(info->dev, "disable function %s group %s\n",
500 info->functions[selector].name, info->groups[group].name);
501
502 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
503 bank = pin_to_bank(info, pins[cnt]);
504 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
505 }
506 }
507
508 /*
509 * The calls to gpio_direction_output() and gpio_direction_input()
510 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
511 * function called from the gpiolib interface).
512 */
513 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
514 struct pinctrl_gpio_range *range,
515 unsigned offset, bool input)
516 {
517 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
518 struct rockchip_pin_bank *bank;
519 struct gpio_chip *chip;
520 int pin;
521 u32 data;
522
523 chip = range->gc;
524 bank = gc_to_pin_bank(chip);
525 pin = offset - chip->base;
526
527 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
528 offset, range->name, pin, input ? "input" : "output");
529
530 rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
531
532 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
533 /* set bit to 1 for output, 0 for input */
534 if (!input)
535 data |= BIT(pin);
536 else
537 data &= ~BIT(pin);
538 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
539
540 return 0;
541 }
542
543 static const struct pinmux_ops rockchip_pmx_ops = {
544 .get_functions_count = rockchip_pmx_get_funcs_count,
545 .get_function_name = rockchip_pmx_get_func_name,
546 .get_function_groups = rockchip_pmx_get_groups,
547 .enable = rockchip_pmx_enable,
548 .disable = rockchip_pmx_disable,
549 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
550 };
551
552 /*
553 * Pinconf_ops handling
554 */
555
556 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
557 enum pin_config_param pull)
558 {
559 /* rk3066b does support any pulls */
560 if (!ctrl->pull_offset)
561 return pull ? false : true;
562
563 if (ctrl->pull_auto) {
564 if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
565 pull != PIN_CONFIG_BIAS_DISABLE)
566 return false;
567 } else {
568 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
569 return false;
570 }
571
572 return true;
573 }
574
575 /* set the pin config settings for a specified pin */
576 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
577 unsigned long config)
578 {
579 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
580 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
581 enum pin_config_param param = pinconf_to_config_param(config);
582 u16 arg = pinconf_to_config_argument(config);
583
584 switch (param) {
585 case PIN_CONFIG_BIAS_DISABLE:
586 return rockchip_set_pull(bank, pin - bank->pin_base, param);
587 break;
588 case PIN_CONFIG_BIAS_PULL_UP:
589 case PIN_CONFIG_BIAS_PULL_DOWN:
590 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
591 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
592 return -ENOTSUPP;
593
594 if (!arg)
595 return -EINVAL;
596
597 return rockchip_set_pull(bank, pin - bank->pin_base, param);
598 break;
599 default:
600 return -ENOTSUPP;
601 break;
602 }
603
604 return 0;
605 }
606
607 /* get the pin config settings for a specified pin */
608 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
609 unsigned long *config)
610 {
611 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
612 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
613 enum pin_config_param param = pinconf_to_config_param(*config);
614
615 switch (param) {
616 case PIN_CONFIG_BIAS_DISABLE:
617 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
618 return -EINVAL;
619
620 *config = 0;
621 break;
622 case PIN_CONFIG_BIAS_PULL_UP:
623 case PIN_CONFIG_BIAS_PULL_DOWN:
624 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
625 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
626 return -ENOTSUPP;
627
628 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
629 return -EINVAL;
630
631 *config = 1;
632 break;
633 default:
634 return -ENOTSUPP;
635 break;
636 }
637
638 return 0;
639 }
640
641 static const struct pinconf_ops rockchip_pinconf_ops = {
642 .pin_config_get = rockchip_pinconf_get,
643 .pin_config_set = rockchip_pinconf_set,
644 };
645
646 static const char *gpio_compat = "rockchip,gpio-bank";
647
648 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
649 struct device_node *np)
650 {
651 struct device_node *child;
652
653 for_each_child_of_node(np, child) {
654 if (of_device_is_compatible(child, gpio_compat))
655 continue;
656
657 info->nfunctions++;
658 info->ngroups += of_get_child_count(child);
659 }
660 }
661
662 static int rockchip_pinctrl_parse_groups(struct device_node *np,
663 struct rockchip_pin_group *grp,
664 struct rockchip_pinctrl *info,
665 u32 index)
666 {
667 struct rockchip_pin_bank *bank;
668 int size;
669 const __be32 *list;
670 int num;
671 int i, j;
672 int ret;
673
674 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
675
676 /* Initialise group */
677 grp->name = np->name;
678
679 /*
680 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
681 * do sanity check and calculate pins number
682 */
683 list = of_get_property(np, "rockchip,pins", &size);
684 /* we do not check return since it's safe node passed down */
685 size /= sizeof(*list);
686 if (!size || size % 4) {
687 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
688 return -EINVAL;
689 }
690
691 grp->npins = size / 4;
692
693 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
694 GFP_KERNEL);
695 grp->data = devm_kzalloc(info->dev, grp->npins *
696 sizeof(struct rockchip_pin_config),
697 GFP_KERNEL);
698 if (!grp->pins || !grp->data)
699 return -ENOMEM;
700
701 for (i = 0, j = 0; i < size; i += 4, j++) {
702 const __be32 *phandle;
703 struct device_node *np_config;
704
705 num = be32_to_cpu(*list++);
706 bank = bank_num_to_bank(info, num);
707 if (IS_ERR(bank))
708 return PTR_ERR(bank);
709
710 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
711 grp->data[j].func = be32_to_cpu(*list++);
712
713 phandle = list++;
714 if (!phandle)
715 return -EINVAL;
716
717 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
718 ret = pinconf_generic_parse_dt_config(np_config,
719 &grp->data[j].configs, &grp->data[j].nconfigs);
720 if (ret)
721 return ret;
722 }
723
724 return 0;
725 }
726
727 static int rockchip_pinctrl_parse_functions(struct device_node *np,
728 struct rockchip_pinctrl *info,
729 u32 index)
730 {
731 struct device_node *child;
732 struct rockchip_pmx_func *func;
733 struct rockchip_pin_group *grp;
734 int ret;
735 static u32 grp_index;
736 u32 i = 0;
737
738 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
739
740 func = &info->functions[index];
741
742 /* Initialise function */
743 func->name = np->name;
744 func->ngroups = of_get_child_count(np);
745 if (func->ngroups <= 0)
746 return 0;
747
748 func->groups = devm_kzalloc(info->dev,
749 func->ngroups * sizeof(char *), GFP_KERNEL);
750 if (!func->groups)
751 return -ENOMEM;
752
753 for_each_child_of_node(np, child) {
754 func->groups[i] = child->name;
755 grp = &info->groups[grp_index++];
756 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
757 if (ret)
758 return ret;
759 }
760
761 return 0;
762 }
763
764 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
765 struct rockchip_pinctrl *info)
766 {
767 struct device *dev = &pdev->dev;
768 struct device_node *np = dev->of_node;
769 struct device_node *child;
770 int ret;
771 int i;
772
773 rockchip_pinctrl_child_count(info, np);
774
775 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
776 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
777
778 info->functions = devm_kzalloc(dev, info->nfunctions *
779 sizeof(struct rockchip_pmx_func),
780 GFP_KERNEL);
781 if (!info->functions) {
782 dev_err(dev, "failed to allocate memory for function list\n");
783 return -EINVAL;
784 }
785
786 info->groups = devm_kzalloc(dev, info->ngroups *
787 sizeof(struct rockchip_pin_group),
788 GFP_KERNEL);
789 if (!info->groups) {
790 dev_err(dev, "failed allocate memory for ping group list\n");
791 return -EINVAL;
792 }
793
794 i = 0;
795
796 for_each_child_of_node(np, child) {
797 if (of_device_is_compatible(child, gpio_compat))
798 continue;
799 ret = rockchip_pinctrl_parse_functions(child, info, i++);
800 if (ret) {
801 dev_err(&pdev->dev, "failed to parse function\n");
802 return ret;
803 }
804 }
805
806 return 0;
807 }
808
809 static int rockchip_pinctrl_register(struct platform_device *pdev,
810 struct rockchip_pinctrl *info)
811 {
812 struct pinctrl_desc *ctrldesc = &info->pctl;
813 struct pinctrl_pin_desc *pindesc, *pdesc;
814 struct rockchip_pin_bank *pin_bank;
815 int pin, bank, ret;
816 int k;
817
818 ctrldesc->name = "rockchip-pinctrl";
819 ctrldesc->owner = THIS_MODULE;
820 ctrldesc->pctlops = &rockchip_pctrl_ops;
821 ctrldesc->pmxops = &rockchip_pmx_ops;
822 ctrldesc->confops = &rockchip_pinconf_ops;
823
824 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
825 info->ctrl->nr_pins, GFP_KERNEL);
826 if (!pindesc) {
827 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
828 return -ENOMEM;
829 }
830 ctrldesc->pins = pindesc;
831 ctrldesc->npins = info->ctrl->nr_pins;
832
833 pdesc = pindesc;
834 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
835 pin_bank = &info->ctrl->pin_banks[bank];
836 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
837 pdesc->number = k;
838 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
839 pin_bank->name, pin);
840 pdesc++;
841 }
842 }
843
844 info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
845 if (!info->pctl_dev) {
846 dev_err(&pdev->dev, "could not register pinctrl driver\n");
847 return -EINVAL;
848 }
849
850 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
851 pin_bank = &info->ctrl->pin_banks[bank];
852 pin_bank->grange.name = pin_bank->name;
853 pin_bank->grange.id = bank;
854 pin_bank->grange.pin_base = pin_bank->pin_base;
855 pin_bank->grange.base = pin_bank->gpio_chip.base;
856 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
857 pin_bank->grange.gc = &pin_bank->gpio_chip;
858 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
859 }
860
861 ret = rockchip_pinctrl_parse_dt(pdev, info);
862 if (ret) {
863 pinctrl_unregister(info->pctl_dev);
864 return ret;
865 }
866
867 return 0;
868 }
869
870 /*
871 * GPIO handling
872 */
873
874 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
875 {
876 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
877 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
878 unsigned long flags;
879 u32 data;
880
881 spin_lock_irqsave(&bank->slock, flags);
882
883 data = readl(reg);
884 data &= ~BIT(offset);
885 if (value)
886 data |= BIT(offset);
887 writel(data, reg);
888
889 spin_unlock_irqrestore(&bank->slock, flags);
890 }
891
892 /*
893 * Returns the level of the pin for input direction and setting of the DR
894 * register for output gpios.
895 */
896 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
897 {
898 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
899 u32 data;
900
901 data = readl(bank->reg_base + GPIO_EXT_PORT);
902 data >>= offset;
903 data &= 1;
904 return data;
905 }
906
907 /*
908 * gpiolib gpio_direction_input callback function. The setting of the pin
909 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
910 * interface.
911 */
912 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
913 {
914 return pinctrl_gpio_direction_input(gc->base + offset);
915 }
916
917 /*
918 * gpiolib gpio_direction_output callback function. The setting of the pin
919 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
920 * interface.
921 */
922 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
923 unsigned offset, int value)
924 {
925 rockchip_gpio_set(gc, offset, value);
926 return pinctrl_gpio_direction_output(gc->base + offset);
927 }
928
929 /*
930 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
931 * and a virtual IRQ, if not already present.
932 */
933 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
934 {
935 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
936 unsigned int virq;
937
938 if (!bank->domain)
939 return -ENXIO;
940
941 virq = irq_create_mapping(bank->domain, offset);
942
943 return (virq) ? : -ENXIO;
944 }
945
946 static const struct gpio_chip rockchip_gpiolib_chip = {
947 .set = rockchip_gpio_set,
948 .get = rockchip_gpio_get,
949 .direction_input = rockchip_gpio_direction_input,
950 .direction_output = rockchip_gpio_direction_output,
951 .to_irq = rockchip_gpio_to_irq,
952 .owner = THIS_MODULE,
953 };
954
955 /*
956 * Interrupt handling
957 */
958
959 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
960 {
961 struct irq_chip *chip = irq_get_chip(irq);
962 struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
963 u32 pend;
964
965 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
966
967 chained_irq_enter(chip, desc);
968
969 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
970
971 while (pend) {
972 unsigned int virq;
973
974 irq = __ffs(pend);
975 pend &= ~BIT(irq);
976 virq = irq_linear_revmap(bank->domain, irq);
977
978 if (!virq) {
979 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
980 continue;
981 }
982
983 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
984
985 generic_handle_irq(virq);
986 }
987
988 chained_irq_exit(chip, desc);
989 }
990
991 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
992 {
993 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
994 struct rockchip_pin_bank *bank = gc->private;
995 u32 mask = BIT(d->hwirq);
996 u32 polarity;
997 u32 level;
998 u32 data;
999
1000 if (type & IRQ_TYPE_EDGE_BOTH)
1001 __irq_set_handler_locked(d->irq, handle_edge_irq);
1002 else
1003 __irq_set_handler_locked(d->irq, handle_level_irq);
1004
1005 irq_gc_lock(gc);
1006
1007 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1008 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1009
1010 switch (type) {
1011 case IRQ_TYPE_EDGE_RISING:
1012 level |= mask;
1013 polarity |= mask;
1014 break;
1015 case IRQ_TYPE_EDGE_FALLING:
1016 level |= mask;
1017 polarity &= ~mask;
1018 break;
1019 case IRQ_TYPE_LEVEL_HIGH:
1020 level &= ~mask;
1021 polarity |= mask;
1022 break;
1023 case IRQ_TYPE_LEVEL_LOW:
1024 level &= ~mask;
1025 polarity &= ~mask;
1026 break;
1027 default:
1028 irq_gc_unlock(gc);
1029 return -EINVAL;
1030 }
1031
1032 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1033 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1034
1035 irq_gc_unlock(gc);
1036
1037 /* make sure the pin is configured as gpio input */
1038 rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1039 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1040 data &= ~mask;
1041 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1042
1043 return 0;
1044 }
1045
1046 static int rockchip_interrupts_register(struct platform_device *pdev,
1047 struct rockchip_pinctrl *info)
1048 {
1049 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1050 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1051 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1052 struct irq_chip_generic *gc;
1053 int ret;
1054 int i;
1055
1056 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1057 if (!bank->valid) {
1058 dev_warn(&pdev->dev, "bank %s is not valid\n",
1059 bank->name);
1060 continue;
1061 }
1062
1063 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1064 &irq_generic_chip_ops, NULL);
1065 if (!bank->domain) {
1066 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1067 bank->name);
1068 continue;
1069 }
1070
1071 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1072 "rockchip_gpio_irq", handle_level_irq,
1073 clr, 0, IRQ_GC_INIT_MASK_CACHE);
1074 if (ret) {
1075 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1076 bank->name);
1077 irq_domain_remove(bank->domain);
1078 continue;
1079 }
1080
1081 gc = irq_get_domain_generic_chip(bank->domain, 0);
1082 gc->reg_base = bank->reg_base;
1083 gc->private = bank;
1084 gc->chip_types[0].regs.mask = GPIO_INTEN;
1085 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1086 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1087 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
1088 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
1089 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1090 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1091
1092 irq_set_handler_data(bank->irq, bank);
1093 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1094 }
1095
1096 return 0;
1097 }
1098
1099 static int rockchip_gpiolib_register(struct platform_device *pdev,
1100 struct rockchip_pinctrl *info)
1101 {
1102 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1103 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1104 struct gpio_chip *gc;
1105 int ret;
1106 int i;
1107
1108 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1109 if (!bank->valid) {
1110 dev_warn(&pdev->dev, "bank %s is not valid\n",
1111 bank->name);
1112 continue;
1113 }
1114
1115 bank->gpio_chip = rockchip_gpiolib_chip;
1116
1117 gc = &bank->gpio_chip;
1118 gc->base = bank->pin_base;
1119 gc->ngpio = bank->nr_pins;
1120 gc->dev = &pdev->dev;
1121 gc->of_node = bank->of_node;
1122 gc->label = bank->name;
1123
1124 ret = gpiochip_add(gc);
1125 if (ret) {
1126 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1127 gc->label, ret);
1128 goto fail;
1129 }
1130 }
1131
1132 rockchip_interrupts_register(pdev, info);
1133
1134 return 0;
1135
1136 fail:
1137 for (--i, --bank; i >= 0; --i, --bank) {
1138 if (!bank->valid)
1139 continue;
1140
1141 if (gpiochip_remove(&bank->gpio_chip))
1142 dev_err(&pdev->dev, "gpio chip %s remove failed\n",
1143 bank->gpio_chip.label);
1144 }
1145 return ret;
1146 }
1147
1148 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1149 struct rockchip_pinctrl *info)
1150 {
1151 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1152 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1153 int ret = 0;
1154 int i;
1155
1156 for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
1157 if (!bank->valid)
1158 continue;
1159
1160 ret = gpiochip_remove(&bank->gpio_chip);
1161 }
1162
1163 if (ret)
1164 dev_err(&pdev->dev, "gpio chip remove failed\n");
1165
1166 return ret;
1167 }
1168
1169 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1170 struct device *dev)
1171 {
1172 struct resource res;
1173
1174 if (of_address_to_resource(bank->of_node, 0, &res)) {
1175 dev_err(dev, "cannot find IO resource for bank\n");
1176 return -ENOENT;
1177 }
1178
1179 bank->reg_base = devm_ioremap_resource(dev, &res);
1180 if (IS_ERR(bank->reg_base))
1181 return PTR_ERR(bank->reg_base);
1182
1183 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1184
1185 bank->clk = of_clk_get(bank->of_node, 0);
1186 if (IS_ERR(bank->clk))
1187 return PTR_ERR(bank->clk);
1188
1189 return clk_prepare_enable(bank->clk);
1190 }
1191
1192 static const struct of_device_id rockchip_pinctrl_dt_match[];
1193
1194 /* retrieve the soc specific data */
1195 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1196 struct rockchip_pinctrl *d,
1197 struct platform_device *pdev)
1198 {
1199 const struct of_device_id *match;
1200 struct device_node *node = pdev->dev.of_node;
1201 struct device_node *np;
1202 struct rockchip_pin_ctrl *ctrl;
1203 struct rockchip_pin_bank *bank;
1204 int i;
1205
1206 match = of_match_node(rockchip_pinctrl_dt_match, node);
1207 ctrl = (struct rockchip_pin_ctrl *)match->data;
1208
1209 for_each_child_of_node(node, np) {
1210 if (!of_find_property(np, "gpio-controller", NULL))
1211 continue;
1212
1213 bank = ctrl->pin_banks;
1214 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1215 if (!strcmp(bank->name, np->name)) {
1216 bank->of_node = np;
1217
1218 if (!rockchip_get_bank_data(bank, &pdev->dev))
1219 bank->valid = true;
1220
1221 break;
1222 }
1223 }
1224 }
1225
1226 bank = ctrl->pin_banks;
1227 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1228 spin_lock_init(&bank->slock);
1229 bank->drvdata = d;
1230 bank->pin_base = ctrl->nr_pins;
1231 ctrl->nr_pins += bank->nr_pins;
1232 }
1233
1234 return ctrl;
1235 }
1236
1237 static int rockchip_pinctrl_probe(struct platform_device *pdev)
1238 {
1239 struct rockchip_pinctrl *info;
1240 struct device *dev = &pdev->dev;
1241 struct rockchip_pin_ctrl *ctrl;
1242 struct resource *res;
1243 int ret;
1244
1245 if (!dev->of_node) {
1246 dev_err(dev, "device tree node not found\n");
1247 return -ENODEV;
1248 }
1249
1250 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
1251 if (!info)
1252 return -ENOMEM;
1253
1254 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
1255 if (!ctrl) {
1256 dev_err(dev, "driver data not available\n");
1257 return -EINVAL;
1258 }
1259 info->ctrl = ctrl;
1260 info->dev = dev;
1261
1262 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1263 info->reg_base = devm_ioremap_resource(&pdev->dev, res);
1264 if (IS_ERR(info->reg_base))
1265 return PTR_ERR(info->reg_base);
1266
1267 ret = rockchip_gpiolib_register(pdev, info);
1268 if (ret)
1269 return ret;
1270
1271 ret = rockchip_pinctrl_register(pdev, info);
1272 if (ret) {
1273 rockchip_gpiolib_unregister(pdev, info);
1274 return ret;
1275 }
1276
1277 platform_set_drvdata(pdev, info);
1278
1279 return 0;
1280 }
1281
1282 static struct rockchip_pin_bank rk2928_pin_banks[] = {
1283 PIN_BANK(0, 32, "gpio0"),
1284 PIN_BANK(1, 32, "gpio1"),
1285 PIN_BANK(2, 32, "gpio2"),
1286 PIN_BANK(3, 32, "gpio3"),
1287 };
1288
1289 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1290 .pin_banks = rk2928_pin_banks,
1291 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
1292 .label = "RK2928-GPIO",
1293 .mux_offset = 0xa8,
1294 .pull_offset = 0x118,
1295 .pull_auto = 1,
1296 .pull_bank_stride = 8,
1297 };
1298
1299 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
1300 PIN_BANK(0, 32, "gpio0"),
1301 PIN_BANK(1, 32, "gpio1"),
1302 PIN_BANK(2, 32, "gpio2"),
1303 PIN_BANK(3, 32, "gpio3"),
1304 PIN_BANK(4, 32, "gpio4"),
1305 PIN_BANK(6, 16, "gpio6"),
1306 };
1307
1308 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
1309 .pin_banks = rk3066a_pin_banks,
1310 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
1311 .label = "RK3066a-GPIO",
1312 .mux_offset = 0xa8,
1313 .pull_offset = 0x118,
1314 .pull_auto = 1,
1315 .pull_bank_stride = 8,
1316 };
1317
1318 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
1319 PIN_BANK(0, 32, "gpio0"),
1320 PIN_BANK(1, 32, "gpio1"),
1321 PIN_BANK(2, 32, "gpio2"),
1322 PIN_BANK(3, 32, "gpio3"),
1323 };
1324
1325 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
1326 .pin_banks = rk3066b_pin_banks,
1327 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
1328 .label = "RK3066b-GPIO",
1329 .mux_offset = 0x60,
1330 .pull_offset = -EINVAL,
1331 };
1332
1333 static struct rockchip_pin_bank rk3188_pin_banks[] = {
1334 PIN_BANK(0, 32, "gpio0"),
1335 PIN_BANK(1, 32, "gpio1"),
1336 PIN_BANK(2, 32, "gpio2"),
1337 PIN_BANK(3, 32, "gpio3"),
1338 };
1339
1340 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
1341 .pin_banks = rk3188_pin_banks,
1342 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
1343 .label = "RK3188-GPIO",
1344 .mux_offset = 0x68,
1345 .pull_offset = 0x164,
1346 .pull_bank_stride = 16,
1347 };
1348
1349 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
1350 { .compatible = "rockchip,rk2928-pinctrl",
1351 .data = (void *)&rk2928_pin_ctrl },
1352 { .compatible = "rockchip,rk3066a-pinctrl",
1353 .data = (void *)&rk3066a_pin_ctrl },
1354 { .compatible = "rockchip,rk3066b-pinctrl",
1355 .data = (void *)&rk3066b_pin_ctrl },
1356 { .compatible = "rockchip,rk3188-pinctrl",
1357 .data = (void *)&rk3188_pin_ctrl },
1358 {},
1359 };
1360 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
1361
1362 static struct platform_driver rockchip_pinctrl_driver = {
1363 .probe = rockchip_pinctrl_probe,
1364 .driver = {
1365 .name = "rockchip-pinctrl",
1366 .owner = THIS_MODULE,
1367 .of_match_table = rockchip_pinctrl_dt_match,
1368 },
1369 };
1370
1371 static int __init rockchip_pinctrl_drv_register(void)
1372 {
1373 return platform_driver_register(&rockchip_pinctrl_driver);
1374 }
1375 postcore_initcall(rockchip_pinctrl_drv_register);
1376
1377 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
1378 MODULE_DESCRIPTION("Rockchip pinctrl driver");
1379 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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