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pinctrl: single: Prepare for supporting SoC specific features
[deliverable/linux.git] / drivers / pinctrl / pinctrl-single.c
1 /*
2 * Generic device tree based pinctrl driver for one register per pin
3 * type pinmux controllers
4 *
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/io.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/list.h>
18
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/of_address.h>
22
23 #include <linux/pinctrl/pinctrl.h>
24 #include <linux/pinctrl/pinmux.h>
25 #include <linux/pinctrl/pinconf-generic.h>
26
27 #include "core.h"
28 #include "pinconf.h"
29
30 #define DRIVER_NAME "pinctrl-single"
31 #define PCS_MUX_PINS_NAME "pinctrl-single,pins"
32 #define PCS_MUX_BITS_NAME "pinctrl-single,bits"
33 #define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 3)
34 #define PCS_OFF_DISABLED ~0U
35
36 /**
37 * struct pcs_pingroup - pingroups for a function
38 * @np: pingroup device node pointer
39 * @name: pingroup name
40 * @gpins: array of the pins in the group
41 * @ngpins: number of pins in the group
42 * @node: list node
43 */
44 struct pcs_pingroup {
45 struct device_node *np;
46 const char *name;
47 int *gpins;
48 int ngpins;
49 struct list_head node;
50 };
51
52 /**
53 * struct pcs_func_vals - mux function register offset and value pair
54 * @reg: register virtual address
55 * @val: register value
56 */
57 struct pcs_func_vals {
58 void __iomem *reg;
59 unsigned val;
60 unsigned mask;
61 };
62
63 /**
64 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
65 * and value, enable, disable, mask
66 * @param: config parameter
67 * @val: user input bits in the pinconf register
68 * @enable: enable bits in the pinconf register
69 * @disable: disable bits in the pinconf register
70 * @mask: mask bits in the register value
71 */
72 struct pcs_conf_vals {
73 enum pin_config_param param;
74 unsigned val;
75 unsigned enable;
76 unsigned disable;
77 unsigned mask;
78 };
79
80 /**
81 * struct pcs_conf_type - pinconf property name, pinconf param pair
82 * @name: property name in DTS file
83 * @param: config parameter
84 */
85 struct pcs_conf_type {
86 const char *name;
87 enum pin_config_param param;
88 };
89
90 /**
91 * struct pcs_function - pinctrl function
92 * @name: pinctrl function name
93 * @vals: register and vals array
94 * @nvals: number of entries in vals array
95 * @pgnames: array of pingroup names the function uses
96 * @npgnames: number of pingroup names the function uses
97 * @node: list node
98 */
99 struct pcs_function {
100 const char *name;
101 struct pcs_func_vals *vals;
102 unsigned nvals;
103 const char **pgnames;
104 int npgnames;
105 struct pcs_conf_vals *conf;
106 int nconfs;
107 struct list_head node;
108 };
109
110 /**
111 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
112 * @offset: offset base of pins
113 * @npins: number pins with the same mux value of gpio function
114 * @gpiofunc: mux value of gpio function
115 * @node: list node
116 */
117 struct pcs_gpiofunc_range {
118 unsigned offset;
119 unsigned npins;
120 unsigned gpiofunc;
121 struct list_head node;
122 };
123
124 /**
125 * struct pcs_data - wrapper for data needed by pinctrl framework
126 * @pa: pindesc array
127 * @cur: index to current element
128 *
129 * REVISIT: We should be able to drop this eventually by adding
130 * support for registering pins individually in the pinctrl
131 * framework for those drivers that don't need a static array.
132 */
133 struct pcs_data {
134 struct pinctrl_pin_desc *pa;
135 int cur;
136 };
137
138 /**
139 * struct pcs_name - register name for a pin
140 * @name: name of the pinctrl register
141 *
142 * REVISIT: We may want to make names optional in the pinctrl
143 * framework as some drivers may not care about pin names to
144 * avoid kernel bloat. The pin names can be deciphered by user
145 * space tools using debugfs based on the register address and
146 * SoC packaging information.
147 */
148 struct pcs_name {
149 char name[PCS_REG_NAME_LEN];
150 };
151
152 /**
153 * struct pcs_soc_data - SoC specific settings
154 * @flags: initial SoC specific PCS_FEAT_xxx values
155 */
156 struct pcs_soc_data {
157 unsigned flags;
158 };
159
160 /**
161 * struct pcs_device - pinctrl device instance
162 * @res: resources
163 * @base: virtual address of the controller
164 * @size: size of the ioremapped area
165 * @dev: device entry
166 * @pctl: pin controller device
167 * @flags: mask of PCS_FEAT_xxx values
168 * @mutex: mutex protecting the lists
169 * @width: bits per mux register
170 * @fmask: function register mask
171 * @fshift: function register shift
172 * @foff: value to turn mux off
173 * @fmax: max number of functions in fmask
174 * @bits_per_pin:number of bits per pin
175 * @names: array of register names for pins
176 * @pins: physical pins on the SoC
177 * @pgtree: pingroup index radix tree
178 * @ftree: function index radix tree
179 * @pingroups: list of pingroups
180 * @functions: list of functions
181 * @gpiofuncs: list of gpio functions
182 * @ngroups: number of pingroups
183 * @nfuncs: number of functions
184 * @desc: pin controller descriptor
185 * @read: register read function to use
186 * @write: register write function to use
187 */
188 struct pcs_device {
189 struct resource *res;
190 void __iomem *base;
191 unsigned size;
192 struct device *dev;
193 struct pinctrl_dev *pctl;
194 unsigned flags;
195 #define PCS_FEAT_PINCONF (1 << 0)
196 struct mutex mutex;
197 unsigned width;
198 unsigned fmask;
199 unsigned fshift;
200 unsigned foff;
201 unsigned fmax;
202 bool bits_per_mux;
203 unsigned bits_per_pin;
204 struct pcs_name *names;
205 struct pcs_data pins;
206 struct radix_tree_root pgtree;
207 struct radix_tree_root ftree;
208 struct list_head pingroups;
209 struct list_head functions;
210 struct list_head gpiofuncs;
211 unsigned ngroups;
212 unsigned nfuncs;
213 struct pinctrl_desc desc;
214 unsigned (*read)(void __iomem *reg);
215 void (*write)(unsigned val, void __iomem *reg);
216 };
217
218 #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
219
220 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
221 unsigned long *config);
222 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
223 unsigned long *configs, unsigned num_configs);
224
225 static enum pin_config_param pcs_bias[] = {
226 PIN_CONFIG_BIAS_PULL_DOWN,
227 PIN_CONFIG_BIAS_PULL_UP,
228 };
229
230 /*
231 * REVISIT: Reads and writes could eventually use regmap or something
232 * generic. But at least on omaps, some mux registers are performance
233 * critical as they may need to be remuxed every time before and after
234 * idle. Adding tests for register access width for every read and
235 * write like regmap is doing is not desired, and caching the registers
236 * does not help in this case.
237 */
238
239 static unsigned __maybe_unused pcs_readb(void __iomem *reg)
240 {
241 return readb(reg);
242 }
243
244 static unsigned __maybe_unused pcs_readw(void __iomem *reg)
245 {
246 return readw(reg);
247 }
248
249 static unsigned __maybe_unused pcs_readl(void __iomem *reg)
250 {
251 return readl(reg);
252 }
253
254 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
255 {
256 writeb(val, reg);
257 }
258
259 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
260 {
261 writew(val, reg);
262 }
263
264 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
265 {
266 writel(val, reg);
267 }
268
269 static int pcs_get_groups_count(struct pinctrl_dev *pctldev)
270 {
271 struct pcs_device *pcs;
272
273 pcs = pinctrl_dev_get_drvdata(pctldev);
274
275 return pcs->ngroups;
276 }
277
278 static const char *pcs_get_group_name(struct pinctrl_dev *pctldev,
279 unsigned gselector)
280 {
281 struct pcs_device *pcs;
282 struct pcs_pingroup *group;
283
284 pcs = pinctrl_dev_get_drvdata(pctldev);
285 group = radix_tree_lookup(&pcs->pgtree, gselector);
286 if (!group) {
287 dev_err(pcs->dev, "%s could not find pingroup%i\n",
288 __func__, gselector);
289 return NULL;
290 }
291
292 return group->name;
293 }
294
295 static int pcs_get_group_pins(struct pinctrl_dev *pctldev,
296 unsigned gselector,
297 const unsigned **pins,
298 unsigned *npins)
299 {
300 struct pcs_device *pcs;
301 struct pcs_pingroup *group;
302
303 pcs = pinctrl_dev_get_drvdata(pctldev);
304 group = radix_tree_lookup(&pcs->pgtree, gselector);
305 if (!group) {
306 dev_err(pcs->dev, "%s could not find pingroup%i\n",
307 __func__, gselector);
308 return -EINVAL;
309 }
310
311 *pins = group->gpins;
312 *npins = group->ngpins;
313
314 return 0;
315 }
316
317 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
318 struct seq_file *s,
319 unsigned pin)
320 {
321 struct pcs_device *pcs;
322 unsigned val, mux_bytes;
323
324 pcs = pinctrl_dev_get_drvdata(pctldev);
325
326 mux_bytes = pcs->width / BITS_PER_BYTE;
327 val = pcs->read(pcs->base + pin * mux_bytes);
328
329 seq_printf(s, "%08x %s " , val, DRIVER_NAME);
330 }
331
332 static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
333 struct pinctrl_map *map, unsigned num_maps)
334 {
335 struct pcs_device *pcs;
336
337 pcs = pinctrl_dev_get_drvdata(pctldev);
338 devm_kfree(pcs->dev, map);
339 }
340
341 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
342 struct device_node *np_config,
343 struct pinctrl_map **map, unsigned *num_maps);
344
345 static const struct pinctrl_ops pcs_pinctrl_ops = {
346 .get_groups_count = pcs_get_groups_count,
347 .get_group_name = pcs_get_group_name,
348 .get_group_pins = pcs_get_group_pins,
349 .pin_dbg_show = pcs_pin_dbg_show,
350 .dt_node_to_map = pcs_dt_node_to_map,
351 .dt_free_map = pcs_dt_free_map,
352 };
353
354 static int pcs_get_functions_count(struct pinctrl_dev *pctldev)
355 {
356 struct pcs_device *pcs;
357
358 pcs = pinctrl_dev_get_drvdata(pctldev);
359
360 return pcs->nfuncs;
361 }
362
363 static const char *pcs_get_function_name(struct pinctrl_dev *pctldev,
364 unsigned fselector)
365 {
366 struct pcs_device *pcs;
367 struct pcs_function *func;
368
369 pcs = pinctrl_dev_get_drvdata(pctldev);
370 func = radix_tree_lookup(&pcs->ftree, fselector);
371 if (!func) {
372 dev_err(pcs->dev, "%s could not find function%i\n",
373 __func__, fselector);
374 return NULL;
375 }
376
377 return func->name;
378 }
379
380 static int pcs_get_function_groups(struct pinctrl_dev *pctldev,
381 unsigned fselector,
382 const char * const **groups,
383 unsigned * const ngroups)
384 {
385 struct pcs_device *pcs;
386 struct pcs_function *func;
387
388 pcs = pinctrl_dev_get_drvdata(pctldev);
389 func = radix_tree_lookup(&pcs->ftree, fselector);
390 if (!func) {
391 dev_err(pcs->dev, "%s could not find function%i\n",
392 __func__, fselector);
393 return -EINVAL;
394 }
395 *groups = func->pgnames;
396 *ngroups = func->npgnames;
397
398 return 0;
399 }
400
401 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
402 struct pcs_function **func)
403 {
404 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
405 struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
406 const struct pinctrl_setting_mux *setting;
407 unsigned fselector;
408
409 /* If pin is not described in DTS & enabled, mux_setting is NULL. */
410 setting = pdesc->mux_setting;
411 if (!setting)
412 return -ENOTSUPP;
413 fselector = setting->func;
414 *func = radix_tree_lookup(&pcs->ftree, fselector);
415 if (!(*func)) {
416 dev_err(pcs->dev, "%s could not find function%i\n",
417 __func__, fselector);
418 return -ENOTSUPP;
419 }
420 return 0;
421 }
422
423 static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
424 unsigned group)
425 {
426 struct pcs_device *pcs;
427 struct pcs_function *func;
428 int i;
429
430 pcs = pinctrl_dev_get_drvdata(pctldev);
431 /* If function mask is null, needn't enable it. */
432 if (!pcs->fmask)
433 return 0;
434 func = radix_tree_lookup(&pcs->ftree, fselector);
435 if (!func)
436 return -EINVAL;
437
438 dev_dbg(pcs->dev, "enabling %s function%i\n",
439 func->name, fselector);
440
441 for (i = 0; i < func->nvals; i++) {
442 struct pcs_func_vals *vals;
443 unsigned val, mask;
444
445 vals = &func->vals[i];
446 val = pcs->read(vals->reg);
447
448 if (pcs->bits_per_mux)
449 mask = vals->mask;
450 else
451 mask = pcs->fmask;
452
453 val &= ~mask;
454 val |= (vals->val & mask);
455 pcs->write(val, vals->reg);
456 }
457
458 return 0;
459 }
460
461 static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector,
462 unsigned group)
463 {
464 struct pcs_device *pcs;
465 struct pcs_function *func;
466 int i;
467
468 pcs = pinctrl_dev_get_drvdata(pctldev);
469 /* If function mask is null, needn't disable it. */
470 if (!pcs->fmask)
471 return;
472
473 func = radix_tree_lookup(&pcs->ftree, fselector);
474 if (!func) {
475 dev_err(pcs->dev, "%s could not find function%i\n",
476 __func__, fselector);
477 return;
478 }
479
480 /*
481 * Ignore disable if function-off is not specified. Some hardware
482 * does not have clearly defined disable function. For pin specific
483 * off modes, you can use alternate named states as described in
484 * pinctrl-bindings.txt.
485 */
486 if (pcs->foff == PCS_OFF_DISABLED) {
487 dev_dbg(pcs->dev, "ignoring disable for %s function%i\n",
488 func->name, fselector);
489 return;
490 }
491
492 dev_dbg(pcs->dev, "disabling function%i %s\n",
493 fselector, func->name);
494
495 for (i = 0; i < func->nvals; i++) {
496 struct pcs_func_vals *vals;
497 unsigned val;
498
499 vals = &func->vals[i];
500 val = pcs->read(vals->reg);
501 val &= ~pcs->fmask;
502 val |= pcs->foff << pcs->fshift;
503 pcs->write(val, vals->reg);
504 }
505 }
506
507 static int pcs_request_gpio(struct pinctrl_dev *pctldev,
508 struct pinctrl_gpio_range *range, unsigned pin)
509 {
510 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
511 struct pcs_gpiofunc_range *frange = NULL;
512 struct list_head *pos, *tmp;
513 int mux_bytes = 0;
514 unsigned data;
515
516 /* If function mask is null, return directly. */
517 if (!pcs->fmask)
518 return -ENOTSUPP;
519
520 list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
521 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
522 if (pin >= frange->offset + frange->npins
523 || pin < frange->offset)
524 continue;
525 mux_bytes = pcs->width / BITS_PER_BYTE;
526 data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask;
527 data |= frange->gpiofunc;
528 pcs->write(data, pcs->base + pin * mux_bytes);
529 break;
530 }
531 return 0;
532 }
533
534 static const struct pinmux_ops pcs_pinmux_ops = {
535 .get_functions_count = pcs_get_functions_count,
536 .get_function_name = pcs_get_function_name,
537 .get_function_groups = pcs_get_function_groups,
538 .enable = pcs_enable,
539 .disable = pcs_disable,
540 .gpio_request_enable = pcs_request_gpio,
541 };
542
543 /* Clear BIAS value */
544 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
545 {
546 unsigned long config;
547 int i;
548 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
549 config = pinconf_to_config_packed(pcs_bias[i], 0);
550 pcs_pinconf_set(pctldev, pin, &config, 1);
551 }
552 }
553
554 /*
555 * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
556 * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
557 */
558 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
559 {
560 unsigned long config;
561 int i;
562
563 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
564 config = pinconf_to_config_packed(pcs_bias[i], 0);
565 if (!pcs_pinconf_get(pctldev, pin, &config))
566 goto out;
567 }
568 return true;
569 out:
570 return false;
571 }
572
573 static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
574 unsigned pin, unsigned long *config)
575 {
576 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
577 struct pcs_function *func;
578 enum pin_config_param param;
579 unsigned offset = 0, data = 0, i, j, ret;
580
581 ret = pcs_get_function(pctldev, pin, &func);
582 if (ret)
583 return ret;
584
585 for (i = 0; i < func->nconfs; i++) {
586 param = pinconf_to_config_param(*config);
587 if (param == PIN_CONFIG_BIAS_DISABLE) {
588 if (pcs_pinconf_bias_disable(pctldev, pin)) {
589 *config = 0;
590 return 0;
591 } else {
592 return -ENOTSUPP;
593 }
594 } else if (param != func->conf[i].param) {
595 continue;
596 }
597
598 offset = pin * (pcs->width / BITS_PER_BYTE);
599 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
600 switch (func->conf[i].param) {
601 /* 4 parameters */
602 case PIN_CONFIG_BIAS_PULL_DOWN:
603 case PIN_CONFIG_BIAS_PULL_UP:
604 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
605 if ((data != func->conf[i].enable) ||
606 (data == func->conf[i].disable))
607 return -ENOTSUPP;
608 *config = 0;
609 break;
610 /* 2 parameters */
611 case PIN_CONFIG_INPUT_SCHMITT:
612 for (j = 0; j < func->nconfs; j++) {
613 switch (func->conf[j].param) {
614 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
615 if (data != func->conf[j].enable)
616 return -ENOTSUPP;
617 break;
618 default:
619 break;
620 }
621 }
622 *config = data;
623 break;
624 case PIN_CONFIG_DRIVE_STRENGTH:
625 case PIN_CONFIG_SLEW_RATE:
626 default:
627 *config = data;
628 break;
629 }
630 return 0;
631 }
632 return -ENOTSUPP;
633 }
634
635 static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
636 unsigned pin, unsigned long *configs,
637 unsigned num_configs)
638 {
639 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
640 struct pcs_function *func;
641 unsigned offset = 0, shift = 0, i, data, ret;
642 u16 arg;
643 int j;
644
645 ret = pcs_get_function(pctldev, pin, &func);
646 if (ret)
647 return ret;
648
649 for (j = 0; j < num_configs; j++) {
650 for (i = 0; i < func->nconfs; i++) {
651 if (pinconf_to_config_param(configs[j])
652 != func->conf[i].param)
653 continue;
654
655 offset = pin * (pcs->width / BITS_PER_BYTE);
656 data = pcs->read(pcs->base + offset);
657 arg = pinconf_to_config_argument(configs[j]);
658 switch (func->conf[i].param) {
659 /* 2 parameters */
660 case PIN_CONFIG_INPUT_SCHMITT:
661 case PIN_CONFIG_DRIVE_STRENGTH:
662 case PIN_CONFIG_SLEW_RATE:
663 shift = ffs(func->conf[i].mask) - 1;
664 data &= ~func->conf[i].mask;
665 data |= (arg << shift) & func->conf[i].mask;
666 break;
667 /* 4 parameters */
668 case PIN_CONFIG_BIAS_DISABLE:
669 pcs_pinconf_clear_bias(pctldev, pin);
670 break;
671 case PIN_CONFIG_BIAS_PULL_DOWN:
672 case PIN_CONFIG_BIAS_PULL_UP:
673 if (arg)
674 pcs_pinconf_clear_bias(pctldev, pin);
675 /* fall through */
676 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
677 data &= ~func->conf[i].mask;
678 if (arg)
679 data |= func->conf[i].enable;
680 else
681 data |= func->conf[i].disable;
682 break;
683 default:
684 return -ENOTSUPP;
685 }
686 pcs->write(data, pcs->base + offset);
687
688 break;
689 }
690 if (i >= func->nconfs)
691 return -ENOTSUPP;
692 } /* for each config */
693
694 return 0;
695 }
696
697 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
698 unsigned group, unsigned long *config)
699 {
700 const unsigned *pins;
701 unsigned npins, old = 0;
702 int i, ret;
703
704 ret = pcs_get_group_pins(pctldev, group, &pins, &npins);
705 if (ret)
706 return ret;
707 for (i = 0; i < npins; i++) {
708 if (pcs_pinconf_get(pctldev, pins[i], config))
709 return -ENOTSUPP;
710 /* configs do not match between two pins */
711 if (i && (old != *config))
712 return -ENOTSUPP;
713 old = *config;
714 }
715 return 0;
716 }
717
718 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
719 unsigned group, unsigned long *configs,
720 unsigned num_configs)
721 {
722 const unsigned *pins;
723 unsigned npins;
724 int i, ret;
725
726 ret = pcs_get_group_pins(pctldev, group, &pins, &npins);
727 if (ret)
728 return ret;
729 for (i = 0; i < npins; i++) {
730 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
731 return -ENOTSUPP;
732 }
733 return 0;
734 }
735
736 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
737 struct seq_file *s, unsigned pin)
738 {
739 }
740
741 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
742 struct seq_file *s, unsigned selector)
743 {
744 }
745
746 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
747 struct seq_file *s,
748 unsigned long config)
749 {
750 pinconf_generic_dump_config(pctldev, s, config);
751 }
752
753 static const struct pinconf_ops pcs_pinconf_ops = {
754 .pin_config_get = pcs_pinconf_get,
755 .pin_config_set = pcs_pinconf_set,
756 .pin_config_group_get = pcs_pinconf_group_get,
757 .pin_config_group_set = pcs_pinconf_group_set,
758 .pin_config_dbg_show = pcs_pinconf_dbg_show,
759 .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
760 .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
761 .is_generic = true,
762 };
763
764 /**
765 * pcs_add_pin() - add a pin to the static per controller pin array
766 * @pcs: pcs driver instance
767 * @offset: register offset from base
768 */
769 static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
770 unsigned pin_pos)
771 {
772 struct pinctrl_pin_desc *pin;
773 struct pcs_name *pn;
774 int i;
775
776 i = pcs->pins.cur;
777 if (i >= pcs->desc.npins) {
778 dev_err(pcs->dev, "too many pins, max %i\n",
779 pcs->desc.npins);
780 return -ENOMEM;
781 }
782
783 pin = &pcs->pins.pa[i];
784 pn = &pcs->names[i];
785 sprintf(pn->name, "%lx.%d",
786 (unsigned long)pcs->res->start + offset, pin_pos);
787 pin->name = pn->name;
788 pin->number = i;
789 pcs->pins.cur++;
790
791 return i;
792 }
793
794 /**
795 * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
796 * @pcs: pcs driver instance
797 *
798 * In case of errors, resources are freed in pcs_free_resources.
799 *
800 * If your hardware needs holes in the address space, then just set
801 * up multiple driver instances.
802 */
803 static int pcs_allocate_pin_table(struct pcs_device *pcs)
804 {
805 int mux_bytes, nr_pins, i;
806 int num_pins_in_register = 0;
807
808 mux_bytes = pcs->width / BITS_PER_BYTE;
809
810 if (pcs->bits_per_mux) {
811 pcs->bits_per_pin = fls(pcs->fmask);
812 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
813 num_pins_in_register = pcs->width / pcs->bits_per_pin;
814 } else {
815 nr_pins = pcs->size / mux_bytes;
816 }
817
818 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
819 pcs->pins.pa = devm_kzalloc(pcs->dev,
820 sizeof(*pcs->pins.pa) * nr_pins,
821 GFP_KERNEL);
822 if (!pcs->pins.pa)
823 return -ENOMEM;
824
825 pcs->names = devm_kzalloc(pcs->dev,
826 sizeof(struct pcs_name) * nr_pins,
827 GFP_KERNEL);
828 if (!pcs->names)
829 return -ENOMEM;
830
831 pcs->desc.pins = pcs->pins.pa;
832 pcs->desc.npins = nr_pins;
833
834 for (i = 0; i < pcs->desc.npins; i++) {
835 unsigned offset;
836 int res;
837 int byte_num;
838 int pin_pos = 0;
839
840 if (pcs->bits_per_mux) {
841 byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
842 offset = (byte_num / mux_bytes) * mux_bytes;
843 pin_pos = i % num_pins_in_register;
844 } else {
845 offset = i * mux_bytes;
846 }
847 res = pcs_add_pin(pcs, offset, pin_pos);
848 if (res < 0) {
849 dev_err(pcs->dev, "error adding pins: %i\n", res);
850 return res;
851 }
852 }
853
854 return 0;
855 }
856
857 /**
858 * pcs_add_function() - adds a new function to the function list
859 * @pcs: pcs driver instance
860 * @np: device node of the mux entry
861 * @name: name of the function
862 * @vals: array of mux register value pairs used by the function
863 * @nvals: number of mux register value pairs
864 * @pgnames: array of pingroup names for the function
865 * @npgnames: number of pingroup names
866 */
867 static struct pcs_function *pcs_add_function(struct pcs_device *pcs,
868 struct device_node *np,
869 const char *name,
870 struct pcs_func_vals *vals,
871 unsigned nvals,
872 const char **pgnames,
873 unsigned npgnames)
874 {
875 struct pcs_function *function;
876
877 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
878 if (!function)
879 return NULL;
880
881 function->name = name;
882 function->vals = vals;
883 function->nvals = nvals;
884 function->pgnames = pgnames;
885 function->npgnames = npgnames;
886
887 mutex_lock(&pcs->mutex);
888 list_add_tail(&function->node, &pcs->functions);
889 radix_tree_insert(&pcs->ftree, pcs->nfuncs, function);
890 pcs->nfuncs++;
891 mutex_unlock(&pcs->mutex);
892
893 return function;
894 }
895
896 static void pcs_remove_function(struct pcs_device *pcs,
897 struct pcs_function *function)
898 {
899 int i;
900
901 mutex_lock(&pcs->mutex);
902 for (i = 0; i < pcs->nfuncs; i++) {
903 struct pcs_function *found;
904
905 found = radix_tree_lookup(&pcs->ftree, i);
906 if (found == function)
907 radix_tree_delete(&pcs->ftree, i);
908 }
909 list_del(&function->node);
910 mutex_unlock(&pcs->mutex);
911 }
912
913 /**
914 * pcs_add_pingroup() - add a pingroup to the pingroup list
915 * @pcs: pcs driver instance
916 * @np: device node of the mux entry
917 * @name: name of the pingroup
918 * @gpins: array of the pins that belong to the group
919 * @ngpins: number of pins in the group
920 */
921 static int pcs_add_pingroup(struct pcs_device *pcs,
922 struct device_node *np,
923 const char *name,
924 int *gpins,
925 int ngpins)
926 {
927 struct pcs_pingroup *pingroup;
928
929 pingroup = devm_kzalloc(pcs->dev, sizeof(*pingroup), GFP_KERNEL);
930 if (!pingroup)
931 return -ENOMEM;
932
933 pingroup->name = name;
934 pingroup->np = np;
935 pingroup->gpins = gpins;
936 pingroup->ngpins = ngpins;
937
938 mutex_lock(&pcs->mutex);
939 list_add_tail(&pingroup->node, &pcs->pingroups);
940 radix_tree_insert(&pcs->pgtree, pcs->ngroups, pingroup);
941 pcs->ngroups++;
942 mutex_unlock(&pcs->mutex);
943
944 return 0;
945 }
946
947 /**
948 * pcs_get_pin_by_offset() - get a pin index based on the register offset
949 * @pcs: pcs driver instance
950 * @offset: register offset from the base
951 *
952 * Note that this is OK as long as the pins are in a static array.
953 */
954 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
955 {
956 unsigned index;
957
958 if (offset >= pcs->size) {
959 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
960 offset, pcs->size);
961 return -EINVAL;
962 }
963
964 if (pcs->bits_per_mux)
965 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
966 else
967 index = offset / (pcs->width / BITS_PER_BYTE);
968
969 return index;
970 }
971
972 /*
973 * check whether data matches enable bits or disable bits
974 * Return value: 1 for matching enable bits, 0 for matching disable bits,
975 * and negative value for matching failure.
976 */
977 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
978 {
979 int ret = -EINVAL;
980
981 if (data == enable)
982 ret = 1;
983 else if (data == disable)
984 ret = 0;
985 return ret;
986 }
987
988 static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
989 unsigned value, unsigned enable, unsigned disable,
990 unsigned mask)
991 {
992 (*conf)->param = param;
993 (*conf)->val = value;
994 (*conf)->enable = enable;
995 (*conf)->disable = disable;
996 (*conf)->mask = mask;
997 (*conf)++;
998 }
999
1000 static void add_setting(unsigned long **setting, enum pin_config_param param,
1001 unsigned arg)
1002 {
1003 **setting = pinconf_to_config_packed(param, arg);
1004 (*setting)++;
1005 }
1006
1007 /* add pinconf setting with 2 parameters */
1008 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
1009 const char *name, enum pin_config_param param,
1010 struct pcs_conf_vals **conf, unsigned long **settings)
1011 {
1012 unsigned value[2], shift;
1013 int ret;
1014
1015 ret = of_property_read_u32_array(np, name, value, 2);
1016 if (ret)
1017 return;
1018 /* set value & mask */
1019 value[0] &= value[1];
1020 shift = ffs(value[1]) - 1;
1021 /* skip enable & disable */
1022 add_config(conf, param, value[0], 0, 0, value[1]);
1023 add_setting(settings, param, value[0] >> shift);
1024 }
1025
1026 /* add pinconf setting with 4 parameters */
1027 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
1028 const char *name, enum pin_config_param param,
1029 struct pcs_conf_vals **conf, unsigned long **settings)
1030 {
1031 unsigned value[4];
1032 int ret;
1033
1034 /* value to set, enable, disable, mask */
1035 ret = of_property_read_u32_array(np, name, value, 4);
1036 if (ret)
1037 return;
1038 if (!value[3]) {
1039 dev_err(pcs->dev, "mask field of the property can't be 0\n");
1040 return;
1041 }
1042 value[0] &= value[3];
1043 value[1] &= value[3];
1044 value[2] &= value[3];
1045 ret = pcs_config_match(value[0], value[1], value[2]);
1046 if (ret < 0)
1047 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
1048 add_config(conf, param, value[0], value[1], value[2], value[3]);
1049 add_setting(settings, param, ret);
1050 }
1051
1052 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
1053 struct pcs_function *func,
1054 struct pinctrl_map **map)
1055
1056 {
1057 struct pinctrl_map *m = *map;
1058 int i = 0, nconfs = 0;
1059 unsigned long *settings = NULL, *s = NULL;
1060 struct pcs_conf_vals *conf = NULL;
1061 struct pcs_conf_type prop2[] = {
1062 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
1063 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
1064 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
1065 };
1066 struct pcs_conf_type prop4[] = {
1067 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
1068 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
1069 { "pinctrl-single,input-schmitt-enable",
1070 PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
1071 };
1072
1073 /* If pinconf isn't supported, don't parse properties in below. */
1074 if (!PCS_HAS_PINCONF)
1075 return 0;
1076
1077 /* cacluate how much properties are supported in current node */
1078 for (i = 0; i < ARRAY_SIZE(prop2); i++) {
1079 if (of_find_property(np, prop2[i].name, NULL))
1080 nconfs++;
1081 }
1082 for (i = 0; i < ARRAY_SIZE(prop4); i++) {
1083 if (of_find_property(np, prop4[i].name, NULL))
1084 nconfs++;
1085 }
1086 if (!nconfs)
1087 return 0;
1088
1089 func->conf = devm_kzalloc(pcs->dev,
1090 sizeof(struct pcs_conf_vals) * nconfs,
1091 GFP_KERNEL);
1092 if (!func->conf)
1093 return -ENOMEM;
1094 func->nconfs = nconfs;
1095 conf = &(func->conf[0]);
1096 m++;
1097 settings = devm_kzalloc(pcs->dev, sizeof(unsigned long) * nconfs,
1098 GFP_KERNEL);
1099 if (!settings)
1100 return -ENOMEM;
1101 s = &settings[0];
1102
1103 for (i = 0; i < ARRAY_SIZE(prop2); i++)
1104 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
1105 &conf, &s);
1106 for (i = 0; i < ARRAY_SIZE(prop4); i++)
1107 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
1108 &conf, &s);
1109 m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
1110 m->data.configs.group_or_pin = np->name;
1111 m->data.configs.configs = settings;
1112 m->data.configs.num_configs = nconfs;
1113 return 0;
1114 }
1115
1116 static void pcs_free_pingroups(struct pcs_device *pcs);
1117
1118 /**
1119 * smux_parse_one_pinctrl_entry() - parses a device tree mux entry
1120 * @pcs: pinctrl driver instance
1121 * @np: device node of the mux entry
1122 * @map: map entry
1123 * @num_maps: number of map
1124 * @pgnames: pingroup names
1125 *
1126 * Note that this binding currently supports only sets of one register + value.
1127 *
1128 * Also note that this driver tries to avoid understanding pin and function
1129 * names because of the extra bloat they would cause especially in the case of
1130 * a large number of pins. This driver just sets what is specified for the board
1131 * in the .dts file. Further user space debugging tools can be developed to
1132 * decipher the pin and function names using debugfs.
1133 *
1134 * If you are concerned about the boot time, set up the static pins in
1135 * the bootloader, and only set up selected pins as device tree entries.
1136 */
1137 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
1138 struct device_node *np,
1139 struct pinctrl_map **map,
1140 unsigned *num_maps,
1141 const char **pgnames)
1142 {
1143 struct pcs_func_vals *vals;
1144 const __be32 *mux;
1145 int size, rows, *pins, index = 0, found = 0, res = -ENOMEM;
1146 struct pcs_function *function;
1147
1148 mux = of_get_property(np, PCS_MUX_PINS_NAME, &size);
1149 if ((!mux) || (size < sizeof(*mux) * 2)) {
1150 dev_err(pcs->dev, "bad data for mux %s\n",
1151 np->name);
1152 return -EINVAL;
1153 }
1154
1155 size /= sizeof(*mux); /* Number of elements in array */
1156 rows = size / 2;
1157
1158 vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL);
1159 if (!vals)
1160 return -ENOMEM;
1161
1162 pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows, GFP_KERNEL);
1163 if (!pins)
1164 goto free_vals;
1165
1166 while (index < size) {
1167 unsigned offset, val;
1168 int pin;
1169
1170 offset = be32_to_cpup(mux + index++);
1171 val = be32_to_cpup(mux + index++);
1172 vals[found].reg = pcs->base + offset;
1173 vals[found].val = val;
1174
1175 pin = pcs_get_pin_by_offset(pcs, offset);
1176 if (pin < 0) {
1177 dev_err(pcs->dev,
1178 "could not add functions for %s %ux\n",
1179 np->name, offset);
1180 break;
1181 }
1182 pins[found++] = pin;
1183 }
1184
1185 pgnames[0] = np->name;
1186 function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1187 if (!function)
1188 goto free_pins;
1189
1190 res = pcs_add_pingroup(pcs, np, np->name, pins, found);
1191 if (res < 0)
1192 goto free_function;
1193
1194 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1195 (*map)->data.mux.group = np->name;
1196 (*map)->data.mux.function = np->name;
1197
1198 if (PCS_HAS_PINCONF) {
1199 res = pcs_parse_pinconf(pcs, np, function, map);
1200 if (res)
1201 goto free_pingroups;
1202 *num_maps = 2;
1203 } else {
1204 *num_maps = 1;
1205 }
1206 return 0;
1207
1208 free_pingroups:
1209 pcs_free_pingroups(pcs);
1210 *num_maps = 1;
1211 free_function:
1212 pcs_remove_function(pcs, function);
1213
1214 free_pins:
1215 devm_kfree(pcs->dev, pins);
1216
1217 free_vals:
1218 devm_kfree(pcs->dev, vals);
1219
1220 return res;
1221 }
1222
1223 #define PARAMS_FOR_BITS_PER_MUX 3
1224
1225 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1226 struct device_node *np,
1227 struct pinctrl_map **map,
1228 unsigned *num_maps,
1229 const char **pgnames)
1230 {
1231 struct pcs_func_vals *vals;
1232 const __be32 *mux;
1233 int size, rows, *pins, index = 0, found = 0, res = -ENOMEM;
1234 int npins_in_row;
1235 struct pcs_function *function;
1236
1237 mux = of_get_property(np, PCS_MUX_BITS_NAME, &size);
1238
1239 if (!mux) {
1240 dev_err(pcs->dev, "no valid property for %s\n", np->name);
1241 return -EINVAL;
1242 }
1243
1244 if (size < (sizeof(*mux) * PARAMS_FOR_BITS_PER_MUX)) {
1245 dev_err(pcs->dev, "bad data for %s\n", np->name);
1246 return -EINVAL;
1247 }
1248
1249 /* Number of elements in array */
1250 size /= sizeof(*mux);
1251
1252 rows = size / PARAMS_FOR_BITS_PER_MUX;
1253 npins_in_row = pcs->width / pcs->bits_per_pin;
1254
1255 vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows * npins_in_row,
1256 GFP_KERNEL);
1257 if (!vals)
1258 return -ENOMEM;
1259
1260 pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows * npins_in_row,
1261 GFP_KERNEL);
1262 if (!pins)
1263 goto free_vals;
1264
1265 while (index < size) {
1266 unsigned offset, val;
1267 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1268 unsigned pin_num_from_lsb;
1269 int pin;
1270
1271 offset = be32_to_cpup(mux + index++);
1272 val = be32_to_cpup(mux + index++);
1273 mask = be32_to_cpup(mux + index++);
1274
1275 /* Parse pins in each row from LSB */
1276 while (mask) {
1277 bit_pos = ffs(mask);
1278 pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1279 mask_pos = ((pcs->fmask) << (bit_pos - 1));
1280 val_pos = val & mask_pos;
1281 submask = mask & mask_pos;
1282 mask &= ~mask_pos;
1283
1284 if (submask != mask_pos) {
1285 dev_warn(pcs->dev,
1286 "Invalid submask 0x%x for %s at 0x%x\n",
1287 submask, np->name, offset);
1288 continue;
1289 }
1290
1291 vals[found].mask = submask;
1292 vals[found].reg = pcs->base + offset;
1293 vals[found].val = val_pos;
1294
1295 pin = pcs_get_pin_by_offset(pcs, offset);
1296 if (pin < 0) {
1297 dev_err(pcs->dev,
1298 "could not add functions for %s %ux\n",
1299 np->name, offset);
1300 break;
1301 }
1302 pins[found++] = pin + pin_num_from_lsb;
1303 }
1304 }
1305
1306 pgnames[0] = np->name;
1307 function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1308 if (!function)
1309 goto free_pins;
1310
1311 res = pcs_add_pingroup(pcs, np, np->name, pins, found);
1312 if (res < 0)
1313 goto free_function;
1314
1315 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1316 (*map)->data.mux.group = np->name;
1317 (*map)->data.mux.function = np->name;
1318
1319 if (PCS_HAS_PINCONF) {
1320 dev_err(pcs->dev, "pinconf not supported\n");
1321 goto free_pingroups;
1322 }
1323
1324 *num_maps = 1;
1325 return 0;
1326
1327 free_pingroups:
1328 pcs_free_pingroups(pcs);
1329 *num_maps = 1;
1330 free_function:
1331 pcs_remove_function(pcs, function);
1332
1333 free_pins:
1334 devm_kfree(pcs->dev, pins);
1335
1336 free_vals:
1337 devm_kfree(pcs->dev, vals);
1338
1339 return res;
1340 }
1341 /**
1342 * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1343 * @pctldev: pinctrl instance
1344 * @np_config: device tree pinmux entry
1345 * @map: array of map entries
1346 * @num_maps: number of maps
1347 */
1348 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1349 struct device_node *np_config,
1350 struct pinctrl_map **map, unsigned *num_maps)
1351 {
1352 struct pcs_device *pcs;
1353 const char **pgnames;
1354 int ret;
1355
1356 pcs = pinctrl_dev_get_drvdata(pctldev);
1357
1358 /* create 2 maps. One is for pinmux, and the other is for pinconf. */
1359 *map = devm_kzalloc(pcs->dev, sizeof(**map) * 2, GFP_KERNEL);
1360 if (!*map)
1361 return -ENOMEM;
1362
1363 *num_maps = 0;
1364
1365 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1366 if (!pgnames) {
1367 ret = -ENOMEM;
1368 goto free_map;
1369 }
1370
1371 if (pcs->bits_per_mux) {
1372 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1373 num_maps, pgnames);
1374 if (ret < 0) {
1375 dev_err(pcs->dev, "no pins entries for %s\n",
1376 np_config->name);
1377 goto free_pgnames;
1378 }
1379 } else {
1380 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1381 num_maps, pgnames);
1382 if (ret < 0) {
1383 dev_err(pcs->dev, "no pins entries for %s\n",
1384 np_config->name);
1385 goto free_pgnames;
1386 }
1387 }
1388
1389 return 0;
1390
1391 free_pgnames:
1392 devm_kfree(pcs->dev, pgnames);
1393 free_map:
1394 devm_kfree(pcs->dev, *map);
1395
1396 return ret;
1397 }
1398
1399 /**
1400 * pcs_free_funcs() - free memory used by functions
1401 * @pcs: pcs driver instance
1402 */
1403 static void pcs_free_funcs(struct pcs_device *pcs)
1404 {
1405 struct list_head *pos, *tmp;
1406 int i;
1407
1408 mutex_lock(&pcs->mutex);
1409 for (i = 0; i < pcs->nfuncs; i++) {
1410 struct pcs_function *func;
1411
1412 func = radix_tree_lookup(&pcs->ftree, i);
1413 if (!func)
1414 continue;
1415 radix_tree_delete(&pcs->ftree, i);
1416 }
1417 list_for_each_safe(pos, tmp, &pcs->functions) {
1418 struct pcs_function *function;
1419
1420 function = list_entry(pos, struct pcs_function, node);
1421 list_del(&function->node);
1422 }
1423 mutex_unlock(&pcs->mutex);
1424 }
1425
1426 /**
1427 * pcs_free_pingroups() - free memory used by pingroups
1428 * @pcs: pcs driver instance
1429 */
1430 static void pcs_free_pingroups(struct pcs_device *pcs)
1431 {
1432 struct list_head *pos, *tmp;
1433 int i;
1434
1435 mutex_lock(&pcs->mutex);
1436 for (i = 0; i < pcs->ngroups; i++) {
1437 struct pcs_pingroup *pingroup;
1438
1439 pingroup = radix_tree_lookup(&pcs->pgtree, i);
1440 if (!pingroup)
1441 continue;
1442 radix_tree_delete(&pcs->pgtree, i);
1443 }
1444 list_for_each_safe(pos, tmp, &pcs->pingroups) {
1445 struct pcs_pingroup *pingroup;
1446
1447 pingroup = list_entry(pos, struct pcs_pingroup, node);
1448 list_del(&pingroup->node);
1449 }
1450 mutex_unlock(&pcs->mutex);
1451 }
1452
1453 /**
1454 * pcs_free_resources() - free memory used by this driver
1455 * @pcs: pcs driver instance
1456 */
1457 static void pcs_free_resources(struct pcs_device *pcs)
1458 {
1459 if (pcs->pctl)
1460 pinctrl_unregister(pcs->pctl);
1461
1462 pcs_free_funcs(pcs);
1463 pcs_free_pingroups(pcs);
1464 }
1465
1466 #define PCS_GET_PROP_U32(name, reg, err) \
1467 do { \
1468 ret = of_property_read_u32(np, name, reg); \
1469 if (ret) { \
1470 dev_err(pcs->dev, err); \
1471 return ret; \
1472 } \
1473 } while (0);
1474
1475 static struct of_device_id pcs_of_match[];
1476
1477 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1478 {
1479 const char *propname = "pinctrl-single,gpio-range";
1480 const char *cellname = "#pinctrl-single,gpio-range-cells";
1481 struct of_phandle_args gpiospec;
1482 struct pcs_gpiofunc_range *range;
1483 int ret, i;
1484
1485 for (i = 0; ; i++) {
1486 ret = of_parse_phandle_with_args(node, propname, cellname,
1487 i, &gpiospec);
1488 /* Do not treat it as error. Only treat it as end condition. */
1489 if (ret) {
1490 ret = 0;
1491 break;
1492 }
1493 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1494 if (!range) {
1495 ret = -ENOMEM;
1496 break;
1497 }
1498 range->offset = gpiospec.args[0];
1499 range->npins = gpiospec.args[1];
1500 range->gpiofunc = gpiospec.args[2];
1501 mutex_lock(&pcs->mutex);
1502 list_add_tail(&range->node, &pcs->gpiofuncs);
1503 mutex_unlock(&pcs->mutex);
1504 }
1505 return ret;
1506 }
1507
1508 #ifdef CONFIG_PM
1509 static int pinctrl_single_suspend(struct platform_device *pdev,
1510 pm_message_t state)
1511 {
1512 struct pcs_device *pcs;
1513
1514 pcs = platform_get_drvdata(pdev);
1515 if (!pcs)
1516 return -EINVAL;
1517
1518 return pinctrl_force_sleep(pcs->pctl);
1519 }
1520
1521 static int pinctrl_single_resume(struct platform_device *pdev)
1522 {
1523 struct pcs_device *pcs;
1524
1525 pcs = platform_get_drvdata(pdev);
1526 if (!pcs)
1527 return -EINVAL;
1528
1529 return pinctrl_force_default(pcs->pctl);
1530 }
1531 #endif
1532
1533 static int pcs_probe(struct platform_device *pdev)
1534 {
1535 struct device_node *np = pdev->dev.of_node;
1536 const struct of_device_id *match;
1537 struct resource *res;
1538 struct pcs_device *pcs;
1539 const struct pcs_soc_data *soc;
1540 int ret;
1541
1542 match = of_match_device(pcs_of_match, &pdev->dev);
1543 if (!match)
1544 return -EINVAL;
1545
1546 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1547 if (!pcs) {
1548 dev_err(&pdev->dev, "could not allocate\n");
1549 return -ENOMEM;
1550 }
1551 pcs->dev = &pdev->dev;
1552 mutex_init(&pcs->mutex);
1553 INIT_LIST_HEAD(&pcs->pingroups);
1554 INIT_LIST_HEAD(&pcs->functions);
1555 INIT_LIST_HEAD(&pcs->gpiofuncs);
1556 soc = match->data;
1557 pcs->flags = soc->flags;
1558
1559 PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width,
1560 "register width not specified\n");
1561
1562 ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1563 &pcs->fmask);
1564 if (!ret) {
1565 pcs->fshift = ffs(pcs->fmask) - 1;
1566 pcs->fmax = pcs->fmask >> pcs->fshift;
1567 } else {
1568 /* If mask property doesn't exist, function mux is invalid. */
1569 pcs->fmask = 0;
1570 pcs->fshift = 0;
1571 pcs->fmax = 0;
1572 }
1573
1574 ret = of_property_read_u32(np, "pinctrl-single,function-off",
1575 &pcs->foff);
1576 if (ret)
1577 pcs->foff = PCS_OFF_DISABLED;
1578
1579 pcs->bits_per_mux = of_property_read_bool(np,
1580 "pinctrl-single,bit-per-mux");
1581
1582 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1583 if (!res) {
1584 dev_err(pcs->dev, "could not get resource\n");
1585 return -ENODEV;
1586 }
1587
1588 pcs->res = devm_request_mem_region(pcs->dev, res->start,
1589 resource_size(res), DRIVER_NAME);
1590 if (!pcs->res) {
1591 dev_err(pcs->dev, "could not get mem_region\n");
1592 return -EBUSY;
1593 }
1594
1595 pcs->size = resource_size(pcs->res);
1596 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1597 if (!pcs->base) {
1598 dev_err(pcs->dev, "could not ioremap\n");
1599 return -ENODEV;
1600 }
1601
1602 INIT_RADIX_TREE(&pcs->pgtree, GFP_KERNEL);
1603 INIT_RADIX_TREE(&pcs->ftree, GFP_KERNEL);
1604 platform_set_drvdata(pdev, pcs);
1605
1606 switch (pcs->width) {
1607 case 8:
1608 pcs->read = pcs_readb;
1609 pcs->write = pcs_writeb;
1610 break;
1611 case 16:
1612 pcs->read = pcs_readw;
1613 pcs->write = pcs_writew;
1614 break;
1615 case 32:
1616 pcs->read = pcs_readl;
1617 pcs->write = pcs_writel;
1618 break;
1619 default:
1620 break;
1621 }
1622
1623 pcs->desc.name = DRIVER_NAME;
1624 pcs->desc.pctlops = &pcs_pinctrl_ops;
1625 pcs->desc.pmxops = &pcs_pinmux_ops;
1626 if (PCS_HAS_PINCONF)
1627 pcs->desc.confops = &pcs_pinconf_ops;
1628 pcs->desc.owner = THIS_MODULE;
1629
1630 ret = pcs_allocate_pin_table(pcs);
1631 if (ret < 0)
1632 goto free;
1633
1634 pcs->pctl = pinctrl_register(&pcs->desc, pcs->dev, pcs);
1635 if (!pcs->pctl) {
1636 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1637 ret = -EINVAL;
1638 goto free;
1639 }
1640
1641 ret = pcs_add_gpio_func(np, pcs);
1642 if (ret < 0)
1643 goto free;
1644
1645 dev_info(pcs->dev, "%i pins at pa %p size %u\n",
1646 pcs->desc.npins, pcs->base, pcs->size);
1647
1648 return 0;
1649
1650 free:
1651 pcs_free_resources(pcs);
1652
1653 return ret;
1654 }
1655
1656 static int pcs_remove(struct platform_device *pdev)
1657 {
1658 struct pcs_device *pcs = platform_get_drvdata(pdev);
1659
1660 if (!pcs)
1661 return 0;
1662
1663 pcs_free_resources(pcs);
1664
1665 return 0;
1666 }
1667
1668 static const struct pcs_soc_data pinctrl_single = {
1669 };
1670
1671 static const struct pcs_soc_data pinconf_single = {
1672 .flags = PCS_FEAT_PINCONF,
1673 };
1674
1675 static struct of_device_id pcs_of_match[] = {
1676 { .compatible = "pinctrl-single", .data = &pinctrl_single },
1677 { .compatible = "pinconf-single", .data = &pinconf_single },
1678 { },
1679 };
1680 MODULE_DEVICE_TABLE(of, pcs_of_match);
1681
1682 static struct platform_driver pcs_driver = {
1683 .probe = pcs_probe,
1684 .remove = pcs_remove,
1685 .driver = {
1686 .owner = THIS_MODULE,
1687 .name = DRIVER_NAME,
1688 .of_match_table = pcs_of_match,
1689 },
1690 #ifdef CONFIG_PM
1691 .suspend = pinctrl_single_suspend,
1692 .resume = pinctrl_single_resume,
1693 #endif
1694 };
1695
1696 module_platform_driver(pcs_driver);
1697
1698 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
1699 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
1700 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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