2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
4 * Srinivas Kandagatla <srinivas.kandagatla@st.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/slab.h>
14 #include <linux/err.h>
17 #include <linux/of_irq.h>
18 #include <linux/of_gpio.h>
19 #include <linux/of_address.h>
20 #include <linux/regmap.h>
21 #include <linux/mfd/syscon.h>
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/platform_device.h>
28 /* PIO Block registers */
30 #define REG_PIO_POUT 0x00
31 /* Set bits of POUT */
32 #define REG_PIO_SET_POUT 0x04
33 /* Clear bits of POUT */
34 #define REG_PIO_CLR_POUT 0x08
36 #define REG_PIO_PIN 0x10
37 /* PIO configuration */
38 #define REG_PIO_PC(n) (0x20 + (n) * 0x10)
39 /* Set bits of PC[2:0] */
40 #define REG_PIO_SET_PC(n) (0x24 + (n) * 0x10)
41 /* Clear bits of PC[2:0] */
42 #define REG_PIO_CLR_PC(n) (0x28 + (n) * 0x10)
43 /* PIO input comparison */
44 #define REG_PIO_PCOMP 0x50
45 /* Set bits of PCOMP */
46 #define REG_PIO_SET_PCOMP 0x54
47 /* Clear bits of PCOMP */
48 #define REG_PIO_CLR_PCOMP 0x58
49 /* PIO input comparison mask */
50 #define REG_PIO_PMASK 0x60
51 /* Set bits of PMASK */
52 #define REG_PIO_SET_PMASK 0x64
53 /* Clear bits of PMASK */
54 #define REG_PIO_CLR_PMASK 0x68
56 #define ST_GPIO_DIRECTION_BIDIR 0x1
57 #define ST_GPIO_DIRECTION_OUT 0x2
58 #define ST_GPIO_DIRECTION_IN 0x4
61 * Packed style retime configuration.
62 * There are two registers cfg0 and cfg1 in this style for each bank.
63 * Each field in this register is 8 bit corresponding to 8 pins in the bank.
65 #define RT_P_CFGS_PER_BANK 2
66 #define RT_P_CFG0_CLK1NOTCLK0_FIELD(reg) REG_FIELD(reg, 0, 7)
67 #define RT_P_CFG0_DELAY_0_FIELD(reg) REG_FIELD(reg, 16, 23)
68 #define RT_P_CFG0_DELAY_1_FIELD(reg) REG_FIELD(reg, 24, 31)
69 #define RT_P_CFG1_INVERTCLK_FIELD(reg) REG_FIELD(reg, 0, 7)
70 #define RT_P_CFG1_RETIME_FIELD(reg) REG_FIELD(reg, 8, 15)
71 #define RT_P_CFG1_CLKNOTDATA_FIELD(reg) REG_FIELD(reg, 16, 23)
72 #define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg) REG_FIELD(reg, 24, 31)
75 * Dedicated style retime Configuration register
76 * each register is dedicated per pin.
78 #define RT_D_CFGS_PER_BANK 8
79 #define RT_D_CFG_CLK_SHIFT 0
80 #define RT_D_CFG_CLK_MASK (0x3 << 0)
81 #define RT_D_CFG_CLKNOTDATA_SHIFT 2
82 #define RT_D_CFG_CLKNOTDATA_MASK BIT(2)
83 #define RT_D_CFG_DELAY_SHIFT 3
84 #define RT_D_CFG_DELAY_MASK (0xf << 3)
85 #define RT_D_CFG_DELAY_INNOTOUT_SHIFT 7
86 #define RT_D_CFG_DELAY_INNOTOUT_MASK BIT(7)
87 #define RT_D_CFG_DOUBLE_EDGE_SHIFT 8
88 #define RT_D_CFG_DOUBLE_EDGE_MASK BIT(8)
89 #define RT_D_CFG_INVERTCLK_SHIFT 9
90 #define RT_D_CFG_INVERTCLK_MASK BIT(9)
91 #define RT_D_CFG_RETIME_SHIFT 10
92 #define RT_D_CFG_RETIME_MASK BIT(10)
95 * Pinconf is represented in an opaque unsigned long variable.
96 * Below is the bit allocation details for each possible configuration.
97 * All the bit fields can be encapsulated into four variables
98 * (direction, retime-type, retime-clk, retime-delay)
101 *[31:28]| reserved-3 |
102 * +----------------+-------------
104 * +----------------+ v
105 *[26] | pu | [Direction ]
106 * +----------------+ ^
108 * +----------------+-------------
110 * +----------------+-------------
112 * +----------------+ |
113 *[22] | retime-invclk | |
114 * +----------------+ v
115 *[21] |retime-clknotdat| [Retime-type ]
116 * +----------------+ ^
117 *[20] | retime-de | |
118 * +----------------+-------------
119 *[19:18]| retime-clk |------>[Retime-Clk ]
121 *[17:16]| reserved-1 |
123 *[15..0]| retime-delay |------>[Retime Delay]
127 #define ST_PINCONF_UNPACK(conf, param)\
128 ((conf >> ST_PINCONF_ ##param ##_SHIFT) \
129 & ST_PINCONF_ ##param ##_MASK)
131 #define ST_PINCONF_PACK(conf, val, param) (conf |=\
132 ((val & ST_PINCONF_ ##param ##_MASK) << \
133 ST_PINCONF_ ##param ##_SHIFT))
136 #define ST_PINCONF_OE_MASK 0x1
137 #define ST_PINCONF_OE_SHIFT 27
138 #define ST_PINCONF_OE BIT(27)
139 #define ST_PINCONF_UNPACK_OE(conf) ST_PINCONF_UNPACK(conf, OE)
140 #define ST_PINCONF_PACK_OE(conf) ST_PINCONF_PACK(conf, 1, OE)
143 #define ST_PINCONF_PU_MASK 0x1
144 #define ST_PINCONF_PU_SHIFT 26
145 #define ST_PINCONF_PU BIT(26)
146 #define ST_PINCONF_UNPACK_PU(conf) ST_PINCONF_UNPACK(conf, PU)
147 #define ST_PINCONF_PACK_PU(conf) ST_PINCONF_PACK(conf, 1, PU)
150 #define ST_PINCONF_OD_MASK 0x1
151 #define ST_PINCONF_OD_SHIFT 25
152 #define ST_PINCONF_OD BIT(25)
153 #define ST_PINCONF_UNPACK_OD(conf) ST_PINCONF_UNPACK(conf, OD)
154 #define ST_PINCONF_PACK_OD(conf) ST_PINCONF_PACK(conf, 1, OD)
156 #define ST_PINCONF_RT_MASK 0x1
157 #define ST_PINCONF_RT_SHIFT 23
158 #define ST_PINCONF_RT BIT(23)
159 #define ST_PINCONF_UNPACK_RT(conf) ST_PINCONF_UNPACK(conf, RT)
160 #define ST_PINCONF_PACK_RT(conf) ST_PINCONF_PACK(conf, 1, RT)
162 #define ST_PINCONF_RT_INVERTCLK_MASK 0x1
163 #define ST_PINCONF_RT_INVERTCLK_SHIFT 22
164 #define ST_PINCONF_RT_INVERTCLK BIT(22)
165 #define ST_PINCONF_UNPACK_RT_INVERTCLK(conf) \
166 ST_PINCONF_UNPACK(conf, RT_INVERTCLK)
167 #define ST_PINCONF_PACK_RT_INVERTCLK(conf) \
168 ST_PINCONF_PACK(conf, 1, RT_INVERTCLK)
170 #define ST_PINCONF_RT_CLKNOTDATA_MASK 0x1
171 #define ST_PINCONF_RT_CLKNOTDATA_SHIFT 21
172 #define ST_PINCONF_RT_CLKNOTDATA BIT(21)
173 #define ST_PINCONF_UNPACK_RT_CLKNOTDATA(conf) \
174 ST_PINCONF_UNPACK(conf, RT_CLKNOTDATA)
175 #define ST_PINCONF_PACK_RT_CLKNOTDATA(conf) \
176 ST_PINCONF_PACK(conf, 1, RT_CLKNOTDATA)
178 #define ST_PINCONF_RT_DOUBLE_EDGE_MASK 0x1
179 #define ST_PINCONF_RT_DOUBLE_EDGE_SHIFT 20
180 #define ST_PINCONF_RT_DOUBLE_EDGE BIT(20)
181 #define ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \
182 ST_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE)
183 #define ST_PINCONF_PACK_RT_DOUBLE_EDGE(conf) \
184 ST_PINCONF_PACK(conf, 1, RT_DOUBLE_EDGE)
186 #define ST_PINCONF_RT_CLK_MASK 0x3
187 #define ST_PINCONF_RT_CLK_SHIFT 18
188 #define ST_PINCONF_RT_CLK BIT(18)
189 #define ST_PINCONF_UNPACK_RT_CLK(conf) ST_PINCONF_UNPACK(conf, RT_CLK)
190 #define ST_PINCONF_PACK_RT_CLK(conf, val) ST_PINCONF_PACK(conf, val, RT_CLK)
192 /* RETIME_DELAY in Pico Secs */
193 #define ST_PINCONF_RT_DELAY_MASK 0xffff
194 #define ST_PINCONF_RT_DELAY_SHIFT 0
195 #define ST_PINCONF_UNPACK_RT_DELAY(conf) ST_PINCONF_UNPACK(conf, RT_DELAY)
196 #define ST_PINCONF_PACK_RT_DELAY(conf, val) \
197 ST_PINCONF_PACK(conf, val, RT_DELAY)
199 #define ST_GPIO_PINS_PER_BANK (8)
200 #define OF_GPIO_ARGS_MIN (4)
201 #define OF_RT_ARGS_MIN (2)
203 #define gpio_range_to_bank(chip) \
204 container_of(chip, struct st_gpio_bank, range)
206 #define gpio_chip_to_bank(chip) \
207 container_of(chip, struct st_gpio_bank, gpio_chip)
210 enum st_retime_style
{
211 st_retime_style_none
,
212 st_retime_style_packed
,
213 st_retime_style_dedicated
,
216 struct st_retime_dedicated
{
217 struct regmap_field
*rt
[ST_GPIO_PINS_PER_BANK
];
220 struct st_retime_packed
{
221 struct regmap_field
*clk1notclk0
;
222 struct regmap_field
*delay_0
;
223 struct regmap_field
*delay_1
;
224 struct regmap_field
*invertclk
;
225 struct regmap_field
*retime
;
226 struct regmap_field
*clknotdata
;
227 struct regmap_field
*double_edge
;
230 struct st_pio_control
{
232 struct regmap_field
*alt
, *oe
, *pu
, *od
;
235 struct st_retime_packed rt_p
;
236 struct st_retime_dedicated rt_d
;
240 struct st_pctl_data
{
241 const enum st_retime_style rt_style
;
242 const unsigned int *input_delays
;
243 const int ninput_delays
;
244 const unsigned int *output_delays
;
245 const int noutput_delays
;
246 /* register offset information */
247 const int alt
, oe
, pu
, od
, rt
;
253 unsigned long config
;
263 struct st_pctl_group
{
267 struct st_pinconf
*pin_conf
;
271 * Edge triggers are not supported at hardware level, it is supported by
272 * software by exploiting the level trigger support in hardware.
273 * Software uses a virtual register (EDGE_CONF) for edge trigger configuration
274 * of each gpio pin in a GPIO bank.
276 * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of
277 * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank.
279 * bit allocation per pin is:
280 * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31]
281 * --------------------------------------------------------
282 * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 |
283 * --------------------------------------------------------
285 * A pin can have one of following the values in its edge configuration field.
287 * ------- ----------------------------
288 * [0-3] - Description
289 * ------- ----------------------------
290 * 0000 - No edge IRQ.
291 * 0001 - Falling edge IRQ.
292 * 0010 - Rising edge IRQ.
293 * 0011 - Rising and Falling edge IRQ.
294 * ------- ----------------------------
297 #define ST_IRQ_EDGE_CONF_BITS_PER_PIN 4
298 #define ST_IRQ_EDGE_MASK 0xf
299 #define ST_IRQ_EDGE_FALLING BIT(0)
300 #define ST_IRQ_EDGE_RISING BIT(1)
301 #define ST_IRQ_EDGE_BOTH (BIT(0) | BIT(1))
303 #define ST_IRQ_RISING_EDGE_CONF(pin) \
304 (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
306 #define ST_IRQ_FALLING_EDGE_CONF(pin) \
307 (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
309 #define ST_IRQ_BOTH_EDGE_CONF(pin) \
310 (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
312 #define ST_IRQ_EDGE_CONF(conf, pin) \
313 (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK)
315 struct st_gpio_bank
{
316 struct gpio_chip gpio_chip
;
317 struct pinctrl_gpio_range range
;
319 struct st_pio_control pc
;
320 unsigned long irq_edge_conf
;
326 struct pinctrl_dev
*pctl
;
327 struct st_gpio_bank
*banks
;
329 struct st_pmx_func
*functions
;
331 struct st_pctl_group
*groups
;
333 struct regmap
*regmap
;
334 const struct st_pctl_data
*data
;
335 void __iomem
*irqmux_base
;
338 /* SOC specific data */
340 static const unsigned int stih415_input_delays
[] = {0, 500, 1000, 1500};
341 static const unsigned int stih415_output_delays
[] = {0, 1000, 2000, 3000};
343 #define STIH415_PCTRL_COMMON_DATA \
344 .rt_style = st_retime_style_packed, \
345 .input_delays = stih415_input_delays, \
346 .ninput_delays = ARRAY_SIZE(stih415_input_delays), \
347 .output_delays = stih415_output_delays, \
348 .noutput_delays = ARRAY_SIZE(stih415_output_delays)
350 static const struct st_pctl_data stih415_sbc_data
= {
351 STIH415_PCTRL_COMMON_DATA
,
352 .alt
= 0, .oe
= 5, .pu
= 7, .od
= 9, .rt
= 16,
355 static const struct st_pctl_data stih415_front_data
= {
356 STIH415_PCTRL_COMMON_DATA
,
357 .alt
= 0, .oe
= 8, .pu
= 10, .od
= 12, .rt
= 16,
360 static const struct st_pctl_data stih415_rear_data
= {
361 STIH415_PCTRL_COMMON_DATA
,
362 .alt
= 0, .oe
= 6, .pu
= 8, .od
= 10, .rt
= 38,
365 static const struct st_pctl_data stih415_left_data
= {
366 STIH415_PCTRL_COMMON_DATA
,
367 .alt
= 0, .oe
= 3, .pu
= 4, .od
= 5, .rt
= 6,
370 static const struct st_pctl_data stih415_right_data
= {
371 STIH415_PCTRL_COMMON_DATA
,
372 .alt
= 0, .oe
= 5, .pu
= 7, .od
= 9, .rt
= 11,
376 static const unsigned int stih416_delays
[] = {0, 300, 500, 750, 1000, 1250,
377 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250 };
379 static const struct st_pctl_data stih416_data
= {
380 .rt_style
= st_retime_style_dedicated
,
381 .input_delays
= stih416_delays
,
382 .ninput_delays
= ARRAY_SIZE(stih416_delays
),
383 .output_delays
= stih416_delays
,
384 .noutput_delays
= ARRAY_SIZE(stih416_delays
),
385 .alt
= 0, .oe
= 40, .pu
= 50, .od
= 60, .rt
= 100,
388 static const struct st_pctl_data stih407_flashdata
= {
389 .rt_style
= st_retime_style_none
,
390 .input_delays
= stih416_delays
,
391 .ninput_delays
= ARRAY_SIZE(stih416_delays
),
392 .output_delays
= stih416_delays
,
393 .noutput_delays
= ARRAY_SIZE(stih416_delays
),
395 .oe
= -1, /* Not Available */
396 .pu
= -1, /* Not Available */
401 /* Low level functions.. */
402 static inline int st_gpio_bank(int gpio
)
404 return gpio
/ST_GPIO_PINS_PER_BANK
;
407 static inline int st_gpio_pin(int gpio
)
409 return gpio
%ST_GPIO_PINS_PER_BANK
;
412 static void st_pinconf_set_config(struct st_pio_control
*pc
,
413 int pin
, unsigned long config
)
415 struct regmap_field
*output_enable
= pc
->oe
;
416 struct regmap_field
*pull_up
= pc
->pu
;
417 struct regmap_field
*open_drain
= pc
->od
;
418 unsigned int oe_value
, pu_value
, od_value
;
419 unsigned long mask
= BIT(pin
);
422 regmap_field_read(output_enable
, &oe_value
);
424 if (config
& ST_PINCONF_OE
)
426 regmap_field_write(output_enable
, oe_value
);
430 regmap_field_read(pull_up
, &pu_value
);
432 if (config
& ST_PINCONF_PU
)
434 regmap_field_write(pull_up
, pu_value
);
438 regmap_field_read(open_drain
, &od_value
);
440 if (config
& ST_PINCONF_OD
)
442 regmap_field_write(open_drain
, od_value
);
446 static void st_pctl_set_function(struct st_pio_control
*pc
,
447 int pin_id
, int function
)
449 struct regmap_field
*alt
= pc
->alt
;
451 int pin
= st_gpio_pin(pin_id
);
452 int offset
= pin
* 4;
457 regmap_field_read(alt
, &val
);
458 val
&= ~(0xf << offset
);
459 val
|= function
<< offset
;
460 regmap_field_write(alt
, val
);
463 static unsigned long st_pinconf_delay_to_bit(unsigned int delay
,
464 const struct st_pctl_data
*data
, unsigned long config
)
466 const unsigned int *delay_times
;
467 int num_delay_times
, i
, closest_index
= -1;
468 unsigned int closest_divergence
= UINT_MAX
;
470 if (ST_PINCONF_UNPACK_OE(config
)) {
471 delay_times
= data
->output_delays
;
472 num_delay_times
= data
->noutput_delays
;
474 delay_times
= data
->input_delays
;
475 num_delay_times
= data
->ninput_delays
;
478 for (i
= 0; i
< num_delay_times
; i
++) {
479 unsigned int divergence
= abs(delay
- delay_times
[i
]);
484 if (divergence
< closest_divergence
) {
485 closest_divergence
= divergence
;
490 pr_warn("Attempt to set delay %d, closest available %d\n",
491 delay
, delay_times
[closest_index
]);
493 return closest_index
;
496 static unsigned long st_pinconf_bit_to_delay(unsigned int index
,
497 const struct st_pctl_data
*data
, unsigned long output
)
499 const unsigned int *delay_times
;
503 delay_times
= data
->output_delays
;
504 num_delay_times
= data
->noutput_delays
;
506 delay_times
= data
->input_delays
;
507 num_delay_times
= data
->ninput_delays
;
510 if (index
< num_delay_times
) {
511 return delay_times
[index
];
513 pr_warn("Delay not found in/out delay list\n");
518 static void st_regmap_field_bit_set_clear_pin(struct regmap_field
*field
,
521 unsigned int val
= 0;
523 regmap_field_read(field
, &val
);
528 regmap_field_write(field
, val
);
531 static void st_pinconf_set_retime_packed(struct st_pinctrl
*info
,
532 struct st_pio_control
*pc
, unsigned long config
, int pin
)
534 const struct st_pctl_data
*data
= info
->data
;
535 struct st_retime_packed
*rt_p
= &pc
->rt
.rt_p
;
538 st_regmap_field_bit_set_clear_pin(rt_p
->clk1notclk0
,
539 ST_PINCONF_UNPACK_RT_CLK(config
), pin
);
541 st_regmap_field_bit_set_clear_pin(rt_p
->clknotdata
,
542 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config
), pin
);
544 st_regmap_field_bit_set_clear_pin(rt_p
->double_edge
,
545 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config
), pin
);
547 st_regmap_field_bit_set_clear_pin(rt_p
->invertclk
,
548 ST_PINCONF_UNPACK_RT_INVERTCLK(config
), pin
);
550 st_regmap_field_bit_set_clear_pin(rt_p
->retime
,
551 ST_PINCONF_UNPACK_RT(config
), pin
);
553 delay
= st_pinconf_delay_to_bit(ST_PINCONF_UNPACK_RT_DELAY(config
),
555 /* 2 bit delay, lsb */
556 st_regmap_field_bit_set_clear_pin(rt_p
->delay_0
, delay
& 0x1, pin
);
557 /* 2 bit delay, msb */
558 st_regmap_field_bit_set_clear_pin(rt_p
->delay_1
, delay
& 0x2, pin
);
562 static void st_pinconf_set_retime_dedicated(struct st_pinctrl
*info
,
563 struct st_pio_control
*pc
, unsigned long config
, int pin
)
565 int input
= ST_PINCONF_UNPACK_OE(config
) ? 0 : 1;
566 int clk
= ST_PINCONF_UNPACK_RT_CLK(config
);
567 int clknotdata
= ST_PINCONF_UNPACK_RT_CLKNOTDATA(config
);
568 int double_edge
= ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config
);
569 int invertclk
= ST_PINCONF_UNPACK_RT_INVERTCLK(config
);
570 int retime
= ST_PINCONF_UNPACK_RT(config
);
572 unsigned long delay
= st_pinconf_delay_to_bit(
573 ST_PINCONF_UNPACK_RT_DELAY(config
),
575 struct st_retime_dedicated
*rt_d
= &pc
->rt
.rt_d
;
577 unsigned long retime_config
=
578 ((clk
) << RT_D_CFG_CLK_SHIFT
) |
579 ((delay
) << RT_D_CFG_DELAY_SHIFT
) |
580 ((input
) << RT_D_CFG_DELAY_INNOTOUT_SHIFT
) |
581 ((retime
) << RT_D_CFG_RETIME_SHIFT
) |
582 ((clknotdata
) << RT_D_CFG_CLKNOTDATA_SHIFT
) |
583 ((invertclk
) << RT_D_CFG_INVERTCLK_SHIFT
) |
584 ((double_edge
) << RT_D_CFG_DOUBLE_EDGE_SHIFT
);
586 regmap_field_write(rt_d
->rt
[pin
], retime_config
);
589 static void st_pinconf_get_direction(struct st_pio_control
*pc
,
590 int pin
, unsigned long *config
)
592 unsigned int oe_value
, pu_value
, od_value
;
595 regmap_field_read(pc
->oe
, &oe_value
);
596 if (oe_value
& BIT(pin
))
597 ST_PINCONF_PACK_OE(*config
);
601 regmap_field_read(pc
->pu
, &pu_value
);
602 if (pu_value
& BIT(pin
))
603 ST_PINCONF_PACK_PU(*config
);
607 regmap_field_read(pc
->od
, &od_value
);
608 if (od_value
& BIT(pin
))
609 ST_PINCONF_PACK_OD(*config
);
613 static int st_pinconf_get_retime_packed(struct st_pinctrl
*info
,
614 struct st_pio_control
*pc
, int pin
, unsigned long *config
)
616 const struct st_pctl_data
*data
= info
->data
;
617 struct st_retime_packed
*rt_p
= &pc
->rt
.rt_p
;
618 unsigned int delay_bits
, delay
, delay0
, delay1
, val
;
619 int output
= ST_PINCONF_UNPACK_OE(*config
);
621 if (!regmap_field_read(rt_p
->retime
, &val
) && (val
& BIT(pin
)))
622 ST_PINCONF_PACK_RT(*config
);
624 if (!regmap_field_read(rt_p
->clk1notclk0
, &val
) && (val
& BIT(pin
)))
625 ST_PINCONF_PACK_RT_CLK(*config
, 1);
627 if (!regmap_field_read(rt_p
->clknotdata
, &val
) && (val
& BIT(pin
)))
628 ST_PINCONF_PACK_RT_CLKNOTDATA(*config
);
630 if (!regmap_field_read(rt_p
->double_edge
, &val
) && (val
& BIT(pin
)))
631 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config
);
633 if (!regmap_field_read(rt_p
->invertclk
, &val
) && (val
& BIT(pin
)))
634 ST_PINCONF_PACK_RT_INVERTCLK(*config
);
636 regmap_field_read(rt_p
->delay_0
, &delay0
);
637 regmap_field_read(rt_p
->delay_1
, &delay1
);
638 delay_bits
= (((delay1
& BIT(pin
)) ? 1 : 0) << 1) |
639 (((delay0
& BIT(pin
)) ? 1 : 0));
640 delay
= st_pinconf_bit_to_delay(delay_bits
, data
, output
);
641 ST_PINCONF_PACK_RT_DELAY(*config
, delay
);
646 static int st_pinconf_get_retime_dedicated(struct st_pinctrl
*info
,
647 struct st_pio_control
*pc
, int pin
, unsigned long *config
)
650 unsigned long delay_bits
, delay
, rt_clk
;
651 int output
= ST_PINCONF_UNPACK_OE(*config
);
652 struct st_retime_dedicated
*rt_d
= &pc
->rt
.rt_d
;
654 regmap_field_read(rt_d
->rt
[pin
], &value
);
656 rt_clk
= (value
& RT_D_CFG_CLK_MASK
) >> RT_D_CFG_CLK_SHIFT
;
657 ST_PINCONF_PACK_RT_CLK(*config
, rt_clk
);
659 delay_bits
= (value
& RT_D_CFG_DELAY_MASK
) >> RT_D_CFG_DELAY_SHIFT
;
660 delay
= st_pinconf_bit_to_delay(delay_bits
, info
->data
, output
);
661 ST_PINCONF_PACK_RT_DELAY(*config
, delay
);
663 if (value
& RT_D_CFG_CLKNOTDATA_MASK
)
664 ST_PINCONF_PACK_RT_CLKNOTDATA(*config
);
666 if (value
& RT_D_CFG_DOUBLE_EDGE_MASK
)
667 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config
);
669 if (value
& RT_D_CFG_INVERTCLK_MASK
)
670 ST_PINCONF_PACK_RT_INVERTCLK(*config
);
672 if (value
& RT_D_CFG_RETIME_MASK
)
673 ST_PINCONF_PACK_RT(*config
);
678 /* GPIO related functions */
680 static inline void __st_gpio_set(struct st_gpio_bank
*bank
,
681 unsigned offset
, int value
)
684 writel(BIT(offset
), bank
->base
+ REG_PIO_SET_POUT
);
686 writel(BIT(offset
), bank
->base
+ REG_PIO_CLR_POUT
);
689 static void st_gpio_direction(struct st_gpio_bank
*bank
,
690 unsigned int gpio
, unsigned int direction
)
692 int offset
= st_gpio_pin(gpio
);
695 * There are three configuration registers (PIOn_PC0, PIOn_PC1
696 * and PIOn_PC2) for each port. These are used to configure the
697 * PIO port pins. Each pin can be configured as an input, output,
698 * bidirectional, or alternative function pin. Three bits, one bit
699 * from each of the three registers, configure the corresponding bit of
700 * the port. Valid bit settings is:
702 * PC2 PC1 PC0 Direction.
703 * 0 0 0 [Input Weak pull-up]
704 * 0 0 or 1 1 [Bidirection]
708 * PIOn_SET_PC and PIOn_CLR_PC registers are used to set and clear bits
711 for (i
= 0; i
<= 2; i
++) {
712 if (direction
& BIT(i
))
713 writel(BIT(offset
), bank
->base
+ REG_PIO_SET_PC(i
));
715 writel(BIT(offset
), bank
->base
+ REG_PIO_CLR_PC(i
));
719 static int st_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
721 return pinctrl_request_gpio(chip
->base
+ offset
);
724 static void st_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
726 pinctrl_free_gpio(chip
->base
+ offset
);
729 static int st_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
731 struct st_gpio_bank
*bank
= gpio_chip_to_bank(chip
);
733 return !!(readl(bank
->base
+ REG_PIO_PIN
) & BIT(offset
));
736 static void st_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
738 struct st_gpio_bank
*bank
= gpio_chip_to_bank(chip
);
739 __st_gpio_set(bank
, offset
, value
);
742 static int st_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
744 pinctrl_gpio_direction_input(chip
->base
+ offset
);
749 static int st_gpio_direction_output(struct gpio_chip
*chip
,
750 unsigned offset
, int value
)
752 struct st_gpio_bank
*bank
= gpio_chip_to_bank(chip
);
754 __st_gpio_set(bank
, offset
, value
);
755 pinctrl_gpio_direction_output(chip
->base
+ offset
);
760 static int st_gpio_xlate(struct gpio_chip
*gc
,
761 const struct of_phandle_args
*gpiospec
, u32
*flags
)
763 if (WARN_ON(gc
->of_gpio_n_cells
< 1))
766 if (WARN_ON(gpiospec
->args_count
< gc
->of_gpio_n_cells
))
769 if (gpiospec
->args
[0] > gc
->ngpio
)
772 return gpiospec
->args
[0];
776 static int st_pctl_get_groups_count(struct pinctrl_dev
*pctldev
)
778 struct st_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
780 return info
->ngroups
;
783 static const char *st_pctl_get_group_name(struct pinctrl_dev
*pctldev
,
786 struct st_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
788 return info
->groups
[selector
].name
;
791 static int st_pctl_get_group_pins(struct pinctrl_dev
*pctldev
,
792 unsigned selector
, const unsigned **pins
, unsigned *npins
)
794 struct st_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
796 if (selector
>= info
->ngroups
)
799 *pins
= info
->groups
[selector
].pins
;
800 *npins
= info
->groups
[selector
].npins
;
805 static const inline struct st_pctl_group
*st_pctl_find_group_by_name(
806 const struct st_pinctrl
*info
, const char *name
)
810 for (i
= 0; i
< info
->ngroups
; i
++) {
811 if (!strcmp(info
->groups
[i
].name
, name
))
812 return &info
->groups
[i
];
818 static int st_pctl_dt_node_to_map(struct pinctrl_dev
*pctldev
,
819 struct device_node
*np
, struct pinctrl_map
**map
, unsigned *num_maps
)
821 struct st_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
822 const struct st_pctl_group
*grp
;
823 struct pinctrl_map
*new_map
;
824 struct device_node
*parent
;
827 grp
= st_pctl_find_group_by_name(info
, np
->name
);
829 dev_err(info
->dev
, "unable to find group for node %s\n",
834 map_num
= grp
->npins
+ 1;
835 new_map
= devm_kzalloc(pctldev
->dev
,
836 sizeof(*new_map
) * map_num
, GFP_KERNEL
);
840 parent
= of_get_parent(np
);
842 devm_kfree(pctldev
->dev
, new_map
);
848 new_map
[0].type
= PIN_MAP_TYPE_MUX_GROUP
;
849 new_map
[0].data
.mux
.function
= parent
->name
;
850 new_map
[0].data
.mux
.group
= np
->name
;
853 /* create config map per pin */
855 for (i
= 0; i
< grp
->npins
; i
++) {
856 new_map
[i
].type
= PIN_MAP_TYPE_CONFIGS_PIN
;
857 new_map
[i
].data
.configs
.group_or_pin
=
858 pin_get_name(pctldev
, grp
->pins
[i
]);
859 new_map
[i
].data
.configs
.configs
= &grp
->pin_conf
[i
].config
;
860 new_map
[i
].data
.configs
.num_configs
= 1;
862 dev_info(pctldev
->dev
, "maps: function %s group %s num %d\n",
863 (*map
)->data
.mux
.function
, grp
->name
, map_num
);
868 static void st_pctl_dt_free_map(struct pinctrl_dev
*pctldev
,
869 struct pinctrl_map
*map
, unsigned num_maps
)
873 static struct pinctrl_ops st_pctlops
= {
874 .get_groups_count
= st_pctl_get_groups_count
,
875 .get_group_pins
= st_pctl_get_group_pins
,
876 .get_group_name
= st_pctl_get_group_name
,
877 .dt_node_to_map
= st_pctl_dt_node_to_map
,
878 .dt_free_map
= st_pctl_dt_free_map
,
882 static int st_pmx_get_funcs_count(struct pinctrl_dev
*pctldev
)
884 struct st_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
886 return info
->nfunctions
;
889 static const char *st_pmx_get_fname(struct pinctrl_dev
*pctldev
,
892 struct st_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
894 return info
->functions
[selector
].name
;
897 static int st_pmx_get_groups(struct pinctrl_dev
*pctldev
,
898 unsigned selector
, const char * const **grps
, unsigned * const ngrps
)
900 struct st_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
901 *grps
= info
->functions
[selector
].groups
;
902 *ngrps
= info
->functions
[selector
].ngroups
;
907 static struct st_pio_control
*st_get_pio_control(
908 struct pinctrl_dev
*pctldev
, int pin
)
910 struct pinctrl_gpio_range
*range
=
911 pinctrl_find_gpio_range_from_pin(pctldev
, pin
);
912 struct st_gpio_bank
*bank
= gpio_range_to_bank(range
);
917 static int st_pmx_enable(struct pinctrl_dev
*pctldev
, unsigned fselector
,
920 struct st_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
921 struct st_pinconf
*conf
= info
->groups
[group
].pin_conf
;
922 struct st_pio_control
*pc
;
925 for (i
= 0; i
< info
->groups
[group
].npins
; i
++) {
926 pc
= st_get_pio_control(pctldev
, conf
[i
].pin
);
927 st_pctl_set_function(pc
, conf
[i
].pin
, conf
[i
].altfunc
);
933 static int st_pmx_set_gpio_direction(struct pinctrl_dev
*pctldev
,
934 struct pinctrl_gpio_range
*range
, unsigned gpio
,
937 struct st_gpio_bank
*bank
= gpio_range_to_bank(range
);
939 * When a PIO bank is used in its primary function mode (altfunc = 0)
940 * Output Enable (OE), Open Drain(OD), and Pull Up (PU)
941 * for the primary PIO functions are driven by the related PIO block
943 st_pctl_set_function(&bank
->pc
, gpio
, 0);
944 st_gpio_direction(bank
, gpio
, input
?
945 ST_GPIO_DIRECTION_IN
: ST_GPIO_DIRECTION_OUT
);
950 static struct pinmux_ops st_pmxops
= {
951 .get_functions_count
= st_pmx_get_funcs_count
,
952 .get_function_name
= st_pmx_get_fname
,
953 .get_function_groups
= st_pmx_get_groups
,
954 .enable
= st_pmx_enable
,
955 .gpio_set_direction
= st_pmx_set_gpio_direction
,
959 static void st_pinconf_get_retime(struct st_pinctrl
*info
,
960 struct st_pio_control
*pc
, int pin
, unsigned long *config
)
962 if (info
->data
->rt_style
== st_retime_style_packed
)
963 st_pinconf_get_retime_packed(info
, pc
, pin
, config
);
964 else if (info
->data
->rt_style
== st_retime_style_dedicated
)
965 if ((BIT(pin
) & pc
->rt_pin_mask
))
966 st_pinconf_get_retime_dedicated(info
, pc
,
970 static void st_pinconf_set_retime(struct st_pinctrl
*info
,
971 struct st_pio_control
*pc
, int pin
, unsigned long config
)
973 if (info
->data
->rt_style
== st_retime_style_packed
)
974 st_pinconf_set_retime_packed(info
, pc
, config
, pin
);
975 else if (info
->data
->rt_style
== st_retime_style_dedicated
)
976 if ((BIT(pin
) & pc
->rt_pin_mask
))
977 st_pinconf_set_retime_dedicated(info
, pc
,
981 static int st_pinconf_set(struct pinctrl_dev
*pctldev
, unsigned pin_id
,
982 unsigned long *configs
, unsigned num_configs
)
984 int pin
= st_gpio_pin(pin_id
);
985 struct st_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
986 struct st_pio_control
*pc
= st_get_pio_control(pctldev
, pin_id
);
989 for (i
= 0; i
< num_configs
; i
++) {
990 st_pinconf_set_config(pc
, pin
, configs
[i
]);
991 st_pinconf_set_retime(info
, pc
, pin
, configs
[i
]);
992 } /* for each config */
997 static int st_pinconf_get(struct pinctrl_dev
*pctldev
,
998 unsigned pin_id
, unsigned long *config
)
1000 int pin
= st_gpio_pin(pin_id
);
1001 struct st_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
1002 struct st_pio_control
*pc
= st_get_pio_control(pctldev
, pin_id
);
1005 st_pinconf_get_direction(pc
, pin
, config
);
1006 st_pinconf_get_retime(info
, pc
, pin
, config
);
1011 static void st_pinconf_dbg_show(struct pinctrl_dev
*pctldev
,
1012 struct seq_file
*s
, unsigned pin_id
)
1014 unsigned long config
;
1015 st_pinconf_get(pctldev
, pin_id
, &config
);
1017 seq_printf(s
, "[OE:%ld,PU:%ld,OD:%ld]\n"
1018 "\t\t[retime:%ld,invclk:%ld,clknotdat:%ld,"
1019 "de:%ld,rt-clk:%ld,rt-delay:%ld]",
1020 ST_PINCONF_UNPACK_OE(config
),
1021 ST_PINCONF_UNPACK_PU(config
),
1022 ST_PINCONF_UNPACK_OD(config
),
1023 ST_PINCONF_UNPACK_RT(config
),
1024 ST_PINCONF_UNPACK_RT_INVERTCLK(config
),
1025 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config
),
1026 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config
),
1027 ST_PINCONF_UNPACK_RT_CLK(config
),
1028 ST_PINCONF_UNPACK_RT_DELAY(config
));
1031 static struct pinconf_ops st_confops
= {
1032 .pin_config_get
= st_pinconf_get
,
1033 .pin_config_set
= st_pinconf_set
,
1034 .pin_config_dbg_show
= st_pinconf_dbg_show
,
1037 static void st_pctl_dt_child_count(struct st_pinctrl
*info
,
1038 struct device_node
*np
)
1040 struct device_node
*child
;
1041 for_each_child_of_node(np
, child
) {
1042 if (of_property_read_bool(child
, "gpio-controller")) {
1046 info
->ngroups
+= of_get_child_count(child
);
1051 static int st_pctl_dt_setup_retime_packed(struct st_pinctrl
*info
,
1052 int bank
, struct st_pio_control
*pc
)
1054 struct device
*dev
= info
->dev
;
1055 struct regmap
*rm
= info
->regmap
;
1056 const struct st_pctl_data
*data
= info
->data
;
1057 /* 2 registers per bank */
1058 int reg
= (data
->rt
+ bank
* RT_P_CFGS_PER_BANK
) * 4;
1059 struct st_retime_packed
*rt_p
= &pc
->rt
.rt_p
;
1061 struct reg_field clk1notclk0
= RT_P_CFG0_CLK1NOTCLK0_FIELD(reg
);
1062 struct reg_field delay_0
= RT_P_CFG0_DELAY_0_FIELD(reg
);
1063 struct reg_field delay_1
= RT_P_CFG0_DELAY_1_FIELD(reg
);
1065 struct reg_field invertclk
= RT_P_CFG1_INVERTCLK_FIELD(reg
+ 4);
1066 struct reg_field retime
= RT_P_CFG1_RETIME_FIELD(reg
+ 4);
1067 struct reg_field clknotdata
= RT_P_CFG1_CLKNOTDATA_FIELD(reg
+ 4);
1068 struct reg_field double_edge
= RT_P_CFG1_DOUBLE_EDGE_FIELD(reg
+ 4);
1070 rt_p
->clk1notclk0
= devm_regmap_field_alloc(dev
, rm
, clk1notclk0
);
1071 rt_p
->delay_0
= devm_regmap_field_alloc(dev
, rm
, delay_0
);
1072 rt_p
->delay_1
= devm_regmap_field_alloc(dev
, rm
, delay_1
);
1073 rt_p
->invertclk
= devm_regmap_field_alloc(dev
, rm
, invertclk
);
1074 rt_p
->retime
= devm_regmap_field_alloc(dev
, rm
, retime
);
1075 rt_p
->clknotdata
= devm_regmap_field_alloc(dev
, rm
, clknotdata
);
1076 rt_p
->double_edge
= devm_regmap_field_alloc(dev
, rm
, double_edge
);
1078 if (IS_ERR(rt_p
->clk1notclk0
) || IS_ERR(rt_p
->delay_0
) ||
1079 IS_ERR(rt_p
->delay_1
) || IS_ERR(rt_p
->invertclk
) ||
1080 IS_ERR(rt_p
->retime
) || IS_ERR(rt_p
->clknotdata
) ||
1081 IS_ERR(rt_p
->double_edge
))
1087 static int st_pctl_dt_setup_retime_dedicated(struct st_pinctrl
*info
,
1088 int bank
, struct st_pio_control
*pc
)
1090 struct device
*dev
= info
->dev
;
1091 struct regmap
*rm
= info
->regmap
;
1092 const struct st_pctl_data
*data
= info
->data
;
1093 /* 8 registers per bank */
1094 int reg_offset
= (data
->rt
+ bank
* RT_D_CFGS_PER_BANK
) * 4;
1095 struct st_retime_dedicated
*rt_d
= &pc
->rt
.rt_d
;
1097 u32 pin_mask
= pc
->rt_pin_mask
;
1099 for (j
= 0; j
< RT_D_CFGS_PER_BANK
; j
++) {
1100 if (BIT(j
) & pin_mask
) {
1101 struct reg_field reg
= REG_FIELD(reg_offset
, 0, 31);
1102 rt_d
->rt
[j
] = devm_regmap_field_alloc(dev
, rm
, reg
);
1103 if (IS_ERR(rt_d
->rt
[j
]))
1111 static int st_pctl_dt_setup_retime(struct st_pinctrl
*info
,
1112 int bank
, struct st_pio_control
*pc
)
1114 const struct st_pctl_data
*data
= info
->data
;
1115 if (data
->rt_style
== st_retime_style_packed
)
1116 return st_pctl_dt_setup_retime_packed(info
, bank
, pc
);
1117 else if (data
->rt_style
== st_retime_style_dedicated
)
1118 return st_pctl_dt_setup_retime_dedicated(info
, bank
, pc
);
1124 static struct regmap_field
*st_pc_get_value(struct device
*dev
,
1125 struct regmap
*regmap
, int bank
,
1126 int data
, int lsb
, int msb
)
1128 struct reg_field reg
= REG_FIELD((data
+ bank
) * 4, lsb
, msb
);
1133 return devm_regmap_field_alloc(dev
, regmap
, reg
);
1136 static void st_parse_syscfgs(struct st_pinctrl
*info
, int bank
,
1137 struct device_node
*np
)
1139 const struct st_pctl_data
*data
= info
->data
;
1141 * For a given shared register like OE/PU/OD, there are 8 bits per bank
1142 * 0:7 belongs to bank0, 8:15 belongs to bank1 ...
1143 * So each register is shared across 4 banks.
1145 int lsb
= (bank
%4) * ST_GPIO_PINS_PER_BANK
;
1146 int msb
= lsb
+ ST_GPIO_PINS_PER_BANK
- 1;
1147 struct st_pio_control
*pc
= &info
->banks
[bank
].pc
;
1148 struct device
*dev
= info
->dev
;
1149 struct regmap
*regmap
= info
->regmap
;
1151 pc
->alt
= st_pc_get_value(dev
, regmap
, bank
, data
->alt
, 0, 31);
1152 pc
->oe
= st_pc_get_value(dev
, regmap
, bank
/4, data
->oe
, lsb
, msb
);
1153 pc
->pu
= st_pc_get_value(dev
, regmap
, bank
/4, data
->pu
, lsb
, msb
);
1154 pc
->od
= st_pc_get_value(dev
, regmap
, bank
/4, data
->od
, lsb
, msb
);
1156 /* retime avaiable for all pins by default */
1157 pc
->rt_pin_mask
= 0xff;
1158 of_property_read_u32(np
, "st,retime-pin-mask", &pc
->rt_pin_mask
);
1159 st_pctl_dt_setup_retime(info
, bank
, pc
);
1165 * Each pin is represented in of the below forms.
1166 * <bank offset mux direction rt_type rt_delay rt_clk>
1168 static int st_pctl_dt_parse_groups(struct device_node
*np
,
1169 struct st_pctl_group
*grp
, struct st_pinctrl
*info
, int idx
)
1171 /* bank pad direction val altfunction */
1173 struct property
*pp
;
1174 struct st_pinconf
*conf
;
1175 struct device_node
*pins
;
1176 int i
= 0, npins
= 0, nr_props
;
1178 pins
= of_get_child_by_name(np
, "st,pins");
1182 for_each_property_of_node(pins
, pp
) {
1183 /* Skip those we do not want to proceed */
1184 if (!strcmp(pp
->name
, "name"))
1187 if (pp
&& (pp
->length
/sizeof(__be32
)) >= OF_GPIO_ARGS_MIN
) {
1190 pr_warn("Invalid st,pins in %s node\n", np
->name
);
1196 grp
->name
= np
->name
;
1197 grp
->pins
= devm_kzalloc(info
->dev
, npins
* sizeof(u32
), GFP_KERNEL
);
1198 grp
->pin_conf
= devm_kzalloc(info
->dev
,
1199 npins
* sizeof(*conf
), GFP_KERNEL
);
1201 if (!grp
->pins
|| !grp
->pin_conf
)
1204 /* <bank offset mux direction rt_type rt_delay rt_clk> */
1205 for_each_property_of_node(pins
, pp
) {
1206 if (!strcmp(pp
->name
, "name"))
1208 nr_props
= pp
->length
/sizeof(u32
);
1210 conf
= &grp
->pin_conf
[i
];
1213 be32_to_cpup(list
++);
1214 be32_to_cpup(list
++);
1215 conf
->pin
= of_get_named_gpio(pins
, pp
->name
, 0);
1216 conf
->name
= pp
->name
;
1217 grp
->pins
[i
] = conf
->pin
;
1219 conf
->altfunc
= be32_to_cpup(list
++);
1222 conf
->config
|= be32_to_cpup(list
++);
1223 /* rt_type rt_delay rt_clk */
1224 if (nr_props
>= OF_GPIO_ARGS_MIN
+ OF_RT_ARGS_MIN
) {
1226 conf
->config
|= be32_to_cpup(list
++);
1228 conf
->config
|= be32_to_cpup(list
++);
1230 if (nr_props
> OF_GPIO_ARGS_MIN
+ OF_RT_ARGS_MIN
)
1231 conf
->config
|= be32_to_cpup(list
++);
1240 static int st_pctl_parse_functions(struct device_node
*np
,
1241 struct st_pinctrl
*info
, u32 index
, int *grp_index
)
1243 struct device_node
*child
;
1244 struct st_pmx_func
*func
;
1245 struct st_pctl_group
*grp
;
1248 func
= &info
->functions
[index
];
1249 func
->name
= np
->name
;
1250 func
->ngroups
= of_get_child_count(np
);
1251 if (func
->ngroups
== 0) {
1252 dev_err(info
->dev
, "No groups defined\n");
1255 func
->groups
= devm_kzalloc(info
->dev
,
1256 func
->ngroups
* sizeof(char *), GFP_KERNEL
);
1261 for_each_child_of_node(np
, child
) {
1262 func
->groups
[i
] = child
->name
;
1263 grp
= &info
->groups
[*grp_index
];
1265 ret
= st_pctl_dt_parse_groups(child
, grp
, info
, i
++);
1269 dev_info(info
->dev
, "Function[%d\t name:%s,\tgroups:%d]\n",
1270 index
, func
->name
, func
->ngroups
);
1275 static void st_gpio_irq_mask(struct irq_data
*d
)
1277 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
1278 struct st_gpio_bank
*bank
= gpio_chip_to_bank(gc
);
1280 writel(BIT(d
->hwirq
), bank
->base
+ REG_PIO_CLR_PMASK
);
1283 static void st_gpio_irq_unmask(struct irq_data
*d
)
1285 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
1286 struct st_gpio_bank
*bank
= gpio_chip_to_bank(gc
);
1288 writel(BIT(d
->hwirq
), bank
->base
+ REG_PIO_SET_PMASK
);
1291 static int st_gpio_irq_set_type(struct irq_data
*d
, unsigned type
)
1293 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
1294 struct st_gpio_bank
*bank
= gpio_chip_to_bank(gc
);
1295 unsigned long flags
;
1296 int comp
, pin
= d
->hwirq
;
1298 u32 pin_edge_conf
= 0;
1301 case IRQ_TYPE_LEVEL_HIGH
:
1304 case IRQ_TYPE_EDGE_FALLING
:
1306 pin_edge_conf
= ST_IRQ_FALLING_EDGE_CONF(pin
);
1308 case IRQ_TYPE_LEVEL_LOW
:
1311 case IRQ_TYPE_EDGE_RISING
:
1313 pin_edge_conf
= ST_IRQ_RISING_EDGE_CONF(pin
);
1315 case IRQ_TYPE_EDGE_BOTH
:
1316 comp
= st_gpio_get(&bank
->gpio_chip
, pin
);
1317 pin_edge_conf
= ST_IRQ_BOTH_EDGE_CONF(pin
);
1323 spin_lock_irqsave(&bank
->lock
, flags
);
1324 bank
->irq_edge_conf
&= ~(ST_IRQ_EDGE_MASK
<< (
1325 pin
* ST_IRQ_EDGE_CONF_BITS_PER_PIN
));
1326 bank
->irq_edge_conf
|= pin_edge_conf
;
1327 spin_unlock_irqrestore(&bank
->lock
, flags
);
1329 val
= readl(bank
->base
+ REG_PIO_PCOMP
);
1331 val
|= (comp
<< pin
);
1332 writel(val
, bank
->base
+ REG_PIO_PCOMP
);
1338 * As edge triggers are not supported at hardware level, it is supported by
1339 * software by exploiting the level trigger support in hardware.
1341 * Steps for detection raising edge interrupt in software.
1343 * Step 1: CONFIGURE pin to detect level LOW interrupts.
1345 * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler,
1346 * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt.
1347 * IGNORE calling the actual interrupt handler for the pin at this stage.
1349 * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler
1350 * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then
1351 * DISPATCH the interrupt to the interrupt handler of the pin.
1353 * step-1 ________ __________
1358 * falling edge is also detected int the same way.
1361 static void __gpio_irq_handler(struct st_gpio_bank
*bank
)
1363 unsigned long port_in
, port_mask
, port_comp
, active_irqs
;
1364 unsigned long bank_edge_mask
, flags
;
1367 spin_lock_irqsave(&bank
->lock
, flags
);
1368 bank_edge_mask
= bank
->irq_edge_conf
;
1369 spin_unlock_irqrestore(&bank
->lock
, flags
);
1372 port_in
= readl(bank
->base
+ REG_PIO_PIN
);
1373 port_comp
= readl(bank
->base
+ REG_PIO_PCOMP
);
1374 port_mask
= readl(bank
->base
+ REG_PIO_PMASK
);
1376 active_irqs
= (port_in
^ port_comp
) & port_mask
;
1378 if (active_irqs
== 0)
1381 for_each_set_bit(n
, &active_irqs
, BITS_PER_LONG
) {
1382 /* check if we are detecting fake edges ... */
1383 ecfg
= ST_IRQ_EDGE_CONF(bank_edge_mask
, n
);
1386 /* edge detection. */
1387 val
= st_gpio_get(&bank
->gpio_chip
, n
);
1390 val
? bank
->base
+ REG_PIO_SET_PCOMP
:
1391 bank
->base
+ REG_PIO_CLR_PCOMP
);
1393 if (ecfg
!= ST_IRQ_EDGE_BOTH
&&
1394 !((ecfg
& ST_IRQ_EDGE_FALLING
) ^ val
))
1398 generic_handle_irq(irq_find_mapping(bank
->gpio_chip
.irqdomain
, n
));
1403 static void st_gpio_irq_handler(unsigned irq
, struct irq_desc
*desc
)
1405 /* interrupt dedicated per bank */
1406 struct irq_chip
*chip
= irq_get_chip(irq
);
1407 struct gpio_chip
*gc
= irq_desc_get_handler_data(desc
);
1408 struct st_gpio_bank
*bank
= gpio_chip_to_bank(gc
);
1410 chained_irq_enter(chip
, desc
);
1411 __gpio_irq_handler(bank
);
1412 chained_irq_exit(chip
, desc
);
1415 static void st_gpio_irqmux_handler(unsigned irq
, struct irq_desc
*desc
)
1417 struct irq_chip
*chip
= irq_get_chip(irq
);
1418 struct st_pinctrl
*info
= irq_get_handler_data(irq
);
1419 unsigned long status
;
1422 chained_irq_enter(chip
, desc
);
1424 status
= readl(info
->irqmux_base
);
1426 for_each_set_bit(n
, &status
, info
->nbanks
)
1427 __gpio_irq_handler(&info
->banks
[n
]);
1429 chained_irq_exit(chip
, desc
);
1432 static struct gpio_chip st_gpio_template
= {
1433 .request
= st_gpio_request
,
1434 .free
= st_gpio_free
,
1437 .direction_input
= st_gpio_direction_input
,
1438 .direction_output
= st_gpio_direction_output
,
1439 .ngpio
= ST_GPIO_PINS_PER_BANK
,
1440 .of_gpio_n_cells
= 1,
1441 .of_xlate
= st_gpio_xlate
,
1444 static struct irq_chip st_gpio_irqchip
= {
1446 .irq_mask
= st_gpio_irq_mask
,
1447 .irq_unmask
= st_gpio_irq_unmask
,
1448 .irq_set_type
= st_gpio_irq_set_type
,
1449 .flags
= IRQCHIP_SKIP_SET_WAKE
,
1452 static int st_gpiolib_register_bank(struct st_pinctrl
*info
,
1453 int bank_nr
, struct device_node
*np
)
1455 struct st_gpio_bank
*bank
= &info
->banks
[bank_nr
];
1456 struct pinctrl_gpio_range
*range
= &bank
->range
;
1457 struct device
*dev
= info
->dev
;
1458 int bank_num
= of_alias_get_id(np
, "gpio");
1459 struct resource res
, irq_res
;
1460 int gpio_irq
= 0, err
;
1462 if (of_address_to_resource(np
, 0, &res
))
1465 bank
->base
= devm_ioremap_resource(dev
, &res
);
1466 if (IS_ERR(bank
->base
))
1467 return PTR_ERR(bank
->base
);
1469 bank
->gpio_chip
= st_gpio_template
;
1470 bank
->gpio_chip
.base
= bank_num
* ST_GPIO_PINS_PER_BANK
;
1471 bank
->gpio_chip
.ngpio
= ST_GPIO_PINS_PER_BANK
;
1472 bank
->gpio_chip
.of_node
= np
;
1473 bank
->gpio_chip
.dev
= dev
;
1474 spin_lock_init(&bank
->lock
);
1476 of_property_read_string(np
, "st,bank-name", &range
->name
);
1477 bank
->gpio_chip
.label
= range
->name
;
1479 range
->id
= bank_num
;
1480 range
->pin_base
= range
->base
= range
->id
* ST_GPIO_PINS_PER_BANK
;
1481 range
->npins
= bank
->gpio_chip
.ngpio
;
1482 range
->gc
= &bank
->gpio_chip
;
1483 err
= gpiochip_add(&bank
->gpio_chip
);
1485 dev_err(dev
, "Failed to add gpiochip(%d)!\n", bank_num
);
1488 dev_info(dev
, "%s bank added.\n", range
->name
);
1491 * GPIO bank can have one of the two possible types of
1492 * interrupt-wirings.
1494 * First type is via irqmux, single interrupt is used by multiple
1495 * gpio banks. This reduces number of overall interrupts numbers
1496 * required. All these banks belong to a single pincontroller.
1498 * | |----> [gpio-bank (n) ]
1499 * | |----> [gpio-bank (n + 1)]
1500 * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
1501 * | |----> [gpio-bank (... )]
1502 * |_________|----> [gpio-bank (n + 7)]
1504 * Second type has a dedicated interrupt per each gpio bank.
1506 * [irqN]----> [gpio-bank (n)]
1509 if (of_irq_to_resource(np
, 0, &irq_res
)) {
1510 gpio_irq
= irq_res
.start
;
1511 gpiochip_set_chained_irqchip(&bank
->gpio_chip
, &st_gpio_irqchip
,
1512 gpio_irq
, st_gpio_irq_handler
);
1515 if (info
->irqmux_base
> 0 || gpio_irq
> 0) {
1516 err
= gpiochip_irqchip_add(&bank
->gpio_chip
, &st_gpio_irqchip
,
1517 0, handle_simple_irq
,
1518 IRQ_TYPE_LEVEL_LOW
);
1520 dev_info(dev
, "could not add irqchip\n");
1524 dev_info(dev
, "No IRQ support for %s bank\n", np
->full_name
);
1530 static struct of_device_id st_pctl_of_match
[] = {
1531 { .compatible
= "st,stih415-sbc-pinctrl", .data
= &stih415_sbc_data
},
1532 { .compatible
= "st,stih415-rear-pinctrl", .data
= &stih415_rear_data
},
1533 { .compatible
= "st,stih415-left-pinctrl", .data
= &stih415_left_data
},
1534 { .compatible
= "st,stih415-right-pinctrl",
1535 .data
= &stih415_right_data
},
1536 { .compatible
= "st,stih415-front-pinctrl",
1537 .data
= &stih415_front_data
},
1538 { .compatible
= "st,stih416-sbc-pinctrl", .data
= &stih416_data
},
1539 { .compatible
= "st,stih416-front-pinctrl", .data
= &stih416_data
},
1540 { .compatible
= "st,stih416-rear-pinctrl", .data
= &stih416_data
},
1541 { .compatible
= "st,stih416-fvdp-fe-pinctrl", .data
= &stih416_data
},
1542 { .compatible
= "st,stih416-fvdp-lite-pinctrl", .data
= &stih416_data
},
1543 { .compatible
= "st,stih407-sbc-pinctrl", .data
= &stih416_data
},
1544 { .compatible
= "st,stih407-front-pinctrl", .data
= &stih416_data
},
1545 { .compatible
= "st,stih407-rear-pinctrl", .data
= &stih416_data
},
1546 { .compatible
= "st,stih407-flash-pinctrl", .data
= &stih407_flashdata
},
1550 static int st_pctl_probe_dt(struct platform_device
*pdev
,
1551 struct pinctrl_desc
*pctl_desc
, struct st_pinctrl
*info
)
1554 int i
= 0, j
= 0, k
= 0, bank
;
1555 struct pinctrl_pin_desc
*pdesc
;
1556 struct device_node
*np
= pdev
->dev
.of_node
;
1557 struct device_node
*child
;
1560 struct resource
*res
;
1562 st_pctl_dt_child_count(info
, np
);
1563 if (!info
->nbanks
) {
1564 dev_err(&pdev
->dev
, "you need atleast one gpio bank\n");
1568 dev_info(&pdev
->dev
, "nbanks = %d\n", info
->nbanks
);
1569 dev_info(&pdev
->dev
, "nfunctions = %d\n", info
->nfunctions
);
1570 dev_info(&pdev
->dev
, "ngroups = %d\n", info
->ngroups
);
1572 info
->functions
= devm_kzalloc(&pdev
->dev
,
1573 info
->nfunctions
* sizeof(*info
->functions
), GFP_KERNEL
);
1575 info
->groups
= devm_kzalloc(&pdev
->dev
,
1576 info
->ngroups
* sizeof(*info
->groups
) , GFP_KERNEL
);
1578 info
->banks
= devm_kzalloc(&pdev
->dev
,
1579 info
->nbanks
* sizeof(*info
->banks
), GFP_KERNEL
);
1581 if (!info
->functions
|| !info
->groups
|| !info
->banks
)
1584 info
->regmap
= syscon_regmap_lookup_by_phandle(np
, "st,syscfg");
1585 if (IS_ERR(info
->regmap
)) {
1586 dev_err(info
->dev
, "No syscfg phandle specified\n");
1587 return PTR_ERR(info
->regmap
);
1589 info
->data
= of_match_node(st_pctl_of_match
, np
)->data
;
1591 irq
= platform_get_irq(pdev
, 0);
1594 res
= platform_get_resource_byname(pdev
,
1595 IORESOURCE_MEM
, "irqmux");
1596 info
->irqmux_base
= devm_ioremap_resource(&pdev
->dev
, res
);
1598 if (IS_ERR(info
->irqmux_base
))
1599 return PTR_ERR(info
->irqmux_base
);
1601 irq_set_chained_handler(irq
, st_gpio_irqmux_handler
);
1602 irq_set_handler_data(irq
, info
);
1606 pctl_desc
->npins
= info
->nbanks
* ST_GPIO_PINS_PER_BANK
;
1607 pdesc
= devm_kzalloc(&pdev
->dev
,
1608 sizeof(*pdesc
) * pctl_desc
->npins
, GFP_KERNEL
);
1612 pctl_desc
->pins
= pdesc
;
1615 for_each_child_of_node(np
, child
) {
1616 if (of_property_read_bool(child
, "gpio-controller")) {
1617 const char *bank_name
= NULL
;
1618 ret
= st_gpiolib_register_bank(info
, bank
, child
);
1622 k
= info
->banks
[bank
].range
.pin_base
;
1623 bank_name
= info
->banks
[bank
].range
.name
;
1624 for (j
= 0; j
< ST_GPIO_PINS_PER_BANK
; j
++, k
++) {
1626 pdesc
->name
= kasprintf(GFP_KERNEL
, "%s[%d]",
1630 st_parse_syscfgs(info
, bank
, child
);
1633 ret
= st_pctl_parse_functions(child
, info
,
1636 dev_err(&pdev
->dev
, "No functions found.\n");
1645 static int st_pctl_probe(struct platform_device
*pdev
)
1647 struct st_pinctrl
*info
;
1648 struct pinctrl_desc
*pctl_desc
;
1651 if (!pdev
->dev
.of_node
) {
1652 dev_err(&pdev
->dev
, "device node not found.\n");
1656 pctl_desc
= devm_kzalloc(&pdev
->dev
, sizeof(*pctl_desc
), GFP_KERNEL
);
1660 info
= devm_kzalloc(&pdev
->dev
, sizeof(*info
), GFP_KERNEL
);
1664 info
->dev
= &pdev
->dev
;
1665 platform_set_drvdata(pdev
, info
);
1666 ret
= st_pctl_probe_dt(pdev
, pctl_desc
, info
);
1670 pctl_desc
->owner
= THIS_MODULE
;
1671 pctl_desc
->pctlops
= &st_pctlops
;
1672 pctl_desc
->pmxops
= &st_pmxops
;
1673 pctl_desc
->confops
= &st_confops
;
1674 pctl_desc
->name
= dev_name(&pdev
->dev
);
1676 info
->pctl
= pinctrl_register(pctl_desc
, &pdev
->dev
, info
);
1678 dev_err(&pdev
->dev
, "Failed pinctrl registration\n");
1682 for (i
= 0; i
< info
->nbanks
; i
++)
1683 pinctrl_add_gpio_range(info
->pctl
, &info
->banks
[i
].range
);
1688 static struct platform_driver st_pctl_driver
= {
1690 .name
= "st-pinctrl",
1691 .owner
= THIS_MODULE
,
1692 .of_match_table
= st_pctl_of_match
,
1694 .probe
= st_pctl_probe
,
1697 static int __init
st_pctl_init(void)
1699 return platform_driver_register(&st_pctl_driver
);
1701 arch_initcall(st_pctl_init
);