2 * Driver for the NVIDIA Tegra pinmux
4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
7 * Copyright (C) 2010 Google, Inc.
8 * Copyright (C) 2010 NVIDIA Corporation
9 * Copyright (C) 2009-2011 ST-Ericsson AB
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms and conditions of the GNU General Public License,
13 * version 2, as published by the Free Software Foundation.
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 #include <linux/err.h>
22 #include <linux/init.h>
24 #include <linux/module.h>
26 #include <linux/platform_device.h>
27 #include <linux/pinctrl/machine.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/pinctrl/pinconf.h>
31 #include <linux/slab.h>
34 #include "pinctrl-tegra.h"
35 #include "pinctrl-utils.h"
39 struct pinctrl_dev
*pctl
;
41 const struct tegra_pinctrl_soc_data
*soc
;
42 const char **group_pins
;
48 static inline u32
pmx_readl(struct tegra_pmx
*pmx
, u32 bank
, u32 reg
)
50 return readl(pmx
->regs
[bank
] + reg
);
53 static inline void pmx_writel(struct tegra_pmx
*pmx
, u32 val
, u32 bank
, u32 reg
)
55 writel(val
, pmx
->regs
[bank
] + reg
);
58 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev
*pctldev
)
60 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
62 return pmx
->soc
->ngroups
;
65 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev
*pctldev
,
68 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
70 return pmx
->soc
->groups
[group
].name
;
73 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev
*pctldev
,
75 const unsigned **pins
,
78 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
80 *pins
= pmx
->soc
->groups
[group
].pins
;
81 *num_pins
= pmx
->soc
->groups
[group
].npins
;
86 #ifdef CONFIG_DEBUG_FS
87 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev
*pctldev
,
91 seq_printf(s
, " %s", dev_name(pctldev
->dev
));
95 static const struct cfg_param
{
97 enum tegra_pinconf_param param
;
99 {"nvidia,pull", TEGRA_PINCONF_PARAM_PULL
},
100 {"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE
},
101 {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT
},
102 {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN
},
103 {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK
},
104 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET
},
105 {"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL
},
106 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE
},
107 {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT
},
108 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE
},
109 {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH
},
110 {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH
},
111 {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING
},
112 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING
},
113 {"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE
},
116 static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev
*pctldev
,
117 struct device_node
*np
,
118 struct pinctrl_map
**map
,
119 unsigned *reserved_maps
,
122 struct device
*dev
= pctldev
->dev
;
124 const char *function
;
126 unsigned long config
;
127 unsigned long *configs
= NULL
;
128 unsigned num_configs
= 0;
130 struct property
*prop
;
133 ret
= of_property_read_string(np
, "nvidia,function", &function
);
135 /* EINVAL=missing, which is fine since it's optional */
138 "could not parse property nvidia,function\n");
142 for (i
= 0; i
< ARRAY_SIZE(cfg_params
); i
++) {
143 ret
= of_property_read_u32(np
, cfg_params
[i
].property
, &val
);
145 config
= TEGRA_PINCONF_PACK(cfg_params
[i
].param
, val
);
146 ret
= pinctrl_utils_add_config(pctldev
, &configs
,
147 &num_configs
, config
);
150 /* EINVAL=missing, which is fine since it's optional */
151 } else if (ret
!= -EINVAL
) {
152 dev_err(dev
, "could not parse property %s\n",
153 cfg_params
[i
].property
);
158 if (function
!= NULL
)
162 ret
= of_property_count_strings(np
, "nvidia,pins");
164 dev_err(dev
, "could not parse property nvidia,pins\n");
169 ret
= pinctrl_utils_reserve_map(pctldev
, map
, reserved_maps
,
174 of_property_for_each_string(np
, "nvidia,pins", prop
, group
) {
176 ret
= pinctrl_utils_add_map_mux(pctldev
, map
,
177 reserved_maps
, num_maps
, group
,
184 ret
= pinctrl_utils_add_map_configs(pctldev
, map
,
185 reserved_maps
, num_maps
, group
,
186 configs
, num_configs
,
187 PIN_MAP_TYPE_CONFIGS_GROUP
);
200 static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev
*pctldev
,
201 struct device_node
*np_config
,
202 struct pinctrl_map
**map
,
205 unsigned reserved_maps
;
206 struct device_node
*np
;
213 for_each_child_of_node(np_config
, np
) {
214 ret
= tegra_pinctrl_dt_subnode_to_map(pctldev
, np
, map
,
215 &reserved_maps
, num_maps
);
217 pinctrl_utils_dt_free_map(pctldev
, *map
,
226 static const struct pinctrl_ops tegra_pinctrl_ops
= {
227 .get_groups_count
= tegra_pinctrl_get_groups_count
,
228 .get_group_name
= tegra_pinctrl_get_group_name
,
229 .get_group_pins
= tegra_pinctrl_get_group_pins
,
230 #ifdef CONFIG_DEBUG_FS
231 .pin_dbg_show
= tegra_pinctrl_pin_dbg_show
,
233 .dt_node_to_map
= tegra_pinctrl_dt_node_to_map
,
234 .dt_free_map
= pinctrl_utils_dt_free_map
,
237 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev
*pctldev
)
239 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
241 return pmx
->soc
->nfunctions
;
244 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev
*pctldev
,
247 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
249 return pmx
->soc
->functions
[function
].name
;
252 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev
*pctldev
,
254 const char * const **groups
,
255 unsigned * const num_groups
)
257 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
259 *groups
= pmx
->soc
->functions
[function
].groups
;
260 *num_groups
= pmx
->soc
->functions
[function
].ngroups
;
265 static int tegra_pinctrl_enable(struct pinctrl_dev
*pctldev
, unsigned function
,
268 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
269 const struct tegra_pingroup
*g
;
273 g
= &pmx
->soc
->groups
[group
];
275 if (WARN_ON(g
->mux_reg
< 0))
278 for (i
= 0; i
< ARRAY_SIZE(g
->funcs
); i
++) {
279 if (g
->funcs
[i
] == function
)
282 if (WARN_ON(i
== ARRAY_SIZE(g
->funcs
)))
285 val
= pmx_readl(pmx
, g
->mux_bank
, g
->mux_reg
);
286 val
&= ~(0x3 << g
->mux_bit
);
287 val
|= i
<< g
->mux_bit
;
288 pmx_writel(pmx
, val
, g
->mux_bank
, g
->mux_reg
);
293 static void tegra_pinctrl_disable(struct pinctrl_dev
*pctldev
,
294 unsigned function
, unsigned group
)
296 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
297 const struct tegra_pingroup
*g
;
300 g
= &pmx
->soc
->groups
[group
];
302 if (WARN_ON(g
->mux_reg
< 0))
305 val
= pmx_readl(pmx
, g
->mux_bank
, g
->mux_reg
);
306 val
&= ~(0x3 << g
->mux_bit
);
307 val
|= g
->func_safe
<< g
->mux_bit
;
308 pmx_writel(pmx
, val
, g
->mux_bank
, g
->mux_reg
);
311 static const struct pinmux_ops tegra_pinmux_ops
= {
312 .get_functions_count
= tegra_pinctrl_get_funcs_count
,
313 .get_function_name
= tegra_pinctrl_get_func_name
,
314 .get_function_groups
= tegra_pinctrl_get_func_groups
,
315 .enable
= tegra_pinctrl_enable
,
316 .disable
= tegra_pinctrl_disable
,
319 static int tegra_pinconf_reg(struct tegra_pmx
*pmx
,
320 const struct tegra_pingroup
*g
,
321 enum tegra_pinconf_param param
,
323 s8
*bank
, s16
*reg
, s8
*bit
, s8
*width
)
326 case TEGRA_PINCONF_PARAM_PULL
:
327 *bank
= g
->pupd_bank
;
332 case TEGRA_PINCONF_PARAM_TRISTATE
:
338 case TEGRA_PINCONF_PARAM_ENABLE_INPUT
:
339 *bank
= g
->einput_bank
;
340 *reg
= g
->einput_reg
;
341 *bit
= g
->einput_bit
;
344 case TEGRA_PINCONF_PARAM_OPEN_DRAIN
:
345 *bank
= g
->odrain_bank
;
346 *reg
= g
->odrain_reg
;
347 *bit
= g
->odrain_bit
;
350 case TEGRA_PINCONF_PARAM_LOCK
:
351 *bank
= g
->lock_bank
;
356 case TEGRA_PINCONF_PARAM_IORESET
:
357 *bank
= g
->ioreset_bank
;
358 *reg
= g
->ioreset_reg
;
359 *bit
= g
->ioreset_bit
;
362 case TEGRA_PINCONF_PARAM_RCV_SEL
:
363 *bank
= g
->rcv_sel_bank
;
364 *reg
= g
->rcv_sel_reg
;
365 *bit
= g
->rcv_sel_bit
;
368 case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE
:
374 case TEGRA_PINCONF_PARAM_SCHMITT
:
377 *bit
= g
->schmitt_bit
;
380 case TEGRA_PINCONF_PARAM_LOW_POWER_MODE
:
386 case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH
:
390 *width
= g
->drvdn_width
;
392 case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH
:
396 *width
= g
->drvup_width
;
398 case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING
:
402 *width
= g
->slwf_width
;
404 case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING
:
408 *width
= g
->slwr_width
;
410 case TEGRA_PINCONF_PARAM_DRIVE_TYPE
:
411 *bank
= g
->drvtype_bank
;
412 *reg
= g
->drvtype_reg
;
413 *bit
= g
->drvtype_bit
;
417 dev_err(pmx
->dev
, "Invalid config param %04x\n", param
);
424 "Config param %04x not supported on group %s\n",
432 static int tegra_pinconf_get(struct pinctrl_dev
*pctldev
,
433 unsigned pin
, unsigned long *config
)
435 dev_err(pctldev
->dev
, "pin_config_get op not supported\n");
439 static int tegra_pinconf_set(struct pinctrl_dev
*pctldev
,
440 unsigned pin
, unsigned long *configs
,
441 unsigned num_configs
)
443 dev_err(pctldev
->dev
, "pin_config_set op not supported\n");
447 static int tegra_pinconf_group_get(struct pinctrl_dev
*pctldev
,
448 unsigned group
, unsigned long *config
)
450 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
451 enum tegra_pinconf_param param
= TEGRA_PINCONF_UNPACK_PARAM(*config
);
453 const struct tegra_pingroup
*g
;
459 g
= &pmx
->soc
->groups
[group
];
461 ret
= tegra_pinconf_reg(pmx
, g
, param
, true, &bank
, ®
, &bit
,
466 val
= pmx_readl(pmx
, bank
, reg
);
467 mask
= (1 << width
) - 1;
468 arg
= (val
>> bit
) & mask
;
470 *config
= TEGRA_PINCONF_PACK(param
, arg
);
475 static int tegra_pinconf_group_set(struct pinctrl_dev
*pctldev
,
476 unsigned group
, unsigned long *configs
,
477 unsigned num_configs
)
479 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
480 enum tegra_pinconf_param param
;
482 const struct tegra_pingroup
*g
;
488 g
= &pmx
->soc
->groups
[group
];
490 for (i
= 0; i
< num_configs
; i
++) {
491 param
= TEGRA_PINCONF_UNPACK_PARAM(configs
[i
]);
492 arg
= TEGRA_PINCONF_UNPACK_ARG(configs
[i
]);
494 ret
= tegra_pinconf_reg(pmx
, g
, param
, true, &bank
, ®
, &bit
,
499 val
= pmx_readl(pmx
, bank
, reg
);
501 /* LOCK can't be cleared */
502 if (param
== TEGRA_PINCONF_PARAM_LOCK
) {
503 if ((val
& BIT(bit
)) && !arg
) {
504 dev_err(pctldev
->dev
, "LOCK bit cannot be cleared\n");
509 /* Special-case Boolean values; allow any non-zero as true */
513 /* Range-check user-supplied value */
514 mask
= (1 << width
) - 1;
516 dev_err(pctldev
->dev
,
517 "config %lx: %x too big for %d bit register\n",
518 configs
[i
], arg
, width
);
522 /* Update register */
523 val
&= ~(mask
<< bit
);
525 pmx_writel(pmx
, val
, bank
, reg
);
526 } /* for each config */
531 #ifdef CONFIG_DEBUG_FS
532 static void tegra_pinconf_dbg_show(struct pinctrl_dev
*pctldev
,
533 struct seq_file
*s
, unsigned offset
)
537 static const char *strip_prefix(const char *s
)
539 const char *comma
= strchr(s
, ',');
546 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev
*pctldev
,
547 struct seq_file
*s
, unsigned group
)
549 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
550 const struct tegra_pingroup
*g
;
556 g
= &pmx
->soc
->groups
[group
];
558 for (i
= 0; i
< ARRAY_SIZE(cfg_params
); i
++) {
559 ret
= tegra_pinconf_reg(pmx
, g
, cfg_params
[i
].param
, false,
560 &bank
, ®
, &bit
, &width
);
564 val
= pmx_readl(pmx
, bank
, reg
);
566 val
&= (1 << width
) - 1;
568 seq_printf(s
, "\n\t%s=%u",
569 strip_prefix(cfg_params
[i
].property
), val
);
573 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev
*pctldev
,
575 unsigned long config
)
577 enum tegra_pinconf_param param
= TEGRA_PINCONF_UNPACK_PARAM(config
);
578 u16 arg
= TEGRA_PINCONF_UNPACK_ARG(config
);
579 const char *pname
= "unknown";
582 for (i
= 0; i
< ARRAY_SIZE(cfg_params
); i
++) {
583 if (cfg_params
[i
].param
== param
) {
584 pname
= cfg_params
[i
].property
;
589 seq_printf(s
, "%s=%d", strip_prefix(pname
), arg
);
593 static const struct pinconf_ops tegra_pinconf_ops
= {
594 .pin_config_get
= tegra_pinconf_get
,
595 .pin_config_set
= tegra_pinconf_set
,
596 .pin_config_group_get
= tegra_pinconf_group_get
,
597 .pin_config_group_set
= tegra_pinconf_group_set
,
598 #ifdef CONFIG_DEBUG_FS
599 .pin_config_dbg_show
= tegra_pinconf_dbg_show
,
600 .pin_config_group_dbg_show
= tegra_pinconf_group_dbg_show
,
601 .pin_config_config_dbg_show
= tegra_pinconf_config_dbg_show
,
605 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range
= {
606 .name
= "Tegra GPIOs",
611 static struct pinctrl_desc tegra_pinctrl_desc
= {
612 .pctlops
= &tegra_pinctrl_ops
,
613 .pmxops
= &tegra_pinmux_ops
,
614 .confops
= &tegra_pinconf_ops
,
615 .owner
= THIS_MODULE
,
618 int tegra_pinctrl_probe(struct platform_device
*pdev
,
619 const struct tegra_pinctrl_soc_data
*soc_data
)
621 struct tegra_pmx
*pmx
;
622 struct resource
*res
;
624 const char **group_pins
;
627 pmx
= devm_kzalloc(&pdev
->dev
, sizeof(*pmx
), GFP_KERNEL
);
629 dev_err(&pdev
->dev
, "Can't alloc tegra_pmx\n");
632 pmx
->dev
= &pdev
->dev
;
636 * Each mux group will appear in 4 functions' list of groups.
637 * This over-allocates slightly, since not all groups are mux groups.
639 pmx
->group_pins
= devm_kzalloc(&pdev
->dev
,
640 soc_data
->ngroups
* 4 * sizeof(*pmx
->group_pins
),
642 if (!pmx
->group_pins
)
645 group_pins
= pmx
->group_pins
;
646 for (fn
= 0; fn
< soc_data
->nfunctions
; fn
++) {
647 struct tegra_function
*func
= &soc_data
->functions
[fn
];
649 func
->groups
= group_pins
;
651 for (gn
= 0; gn
< soc_data
->ngroups
; gn
++) {
652 const struct tegra_pingroup
*g
= &soc_data
->groups
[gn
];
654 if (g
->mux_reg
== -1)
657 for (gfn
= 0; gfn
< 4; gfn
++)
658 if (g
->funcs
[gfn
] == fn
)
663 BUG_ON(group_pins
- pmx
->group_pins
>=
664 soc_data
->ngroups
* 4);
665 *group_pins
++ = g
->name
;
670 tegra_pinctrl_gpio_range
.npins
= pmx
->soc
->ngpios
;
671 tegra_pinctrl_desc
.name
= dev_name(&pdev
->dev
);
672 tegra_pinctrl_desc
.pins
= pmx
->soc
->pins
;
673 tegra_pinctrl_desc
.npins
= pmx
->soc
->npins
;
676 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, i
);
682 pmx
->regs
= devm_kzalloc(&pdev
->dev
, pmx
->nbanks
* sizeof(*pmx
->regs
),
685 dev_err(&pdev
->dev
, "Can't alloc regs pointer\n");
689 for (i
= 0; i
< pmx
->nbanks
; i
++) {
690 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, i
);
691 pmx
->regs
[i
] = devm_ioremap_resource(&pdev
->dev
, res
);
692 if (IS_ERR(pmx
->regs
[i
]))
693 return PTR_ERR(pmx
->regs
[i
]);
696 pmx
->pctl
= pinctrl_register(&tegra_pinctrl_desc
, &pdev
->dev
, pmx
);
698 dev_err(&pdev
->dev
, "Couldn't register pinctrl driver\n");
702 pinctrl_add_gpio_range(pmx
->pctl
, &tegra_pinctrl_gpio_range
);
704 platform_set_drvdata(pdev
, pmx
);
706 dev_dbg(&pdev
->dev
, "Probed Tegra pinctrl driver\n");
710 EXPORT_SYMBOL_GPL(tegra_pinctrl_probe
);
712 int tegra_pinctrl_remove(struct platform_device
*pdev
)
714 struct tegra_pmx
*pmx
= platform_get_drvdata(pdev
);
716 pinctrl_unregister(pmx
->pctl
);
720 EXPORT_SYMBOL_GPL(tegra_pinctrl_remove
);