2 * Driver for the NVIDIA Tegra pinmux
4 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
7 * Copyright (C) 2010 Google, Inc.
8 * Copyright (C) 2010 NVIDIA Corporation
9 * Copyright (C) 2009-2011 ST-Ericsson AB
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms and conditions of the GNU General Public License,
13 * version 2, as published by the Free Software Foundation.
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 #include <linux/err.h>
22 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/pinctrl/machine.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/pinctrl/pinconf.h>
30 #include <linux/slab.h>
32 #include <mach/pinconf-tegra.h>
34 #include "pinctrl-tegra.h"
36 #define DRIVER_NAME "tegra-pinmux-disabled"
40 struct pinctrl_dev
*pctl
;
42 const struct tegra_pinctrl_soc_data
*soc
;
48 static inline u32
pmx_readl(struct tegra_pmx
*pmx
, u32 bank
, u32 reg
)
50 return readl(pmx
->regs
[bank
] + reg
);
53 static inline void pmx_writel(struct tegra_pmx
*pmx
, u32 val
, u32 bank
, u32 reg
)
55 writel(val
, pmx
->regs
[bank
] + reg
);
58 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev
*pctldev
)
60 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
62 return pmx
->soc
->ngroups
;
65 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev
*pctldev
,
68 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
70 return pmx
->soc
->groups
[group
].name
;
73 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev
*pctldev
,
75 const unsigned **pins
,
78 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
80 *pins
= pmx
->soc
->groups
[group
].pins
;
81 *num_pins
= pmx
->soc
->groups
[group
].npins
;
86 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev
*pctldev
,
90 seq_printf(s
, " " DRIVER_NAME
);
93 static int reserve_map(struct pinctrl_map
**map
, unsigned *reserved_maps
,
94 unsigned *num_maps
, unsigned reserve
)
96 unsigned old_num
= *reserved_maps
;
97 unsigned new_num
= *num_maps
+ reserve
;
98 struct pinctrl_map
*new_map
;
100 if (old_num
>= new_num
)
103 new_map
= krealloc(*map
, sizeof(*new_map
) * new_num
, GFP_KERNEL
);
107 memset(new_map
+ old_num
, 0, (new_num
- old_num
) * sizeof(*new_map
));
110 *reserved_maps
= new_num
;
115 static int add_map_mux(struct pinctrl_map
**map
, unsigned *reserved_maps
,
116 unsigned *num_maps
, const char *group
,
117 const char *function
)
119 if (*num_maps
== *reserved_maps
)
122 (*map
)[*num_maps
].type
= PIN_MAP_TYPE_MUX_GROUP
;
123 (*map
)[*num_maps
].data
.mux
.group
= group
;
124 (*map
)[*num_maps
].data
.mux
.function
= function
;
130 static int add_map_configs(struct pinctrl_map
**map
, unsigned *reserved_maps
,
131 unsigned *num_maps
, const char *group
,
132 unsigned long *configs
, unsigned num_configs
)
134 unsigned long *dup_configs
;
136 if (*num_maps
== *reserved_maps
)
139 dup_configs
= kmemdup(configs
, num_configs
* sizeof(*dup_configs
),
144 (*map
)[*num_maps
].type
= PIN_MAP_TYPE_CONFIGS_GROUP
;
145 (*map
)[*num_maps
].data
.configs
.group_or_pin
= group
;
146 (*map
)[*num_maps
].data
.configs
.configs
= dup_configs
;
147 (*map
)[*num_maps
].data
.configs
.num_configs
= num_configs
;
153 static int add_config(unsigned long **configs
, unsigned *num_configs
,
154 unsigned long config
)
156 unsigned old_num
= *num_configs
;
157 unsigned new_num
= old_num
+ 1;
158 unsigned long *new_configs
;
160 new_configs
= krealloc(*configs
, sizeof(*new_configs
) * new_num
,
165 new_configs
[old_num
] = config
;
167 *configs
= new_configs
;
168 *num_configs
= new_num
;
173 void tegra_pinctrl_dt_free_map(struct pinctrl_dev
*pctldev
,
174 struct pinctrl_map
*map
, unsigned num_maps
)
178 for (i
= 0; i
< num_maps
; i
++)
179 if (map
[i
].type
== PIN_MAP_TYPE_CONFIGS_GROUP
)
180 kfree(map
[i
].data
.configs
.configs
);
185 static const struct cfg_param
{
186 const char *property
;
187 enum tegra_pinconf_param param
;
189 {"nvidia,pull", TEGRA_PINCONF_PARAM_PULL
},
190 {"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE
},
191 {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT
},
192 {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN
},
193 {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK
},
194 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET
},
195 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE
},
196 {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT
},
197 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE
},
198 {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH
},
199 {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH
},
200 {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING
},
201 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING
},
204 int tegra_pinctrl_dt_subnode_to_map(struct device_node
*np
,
205 struct pinctrl_map
**map
,
206 unsigned *reserved_maps
,
210 const char *function
;
212 unsigned long config
;
213 unsigned long *configs
= NULL
;
214 unsigned num_configs
= 0;
216 struct property
*prop
;
219 ret
= of_property_read_string(np
, "nvidia,function", &function
);
223 for (i
= 0; i
< ARRAY_SIZE(cfg_params
); i
++) {
224 ret
= of_property_read_u32(np
, cfg_params
[i
].property
, &val
);
226 config
= TEGRA_PINCONF_PACK(cfg_params
[i
].param
, val
);
227 ret
= add_config(&configs
, &num_configs
, config
);
234 if (function
!= NULL
)
238 ret
= of_property_count_strings(np
, "nvidia,pins");
243 ret
= reserve_map(map
, reserved_maps
, num_maps
, reserve
);
247 of_property_for_each_string(np
, "nvidia,pins", prop
, group
) {
249 ret
= add_map_mux(map
, reserved_maps
, num_maps
,
256 ret
= add_map_configs(map
, reserved_maps
, num_maps
,
257 group
, configs
, num_configs
);
270 int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev
*pctldev
,
271 struct device_node
*np_config
,
272 struct pinctrl_map
**map
, unsigned *num_maps
)
274 unsigned reserved_maps
;
275 struct device_node
*np
;
282 for_each_child_of_node(np_config
, np
) {
283 ret
= tegra_pinctrl_dt_subnode_to_map(np
, map
, &reserved_maps
,
286 tegra_pinctrl_dt_free_map(pctldev
, *map
, *num_maps
);
294 static struct pinctrl_ops tegra_pinctrl_ops
= {
295 .get_groups_count
= tegra_pinctrl_get_groups_count
,
296 .get_group_name
= tegra_pinctrl_get_group_name
,
297 .get_group_pins
= tegra_pinctrl_get_group_pins
,
298 .pin_dbg_show
= tegra_pinctrl_pin_dbg_show
,
299 .dt_node_to_map
= tegra_pinctrl_dt_node_to_map
,
300 .dt_free_map
= tegra_pinctrl_dt_free_map
,
303 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev
*pctldev
)
305 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
307 return pmx
->soc
->nfunctions
;
310 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev
*pctldev
,
313 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
315 return pmx
->soc
->functions
[function
].name
;
318 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev
*pctldev
,
320 const char * const **groups
,
321 unsigned * const num_groups
)
323 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
325 *groups
= pmx
->soc
->functions
[function
].groups
;
326 *num_groups
= pmx
->soc
->functions
[function
].ngroups
;
331 static int tegra_pinctrl_enable(struct pinctrl_dev
*pctldev
, unsigned function
,
334 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
335 const struct tegra_pingroup
*g
;
339 g
= &pmx
->soc
->groups
[group
];
344 for (i
= 0; i
< ARRAY_SIZE(g
->funcs
); i
++) {
345 if (g
->funcs
[i
] == function
)
348 if (i
== ARRAY_SIZE(g
->funcs
))
351 val
= pmx_readl(pmx
, g
->mux_bank
, g
->mux_reg
);
352 val
&= ~(0x3 << g
->mux_bit
);
353 val
|= i
<< g
->mux_bit
;
354 pmx_writel(pmx
, val
, g
->mux_bank
, g
->mux_reg
);
359 static void tegra_pinctrl_disable(struct pinctrl_dev
*pctldev
,
360 unsigned function
, unsigned group
)
362 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
363 const struct tegra_pingroup
*g
;
366 g
= &pmx
->soc
->groups
[group
];
371 val
= pmx_readl(pmx
, g
->mux_bank
, g
->mux_reg
);
372 val
&= ~(0x3 << g
->mux_bit
);
373 val
|= g
->func_safe
<< g
->mux_bit
;
374 pmx_writel(pmx
, val
, g
->mux_bank
, g
->mux_reg
);
377 static struct pinmux_ops tegra_pinmux_ops
= {
378 .get_functions_count
= tegra_pinctrl_get_funcs_count
,
379 .get_function_name
= tegra_pinctrl_get_func_name
,
380 .get_function_groups
= tegra_pinctrl_get_func_groups
,
381 .enable
= tegra_pinctrl_enable
,
382 .disable
= tegra_pinctrl_disable
,
385 static int tegra_pinconf_reg(struct tegra_pmx
*pmx
,
386 const struct tegra_pingroup
*g
,
387 enum tegra_pinconf_param param
,
388 s8
*bank
, s16
*reg
, s8
*bit
, s8
*width
)
391 case TEGRA_PINCONF_PARAM_PULL
:
392 *bank
= g
->pupd_bank
;
397 case TEGRA_PINCONF_PARAM_TRISTATE
:
403 case TEGRA_PINCONF_PARAM_ENABLE_INPUT
:
404 *bank
= g
->einput_bank
;
405 *reg
= g
->einput_reg
;
406 *bit
= g
->einput_bit
;
409 case TEGRA_PINCONF_PARAM_OPEN_DRAIN
:
410 *bank
= g
->odrain_bank
;
411 *reg
= g
->odrain_reg
;
412 *bit
= g
->odrain_bit
;
415 case TEGRA_PINCONF_PARAM_LOCK
:
416 *bank
= g
->lock_bank
;
421 case TEGRA_PINCONF_PARAM_IORESET
:
422 *bank
= g
->ioreset_bank
;
423 *reg
= g
->ioreset_reg
;
424 *bit
= g
->ioreset_bit
;
427 case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE
:
433 case TEGRA_PINCONF_PARAM_SCHMITT
:
436 *bit
= g
->schmitt_bit
;
439 case TEGRA_PINCONF_PARAM_LOW_POWER_MODE
:
445 case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH
:
449 *width
= g
->drvdn_width
;
451 case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH
:
455 *width
= g
->drvup_width
;
457 case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING
:
461 *width
= g
->slwf_width
;
463 case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING
:
467 *width
= g
->slwr_width
;
470 dev_err(pmx
->dev
, "Invalid config param %04x\n", param
);
476 "Config param %04x not supported on group %s\n",
484 static int tegra_pinconf_get(struct pinctrl_dev
*pctldev
,
485 unsigned pin
, unsigned long *config
)
490 static int tegra_pinconf_set(struct pinctrl_dev
*pctldev
,
491 unsigned pin
, unsigned long config
)
496 static int tegra_pinconf_group_get(struct pinctrl_dev
*pctldev
,
497 unsigned group
, unsigned long *config
)
499 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
500 enum tegra_pinconf_param param
= TEGRA_PINCONF_UNPACK_PARAM(*config
);
502 const struct tegra_pingroup
*g
;
508 g
= &pmx
->soc
->groups
[group
];
510 ret
= tegra_pinconf_reg(pmx
, g
, param
, &bank
, ®
, &bit
, &width
);
514 val
= pmx_readl(pmx
, bank
, reg
);
515 mask
= (1 << width
) - 1;
516 arg
= (val
>> bit
) & mask
;
518 *config
= TEGRA_PINCONF_PACK(param
, arg
);
523 static int tegra_pinconf_group_set(struct pinctrl_dev
*pctldev
,
524 unsigned group
, unsigned long config
)
526 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
527 enum tegra_pinconf_param param
= TEGRA_PINCONF_UNPACK_PARAM(config
);
528 u16 arg
= TEGRA_PINCONF_UNPACK_ARG(config
);
529 const struct tegra_pingroup
*g
;
535 g
= &pmx
->soc
->groups
[group
];
537 ret
= tegra_pinconf_reg(pmx
, g
, param
, &bank
, ®
, &bit
, &width
);
541 val
= pmx_readl(pmx
, bank
, reg
);
543 /* LOCK can't be cleared */
544 if (param
== TEGRA_PINCONF_PARAM_LOCK
) {
545 if ((val
& BIT(bit
)) && !arg
)
549 /* Special-case Boolean values; allow any non-zero as true */
553 /* Range-check user-supplied value */
554 mask
= (1 << width
) - 1;
558 /* Update register */
559 val
&= ~(mask
<< bit
);
561 pmx_writel(pmx
, val
, bank
, reg
);
566 static void tegra_pinconf_dbg_show(struct pinctrl_dev
*pctldev
,
567 struct seq_file
*s
, unsigned offset
)
571 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev
*pctldev
,
572 struct seq_file
*s
, unsigned selector
)
576 struct pinconf_ops tegra_pinconf_ops
= {
577 .pin_config_get
= tegra_pinconf_get
,
578 .pin_config_set
= tegra_pinconf_set
,
579 .pin_config_group_get
= tegra_pinconf_group_get
,
580 .pin_config_group_set
= tegra_pinconf_group_set
,
581 .pin_config_dbg_show
= tegra_pinconf_dbg_show
,
582 .pin_config_group_dbg_show
= tegra_pinconf_group_dbg_show
,
585 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range
= {
586 .name
= "Tegra GPIOs",
591 static struct pinctrl_desc tegra_pinctrl_desc
= {
593 .pctlops
= &tegra_pinctrl_ops
,
594 .pmxops
= &tegra_pinmux_ops
,
595 .confops
= &tegra_pinconf_ops
,
596 .owner
= THIS_MODULE
,
599 static struct of_device_id tegra_pinctrl_of_match
[] __devinitdata
= {
600 #ifdef CONFIG_PINCTRL_TEGRA20
602 .compatible
= "nvidia,tegra20-pinmux-disabled",
603 .data
= tegra20_pinctrl_init
,
606 #ifdef CONFIG_PINCTRL_TEGRA30
608 .compatible
= "nvidia,tegra30-pinmux-disabled",
609 .data
= tegra30_pinctrl_init
,
615 static int __devinit
tegra_pinctrl_probe(struct platform_device
*pdev
)
617 const struct of_device_id
*match
;
618 tegra_pinctrl_soc_initf initf
= NULL
;
619 struct tegra_pmx
*pmx
;
620 struct resource
*res
;
623 match
= of_match_device(tegra_pinctrl_of_match
, &pdev
->dev
);
625 initf
= (tegra_pinctrl_soc_initf
)match
->data
;
626 #ifdef CONFIG_PINCTRL_TEGRA20
628 initf
= tegra20_pinctrl_init
;
632 "Could not determine SoC-specific init func\n");
636 pmx
= devm_kzalloc(&pdev
->dev
, sizeof(*pmx
), GFP_KERNEL
);
638 dev_err(&pdev
->dev
, "Can't alloc tegra_pmx\n");
641 pmx
->dev
= &pdev
->dev
;
645 tegra_pinctrl_gpio_range
.npins
= pmx
->soc
->ngpios
;
646 tegra_pinctrl_desc
.pins
= pmx
->soc
->pins
;
647 tegra_pinctrl_desc
.npins
= pmx
->soc
->npins
;
650 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, i
);
656 pmx
->regs
= devm_kzalloc(&pdev
->dev
, pmx
->nbanks
* sizeof(*pmx
->regs
),
659 dev_err(&pdev
->dev
, "Can't alloc regs pointer\n");
663 for (i
= 0; i
< pmx
->nbanks
; i
++) {
664 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, i
);
666 dev_err(&pdev
->dev
, "Missing MEM resource\n");
670 if (!devm_request_mem_region(&pdev
->dev
, res
->start
,
672 dev_name(&pdev
->dev
))) {
674 "Couldn't request MEM resource %d\n", i
);
678 pmx
->regs
[i
] = devm_ioremap(&pdev
->dev
, res
->start
,
681 dev_err(&pdev
->dev
, "Couldn't ioremap regs %d\n", i
);
686 pmx
->pctl
= pinctrl_register(&tegra_pinctrl_desc
, &pdev
->dev
, pmx
);
687 if (IS_ERR(pmx
->pctl
)) {
688 dev_err(&pdev
->dev
, "Couldn't register pinctrl driver\n");
689 return PTR_ERR(pmx
->pctl
);
692 pinctrl_add_gpio_range(pmx
->pctl
, &tegra_pinctrl_gpio_range
);
694 platform_set_drvdata(pdev
, pmx
);
696 dev_dbg(&pdev
->dev
, "Probed Tegra pinctrl driver\n");
701 static int __devexit
tegra_pinctrl_remove(struct platform_device
*pdev
)
703 struct tegra_pmx
*pmx
= platform_get_drvdata(pdev
);
705 pinctrl_remove_gpio_range(pmx
->pctl
, &tegra_pinctrl_gpio_range
);
706 pinctrl_unregister(pmx
->pctl
);
711 static struct platform_driver tegra_pinctrl_driver
= {
714 .owner
= THIS_MODULE
,
715 .of_match_table
= tegra_pinctrl_of_match
,
717 .probe
= tegra_pinctrl_probe
,
718 .remove
= __devexit_p(tegra_pinctrl_remove
),
721 static int __init
tegra_pinctrl_init(void)
723 return platform_driver_register(&tegra_pinctrl_driver
);
725 arch_initcall(tegra_pinctrl_init
);
727 static void __exit
tegra_pinctrl_exit(void)
729 platform_driver_unregister(&tegra_pinctrl_driver
);
731 module_exit(tegra_pinctrl_exit
);
733 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
734 MODULE_DESCRIPTION("NVIDIA Tegra pinctrl driver");
735 MODULE_LICENSE("GPL v2");
736 MODULE_DEVICE_TABLE(of
, tegra_pinctrl_of_match
);