2 * linux/drivers/pinctrl/pinmux-xway.c
3 * based on linux/drivers/pinctrl/pinmux-pxa910.c
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
9 * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/of_platform.h>
15 #include <linux/of_address.h>
16 #include <linux/of_gpio.h>
17 #include <linux/ioport.h>
19 #include <linux/device.h>
20 #include <linux/module.h>
22 #include <linux/platform_device.h>
24 #include "pinctrl-lantiq.h"
26 #include <lantiq_soc.h>
28 /* we have 3 1/2 banks of 16 bit each */
31 #define PORT(x) (x / PINS)
32 #define PORT_PIN(x) (x % PINS)
34 /* we have 2 mux bits that can be set for each pin */
39 * each bank has this offset apart from the 1/2 bank that is mixed into the
44 /* these are the offsets to our registers */
45 #define GPIO_BASE(p) (REG_OFF * PORT(p))
46 #define GPIO_OUT(p) GPIO_BASE(p)
47 #define GPIO_IN(p) (GPIO_BASE(p) + 0x04)
48 #define GPIO_DIR(p) (GPIO_BASE(p) + 0x08)
49 #define GPIO_ALT0(p) (GPIO_BASE(p) + 0x0C)
50 #define GPIO_ALT1(p) (GPIO_BASE(p) + 0x10)
51 #define GPIO_OD(p) (GPIO_BASE(p) + 0x14)
52 #define GPIO_PUDSEL(p) (GPIO_BASE(p) + 0x1c)
53 #define GPIO_PUDEN(p) (GPIO_BASE(p) + 0x20)
55 /* the 1/2 port needs special offsets for some registers */
56 #define GPIO3_OD (GPIO_BASE(0) + 0x24)
57 #define GPIO3_PUDSEL (GPIO_BASE(0) + 0x28)
58 #define GPIO3_PUDEN (GPIO_BASE(0) + 0x2C)
59 #define GPIO3_ALT1 (GPIO_BASE(PINS) + 0x24)
61 /* macros to help us access the registers */
62 #define gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & BIT(p)))
63 #define gpio_setbit(m, r, p) ltq_w32_mask(0, BIT(p), m + r)
64 #define gpio_clearbit(m, r, p) ltq_w32_mask(BIT(p), 0, m + r)
66 #define MFP_XWAY(a, f0, f1, f2, f3) \
78 #define GRP_MUX(a, m, p) \
79 { .name = a, .mux = XWAY_MUX_##m, .pins = p, .npins = ARRAY_SIZE(p), }
81 #define FUNC_MUX(f, m) \
82 { .func = f, .mux = XWAY_MUX_##m, }
84 #define XWAY_MAX_PIN 32
85 #define XR9_MAX_PIN 56
106 XWAY_MUX_NONE
= 0xffff,
109 static const struct ltq_mfp_pin xway_mfp
[] = {
110 /* pin f0 f1 f2 f3 */
111 MFP_XWAY(GPIO0
, GPIO
, EXIN
, NONE
, TDM
),
112 MFP_XWAY(GPIO1
, GPIO
, EXIN
, NONE
, NONE
),
113 MFP_XWAY(GPIO2
, GPIO
, CGU
, EXIN
, NONE
),
114 MFP_XWAY(GPIO3
, GPIO
, CGU
, NONE
, PCI
),
115 MFP_XWAY(GPIO4
, GPIO
, STP
, NONE
, ASC
),
116 MFP_XWAY(GPIO5
, GPIO
, STP
, NONE
, NONE
),
117 MFP_XWAY(GPIO6
, GPIO
, STP
, GPT
, ASC
),
118 MFP_XWAY(GPIO7
, GPIO
, CGU
, PCI
, NONE
),
119 MFP_XWAY(GPIO8
, GPIO
, CGU
, NMI
, NONE
),
120 MFP_XWAY(GPIO9
, GPIO
, ASC
, SPI
, EXIN
),
121 MFP_XWAY(GPIO10
, GPIO
, ASC
, SPI
, NONE
),
122 MFP_XWAY(GPIO11
, GPIO
, ASC
, PCI
, SPI
),
123 MFP_XWAY(GPIO12
, GPIO
, ASC
, NONE
, NONE
),
124 MFP_XWAY(GPIO13
, GPIO
, EBU
, SPI
, NONE
),
125 MFP_XWAY(GPIO14
, GPIO
, CGU
, PCI
, NONE
),
126 MFP_XWAY(GPIO15
, GPIO
, SPI
, JTAG
, NONE
),
127 MFP_XWAY(GPIO16
, GPIO
, SPI
, NONE
, JTAG
),
128 MFP_XWAY(GPIO17
, GPIO
, SPI
, NONE
, JTAG
),
129 MFP_XWAY(GPIO18
, GPIO
, SPI
, NONE
, JTAG
),
130 MFP_XWAY(GPIO19
, GPIO
, PCI
, NONE
, NONE
),
131 MFP_XWAY(GPIO20
, GPIO
, JTAG
, NONE
, NONE
),
132 MFP_XWAY(GPIO21
, GPIO
, PCI
, EBU
, GPT
),
133 MFP_XWAY(GPIO22
, GPIO
, SPI
, NONE
, NONE
),
134 MFP_XWAY(GPIO23
, GPIO
, EBU
, PCI
, STP
),
135 MFP_XWAY(GPIO24
, GPIO
, EBU
, TDM
, PCI
),
136 MFP_XWAY(GPIO25
, GPIO
, TDM
, NONE
, ASC
),
137 MFP_XWAY(GPIO26
, GPIO
, EBU
, NONE
, TDM
),
138 MFP_XWAY(GPIO27
, GPIO
, TDM
, NONE
, ASC
),
139 MFP_XWAY(GPIO28
, GPIO
, GPT
, NONE
, NONE
),
140 MFP_XWAY(GPIO29
, GPIO
, PCI
, NONE
, NONE
),
141 MFP_XWAY(GPIO30
, GPIO
, PCI
, NONE
, NONE
),
142 MFP_XWAY(GPIO31
, GPIO
, EBU
, PCI
, NONE
),
143 MFP_XWAY(GPIO32
, GPIO
, NONE
, NONE
, EBU
),
144 MFP_XWAY(GPIO33
, GPIO
, NONE
, NONE
, EBU
),
145 MFP_XWAY(GPIO34
, GPIO
, NONE
, NONE
, EBU
),
146 MFP_XWAY(GPIO35
, GPIO
, NONE
, NONE
, EBU
),
147 MFP_XWAY(GPIO36
, GPIO
, SIN
, NONE
, EBU
),
148 MFP_XWAY(GPIO37
, GPIO
, PCI
, NONE
, NONE
),
149 MFP_XWAY(GPIO38
, GPIO
, PCI
, NONE
, NONE
),
150 MFP_XWAY(GPIO39
, GPIO
, EXIN
, NONE
, NONE
),
151 MFP_XWAY(GPIO40
, GPIO
, NONE
, NONE
, NONE
),
152 MFP_XWAY(GPIO41
, GPIO
, NONE
, NONE
, NONE
),
153 MFP_XWAY(GPIO42
, GPIO
, MDIO
, NONE
, NONE
),
154 MFP_XWAY(GPIO43
, GPIO
, MDIO
, NONE
, NONE
),
155 MFP_XWAY(GPIO44
, GPIO
, NONE
, NONE
, SIN
),
156 MFP_XWAY(GPIO45
, GPIO
, NONE
, NONE
, SIN
),
157 MFP_XWAY(GPIO46
, GPIO
, NONE
, NONE
, EXIN
),
158 MFP_XWAY(GPIO47
, GPIO
, NONE
, NONE
, SIN
),
159 MFP_XWAY(GPIO48
, GPIO
, EBU
, NONE
, NONE
),
160 MFP_XWAY(GPIO49
, GPIO
, EBU
, NONE
, NONE
),
161 MFP_XWAY(GPIO50
, GPIO
, NONE
, NONE
, NONE
),
162 MFP_XWAY(GPIO51
, GPIO
, NONE
, NONE
, NONE
),
163 MFP_XWAY(GPIO52
, GPIO
, NONE
, NONE
, NONE
),
164 MFP_XWAY(GPIO53
, GPIO
, NONE
, NONE
, NONE
),
165 MFP_XWAY(GPIO54
, GPIO
, NONE
, NONE
, NONE
),
166 MFP_XWAY(GPIO55
, GPIO
, NONE
, NONE
, NONE
),
169 static const struct ltq_mfp_pin ase_mfp
[] = {
170 /* pin f0 f1 f2 f3 */
171 MFP_XWAY(GPIO0
, GPIO
, EXIN
, MII
, TDM
),
172 MFP_XWAY(GPIO1
, GPIO
, STP
, DFE
, EBU
),
173 MFP_XWAY(GPIO2
, GPIO
, STP
, DFE
, EPHY
),
174 MFP_XWAY(GPIO3
, GPIO
, STP
, EPHY
, EBU
),
175 MFP_XWAY(GPIO4
, GPIO
, GPT
, EPHY
, MII
),
176 MFP_XWAY(GPIO5
, GPIO
, MII
, ASC
, GPT
),
177 MFP_XWAY(GPIO6
, GPIO
, MII
, ASC
, EXIN
),
178 MFP_XWAY(GPIO7
, GPIO
, SPI
, MII
, JTAG
),
179 MFP_XWAY(GPIO8
, GPIO
, SPI
, MII
, JTAG
),
180 MFP_XWAY(GPIO9
, GPIO
, SPI
, MII
, JTAG
),
181 MFP_XWAY(GPIO10
, GPIO
, SPI
, MII
, JTAG
),
182 MFP_XWAY(GPIO11
, GPIO
, EBU
, CGU
, JTAG
),
183 MFP_XWAY(GPIO12
, GPIO
, EBU
, MII
, SDIO
),
184 MFP_XWAY(GPIO13
, GPIO
, EBU
, MII
, CGU
),
185 MFP_XWAY(GPIO14
, GPIO
, EBU
, SPI
, CGU
),
186 MFP_XWAY(GPIO15
, GPIO
, EBU
, SPI
, SDIO
),
187 MFP_XWAY(GPIO16
, GPIO
, NONE
, NONE
, NONE
),
188 MFP_XWAY(GPIO17
, GPIO
, NONE
, NONE
, NONE
),
189 MFP_XWAY(GPIO18
, GPIO
, NONE
, NONE
, NONE
),
190 MFP_XWAY(GPIO19
, GPIO
, EBU
, MII
, SDIO
),
191 MFP_XWAY(GPIO20
, GPIO
, EBU
, MII
, SDIO
),
192 MFP_XWAY(GPIO21
, GPIO
, EBU
, MII
, SDIO
),
193 MFP_XWAY(GPIO22
, GPIO
, EBU
, MII
, CGU
),
194 MFP_XWAY(GPIO23
, GPIO
, EBU
, MII
, CGU
),
195 MFP_XWAY(GPIO24
, GPIO
, EBU
, NONE
, MII
),
196 MFP_XWAY(GPIO25
, GPIO
, EBU
, MII
, GPT
),
197 MFP_XWAY(GPIO26
, GPIO
, EBU
, MII
, SDIO
),
198 MFP_XWAY(GPIO27
, GPIO
, EBU
, NONE
, MII
),
199 MFP_XWAY(GPIO28
, GPIO
, MII
, EBU
, SDIO
),
200 MFP_XWAY(GPIO29
, GPIO
, EBU
, MII
, EXIN
),
201 MFP_XWAY(GPIO30
, GPIO
, NONE
, NONE
, NONE
),
202 MFP_XWAY(GPIO31
, GPIO
, NONE
, NONE
, NONE
),
205 static const unsigned pins_jtag
[] = {GPIO15
, GPIO16
, GPIO17
, GPIO19
, GPIO35
};
206 static const unsigned pins_asc0
[] = {GPIO11
, GPIO12
};
207 static const unsigned pins_asc0_cts_rts
[] = {GPIO9
, GPIO10
};
208 static const unsigned pins_stp
[] = {GPIO4
, GPIO5
, GPIO6
};
209 static const unsigned pins_nmi
[] = {GPIO8
};
210 static const unsigned pins_mdio
[] = {GPIO42
, GPIO43
};
212 static const unsigned pins_ebu_a24
[] = {GPIO13
};
213 static const unsigned pins_ebu_clk
[] = {GPIO21
};
214 static const unsigned pins_ebu_cs1
[] = {GPIO23
};
215 static const unsigned pins_ebu_a23
[] = {GPIO24
};
216 static const unsigned pins_ebu_wait
[] = {GPIO26
};
217 static const unsigned pins_ebu_a25
[] = {GPIO31
};
218 static const unsigned pins_ebu_rdy
[] = {GPIO48
};
219 static const unsigned pins_ebu_rd
[] = {GPIO49
};
221 static const unsigned pins_nand_ale
[] = {GPIO13
};
222 static const unsigned pins_nand_cs1
[] = {GPIO23
};
223 static const unsigned pins_nand_cle
[] = {GPIO24
};
224 static const unsigned pins_nand_rdy
[] = {GPIO48
};
225 static const unsigned pins_nand_rd
[] = {GPIO49
};
227 static const unsigned pins_exin0
[] = {GPIO0
};
228 static const unsigned pins_exin1
[] = {GPIO1
};
229 static const unsigned pins_exin2
[] = {GPIO2
};
230 static const unsigned pins_exin3
[] = {GPIO39
};
231 static const unsigned pins_exin4
[] = {GPIO46
};
232 static const unsigned pins_exin5
[] = {GPIO9
};
234 static const unsigned pins_spi
[] = {GPIO16
, GPIO17
, GPIO18
};
235 static const unsigned pins_spi_cs1
[] = {GPIO15
};
236 static const unsigned pins_spi_cs2
[] = {GPIO21
};
237 static const unsigned pins_spi_cs3
[] = {GPIO13
};
238 static const unsigned pins_spi_cs4
[] = {GPIO10
};
239 static const unsigned pins_spi_cs5
[] = {GPIO9
};
240 static const unsigned pins_spi_cs6
[] = {GPIO11
};
242 static const unsigned pins_gpt1
[] = {GPIO28
};
243 static const unsigned pins_gpt2
[] = {GPIO21
};
244 static const unsigned pins_gpt3
[] = {GPIO6
};
246 static const unsigned pins_clkout0
[] = {GPIO8
};
247 static const unsigned pins_clkout1
[] = {GPIO7
};
248 static const unsigned pins_clkout2
[] = {GPIO3
};
249 static const unsigned pins_clkout3
[] = {GPIO2
};
251 static const unsigned pins_pci_gnt1
[] = {GPIO30
};
252 static const unsigned pins_pci_gnt2
[] = {GPIO23
};
253 static const unsigned pins_pci_gnt3
[] = {GPIO19
};
254 static const unsigned pins_pci_gnt4
[] = {GPIO38
};
255 static const unsigned pins_pci_req1
[] = {GPIO29
};
256 static const unsigned pins_pci_req2
[] = {GPIO31
};
257 static const unsigned pins_pci_req3
[] = {GPIO3
};
258 static const unsigned pins_pci_req4
[] = {GPIO37
};
260 static const unsigned ase_pins_jtag
[] = {GPIO7
, GPIO8
, GPIO9
, GPIO10
, GPIO11
};
261 static const unsigned ase_pins_asc
[] = {GPIO5
, GPIO6
};
262 static const unsigned ase_pins_stp
[] = {GPIO1
, GPIO2
, GPIO3
};
263 static const unsigned ase_pins_ephy
[] = {GPIO2
, GPIO3
, GPIO4
};
264 static const unsigned ase_pins_dfe
[] = {GPIO1
, GPIO2
};
266 static const unsigned ase_pins_spi
[] = {GPIO8
, GPIO9
, GPIO10
};
267 static const unsigned ase_pins_spi_cs1
[] = {GPIO7
};
268 static const unsigned ase_pins_spi_cs2
[] = {GPIO15
};
269 static const unsigned ase_pins_spi_cs3
[] = {GPIO14
};
271 static const unsigned ase_pins_exin0
[] = {GPIO6
};
272 static const unsigned ase_pins_exin1
[] = {GPIO29
};
273 static const unsigned ase_pins_exin2
[] = {GPIO0
};
275 static const unsigned ase_pins_gpt1
[] = {GPIO5
};
276 static const unsigned ase_pins_gpt2
[] = {GPIO4
};
277 static const unsigned ase_pins_gpt3
[] = {GPIO25
};
279 static const struct ltq_pin_group xway_grps
[] = {
280 GRP_MUX("exin0", EXIN
, pins_exin0
),
281 GRP_MUX("exin1", EXIN
, pins_exin1
),
282 GRP_MUX("exin2", EXIN
, pins_exin2
),
283 GRP_MUX("jtag", JTAG
, pins_jtag
),
284 GRP_MUX("ebu a23", EBU
, pins_ebu_a23
),
285 GRP_MUX("ebu a24", EBU
, pins_ebu_a24
),
286 GRP_MUX("ebu a25", EBU
, pins_ebu_a25
),
287 GRP_MUX("ebu clk", EBU
, pins_ebu_clk
),
288 GRP_MUX("ebu cs1", EBU
, pins_ebu_cs1
),
289 GRP_MUX("ebu wait", EBU
, pins_ebu_wait
),
290 GRP_MUX("nand ale", EBU
, pins_nand_ale
),
291 GRP_MUX("nand cs1", EBU
, pins_nand_cs1
),
292 GRP_MUX("nand cle", EBU
, pins_nand_cle
),
293 GRP_MUX("spi", SPI
, pins_spi
),
294 GRP_MUX("spi_cs1", SPI
, pins_spi_cs1
),
295 GRP_MUX("spi_cs2", SPI
, pins_spi_cs2
),
296 GRP_MUX("spi_cs3", SPI
, pins_spi_cs3
),
297 GRP_MUX("spi_cs4", SPI
, pins_spi_cs4
),
298 GRP_MUX("spi_cs5", SPI
, pins_spi_cs5
),
299 GRP_MUX("spi_cs6", SPI
, pins_spi_cs6
),
300 GRP_MUX("asc0", ASC
, pins_asc0
),
301 GRP_MUX("asc0 cts rts", ASC
, pins_asc0_cts_rts
),
302 GRP_MUX("stp", STP
, pins_stp
),
303 GRP_MUX("nmi", NMI
, pins_nmi
),
304 GRP_MUX("gpt1", GPT
, pins_gpt1
),
305 GRP_MUX("gpt2", GPT
, pins_gpt2
),
306 GRP_MUX("gpt3", GPT
, pins_gpt3
),
307 GRP_MUX("clkout0", CGU
, pins_clkout0
),
308 GRP_MUX("clkout1", CGU
, pins_clkout1
),
309 GRP_MUX("clkout2", CGU
, pins_clkout2
),
310 GRP_MUX("clkout3", CGU
, pins_clkout3
),
311 GRP_MUX("gnt1", PCI
, pins_pci_gnt1
),
312 GRP_MUX("gnt2", PCI
, pins_pci_gnt2
),
313 GRP_MUX("gnt3", PCI
, pins_pci_gnt3
),
314 GRP_MUX("req1", PCI
, pins_pci_req1
),
315 GRP_MUX("req2", PCI
, pins_pci_req2
),
316 GRP_MUX("req3", PCI
, pins_pci_req3
),
318 GRP_MUX("nand rdy", EBU
, pins_nand_rdy
),
319 GRP_MUX("nand rd", EBU
, pins_nand_rd
),
320 GRP_MUX("exin3", EXIN
, pins_exin3
),
321 GRP_MUX("exin4", EXIN
, pins_exin4
),
322 GRP_MUX("exin5", EXIN
, pins_exin5
),
323 GRP_MUX("gnt4", PCI
, pins_pci_gnt4
),
324 GRP_MUX("req4", PCI
, pins_pci_gnt4
),
325 GRP_MUX("mdio", MDIO
, pins_mdio
),
328 static const struct ltq_pin_group ase_grps
[] = {
329 GRP_MUX("exin0", EXIN
, ase_pins_exin0
),
330 GRP_MUX("exin1", EXIN
, ase_pins_exin1
),
331 GRP_MUX("exin2", EXIN
, ase_pins_exin2
),
332 GRP_MUX("jtag", JTAG
, ase_pins_jtag
),
333 GRP_MUX("stp", STP
, ase_pins_stp
),
334 GRP_MUX("asc", ASC
, ase_pins_asc
),
335 GRP_MUX("gpt1", GPT
, ase_pins_gpt1
),
336 GRP_MUX("gpt2", GPT
, ase_pins_gpt2
),
337 GRP_MUX("gpt3", GPT
, ase_pins_gpt3
),
338 GRP_MUX("ephy", EPHY
, ase_pins_ephy
),
339 GRP_MUX("dfe", DFE
, ase_pins_dfe
),
340 GRP_MUX("spi", SPI
, ase_pins_spi
),
341 GRP_MUX("spi_cs1", SPI
, ase_pins_spi_cs1
),
342 GRP_MUX("spi_cs2", SPI
, ase_pins_spi_cs2
),
343 GRP_MUX("spi_cs3", SPI
, ase_pins_spi_cs3
),
346 static const char * const xway_pci_grps
[] = {"gnt1", "gnt2",
349 static const char * const xway_spi_grps
[] = {"spi", "spi_cs1",
350 "spi_cs2", "spi_cs3",
351 "spi_cs4", "spi_cs5",
353 static const char * const xway_cgu_grps
[] = {"clkout0", "clkout1",
354 "clkout2", "clkout3"};
355 static const char * const xway_ebu_grps
[] = {"ebu a23", "ebu a24",
356 "ebu a25", "ebu cs1",
357 "ebu wait", "ebu clk",
358 "nand ale", "nand cs1",
360 static const char * const xway_exin_grps
[] = {"exin0", "exin1", "exin2"};
361 static const char * const xway_gpt_grps
[] = {"gpt1", "gpt2", "gpt3"};
362 static const char * const xway_asc_grps
[] = {"asc0", "asc0 cts rts"};
363 static const char * const xway_jtag_grps
[] = {"jtag"};
364 static const char * const xway_stp_grps
[] = {"stp"};
365 static const char * const xway_nmi_grps
[] = {"nmi"};
368 static const char * const xrx_mdio_grps
[] = {"mdio"};
369 static const char * const xrx_ebu_grps
[] = {"ebu a23", "ebu a24",
370 "ebu a25", "ebu cs1",
371 "ebu wait", "ebu clk",
372 "nand ale", "nand cs1",
373 "nand cle", "nand rdy",
375 static const char * const xrx_exin_grps
[] = {"exin0", "exin1", "exin2",
376 "exin3", "exin4", "exin5"};
377 static const char * const xrx_pci_grps
[] = {"gnt1", "gnt2",
383 static const char * const ase_exin_grps
[] = {"exin0", "exin1", "exin2"};
384 static const char * const ase_gpt_grps
[] = {"gpt1", "gpt2", "gpt3"};
385 static const char * const ase_dfe_grps
[] = {"dfe"};
386 static const char * const ase_ephy_grps
[] = {"ephy"};
387 static const char * const ase_asc_grps
[] = {"asc"};
388 static const char * const ase_jtag_grps
[] = {"jtag"};
389 static const char * const ase_stp_grps
[] = {"stp"};
390 static const char * const ase_spi_grps
[] = {"spi", "spi_cs1",
391 "spi_cs2", "spi_cs3"};
393 static const struct ltq_pmx_func danube_funcs
[] = {
394 {"spi", ARRAY_AND_SIZE(xway_spi_grps
)},
395 {"asc", ARRAY_AND_SIZE(xway_asc_grps
)},
396 {"cgu", ARRAY_AND_SIZE(xway_cgu_grps
)},
397 {"jtag", ARRAY_AND_SIZE(xway_jtag_grps
)},
398 {"exin", ARRAY_AND_SIZE(xway_exin_grps
)},
399 {"stp", ARRAY_AND_SIZE(xway_stp_grps
)},
400 {"gpt", ARRAY_AND_SIZE(xway_gpt_grps
)},
401 {"nmi", ARRAY_AND_SIZE(xway_nmi_grps
)},
402 {"pci", ARRAY_AND_SIZE(xway_pci_grps
)},
403 {"ebu", ARRAY_AND_SIZE(xway_ebu_grps
)},
406 static const struct ltq_pmx_func xrx_funcs
[] = {
407 {"spi", ARRAY_AND_SIZE(xway_spi_grps
)},
408 {"asc", ARRAY_AND_SIZE(xway_asc_grps
)},
409 {"cgu", ARRAY_AND_SIZE(xway_cgu_grps
)},
410 {"jtag", ARRAY_AND_SIZE(xway_jtag_grps
)},
411 {"exin", ARRAY_AND_SIZE(xrx_exin_grps
)},
412 {"stp", ARRAY_AND_SIZE(xway_stp_grps
)},
413 {"gpt", ARRAY_AND_SIZE(xway_gpt_grps
)},
414 {"nmi", ARRAY_AND_SIZE(xway_nmi_grps
)},
415 {"pci", ARRAY_AND_SIZE(xrx_pci_grps
)},
416 {"ebu", ARRAY_AND_SIZE(xrx_ebu_grps
)},
417 {"mdio", ARRAY_AND_SIZE(xrx_mdio_grps
)},
420 static const struct ltq_pmx_func ase_funcs
[] = {
421 {"spi", ARRAY_AND_SIZE(ase_spi_grps
)},
422 {"asc", ARRAY_AND_SIZE(ase_asc_grps
)},
423 {"jtag", ARRAY_AND_SIZE(ase_jtag_grps
)},
424 {"exin", ARRAY_AND_SIZE(ase_exin_grps
)},
425 {"stp", ARRAY_AND_SIZE(ase_stp_grps
)},
426 {"gpt", ARRAY_AND_SIZE(ase_gpt_grps
)},
427 {"ephy", ARRAY_AND_SIZE(ase_ephy_grps
)},
428 {"dfe", ARRAY_AND_SIZE(ase_dfe_grps
)},
431 /* --------- pinconf related code --------- */
432 static int xway_pinconf_get(struct pinctrl_dev
*pctldev
,
434 unsigned long *config
)
436 struct ltq_pinmux_info
*info
= pinctrl_dev_get_drvdata(pctldev
);
437 enum ltq_pinconf_param param
= LTQ_PINCONF_UNPACK_PARAM(*config
);
438 int port
= PORT(pin
);
442 case LTQ_PINCONF_PARAM_OPEN_DRAIN
:
447 *config
= LTQ_PINCONF_PACK(param
,
448 !!gpio_getbit(info
->membase
[0], reg
, PORT_PIN(port
)));
451 case LTQ_PINCONF_PARAM_PULL
:
455 reg
= GPIO_PUDEN(port
);
456 if (!gpio_getbit(info
->membase
[0], reg
, PORT_PIN(port
))) {
457 *config
= LTQ_PINCONF_PACK(param
, 0);
464 reg
= GPIO_PUDSEL(port
);
465 if (!gpio_getbit(info
->membase
[0], reg
, PORT_PIN(port
)))
466 *config
= LTQ_PINCONF_PACK(param
, 2);
468 *config
= LTQ_PINCONF_PACK(param
, 1);
472 dev_err(pctldev
->dev
, "Invalid config param %04x\n", param
);
478 static int xway_pinconf_set(struct pinctrl_dev
*pctldev
,
480 unsigned long config
)
482 struct ltq_pinmux_info
*info
= pinctrl_dev_get_drvdata(pctldev
);
483 enum ltq_pinconf_param param
= LTQ_PINCONF_UNPACK_PARAM(config
);
484 int arg
= LTQ_PINCONF_UNPACK_ARG(config
);
485 int port
= PORT(pin
);
489 case LTQ_PINCONF_PARAM_OPEN_DRAIN
:
494 gpio_setbit(info
->membase
[0], reg
, PORT_PIN(port
));
497 case LTQ_PINCONF_PARAM_PULL
:
501 reg
= GPIO_PUDEN(port
);
503 gpio_clearbit(info
->membase
[0], reg
, PORT_PIN(port
));
506 gpio_setbit(info
->membase
[0], reg
, PORT_PIN(port
));
511 reg
= GPIO_PUDSEL(port
);
513 gpio_clearbit(info
->membase
[0], reg
, PORT_PIN(port
));
515 gpio_setbit(info
->membase
[0], reg
, PORT_PIN(port
));
517 dev_err(pctldev
->dev
, "Invalid pull value %d\n", arg
);
521 dev_err(pctldev
->dev
, "Invalid config param %04x\n", param
);
527 struct pinconf_ops xway_pinconf_ops
= {
528 .pin_config_get
= xway_pinconf_get
,
529 .pin_config_set
= xway_pinconf_set
,
532 static struct pinctrl_desc xway_pctrl_desc
= {
533 .owner
= THIS_MODULE
,
534 .confops
= &xway_pinconf_ops
,
537 static inline int xway_mux_apply(struct pinctrl_dev
*pctrldev
,
540 struct ltq_pinmux_info
*info
= pinctrl_dev_get_drvdata(pctrldev
);
541 int port
= PORT(pin
);
542 u32 alt1_reg
= GPIO_ALT1(pin
);
545 alt1_reg
= GPIO3_ALT1
;
548 gpio_setbit(info
->membase
[0], GPIO_ALT0(pin
), PORT_PIN(pin
));
550 gpio_clearbit(info
->membase
[0], GPIO_ALT0(pin
), PORT_PIN(pin
));
553 gpio_setbit(info
->membase
[0], alt1_reg
, PORT_PIN(pin
));
555 gpio_clearbit(info
->membase
[0], alt1_reg
, PORT_PIN(pin
));
560 static const struct ltq_cfg_param xway_cfg_params
[] = {
561 {"lantiq,pull", LTQ_PINCONF_PARAM_PULL
},
562 {"lantiq,open-drain", LTQ_PINCONF_PARAM_OPEN_DRAIN
},
565 static struct ltq_pinmux_info xway_info
= {
566 .desc
= &xway_pctrl_desc
,
567 .apply_mux
= xway_mux_apply
,
568 .params
= xway_cfg_params
,
569 .num_params
= ARRAY_SIZE(xway_cfg_params
),
572 /* --------- gpio_chip related code --------- */
573 static void xway_gpio_set(struct gpio_chip
*chip
, unsigned int pin
, int val
)
575 struct ltq_pinmux_info
*info
= dev_get_drvdata(chip
->dev
);
578 gpio_setbit(info
->membase
[0], GPIO_OUT(pin
), PORT_PIN(pin
));
580 gpio_clearbit(info
->membase
[0], GPIO_OUT(pin
), PORT_PIN(pin
));
583 static int xway_gpio_get(struct gpio_chip
*chip
, unsigned int pin
)
585 struct ltq_pinmux_info
*info
= dev_get_drvdata(chip
->dev
);
587 return gpio_getbit(info
->membase
[0], GPIO_IN(pin
), PORT_PIN(pin
));
590 static int xway_gpio_dir_in(struct gpio_chip
*chip
, unsigned int pin
)
592 struct ltq_pinmux_info
*info
= dev_get_drvdata(chip
->dev
);
594 gpio_clearbit(info
->membase
[0], GPIO_DIR(pin
), PORT_PIN(pin
));
599 static int xway_gpio_dir_out(struct gpio_chip
*chip
, unsigned int pin
, int val
)
601 struct ltq_pinmux_info
*info
= dev_get_drvdata(chip
->dev
);
603 gpio_setbit(info
->membase
[0], GPIO_DIR(pin
), PORT_PIN(pin
));
604 xway_gpio_set(chip
, pin
, val
);
609 static int xway_gpio_req(struct gpio_chip
*chip
, unsigned offset
)
611 int gpio
= chip
->base
+ offset
;
613 return pinctrl_request_gpio(gpio
);
616 static void xway_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
618 int gpio
= chip
->base
+ offset
;
620 pinctrl_free_gpio(gpio
);
623 static struct gpio_chip xway_chip
= {
624 .label
= "gpio-xway",
625 .direction_input
= xway_gpio_dir_in
,
626 .direction_output
= xway_gpio_dir_out
,
627 .get
= xway_gpio_get
,
628 .set
= xway_gpio_set
,
629 .request
= xway_gpio_req
,
630 .free
= xway_gpio_free
,
635 /* --------- register the pinctrl layer --------- */
636 static const unsigned xway_exin_pin_map
[] = {GPIO0
, GPIO1
, GPIO2
, GPIO39
, GPIO46
, GPIO9
};
637 static const unsigned ase_exin_pins_map
[] = {GPIO6
, GPIO29
, GPIO0
};
639 static struct pinctrl_xway_soc
{
641 const struct ltq_mfp_pin
*mfp
;
642 const struct ltq_pin_group
*grps
;
643 unsigned int num_grps
;
644 const struct ltq_pmx_func
*funcs
;
645 unsigned int num_funcs
;
646 const unsigned *exin
;
647 unsigned int num_exin
;
650 {XWAY_MAX_PIN
, xway_mfp
,
651 xway_grps
, ARRAY_SIZE(xway_grps
),
652 danube_funcs
, ARRAY_SIZE(danube_funcs
),
653 xway_exin_pin_map
, 3},
654 /* xway xr9 series */
655 {XR9_MAX_PIN
, xway_mfp
,
656 xway_grps
, ARRAY_SIZE(xway_grps
),
657 xrx_funcs
, ARRAY_SIZE(xrx_funcs
),
658 xway_exin_pin_map
, 6},
659 /* xway ase series */
660 {XWAY_MAX_PIN
, ase_mfp
,
661 ase_grps
, ARRAY_SIZE(ase_grps
),
662 ase_funcs
, ARRAY_SIZE(ase_funcs
),
663 ase_exin_pins_map
, 3},
666 static struct pinctrl_gpio_range xway_gpio_range
= {
671 static const struct of_device_id xway_match
[] = {
672 { .compatible
= "lantiq,pinctrl-xway", .data
= &soc_cfg
[0]},
673 { .compatible
= "lantiq,pinctrl-xr9", .data
= &soc_cfg
[1]},
674 { .compatible
= "lantiq,pinctrl-ase", .data
= &soc_cfg
[2]},
677 MODULE_DEVICE_TABLE(of
, xway_match
);
679 static int __devinit
pinmux_xway_probe(struct platform_device
*pdev
)
681 const struct of_device_id
*match
;
682 const struct pinctrl_xway_soc
*xway_soc
;
683 struct resource
*res
;
686 /* get and remap our register range */
687 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
689 dev_err(&pdev
->dev
, "Failed to get resource\n");
692 xway_info
.membase
[0] = devm_request_and_ioremap(&pdev
->dev
, res
);
693 if (!xway_info
.membase
[0]) {
694 dev_err(&pdev
->dev
, "Failed to remap resource\n");
698 match
= of_match_device(xway_match
, &pdev
->dev
);
700 xway_soc
= (const struct pinctrl_xway_soc
*) match
->data
;
702 xway_soc
= &soc_cfg
[0];
704 /* find out how many pads we have */
705 xway_chip
.ngpio
= xway_soc
->pin_count
;
707 /* load our pad descriptors */
708 xway_info
.pads
= devm_kzalloc(&pdev
->dev
,
709 sizeof(struct pinctrl_pin_desc
) * xway_chip
.ngpio
,
711 if (!xway_info
.pads
) {
712 dev_err(&pdev
->dev
, "Failed to allocate pads\n");
715 for (i
= 0; i
< xway_chip
.ngpio
; i
++) {
716 /* strlen("ioXY") + 1 = 5 */
717 char *name
= devm_kzalloc(&pdev
->dev
, 5, GFP_KERNEL
);
720 dev_err(&pdev
->dev
, "Failed to allocate pad name\n");
723 snprintf(name
, 5, "io%d", i
);
724 xway_info
.pads
[i
].number
= GPIO0
+ i
;
725 xway_info
.pads
[i
].name
= name
;
727 xway_pctrl_desc
.pins
= xway_info
.pads
;
729 /* load the gpio chip */
730 xway_chip
.dev
= &pdev
->dev
;
731 of_gpiochip_add(&xway_chip
);
732 ret
= gpiochip_add(&xway_chip
);
734 dev_err(&pdev
->dev
, "Failed to register gpio chip\n");
738 /* setup the data needed by pinctrl */
739 xway_pctrl_desc
.name
= dev_name(&pdev
->dev
);
740 xway_pctrl_desc
.npins
= xway_chip
.ngpio
;
742 xway_info
.num_pads
= xway_chip
.ngpio
;
743 xway_info
.num_mfp
= xway_chip
.ngpio
;
744 xway_info
.mfp
= xway_soc
->mfp
;
745 xway_info
.grps
= xway_soc
->grps
;
746 xway_info
.num_grps
= xway_soc
->num_grps
;
747 xway_info
.funcs
= xway_soc
->funcs
;
748 xway_info
.num_funcs
= xway_soc
->num_funcs
;
749 xway_info
.exin
= xway_soc
->exin
;
750 xway_info
.num_exin
= xway_soc
->num_exin
;
752 /* register with the generic lantiq layer */
753 ret
= ltq_pinctrl_register(pdev
, &xway_info
);
755 dev_err(&pdev
->dev
, "Failed to register pinctrl driver\n");
759 /* finish with registering the gpio range in pinctrl */
760 xway_gpio_range
.npins
= xway_chip
.ngpio
;
761 xway_gpio_range
.base
= xway_chip
.base
;
762 pinctrl_add_gpio_range(xway_info
.pctrl
, &xway_gpio_range
);
763 dev_info(&pdev
->dev
, "Init done\n");
767 static struct platform_driver pinmux_xway_driver
= {
768 .probe
= pinmux_xway_probe
,
770 .name
= "pinctrl-xway",
771 .owner
= THIS_MODULE
,
772 .of_match_table
= xway_match
,
776 static int __init
pinmux_xway_init(void)
778 return platform_driver_register(&pinmux_xway_driver
);
781 core_initcall_sync(pinmux_xway_init
);