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Merge tag 'pinctrl-v3.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...
[deliverable/linux.git] / drivers / pinctrl / samsung / pinctrl-exynos.c
1 /*
2 * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2012 Linaro Ltd
7 * http://www.linaro.org
8 *
9 * Author: Thomas Abraham <thomas.ab@samsung.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This file contains the Samsung Exynos specific information required by the
17 * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
18 * external gpio and wakeup interrupt support.
19 */
20
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/irqdomain.h>
25 #include <linux/irq.h>
26 #include <linux/irqchip/chained_irq.h>
27 #include <linux/of_irq.h>
28 #include <linux/io.h>
29 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31 #include <linux/err.h>
32
33 #include "pinctrl-samsung.h"
34 #include "pinctrl-exynos.h"
35
36 struct exynos_irq_chip {
37 struct irq_chip chip;
38
39 u32 eint_con;
40 u32 eint_mask;
41 u32 eint_pend;
42 };
43
44 static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip)
45 {
46 return container_of(chip, struct exynos_irq_chip, chip);
47 }
48
49 static struct samsung_pin_bank_type bank_type_off = {
50 .fld_width = { 4, 1, 2, 2, 2, 2, },
51 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
52 };
53
54 static struct samsung_pin_bank_type bank_type_alive = {
55 .fld_width = { 4, 1, 2, 2, },
56 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
57 };
58
59 /* list of external wakeup controllers supported */
60 static const struct of_device_id exynos_wkup_irq_ids[] = {
61 { .compatible = "samsung,exynos4210-wakeup-eint", },
62 { }
63 };
64
65 static void exynos_irq_mask(struct irq_data *irqd)
66 {
67 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
68 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
69 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
70 struct samsung_pinctrl_drv_data *d = bank->drvdata;
71 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
72 unsigned long mask;
73 unsigned long flags;
74
75 spin_lock_irqsave(&bank->slock, flags);
76
77 mask = readl(d->virt_base + reg_mask);
78 mask |= 1 << irqd->hwirq;
79 writel(mask, d->virt_base + reg_mask);
80
81 spin_unlock_irqrestore(&bank->slock, flags);
82 }
83
84 static void exynos_irq_ack(struct irq_data *irqd)
85 {
86 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
87 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
88 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
89 struct samsung_pinctrl_drv_data *d = bank->drvdata;
90 unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset;
91
92 writel(1 << irqd->hwirq, d->virt_base + reg_pend);
93 }
94
95 static void exynos_irq_unmask(struct irq_data *irqd)
96 {
97 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
98 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
99 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
100 struct samsung_pinctrl_drv_data *d = bank->drvdata;
101 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
102 unsigned long mask;
103 unsigned long flags;
104
105 /*
106 * Ack level interrupts right before unmask
107 *
108 * If we don't do this we'll get a double-interrupt. Level triggered
109 * interrupts must not fire an interrupt if the level is not
110 * _currently_ active, even if it was active while the interrupt was
111 * masked.
112 */
113 if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
114 exynos_irq_ack(irqd);
115
116 spin_lock_irqsave(&bank->slock, flags);
117
118 mask = readl(d->virt_base + reg_mask);
119 mask &= ~(1 << irqd->hwirq);
120 writel(mask, d->virt_base + reg_mask);
121
122 spin_unlock_irqrestore(&bank->slock, flags);
123 }
124
125 static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
126 {
127 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
128 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
129 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
130 struct samsung_pin_bank_type *bank_type = bank->type;
131 struct samsung_pinctrl_drv_data *d = bank->drvdata;
132 unsigned int pin = irqd->hwirq;
133 unsigned int shift = EXYNOS_EINT_CON_LEN * pin;
134 unsigned int con, trig_type;
135 unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
136 unsigned long flags;
137 unsigned int mask;
138
139 switch (type) {
140 case IRQ_TYPE_EDGE_RISING:
141 trig_type = EXYNOS_EINT_EDGE_RISING;
142 break;
143 case IRQ_TYPE_EDGE_FALLING:
144 trig_type = EXYNOS_EINT_EDGE_FALLING;
145 break;
146 case IRQ_TYPE_EDGE_BOTH:
147 trig_type = EXYNOS_EINT_EDGE_BOTH;
148 break;
149 case IRQ_TYPE_LEVEL_HIGH:
150 trig_type = EXYNOS_EINT_LEVEL_HIGH;
151 break;
152 case IRQ_TYPE_LEVEL_LOW:
153 trig_type = EXYNOS_EINT_LEVEL_LOW;
154 break;
155 default:
156 pr_err("unsupported external interrupt type\n");
157 return -EINVAL;
158 }
159
160 if (type & IRQ_TYPE_EDGE_BOTH)
161 __irq_set_handler_locked(irqd->irq, handle_edge_irq);
162 else
163 __irq_set_handler_locked(irqd->irq, handle_level_irq);
164
165 con = readl(d->virt_base + reg_con);
166 con &= ~(EXYNOS_EINT_CON_MASK << shift);
167 con |= trig_type << shift;
168 writel(con, d->virt_base + reg_con);
169
170 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
171 shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC];
172 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
173
174 spin_lock_irqsave(&bank->slock, flags);
175
176 con = readl(d->virt_base + reg_con);
177 con &= ~(mask << shift);
178 con |= EXYNOS_EINT_FUNC << shift;
179 writel(con, d->virt_base + reg_con);
180
181 spin_unlock_irqrestore(&bank->slock, flags);
182
183 return 0;
184 }
185
186 /*
187 * irq_chip for gpio interrupts.
188 */
189 static struct exynos_irq_chip exynos_gpio_irq_chip = {
190 .chip = {
191 .name = "exynos_gpio_irq_chip",
192 .irq_unmask = exynos_irq_unmask,
193 .irq_mask = exynos_irq_mask,
194 .irq_ack = exynos_irq_ack,
195 .irq_set_type = exynos_irq_set_type,
196 },
197 .eint_con = EXYNOS_GPIO_ECON_OFFSET,
198 .eint_mask = EXYNOS_GPIO_EMASK_OFFSET,
199 .eint_pend = EXYNOS_GPIO_EPEND_OFFSET,
200 };
201
202 static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq,
203 irq_hw_number_t hw)
204 {
205 struct samsung_pin_bank *b = h->host_data;
206
207 irq_set_chip_data(virq, b);
208 irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip.chip,
209 handle_level_irq);
210 set_irq_flags(virq, IRQF_VALID);
211 return 0;
212 }
213
214 /*
215 * irq domain callbacks for external gpio interrupt controller.
216 */
217 static const struct irq_domain_ops exynos_gpio_irqd_ops = {
218 .map = exynos_gpio_irq_map,
219 .xlate = irq_domain_xlate_twocell,
220 };
221
222 static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
223 {
224 struct samsung_pinctrl_drv_data *d = data;
225 struct samsung_pin_ctrl *ctrl = d->ctrl;
226 struct samsung_pin_bank *bank = ctrl->pin_banks;
227 unsigned int svc, group, pin, virq;
228
229 svc = readl(d->virt_base + EXYNOS_SVC_OFFSET);
230 group = EXYNOS_SVC_GROUP(svc);
231 pin = svc & EXYNOS_SVC_NUM_MASK;
232
233 if (!group)
234 return IRQ_HANDLED;
235 bank += (group - 1);
236
237 virq = irq_linear_revmap(bank->irq_domain, pin);
238 if (!virq)
239 return IRQ_NONE;
240 generic_handle_irq(virq);
241 return IRQ_HANDLED;
242 }
243
244 struct exynos_eint_gpio_save {
245 u32 eint_con;
246 u32 eint_fltcon0;
247 u32 eint_fltcon1;
248 };
249
250 /*
251 * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
252 * @d: driver data of samsung pinctrl driver.
253 */
254 static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
255 {
256 struct samsung_pin_bank *bank;
257 struct device *dev = d->dev;
258 int ret;
259 int i;
260
261 if (!d->irq) {
262 dev_err(dev, "irq number not available\n");
263 return -EINVAL;
264 }
265
266 ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq,
267 0, dev_name(dev), d);
268 if (ret) {
269 dev_err(dev, "irq request failed\n");
270 return -ENXIO;
271 }
272
273 bank = d->ctrl->pin_banks;
274 for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
275 if (bank->eint_type != EINT_TYPE_GPIO)
276 continue;
277 bank->irq_domain = irq_domain_add_linear(bank->of_node,
278 bank->nr_pins, &exynos_gpio_irqd_ops, bank);
279 if (!bank->irq_domain) {
280 dev_err(dev, "gpio irq domain add failed\n");
281 ret = -ENXIO;
282 goto err_domains;
283 }
284
285 bank->soc_priv = devm_kzalloc(d->dev,
286 sizeof(struct exynos_eint_gpio_save), GFP_KERNEL);
287 if (!bank->soc_priv) {
288 irq_domain_remove(bank->irq_domain);
289 ret = -ENOMEM;
290 goto err_domains;
291 }
292 }
293
294 return 0;
295
296 err_domains:
297 for (--i, --bank; i >= 0; --i, --bank) {
298 if (bank->eint_type != EINT_TYPE_GPIO)
299 continue;
300 irq_domain_remove(bank->irq_domain);
301 }
302
303 return ret;
304 }
305
306 static u32 exynos_eint_wake_mask = 0xffffffff;
307
308 u32 exynos_get_eint_wake_mask(void)
309 {
310 return exynos_eint_wake_mask;
311 }
312
313 static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
314 {
315 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
316 unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq);
317
318 pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq);
319
320 if (!on)
321 exynos_eint_wake_mask |= bit;
322 else
323 exynos_eint_wake_mask &= ~bit;
324
325 return 0;
326 }
327
328 /*
329 * irq_chip for wakeup interrupts
330 */
331 static struct exynos_irq_chip exynos_wkup_irq_chip = {
332 .chip = {
333 .name = "exynos_wkup_irq_chip",
334 .irq_unmask = exynos_irq_unmask,
335 .irq_mask = exynos_irq_mask,
336 .irq_ack = exynos_irq_ack,
337 .irq_set_type = exynos_irq_set_type,
338 .irq_set_wake = exynos_wkup_irq_set_wake,
339 },
340 .eint_con = EXYNOS_WKUP_ECON_OFFSET,
341 .eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
342 .eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
343 };
344
345 /* interrupt handler for wakeup interrupts 0..15 */
346 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
347 {
348 struct exynos_weint_data *eintd = irq_get_handler_data(irq);
349 struct samsung_pin_bank *bank = eintd->bank;
350 struct irq_chip *chip = irq_get_chip(irq);
351 int eint_irq;
352
353 chained_irq_enter(chip, desc);
354 chip->irq_mask(&desc->irq_data);
355
356 if (chip->irq_ack)
357 chip->irq_ack(&desc->irq_data);
358
359 eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq);
360 generic_handle_irq(eint_irq);
361 chip->irq_unmask(&desc->irq_data);
362 chained_irq_exit(chip, desc);
363 }
364
365 static inline void exynos_irq_demux_eint(unsigned long pend,
366 struct irq_domain *domain)
367 {
368 unsigned int irq;
369
370 while (pend) {
371 irq = fls(pend) - 1;
372 generic_handle_irq(irq_find_mapping(domain, irq));
373 pend &= ~(1 << irq);
374 }
375 }
376
377 /* interrupt handler for wakeup interrupt 16 */
378 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
379 {
380 struct irq_chip *chip = irq_get_chip(irq);
381 struct exynos_muxed_weint_data *eintd = irq_get_handler_data(irq);
382 struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata;
383 unsigned long pend;
384 unsigned long mask;
385 int i;
386
387 chained_irq_enter(chip, desc);
388
389 for (i = 0; i < eintd->nr_banks; ++i) {
390 struct samsung_pin_bank *b = eintd->banks[i];
391 pend = readl(d->virt_base + EXYNOS_WKUP_EPEND_OFFSET
392 + b->eint_offset);
393 mask = readl(d->virt_base + EXYNOS_WKUP_EMASK_OFFSET
394 + b->eint_offset);
395 exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
396 }
397
398 chained_irq_exit(chip, desc);
399 }
400
401 static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq,
402 irq_hw_number_t hw)
403 {
404 irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip.chip,
405 handle_level_irq);
406 irq_set_chip_data(virq, h->host_data);
407 set_irq_flags(virq, IRQF_VALID);
408 return 0;
409 }
410
411 /*
412 * irq domain callbacks for external wakeup interrupt controller.
413 */
414 static const struct irq_domain_ops exynos_wkup_irqd_ops = {
415 .map = exynos_wkup_irq_map,
416 .xlate = irq_domain_xlate_twocell,
417 };
418
419 /*
420 * exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
421 * @d: driver data of samsung pinctrl driver.
422 */
423 static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
424 {
425 struct device *dev = d->dev;
426 struct device_node *wkup_np = NULL;
427 struct device_node *np;
428 struct samsung_pin_bank *bank;
429 struct exynos_weint_data *weint_data;
430 struct exynos_muxed_weint_data *muxed_data;
431 unsigned int muxed_banks = 0;
432 unsigned int i;
433 int idx, irq;
434
435 for_each_child_of_node(dev->of_node, np) {
436 if (of_match_node(exynos_wkup_irq_ids, np)) {
437 wkup_np = np;
438 break;
439 }
440 }
441 if (!wkup_np)
442 return -ENODEV;
443
444 bank = d->ctrl->pin_banks;
445 for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
446 if (bank->eint_type != EINT_TYPE_WKUP)
447 continue;
448
449 bank->irq_domain = irq_domain_add_linear(bank->of_node,
450 bank->nr_pins, &exynos_wkup_irqd_ops, bank);
451 if (!bank->irq_domain) {
452 dev_err(dev, "wkup irq domain add failed\n");
453 return -ENXIO;
454 }
455
456 if (!of_find_property(bank->of_node, "interrupts", NULL)) {
457 bank->eint_type = EINT_TYPE_WKUP_MUX;
458 ++muxed_banks;
459 continue;
460 }
461
462 weint_data = devm_kzalloc(dev, bank->nr_pins
463 * sizeof(*weint_data), GFP_KERNEL);
464 if (!weint_data) {
465 dev_err(dev, "could not allocate memory for weint_data\n");
466 return -ENOMEM;
467 }
468
469 for (idx = 0; idx < bank->nr_pins; ++idx) {
470 irq = irq_of_parse_and_map(bank->of_node, idx);
471 if (!irq) {
472 dev_err(dev, "irq number for eint-%s-%d not found\n",
473 bank->name, idx);
474 continue;
475 }
476 weint_data[idx].irq = idx;
477 weint_data[idx].bank = bank;
478 irq_set_handler_data(irq, &weint_data[idx]);
479 irq_set_chained_handler(irq, exynos_irq_eint0_15);
480 }
481 }
482
483 if (!muxed_banks)
484 return 0;
485
486 irq = irq_of_parse_and_map(wkup_np, 0);
487 if (!irq) {
488 dev_err(dev, "irq number for muxed EINTs not found\n");
489 return 0;
490 }
491
492 muxed_data = devm_kzalloc(dev, sizeof(*muxed_data)
493 + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL);
494 if (!muxed_data) {
495 dev_err(dev, "could not allocate memory for muxed_data\n");
496 return -ENOMEM;
497 }
498
499 irq_set_chained_handler(irq, exynos_irq_demux_eint16_31);
500 irq_set_handler_data(irq, muxed_data);
501
502 bank = d->ctrl->pin_banks;
503 idx = 0;
504 for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
505 if (bank->eint_type != EINT_TYPE_WKUP_MUX)
506 continue;
507
508 muxed_data->banks[idx++] = bank;
509 }
510 muxed_data->nr_banks = muxed_banks;
511
512 return 0;
513 }
514
515 static void exynos_pinctrl_suspend_bank(
516 struct samsung_pinctrl_drv_data *drvdata,
517 struct samsung_pin_bank *bank)
518 {
519 struct exynos_eint_gpio_save *save = bank->soc_priv;
520 void __iomem *regs = drvdata->virt_base;
521
522 save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
523 + bank->eint_offset);
524 save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
525 + 2 * bank->eint_offset);
526 save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
527 + 2 * bank->eint_offset + 4);
528
529 pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
530 pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
531 pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
532 }
533
534 static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
535 {
536 struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
537 struct samsung_pin_bank *bank = ctrl->pin_banks;
538 int i;
539
540 for (i = 0; i < ctrl->nr_banks; ++i, ++bank)
541 if (bank->eint_type == EINT_TYPE_GPIO)
542 exynos_pinctrl_suspend_bank(drvdata, bank);
543 }
544
545 static void exynos_pinctrl_resume_bank(
546 struct samsung_pinctrl_drv_data *drvdata,
547 struct samsung_pin_bank *bank)
548 {
549 struct exynos_eint_gpio_save *save = bank->soc_priv;
550 void __iomem *regs = drvdata->virt_base;
551
552 pr_debug("%s: con %#010x => %#010x\n", bank->name,
553 readl(regs + EXYNOS_GPIO_ECON_OFFSET
554 + bank->eint_offset), save->eint_con);
555 pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
556 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
557 + 2 * bank->eint_offset), save->eint_fltcon0);
558 pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
559 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
560 + 2 * bank->eint_offset + 4), save->eint_fltcon1);
561
562 writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
563 + bank->eint_offset);
564 writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
565 + 2 * bank->eint_offset);
566 writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
567 + 2 * bank->eint_offset + 4);
568 }
569
570 static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
571 {
572 struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
573 struct samsung_pin_bank *bank = ctrl->pin_banks;
574 int i;
575
576 for (i = 0; i < ctrl->nr_banks; ++i, ++bank)
577 if (bank->eint_type == EINT_TYPE_GPIO)
578 exynos_pinctrl_resume_bank(drvdata, bank);
579 }
580
581 /* pin banks of s5pv210 pin-controller */
582 static struct samsung_pin_bank s5pv210_pin_bank[] = {
583 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
584 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
585 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
586 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
587 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
588 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
589 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
590 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c),
591 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20),
592 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24),
593 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28),
594 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c),
595 EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30),
596 EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34),
597 EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38),
598 EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c),
599 EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40),
600 EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"),
601 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44),
602 EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48),
603 EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c),
604 EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50),
605 EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54),
606 EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"),
607 EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"),
608 EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"),
609 EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"),
610 EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"),
611 EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"),
612 EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"),
613 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00),
614 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04),
615 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08),
616 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c),
617 };
618
619 struct samsung_pin_ctrl s5pv210_pin_ctrl[] = {
620 {
621 /* pin-controller instance 0 data */
622 .pin_banks = s5pv210_pin_bank,
623 .nr_banks = ARRAY_SIZE(s5pv210_pin_bank),
624 .eint_gpio_init = exynos_eint_gpio_init,
625 .eint_wkup_init = exynos_eint_wkup_init,
626 .suspend = exynos_pinctrl_suspend,
627 .resume = exynos_pinctrl_resume,
628 .label = "s5pv210-gpio-ctrl0",
629 },
630 };
631
632 /* pin banks of exynos3250 pin-controller 0 */
633 static struct samsung_pin_bank exynos3250_pin_banks0[] = {
634 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
635 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
636 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
637 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
638 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
639 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
640 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18),
641 };
642
643 /* pin banks of exynos3250 pin-controller 1 */
644 static struct samsung_pin_bank exynos3250_pin_banks1[] = {
645 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"),
646 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"),
647 EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"),
648 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08),
649 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
650 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
651 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18),
652 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
653 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
654 EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c),
655 EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30),
656 EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34),
657 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
658 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
659 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
660 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
661 };
662
663 /*
664 * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes
665 * two gpio/pin-mux/pinconfig controllers.
666 */
667 struct samsung_pin_ctrl exynos3250_pin_ctrl[] = {
668 {
669 /* pin-controller instance 0 data */
670 .pin_banks = exynos3250_pin_banks0,
671 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0),
672 .eint_gpio_init = exynos_eint_gpio_init,
673 .suspend = exynos_pinctrl_suspend,
674 .resume = exynos_pinctrl_resume,
675 .label = "exynos3250-gpio-ctrl0",
676 }, {
677 /* pin-controller instance 1 data */
678 .pin_banks = exynos3250_pin_banks1,
679 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1),
680 .eint_gpio_init = exynos_eint_gpio_init,
681 .eint_wkup_init = exynos_eint_wkup_init,
682 .suspend = exynos_pinctrl_suspend,
683 .resume = exynos_pinctrl_resume,
684 .label = "exynos3250-gpio-ctrl1",
685 },
686 };
687
688 /* pin banks of exynos4210 pin-controller 0 */
689 static struct samsung_pin_bank exynos4210_pin_banks0[] = {
690 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
691 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
692 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
693 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
694 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
695 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
696 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
697 EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c),
698 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),
699 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24),
700 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28),
701 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c),
702 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
703 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
704 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
705 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
706 };
707
708 /* pin banks of exynos4210 pin-controller 1 */
709 static struct samsung_pin_bank exynos4210_pin_banks1[] = {
710 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),
711 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),
712 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
713 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
714 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
715 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
716 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18),
717 EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c),
718 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
719 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
720 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
721 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
722 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
723 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
724 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
725 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
726 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
727 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
728 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
729 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
730 };
731
732 /* pin banks of exynos4210 pin-controller 2 */
733 static struct samsung_pin_bank exynos4210_pin_banks2[] = {
734 EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
735 };
736
737 /*
738 * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
739 * three gpio/pin-mux/pinconfig controllers.
740 */
741 struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
742 {
743 /* pin-controller instance 0 data */
744 .pin_banks = exynos4210_pin_banks0,
745 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0),
746 .eint_gpio_init = exynos_eint_gpio_init,
747 .suspend = exynos_pinctrl_suspend,
748 .resume = exynos_pinctrl_resume,
749 .label = "exynos4210-gpio-ctrl0",
750 }, {
751 /* pin-controller instance 1 data */
752 .pin_banks = exynos4210_pin_banks1,
753 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1),
754 .eint_gpio_init = exynos_eint_gpio_init,
755 .eint_wkup_init = exynos_eint_wkup_init,
756 .suspend = exynos_pinctrl_suspend,
757 .resume = exynos_pinctrl_resume,
758 .label = "exynos4210-gpio-ctrl1",
759 }, {
760 /* pin-controller instance 2 data */
761 .pin_banks = exynos4210_pin_banks2,
762 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2),
763 .label = "exynos4210-gpio-ctrl2",
764 },
765 };
766
767 /* pin banks of exynos4x12 pin-controller 0 */
768 static struct samsung_pin_bank exynos4x12_pin_banks0[] = {
769 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
770 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
771 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
772 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
773 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
774 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
775 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
776 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
777 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
778 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
779 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
780 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40),
781 EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44),
782 };
783
784 /* pin banks of exynos4x12 pin-controller 1 */
785 static struct samsung_pin_bank exynos4x12_pin_banks1[] = {
786 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
787 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
788 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
789 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
790 EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18),
791 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c),
792 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
793 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
794 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
795 EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
796 EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
797 EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
798 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
799 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
800 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
801 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
802 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
803 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
804 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
805 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
806 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
807 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
808 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
809 };
810
811 /* pin banks of exynos4x12 pin-controller 2 */
812 static struct samsung_pin_bank exynos4x12_pin_banks2[] = {
813 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
814 };
815
816 /* pin banks of exynos4x12 pin-controller 3 */
817 static struct samsung_pin_bank exynos4x12_pin_banks3[] = {
818 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
819 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
820 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
821 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c),
822 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10),
823 };
824
825 /*
826 * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes
827 * four gpio/pin-mux/pinconfig controllers.
828 */
829 struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
830 {
831 /* pin-controller instance 0 data */
832 .pin_banks = exynos4x12_pin_banks0,
833 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0),
834 .eint_gpio_init = exynos_eint_gpio_init,
835 .suspend = exynos_pinctrl_suspend,
836 .resume = exynos_pinctrl_resume,
837 .label = "exynos4x12-gpio-ctrl0",
838 }, {
839 /* pin-controller instance 1 data */
840 .pin_banks = exynos4x12_pin_banks1,
841 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1),
842 .eint_gpio_init = exynos_eint_gpio_init,
843 .eint_wkup_init = exynos_eint_wkup_init,
844 .suspend = exynos_pinctrl_suspend,
845 .resume = exynos_pinctrl_resume,
846 .label = "exynos4x12-gpio-ctrl1",
847 }, {
848 /* pin-controller instance 2 data */
849 .pin_banks = exynos4x12_pin_banks2,
850 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2),
851 .eint_gpio_init = exynos_eint_gpio_init,
852 .suspend = exynos_pinctrl_suspend,
853 .resume = exynos_pinctrl_resume,
854 .label = "exynos4x12-gpio-ctrl2",
855 }, {
856 /* pin-controller instance 3 data */
857 .pin_banks = exynos4x12_pin_banks3,
858 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3),
859 .eint_gpio_init = exynos_eint_gpio_init,
860 .suspend = exynos_pinctrl_suspend,
861 .resume = exynos_pinctrl_resume,
862 .label = "exynos4x12-gpio-ctrl3",
863 },
864 };
865
866 /* pin banks of exynos5250 pin-controller 0 */
867 static struct samsung_pin_bank exynos5250_pin_banks0[] = {
868 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
869 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
870 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
871 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
872 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
873 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
874 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
875 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
876 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),
877 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),
878 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),
879 EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),
880 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),
881 EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),
882 EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),
883 EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),
884 EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),
885 EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),
886 EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),
887 EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),
888 EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),
889 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
890 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
891 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
892 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
893 };
894
895 /* pin banks of exynos5250 pin-controller 1 */
896 static struct samsung_pin_bank exynos5250_pin_banks1[] = {
897 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
898 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
899 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
900 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),
901 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
902 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
903 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
904 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),
905 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),
906 };
907
908 /* pin banks of exynos5250 pin-controller 2 */
909 static struct samsung_pin_bank exynos5250_pin_banks2[] = {
910 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
911 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
912 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
913 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
914 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
915 };
916
917 /* pin banks of exynos5250 pin-controller 3 */
918 static struct samsung_pin_bank exynos5250_pin_banks3[] = {
919 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
920 };
921
922 /*
923 * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
924 * four gpio/pin-mux/pinconfig controllers.
925 */
926 struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
927 {
928 /* pin-controller instance 0 data */
929 .pin_banks = exynos5250_pin_banks0,
930 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0),
931 .eint_gpio_init = exynos_eint_gpio_init,
932 .eint_wkup_init = exynos_eint_wkup_init,
933 .suspend = exynos_pinctrl_suspend,
934 .resume = exynos_pinctrl_resume,
935 .label = "exynos5250-gpio-ctrl0",
936 }, {
937 /* pin-controller instance 1 data */
938 .pin_banks = exynos5250_pin_banks1,
939 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1),
940 .eint_gpio_init = exynos_eint_gpio_init,
941 .suspend = exynos_pinctrl_suspend,
942 .resume = exynos_pinctrl_resume,
943 .label = "exynos5250-gpio-ctrl1",
944 }, {
945 /* pin-controller instance 2 data */
946 .pin_banks = exynos5250_pin_banks2,
947 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2),
948 .eint_gpio_init = exynos_eint_gpio_init,
949 .suspend = exynos_pinctrl_suspend,
950 .resume = exynos_pinctrl_resume,
951 .label = "exynos5250-gpio-ctrl2",
952 }, {
953 /* pin-controller instance 3 data */
954 .pin_banks = exynos5250_pin_banks3,
955 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3),
956 .eint_gpio_init = exynos_eint_gpio_init,
957 .suspend = exynos_pinctrl_suspend,
958 .resume = exynos_pinctrl_resume,
959 .label = "exynos5250-gpio-ctrl3",
960 },
961 };
962
963 /* pin banks of exynos5260 pin-controller 0 */
964 static struct samsung_pin_bank exynos5260_pin_banks0[] = {
965 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
966 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),
967 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
968 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
969 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),
970 EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14),
971 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18),
972 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c),
973 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20),
974 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24),
975 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28),
976 EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
977 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30),
978 EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34),
979 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38),
980 EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c),
981 EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40),
982 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
983 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
984 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
985 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
986 };
987
988 /* pin banks of exynos5260 pin-controller 1 */
989 static struct samsung_pin_bank exynos5260_pin_banks1[] = {
990 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),
991 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),
992 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
993 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
994 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10),
995 };
996
997 /* pin banks of exynos5260 pin-controller 2 */
998 static struct samsung_pin_bank exynos5260_pin_banks2[] = {
999 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
1000 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
1001 };
1002
1003 /*
1004 * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes
1005 * three gpio/pin-mux/pinconfig controllers.
1006 */
1007 struct samsung_pin_ctrl exynos5260_pin_ctrl[] = {
1008 {
1009 /* pin-controller instance 0 data */
1010 .pin_banks = exynos5260_pin_banks0,
1011 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0),
1012 .eint_gpio_init = exynos_eint_gpio_init,
1013 .eint_wkup_init = exynos_eint_wkup_init,
1014 .label = "exynos5260-gpio-ctrl0",
1015 }, {
1016 /* pin-controller instance 1 data */
1017 .pin_banks = exynos5260_pin_banks1,
1018 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1),
1019 .eint_gpio_init = exynos_eint_gpio_init,
1020 .label = "exynos5260-gpio-ctrl1",
1021 }, {
1022 /* pin-controller instance 2 data */
1023 .pin_banks = exynos5260_pin_banks2,
1024 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2),
1025 .eint_gpio_init = exynos_eint_gpio_init,
1026 .label = "exynos5260-gpio-ctrl2",
1027 },
1028 };
1029
1030 /* pin banks of exynos5420 pin-controller 0 */
1031 static struct samsung_pin_bank exynos5420_pin_banks0[] = {
1032 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
1033 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
1034 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
1035 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
1036 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
1037 };
1038
1039 /* pin banks of exynos5420 pin-controller 1 */
1040 static struct samsung_pin_bank exynos5420_pin_banks1[] = {
1041 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00),
1042 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04),
1043 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
1044 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
1045 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10),
1046 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14),
1047 EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"),
1048 EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"),
1049 EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"),
1050 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"),
1051 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"),
1052 EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"),
1053 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"),
1054 };
1055
1056 /* pin banks of exynos5420 pin-controller 2 */
1057 static struct samsung_pin_bank exynos5420_pin_banks2[] = {
1058 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
1059 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
1060 EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08),
1061 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c),
1062 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
1063 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
1064 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
1065 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c),
1066 };
1067
1068 /* pin banks of exynos5420 pin-controller 3 */
1069 static struct samsung_pin_bank exynos5420_pin_banks3[] = {
1070 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
1071 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
1072 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
1073 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
1074 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
1075 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
1076 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18),
1077 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c),
1078 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20),
1079 };
1080
1081 /* pin banks of exynos5420 pin-controller 4 */
1082 static struct samsung_pin_bank exynos5420_pin_banks4[] = {
1083 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
1084 };
1085
1086 /*
1087 * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes
1088 * four gpio/pin-mux/pinconfig controllers.
1089 */
1090 struct samsung_pin_ctrl exynos5420_pin_ctrl[] = {
1091 {
1092 /* pin-controller instance 0 data */
1093 .pin_banks = exynos5420_pin_banks0,
1094 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0),
1095 .eint_gpio_init = exynos_eint_gpio_init,
1096 .eint_wkup_init = exynos_eint_wkup_init,
1097 .label = "exynos5420-gpio-ctrl0",
1098 }, {
1099 /* pin-controller instance 1 data */
1100 .pin_banks = exynos5420_pin_banks1,
1101 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1),
1102 .eint_gpio_init = exynos_eint_gpio_init,
1103 .label = "exynos5420-gpio-ctrl1",
1104 }, {
1105 /* pin-controller instance 2 data */
1106 .pin_banks = exynos5420_pin_banks2,
1107 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2),
1108 .eint_gpio_init = exynos_eint_gpio_init,
1109 .label = "exynos5420-gpio-ctrl2",
1110 }, {
1111 /* pin-controller instance 3 data */
1112 .pin_banks = exynos5420_pin_banks3,
1113 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3),
1114 .eint_gpio_init = exynos_eint_gpio_init,
1115 .label = "exynos5420-gpio-ctrl3",
1116 }, {
1117 /* pin-controller instance 4 data */
1118 .pin_banks = exynos5420_pin_banks4,
1119 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4),
1120 .eint_gpio_init = exynos_eint_gpio_init,
1121 .label = "exynos5420-gpio-ctrl4",
1122 },
1123 };
Linux kernel - Deliverables
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