drivers/pinctrl/sh-pfc/core.c

   1 /*
   2  * SuperH Pin Function Controller support.
   3  *
   4  * Copyright (C) 2008 Magnus Damm
   5  * Copyright (C) 2009 - 2012 Paul Mundt
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11
  12 #define DRV_NAME "sh-pfc"
  13
  14 #include <linux/bitops.h>
  15 #include <linux/err.h>
  16 #include <linux/errno.h>
  17 #include <linux/io.h>
  18 #include <linux/ioport.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23 #include <linux/pinctrl/machine.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/slab.h>
  26
  27 #include "core.h"
  28
  29 static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev)
  30 {
  31         struct resource *res;
  32         int k;
  33
  34         if (pdev->num_resources == 0)
  35                 return -EINVAL;
  36
  37         pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources *
  38                                    sizeof(*pfc->window), GFP_NOWAIT);
  39         if (!pfc->window)
  40                 return -ENOMEM;
  41
  42         pfc->num_windows = pdev->num_resources;
  43
  44         for (k = 0, res = pdev->resource; k < pdev->num_resources; k++, res++) {
  45                 WARN_ON(resource_type(res) != IORESOURCE_MEM);
  46                 pfc->window[k].phys = res->start;
  47                 pfc->window[k].size = resource_size(res);
  48                 pfc->window[k].virt = devm_ioremap_nocache(pfc->dev, res->start,
  49                                                            resource_size(res));
  50                 if (!pfc->window[k].virt)
  51                         return -ENOMEM;
  52         }
  53
  54         return 0;
  55 }
  56
  57 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
  58                                          unsigned long address)
  59 {
  60         struct sh_pfc_window *window;
  61         unsigned int i;
  62
  63         /* scan through physical windows and convert address */
  64         for (i = 0; i < pfc->num_windows; i++) {
  65                 window = pfc->window + i;
  66
  67                 if (address < window->phys)
  68                         continue;
  69
  70                 if (address >= (window->phys + window->size))
  71                         continue;
  72
  73                 return window->virt + (address - window->phys);
  74         }
  75
  76         BUG();
  77         return NULL;
  78 }
  79
  80 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
  81 {
  82         unsigned int offset;
  83         unsigned int i;
  84
  85         for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
  86                 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
  87
  88                 if (pin <= range->end)
  89                         return pin >= range->start
  90                              ? offset + pin - range->start : -1;
  91
  92                 offset += range->end - range->start + 1;
  93         }
  94
  95         return -EINVAL;
  96 }
  97
  98 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
  99 {
 100         if (enum_id < r->begin)
 101                 return 0;
 102
 103         if (enum_id > r->end)
 104                 return 0;
 105
 106         return 1;
 107 }
 108
 109 unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
 110                                   unsigned long reg_width)
 111 {
 112         switch (reg_width) {
 113         case 8:
 114                 return ioread8(mapped_reg);
 115         case 16:
 116                 return ioread16(mapped_reg);
 117         case 32:
 118                 return ioread32(mapped_reg);
 119         }
 120
 121         BUG();
 122         return 0;
 123 }
 124
 125 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
 126                           unsigned long data)
 127 {
 128         switch (reg_width) {
 129         case 8:
 130                 iowrite8(data, mapped_reg);
 131                 return;
 132         case 16:
 133                 iowrite16(data, mapped_reg);
 134                 return;
 135         case 32:
 136                 iowrite32(data, mapped_reg);
 137                 return;
 138         }
 139
 140         BUG();
 141 }
 142
 143 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
 144                                      const struct pinmux_cfg_reg *crp,
 145                                      unsigned long in_pos,
 146                                      void __iomem **mapped_regp,
 147                                      unsigned long *maskp,
 148                                      unsigned long *posp)
 149 {
 150         int k;
 151
 152         *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
 153
 154         if (crp->field_width) {
 155                 *maskp = (1 << crp->field_width) - 1;
 156                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
 157         } else {
 158                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
 159                 *posp = crp->reg_width;
 160                 for (k = 0; k <= in_pos; k++)
 161                         *posp -= crp->var_field_width[k];
 162         }
 163 }
 164
 165 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
 166                                     const struct pinmux_cfg_reg *crp,
 167                                     unsigned long field, unsigned long value)
 168 {
 169         void __iomem *mapped_reg;
 170         unsigned long mask, pos, data;
 171
 172         sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 173
 174         dev_dbg(pfc->dev, "write_reg addr = %lx, value = %ld, field = %ld, "
 175                 "r_width = %ld, f_width = %ld\n",
 176                 crp->reg, value, field, crp->reg_width, crp->field_width);
 177
 178         mask = ~(mask << pos);
 179         value = value << pos;
 180
 181         data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
 182         data &= mask;
 183         data |= value;
 184
 185         if (pfc->info->unlock_reg)
 186                 sh_pfc_write_raw_reg(
 187                         sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
 188                         ~data);
 189
 190         sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
 191 }
 192
 193 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
 194                                  const struct pinmux_cfg_reg **crp, int *fieldp,
 195                                  int *valuep)
 196 {
 197         const struct pinmux_cfg_reg *config_reg;
 198         unsigned long r_width, f_width, curr_width, ncomb;
 199         int k, m, n, pos, bit_pos;
 200
 201         k = 0;
 202         while (1) {
 203                 config_reg = pfc->info->cfg_regs + k;
 204
 205                 r_width = config_reg->reg_width;
 206                 f_width = config_reg->field_width;
 207
 208                 if (!r_width)
 209                         break;
 210
 211                 pos = 0;
 212                 m = 0;
 213                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
 214                         if (f_width)
 215                                 curr_width = f_width;
 216                         else
 217                                 curr_width = config_reg->var_field_width[m];
 218
 219                         ncomb = 1 << curr_width;
 220                         for (n = 0; n < ncomb; n++) {
 221                                 if (config_reg->enum_ids[pos + n] == enum_id) {
 222                                         *crp = config_reg;
 223                                         *fieldp = m;
 224                                         *valuep = n;
 225                                         return 0;
 226                                 }
 227                         }
 228                         pos += ncomb;
 229                         m++;
 230                 }
 231                 k++;
 232         }
 233
 234         return -EINVAL;
 235 }
 236
 237 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
 238                               u16 *enum_idp)
 239 {
 240         const u16 *data = pfc->info->gpio_data;
 241         int k;
 242
 243         if (pos) {
 244                 *enum_idp = data[pos + 1];
 245                 return pos + 1;
 246         }
 247
 248         for (k = 0; k < pfc->info->gpio_data_size; k++) {
 249                 if (data[k] == mark) {
 250                         *enum_idp = data[k + 1];
 251                         return k + 1;
 252                 }
 253         }
 254
 255         dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
 256                 mark);
 257         return -EINVAL;
 258 }
 259
 260 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 261 {
 262         const struct pinmux_cfg_reg *cr = NULL;
 263         u16 enum_id;
 264         const struct pinmux_range *range;
 265         int in_range, pos, field, value;
 266         int ret;
 267
 268         switch (pinmux_type) {
 269         case PINMUX_TYPE_GPIO:
 270         case PINMUX_TYPE_FUNCTION:
 271                 range = NULL;
 272                 break;
 273
 274         case PINMUX_TYPE_OUTPUT:
 275                 range = &pfc->info->output;
 276                 break;
 277
 278         case PINMUX_TYPE_INPUT:
 279                 range = &pfc->info->input;
 280                 break;
 281
 282         default:
 283                 return -EINVAL;
 284         }
 285
 286         pos = 0;
 287         enum_id = 0;
 288         field = 0;
 289         value = 0;
 290
 291         /* Iterate over all the configuration fields we need to update. */
 292         while (1) {
 293                 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
 294                 if (pos < 0)
 295                         return pos;
 296
 297                 if (!enum_id)
 298                         break;
 299
 300                 /* Check if the configuration field selects a function. If it
 301                  * doesn't, skip the field if it's not applicable to the
 302                  * requested pinmux type.
 303                  */
 304                 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
 305                 if (!in_range) {
 306                         if (pinmux_type == PINMUX_TYPE_FUNCTION) {
 307                                 /* Functions are allowed to modify all
 308                                  * fields.
 309                                  */
 310                                 in_range = 1;
 311                         } else if (pinmux_type != PINMUX_TYPE_GPIO) {
 312                                 /* Input/output types can only modify fields
 313                                  * that correspond to their respective ranges.
 314                                  */
 315                                 in_range = sh_pfc_enum_in_range(enum_id, range);
 316
 317                                 /*
 318                                  * special case pass through for fixed
 319                                  * input-only or output-only pins without
 320                                  * function enum register association.
 321                                  */
 322                                 if (in_range && enum_id == range->force)
 323                                         continue;
 324                         }
 325                         /* GPIOs are only allowed to modify function fields. */
 326                 }
 327
 328                 if (!in_range)
 329                         continue;
 330
 331                 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
 332                 if (ret < 0)
 333                         return ret;
 334
 335                 sh_pfc_write_config_reg(pfc, cr, field, value);
 336         }
 337
 338         return 0;
 339 }
 340
 341 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
 342 {
 343         struct sh_pfc_pin_range *range;
 344         unsigned int nr_ranges;
 345         unsigned int i;
 346
 347         if (pfc->info->pins[0].pin == (u16)-1) {
 348                 /* Pin number -1 denotes that the SoC doesn't report pin numbers
 349                  * in its pin arrays yet. Consider the pin numbers range as
 350                  * continuous and allocate a single range.
 351                  */
 352                 pfc->nr_ranges = 1;
 353                 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
 354                                            GFP_KERNEL);
 355                 if (pfc->ranges == NULL)
 356                         return -ENOMEM;
 357
 358                 pfc->ranges->start = 0;
 359                 pfc->ranges->end = pfc->info->nr_pins - 1;
 360                 pfc->nr_gpio_pins = pfc->info->nr_pins;
 361
 362                 return 0;
 363         }
 364
 365         /* Count, allocate and fill the ranges. The PFC SoC data pins array must
 366          * be sorted by pin numbers, and pins without a GPIO port must come
 367          * last.
 368          */
 369         for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
 370                 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
 371                         nr_ranges++;
 372         }
 373
 374         pfc->nr_ranges = nr_ranges;
 375         pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges) * nr_ranges,
 376                                    GFP_KERNEL);
 377         if (pfc->ranges == NULL)
 378                 return -ENOMEM;
 379
 380         range = pfc->ranges;
 381         range->start = pfc->info->pins[0].pin;
 382
 383         for (i = 1; i < pfc->info->nr_pins; ++i) {
 384                 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
 385                         continue;
 386
 387                 range->end = pfc->info->pins[i-1].pin;
 388                 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 389                         pfc->nr_gpio_pins = range->end + 1;
 390
 391                 range++;
 392                 range->start = pfc->info->pins[i].pin;
 393         }
 394
 395         range->end = pfc->info->pins[i-1].pin;
 396         if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 397                 pfc->nr_gpio_pins = range->end + 1;
 398
 399         return 0;
 400 }
 401
 402 #ifdef CONFIG_OF
 403 static const struct of_device_id sh_pfc_of_table[] = {
 404 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
 405         {
 406                 .compatible = "renesas,pfc-r8a73a4",
 407                 .data = &r8a73a4_pinmux_info,
 408         },
 409 #endif
 410 #ifdef CONFIG_PINCTRL_PFC_R8A7740
 411         {
 412                 .compatible = "renesas,pfc-r8a7740",
 413                 .data = &r8a7740_pinmux_info,
 414         },
 415 #endif
 416 #ifdef CONFIG_PINCTRL_PFC_R8A7778
 417         {
 418                 .compatible = "renesas,pfc-r8a7778",
 419                 .data = &r8a7778_pinmux_info,
 420         },
 421 #endif
 422 #ifdef CONFIG_PINCTRL_PFC_R8A7779
 423         {
 424                 .compatible = "renesas,pfc-r8a7779",
 425                 .data = &r8a7779_pinmux_info,
 426         },
 427 #endif
 428 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 429         {
 430                 .compatible = "renesas,pfc-r8a7790",
 431                 .data = &r8a7790_pinmux_info,
 432         },
 433 #endif
 434 #ifdef CONFIG_PINCTRL_PFC_SH7372
 435         {
 436                 .compatible = "renesas,pfc-sh7372",
 437                 .data = &sh7372_pinmux_info,
 438         },
 439 #endif
 440 #ifdef CONFIG_PINCTRL_PFC_SH73A0
 441         {
 442                 .compatible = "renesas,pfc-sh73a0",
 443                 .data = &sh73a0_pinmux_info,
 444         },
 445 #endif
 446         { },
 447 };
 448 MODULE_DEVICE_TABLE(of, sh_pfc_of_table);
 449 #endif
 450
 451 static int sh_pfc_probe(struct platform_device *pdev)
 452 {
 453         const struct platform_device_id *platid = platform_get_device_id(pdev);
 454 #ifdef CONFIG_OF
 455         struct device_node *np = pdev->dev.of_node;
 456 #endif
 457         const struct sh_pfc_soc_info *info;
 458         struct sh_pfc *pfc;
 459         int ret;
 460
 461 #ifdef CONFIG_OF
 462         if (np)
 463                 info = of_match_device(sh_pfc_of_table, &pdev->dev)->data;
 464         else
 465 #endif
 466                 info = platid ? (const void *)platid->driver_data : NULL;
 467
 468         if (info == NULL)
 469                 return -ENODEV;
 470
 471         pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
 472         if (pfc == NULL)
 473                 return -ENOMEM;
 474
 475         pfc->info = info;
 476         pfc->dev = &pdev->dev;
 477
 478         ret = sh_pfc_ioremap(pfc, pdev);
 479         if (unlikely(ret < 0))
 480                 return ret;
 481
 482         spin_lock_init(&pfc->lock);
 483
 484         if (info->ops && info->ops->init) {
 485                 ret = info->ops->init(pfc);
 486                 if (ret < 0)
 487                         return ret;
 488         }
 489
 490         pinctrl_provide_dummies();
 491
 492         ret = sh_pfc_init_ranges(pfc);
 493         if (ret < 0)
 494                 return ret;
 495
 496         /*
 497          * Initialize pinctrl bindings first
 498          */
 499         ret = sh_pfc_register_pinctrl(pfc);
 500         if (unlikely(ret != 0))
 501                 goto error;
 502
 503 #ifdef CONFIG_GPIO_SH_PFC
 504         /*
 505          * Then the GPIO chip
 506          */
 507         ret = sh_pfc_register_gpiochip(pfc);
 508         if (unlikely(ret != 0)) {
 509                 /*
 510                  * If the GPIO chip fails to come up we still leave the
 511                  * PFC state as it is, given that there are already
 512                  * extant users of it that have succeeded by this point.
 513                  */
 514                 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
 515         }
 516 #endif
 517
 518         platform_set_drvdata(pdev, pfc);
 519
 520         dev_info(pfc->dev, "%s support registered\n", info->name);
 521
 522         return 0;
 523
 524 error:
 525         if (info->ops && info->ops->exit)
 526                 info->ops->exit(pfc);
 527         return ret;
 528 }
 529
 530 static int sh_pfc_remove(struct platform_device *pdev)
 531 {
 532         struct sh_pfc *pfc = platform_get_drvdata(pdev);
 533
 534 #ifdef CONFIG_GPIO_SH_PFC
 535         sh_pfc_unregister_gpiochip(pfc);
 536 #endif
 537         sh_pfc_unregister_pinctrl(pfc);
 538
 539         if (pfc->info->ops && pfc->info->ops->exit)
 540                 pfc->info->ops->exit(pfc);
 541
 542         return 0;
 543 }
 544
 545 static const struct platform_device_id sh_pfc_id_table[] = {
 546 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
 547         { "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info },
 548 #endif
 549 #ifdef CONFIG_PINCTRL_PFC_R8A7740
 550         { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
 551 #endif
 552 #ifdef CONFIG_PINCTRL_PFC_R8A7778
 553         { "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info },
 554 #endif
 555 #ifdef CONFIG_PINCTRL_PFC_R8A7779
 556         { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
 557 #endif
 558 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 559         { "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info },
 560 #endif
 561 #ifdef CONFIG_PINCTRL_PFC_SH7203
 562         { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
 563 #endif
 564 #ifdef CONFIG_PINCTRL_PFC_SH7264
 565         { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
 566 #endif
 567 #ifdef CONFIG_PINCTRL_PFC_SH7269
 568         { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
 569 #endif
 570 #ifdef CONFIG_PINCTRL_PFC_SH7372
 571         { "pfc-sh7372", (kernel_ulong_t)&sh7372_pinmux_info },
 572 #endif
 573 #ifdef CONFIG_PINCTRL_PFC_SH73A0
 574         { "pfc-sh73a0", (kernel_ulong_t)&sh73a0_pinmux_info },
 575 #endif
 576 #ifdef CONFIG_PINCTRL_PFC_SH7720
 577         { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
 578 #endif
 579 #ifdef CONFIG_PINCTRL_PFC_SH7722
 580         { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
 581 #endif
 582 #ifdef CONFIG_PINCTRL_PFC_SH7723
 583         { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
 584 #endif
 585 #ifdef CONFIG_PINCTRL_PFC_SH7724
 586         { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
 587 #endif
 588 #ifdef CONFIG_PINCTRL_PFC_SH7734
 589         { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
 590 #endif
 591 #ifdef CONFIG_PINCTRL_PFC_SH7757
 592         { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
 593 #endif
 594 #ifdef CONFIG_PINCTRL_PFC_SH7785
 595         { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
 596 #endif
 597 #ifdef CONFIG_PINCTRL_PFC_SH7786
 598         { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
 599 #endif
 600 #ifdef CONFIG_PINCTRL_PFC_SHX3
 601         { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
 602 #endif
 603         { "sh-pfc", 0 },
 604         { },
 605 };
 606 MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);
 607
 608 static struct platform_driver sh_pfc_driver = {
 609         .probe          = sh_pfc_probe,
 610         .remove         = sh_pfc_remove,
 611         .id_table       = sh_pfc_id_table,
 612         .driver         = {
 613                 .name   = DRV_NAME,
 614                 .owner  = THIS_MODULE,
 615                 .of_match_table = of_match_ptr(sh_pfc_of_table),
 616         },
 617 };
 618
 619 static int __init sh_pfc_init(void)
 620 {
 621         return platform_driver_register(&sh_pfc_driver);
 622 }
 623 postcore_initcall(sh_pfc_init);
 624
 625 static void __exit sh_pfc_exit(void)
 626 {
 627         platform_driver_unregister(&sh_pfc_driver);
 628 }
 629 module_exit(sh_pfc_exit);
 630
 631 MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
 632 MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
 633 MODULE_LICENSE("GPL v2");