drivers/pinctrl/sh-pfc/core.c

   1 /*
   2  * SuperH Pin Function Controller support.
   3  *
   4  * Copyright (C) 2008 Magnus Damm
   5  * Copyright (C) 2009 - 2012 Paul Mundt
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11
  12 #define DRV_NAME "sh-pfc"
  13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  14
  15 #include <linux/bitops.h>
  16 #include <linux/err.h>
  17 #include <linux/errno.h>
  18 #include <linux/io.h>
  19 #include <linux/ioport.h>
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/pinctrl/machine.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/sh_pfc.h>
  25 #include <linux/slab.h>
  26
  27 #include "core.h"
  28
  29 static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev)
  30 {
  31         struct resource *res;
  32         int k;
  33
  34         if (pdev->num_resources == 0) {
  35                 pfc->num_windows = 0;
  36                 return 0;
  37         }
  38
  39         pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources *
  40                                    sizeof(*pfc->window), GFP_NOWAIT);
  41         if (!pfc->window)
  42                 return -ENOMEM;
  43
  44         pfc->num_windows = pdev->num_resources;
  45
  46         for (k = 0, res = pdev->resource; k < pdev->num_resources; k++, res++) {
  47                 WARN_ON(resource_type(res) != IORESOURCE_MEM);
  48                 pfc->window[k].phys = res->start;
  49                 pfc->window[k].size = resource_size(res);
  50                 pfc->window[k].virt = devm_ioremap_nocache(pfc->dev, res->start,
  51                                                            resource_size(res));
  52                 if (!pfc->window[k].virt)
  53                         return -ENOMEM;
  54         }
  55
  56         return 0;
  57 }
  58
  59 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
  60                                          unsigned long address)
  61 {
  62         struct sh_pfc_window *window;
  63         int k;
  64
  65         /* scan through physical windows and convert address */
  66         for (k = 0; k < pfc->num_windows; k++) {
  67                 window = pfc->window + k;
  68
  69                 if (address < window->phys)
  70                         continue;
  71
  72                 if (address >= (window->phys + window->size))
  73                         continue;
  74
  75                 return window->virt + (address - window->phys);
  76         }
  77
  78         /* no windows defined, register must be 1:1 mapped virt:phys */
  79         return (void __iomem *)address;
  80 }
  81
  82 static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
  83 {
  84         if (enum_id < r->begin)
  85                 return 0;
  86
  87         if (enum_id > r->end)
  88                 return 0;
  89
  90         return 1;
  91 }
  92
  93 static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
  94                                          unsigned long reg_width)
  95 {
  96         switch (reg_width) {
  97         case 8:
  98                 return ioread8(mapped_reg);
  99         case 16:
 100                 return ioread16(mapped_reg);
 101         case 32:
 102                 return ioread32(mapped_reg);
 103         }
 104
 105         BUG();
 106         return 0;
 107 }
 108
 109 static void sh_pfc_write_raw_reg(void __iomem *mapped_reg,
 110                                  unsigned long reg_width, unsigned long data)
 111 {
 112         switch (reg_width) {
 113         case 8:
 114                 iowrite8(data, mapped_reg);
 115                 return;
 116         case 16:
 117                 iowrite16(data, mapped_reg);
 118                 return;
 119         case 32:
 120                 iowrite32(data, mapped_reg);
 121                 return;
 122         }
 123
 124         BUG();
 125 }
 126
 127 int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos)
 128 {
 129         unsigned long pos;
 130
 131         pos = dr->reg_width - (in_pos + 1);
 132
 133         pr_debug("read_bit: addr = %lx, pos = %ld, "
 134                  "r_width = %ld\n", dr->reg, pos, dr->reg_width);
 135
 136         return (sh_pfc_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
 137 }
 138
 139 void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
 140                       unsigned long value)
 141 {
 142         unsigned long pos;
 143
 144         pos = dr->reg_width - (in_pos + 1);
 145
 146         pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
 147                  "r_width = %ld\n",
 148                  dr->reg, !!value, pos, dr->reg_width);
 149
 150         if (value)
 151                 set_bit(pos, &dr->reg_shadow);
 152         else
 153                 clear_bit(pos, &dr->reg_shadow);
 154
 155         sh_pfc_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
 156 }
 157
 158 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
 159                                      struct pinmux_cfg_reg *crp,
 160                                      unsigned long in_pos,
 161                                      void __iomem **mapped_regp,
 162                                      unsigned long *maskp,
 163                                      unsigned long *posp)
 164 {
 165         int k;
 166
 167         *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
 168
 169         if (crp->field_width) {
 170                 *maskp = (1 << crp->field_width) - 1;
 171                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
 172         } else {
 173                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
 174                 *posp = crp->reg_width;
 175                 for (k = 0; k <= in_pos; k++)
 176                         *posp -= crp->var_field_width[k];
 177         }
 178 }
 179
 180 static int sh_pfc_read_config_reg(struct sh_pfc *pfc,
 181                                   struct pinmux_cfg_reg *crp,
 182                                   unsigned long field)
 183 {
 184         void __iomem *mapped_reg;
 185         unsigned long mask, pos;
 186
 187         sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 188
 189         pr_debug("read_reg: addr = %lx, field = %ld, "
 190                  "r_width = %ld, f_width = %ld\n",
 191                  crp->reg, field, crp->reg_width, crp->field_width);
 192
 193         return (sh_pfc_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
 194 }
 195
 196 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
 197                                     struct pinmux_cfg_reg *crp,
 198                                     unsigned long field, unsigned long value)
 199 {
 200         void __iomem *mapped_reg;
 201         unsigned long mask, pos, data;
 202
 203         sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 204
 205         pr_debug("write_reg addr = %lx, value = %ld, field = %ld, "
 206                  "r_width = %ld, f_width = %ld\n",
 207                  crp->reg, value, field, crp->reg_width, crp->field_width);
 208
 209         mask = ~(mask << pos);
 210         value = value << pos;
 211
 212         data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
 213         data &= mask;
 214         data |= value;
 215
 216         if (pfc->info->unlock_reg)
 217                 sh_pfc_write_raw_reg(
 218                         sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
 219                         ~data);
 220
 221         sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
 222 }
 223
 224 static int sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
 225 {
 226         struct pinmux_gpio *gpiop = &pfc->info->gpios[gpio];
 227         struct pinmux_data_reg *data_reg;
 228         int k, n;
 229
 230         if (!sh_pfc_enum_in_range(gpiop->enum_id, &pfc->info->data))
 231                 return -1;
 232
 233         k = 0;
 234         while (1) {
 235                 data_reg = pfc->info->data_regs + k;
 236
 237                 if (!data_reg->reg_width)
 238                         break;
 239
 240                 data_reg->mapped_reg = sh_pfc_phys_to_virt(pfc, data_reg->reg);
 241
 242                 for (n = 0; n < data_reg->reg_width; n++) {
 243                         if (data_reg->enum_ids[n] == gpiop->enum_id) {
 244                                 gpiop->flags &= ~PINMUX_FLAG_DREG;
 245                                 gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
 246                                 gpiop->flags &= ~PINMUX_FLAG_DBIT;
 247                                 gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
 248                                 return 0;
 249                         }
 250                 }
 251                 k++;
 252         }
 253
 254         BUG();
 255
 256         return -1;
 257 }
 258
 259 static void sh_pfc_setup_data_regs(struct sh_pfc *pfc)
 260 {
 261         struct pinmux_data_reg *drp;
 262         int k;
 263
 264         for (k = pfc->info->first_gpio; k <= pfc->info->last_gpio; k++)
 265                 sh_pfc_setup_data_reg(pfc, k);
 266
 267         k = 0;
 268         while (1) {
 269                 drp = pfc->info->data_regs + k;
 270
 271                 if (!drp->reg_width)
 272                         break;
 273
 274                 drp->reg_shadow = sh_pfc_read_raw_reg(drp->mapped_reg,
 275                                                       drp->reg_width);
 276                 k++;
 277         }
 278 }
 279
 280 int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
 281                         struct pinmux_data_reg **drp, int *bitp)
 282 {
 283         struct pinmux_gpio *gpiop = &pfc->info->gpios[gpio];
 284         int k, n;
 285
 286         if (!sh_pfc_enum_in_range(gpiop->enum_id, &pfc->info->data))
 287                 return -1;
 288
 289         k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
 290         n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
 291         *drp = pfc->info->data_regs + k;
 292         *bitp = n;
 293         return 0;
 294 }
 295
 296 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
 297                                  struct pinmux_cfg_reg **crp, int *fieldp,
 298                                  int *valuep, unsigned long **cntp)
 299 {
 300         struct pinmux_cfg_reg *config_reg;
 301         unsigned long r_width, f_width, curr_width, ncomb;
 302         int k, m, n, pos, bit_pos;
 303
 304         k = 0;
 305         while (1) {
 306                 config_reg = pfc->info->cfg_regs + k;
 307
 308                 r_width = config_reg->reg_width;
 309                 f_width = config_reg->field_width;
 310
 311                 if (!r_width)
 312                         break;
 313
 314                 pos = 0;
 315                 m = 0;
 316                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
 317                         if (f_width)
 318                                 curr_width = f_width;
 319                         else
 320                                 curr_width = config_reg->var_field_width[m];
 321
 322                         ncomb = 1 << curr_width;
 323                         for (n = 0; n < ncomb; n++) {
 324                                 if (config_reg->enum_ids[pos + n] == enum_id) {
 325                                         *crp = config_reg;
 326                                         *fieldp = m;
 327                                         *valuep = n;
 328                                         *cntp = &config_reg->cnt[m];
 329                                         return 0;
 330                                 }
 331                         }
 332                         pos += ncomb;
 333                         m++;
 334                 }
 335                 k++;
 336         }
 337
 338         return -1;
 339 }
 340
 341 int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
 342                         pinmux_enum_t *enum_idp)
 343 {
 344         pinmux_enum_t enum_id = pfc->info->gpios[gpio].enum_id;
 345         pinmux_enum_t *data = pfc->info->gpio_data;
 346         int k;
 347
 348         if (!sh_pfc_enum_in_range(enum_id, &pfc->info->data)) {
 349                 if (!sh_pfc_enum_in_range(enum_id, &pfc->info->mark)) {
 350                         pr_err("non data/mark enum_id for gpio %d\n", gpio);
 351                         return -1;
 352                 }
 353         }
 354
 355         if (pos) {
 356                 *enum_idp = data[pos + 1];
 357                 return pos + 1;
 358         }
 359
 360         for (k = 0; k < pfc->info->gpio_data_size; k++) {
 361                 if (data[k] == enum_id) {
 362                         *enum_idp = data[k + 1];
 363                         return k + 1;
 364                 }
 365         }
 366
 367         pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
 368         return -1;
 369 }
 370
 371 int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
 372                        int cfg_mode)
 373 {
 374         struct pinmux_cfg_reg *cr = NULL;
 375         pinmux_enum_t enum_id;
 376         struct pinmux_range *range;
 377         int in_range, pos, field, value;
 378         unsigned long *cntp;
 379
 380         switch (pinmux_type) {
 381
 382         case PINMUX_TYPE_FUNCTION:
 383                 range = NULL;
 384                 break;
 385
 386         case PINMUX_TYPE_OUTPUT:
 387                 range = &pfc->info->output;
 388                 break;
 389
 390         case PINMUX_TYPE_INPUT:
 391                 range = &pfc->info->input;
 392                 break;
 393
 394         case PINMUX_TYPE_INPUT_PULLUP:
 395                 range = &pfc->info->input_pu;
 396                 break;
 397
 398         case PINMUX_TYPE_INPUT_PULLDOWN:
 399                 range = &pfc->info->input_pd;
 400                 break;
 401
 402         default:
 403                 goto out_err;
 404         }
 405
 406         pos = 0;
 407         enum_id = 0;
 408         field = 0;
 409         value = 0;
 410         while (1) {
 411                 pos = sh_pfc_gpio_to_enum(pfc, gpio, pos, &enum_id);
 412                 if (pos <= 0)
 413                         goto out_err;
 414
 415                 if (!enum_id)
 416                         break;
 417
 418                 /* first check if this is a function enum */
 419                 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
 420                 if (!in_range) {
 421                         /* not a function enum */
 422                         if (range) {
 423                                 /*
 424                                  * other range exists, so this pin is
 425                                  * a regular GPIO pin that now is being
 426                                  * bound to a specific direction.
 427                                  *
 428                                  * for this case we only allow function enums
 429                                  * and the enums that match the other range.
 430                                  */
 431                                 in_range = sh_pfc_enum_in_range(enum_id, range);
 432
 433                                 /*
 434                                  * special case pass through for fixed
 435                                  * input-only or output-only pins without
 436                                  * function enum register association.
 437                                  */
 438                                 if (in_range && enum_id == range->force)
 439                                         continue;
 440                         } else {
 441                                 /*
 442                                  * no other range exists, so this pin
 443                                  * must then be of the function type.
 444                                  *
 445                                  * allow function type pins to select
 446                                  * any combination of function/in/out
 447                                  * in their MARK lists.
 448                                  */
 449                                 in_range = 1;
 450                         }
 451                 }
 452
 453                 if (!in_range)
 454                         continue;
 455
 456                 if (sh_pfc_get_config_reg(pfc, enum_id, &cr,
 457                                           &field, &value, &cntp) != 0)
 458                         goto out_err;
 459
 460                 switch (cfg_mode) {
 461                 case GPIO_CFG_DRYRUN:
 462                         if (!*cntp ||
 463                             (sh_pfc_read_config_reg(pfc, cr, field) != value))
 464                                 continue;
 465                         break;
 466
 467                 case GPIO_CFG_REQ:
 468                         sh_pfc_write_config_reg(pfc, cr, field, value);
 469                         *cntp = *cntp + 1;
 470                         break;
 471
 472                 case GPIO_CFG_FREE:
 473                         *cntp = *cntp - 1;
 474                         break;
 475                 }
 476         }
 477
 478         return 0;
 479  out_err:
 480         return -1;
 481 }
 482
 483 static int sh_pfc_probe(struct platform_device *pdev)
 484 {
 485         struct sh_pfc_soc_info *info;
 486         struct sh_pfc *pfc;
 487         int ret;
 488
 489         /*
 490          * Ensure that the type encoding fits
 491          */
 492         BUILD_BUG_ON(PINMUX_FLAG_TYPE > ((1 << PINMUX_FLAG_DBIT_SHIFT) - 1));
 493
 494         info = pdev->id_entry->driver_data
 495               ? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data;
 496         if (info == NULL)
 497                 return -ENODEV;
 498
 499         pfc = devm_kzalloc(&pdev->dev, sizeof(pfc), GFP_KERNEL);
 500         if (pfc == NULL)
 501                 return -ENOMEM;
 502
 503         pfc->info = info;
 504         pfc->dev = &pdev->dev;
 505
 506         ret = sh_pfc_ioremap(pfc, pdev);
 507         if (unlikely(ret < 0))
 508                 return ret;
 509
 510         spin_lock_init(&pfc->lock);
 511
 512         pinctrl_provide_dummies();
 513         sh_pfc_setup_data_regs(pfc);
 514
 515         /*
 516          * Initialize pinctrl bindings first
 517          */
 518         ret = sh_pfc_register_pinctrl(pfc);
 519         if (unlikely(ret != 0))
 520                 return ret;
 521
 522 #ifdef CONFIG_GPIO_SH_PFC
 523         /*
 524          * Then the GPIO chip
 525          */
 526         ret = sh_pfc_register_gpiochip(pfc);
 527         if (unlikely(ret != 0)) {
 528                 /*
 529                  * If the GPIO chip fails to come up we still leave the
 530                  * PFC state as it is, given that there are already
 531                  * extant users of it that have succeeded by this point.
 532                  */
 533                 pr_notice("failed to init GPIO chip, ignoring...\n");
 534         }
 535 #endif
 536
 537         platform_set_drvdata(pdev, pfc);
 538
 539         pr_info("%s support registered\n", info->name);
 540
 541         return 0;
 542 }
 543
 544 static int sh_pfc_remove(struct platform_device *pdev)
 545 {
 546         struct sh_pfc *pfc = platform_get_drvdata(pdev);
 547
 548 #ifdef CONFIG_GPIO_SH_PFC
 549         sh_pfc_unregister_gpiochip(pfc);
 550 #endif
 551         sh_pfc_unregister_pinctrl(pfc);
 552
 553         platform_set_drvdata(pdev, NULL);
 554
 555         return 0;
 556 }
 557
 558 static const struct platform_device_id sh_pfc_id_table[] = {
 559 #ifdef CONFIG_PINCTRL_PFC_R8A7740
 560         { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
 561 #endif
 562 #ifdef CONFIG_PINCTRL_PFC_R8A7779
 563         { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
 564 #endif
 565 #ifdef CONFIG_PINCTRL_PFC_SH7203
 566         { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
 567 #endif
 568 #ifdef CONFIG_PINCTRL_PFC_SH7264
 569         { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
 570 #endif
 571 #ifdef CONFIG_PINCTRL_PFC_SH7269
 572         { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
 573 #endif
 574 #ifdef CONFIG_PINCTRL_PFC_SH7372
 575         { "pfc-sh7372", (kernel_ulong_t)&sh7372_pinmux_info },
 576 #endif
 577 #ifdef CONFIG_PINCTRL_PFC_SH73A0
 578         { "pfc-sh73a0", (kernel_ulong_t)&sh73a0_pinmux_info },
 579 #endif
 580 #ifdef CONFIG_PINCTRL_PFC_SH7720
 581         { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
 582 #endif
 583 #ifdef CONFIG_PINCTRL_PFC_SH7722
 584         { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
 585 #endif
 586 #ifdef CONFIG_PINCTRL_PFC_SH7723
 587         { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
 588 #endif
 589 #ifdef CONFIG_PINCTRL_PFC_SH7724
 590         { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
 591 #endif
 592 #ifdef CONFIG_PINCTRL_PFC_SH7734
 593         { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
 594 #endif
 595         { "sh-pfc", 0 },
 596         { },
 597 };
 598 MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);
 599
 600 static struct platform_driver sh_pfc_driver = {
 601         .probe          = sh_pfc_probe,
 602         .remove         = sh_pfc_remove,
 603         .id_table       = sh_pfc_id_table,
 604         .driver         = {
 605                 .name   = DRV_NAME,
 606                 .owner  = THIS_MODULE,
 607         },
 608 };
 609
 610 static int __init sh_pfc_init(void)
 611 {
 612         return platform_driver_register(&sh_pfc_driver);
 613 }
 614 postcore_initcall(sh_pfc_init);
 615
 616 static void __exit sh_pfc_exit(void)
 617 {
 618         platform_driver_unregister(&sh_pfc_driver);
 619 }
 620 module_exit(sh_pfc_exit);
 621
 622 MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
 623 MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
 624 MODULE_LICENSE("GPL v2");