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dmaengine: pl330: Remove non-NULL check for pl330_submit_req parameters
[deliverable/linux.git] / drivers / pinctrl / sh-pfc / pfc-r8a73a4.c
1 /*
2 * Copyright (C) 2012-2013 Renesas Solutions Corp.
3 * Copyright (C) 2013 Magnus Damm
4 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of the
9 * License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20 #include <linux/io.h>
21 #include <linux/kernel.h>
22 #include <linux/pinctrl/pinconf-generic.h>
23
24 #ifndef CONFIG_ARCH_MULTIPLATFORM
25 #include <mach/irqs.h>
26 #endif
27
28 #include "core.h"
29 #include "sh_pfc.h"
30
31 #define CPU_ALL_PORT(fn, pfx, sfx) \
32 /* Port0 - Port30 */ \
33 PORT_10(0, fn, pfx, sfx), \
34 PORT_10(10, fn, pfx##1, sfx), \
35 PORT_10(20, fn, pfx##2, sfx), \
36 PORT_1(30, fn, pfx##30, sfx), \
37 /* Port32 - Port40 */ \
38 PORT_1(32, fn, pfx##32, sfx), PORT_1(33, fn, pfx##33, sfx), \
39 PORT_1(34, fn, pfx##34, sfx), PORT_1(35, fn, pfx##35, sfx), \
40 PORT_1(36, fn, pfx##36, sfx), PORT_1(37, fn, pfx##37, sfx), \
41 PORT_1(38, fn, pfx##38, sfx), PORT_1(39, fn, pfx##39, sfx), \
42 PORT_1(40, fn, pfx##40, sfx), \
43 /* Port64 - Port85 */ \
44 PORT_1(64, fn, pfx##64, sfx), PORT_1(65, fn, pfx##65, sfx), \
45 PORT_1(66, fn, pfx##66, sfx), PORT_1(67, fn, pfx##67, sfx), \
46 PORT_1(68, fn, pfx##68, sfx), PORT_1(69, fn, pfx##69, sfx), \
47 PORT_10(70, fn, pfx##7, sfx), \
48 PORT_1(80, fn, pfx##80, sfx), PORT_1(81, fn, pfx##81, sfx), \
49 PORT_1(82, fn, pfx##82, sfx), PORT_1(83, fn, pfx##83, sfx), \
50 PORT_1(84, fn, pfx##84, sfx), PORT_1(85, fn, pfx##85, sfx), \
51 /* Port96 - Port126 */ \
52 PORT_1(96, fn, pfx##96, sfx), PORT_1(97, fn, pfx##97, sfx), \
53 PORT_1(98, fn, pfx##98, sfx), PORT_1(99, fn, pfx##99, sfx), \
54 PORT_10(100, fn, pfx##10, sfx), \
55 PORT_10(110, fn, pfx##11, sfx), \
56 PORT_1(120, fn, pfx##120, sfx), PORT_1(121, fn, pfx##121, sfx), \
57 PORT_1(122, fn, pfx##122, sfx), PORT_1(123, fn, pfx##123, sfx), \
58 PORT_1(124, fn, pfx##124, sfx), PORT_1(125, fn, pfx##125, sfx), \
59 PORT_1(126, fn, pfx##126, sfx), \
60 /* Port128 - Port134 */ \
61 PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx), \
62 PORT_1(130, fn, pfx##130, sfx), PORT_1(131, fn, pfx##131, sfx), \
63 PORT_1(132, fn, pfx##132, sfx), PORT_1(133, fn, pfx##133, sfx), \
64 PORT_1(134, fn, pfx##134, sfx), \
65 /* Port160 - Port178 */ \
66 PORT_10(160, fn, pfx##16, sfx), \
67 PORT_1(170, fn, pfx##170, sfx), PORT_1(171, fn, pfx##171, sfx), \
68 PORT_1(172, fn, pfx##172, sfx), PORT_1(173, fn, pfx##173, sfx), \
69 PORT_1(174, fn, pfx##174, sfx), PORT_1(175, fn, pfx##175, sfx), \
70 PORT_1(176, fn, pfx##176, sfx), PORT_1(177, fn, pfx##177, sfx), \
71 PORT_1(178, fn, pfx##178, sfx), \
72 /* Port192 - Port222 */ \
73 PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx), \
74 PORT_1(194, fn, pfx##194, sfx), PORT_1(195, fn, pfx##195, sfx), \
75 PORT_1(196, fn, pfx##196, sfx), PORT_1(197, fn, pfx##197, sfx), \
76 PORT_1(198, fn, pfx##198, sfx), PORT_1(199, fn, pfx##199, sfx), \
77 PORT_10(200, fn, pfx##20, sfx), \
78 PORT_10(210, fn, pfx##21, sfx), \
79 PORT_1(220, fn, pfx##220, sfx), PORT_1(221, fn, pfx##221, sfx), \
80 PORT_1(222, fn, pfx##222, sfx), \
81 /* Port224 - Port250 */ \
82 PORT_1(224, fn, pfx##224, sfx), PORT_1(225, fn, pfx##225, sfx), \
83 PORT_1(226, fn, pfx##226, sfx), PORT_1(227, fn, pfx##227, sfx), \
84 PORT_1(228, fn, pfx##228, sfx), PORT_1(229, fn, pfx##229, sfx), \
85 PORT_10(230, fn, pfx##23, sfx), \
86 PORT_10(240, fn, pfx##24, sfx), \
87 PORT_1(250, fn, pfx##250, sfx), \
88 /* Port256 - Port283 */ \
89 PORT_1(256, fn, pfx##256, sfx), PORT_1(257, fn, pfx##257, sfx), \
90 PORT_1(258, fn, pfx##258, sfx), PORT_1(259, fn, pfx##259, sfx), \
91 PORT_10(260, fn, pfx##26, sfx), \
92 PORT_10(270, fn, pfx##27, sfx), \
93 PORT_1(280, fn, pfx##280, sfx), PORT_1(281, fn, pfx##281, sfx), \
94 PORT_1(282, fn, pfx##282, sfx), PORT_1(283, fn, pfx##283, sfx), \
95 /* Port288 - Port308 */ \
96 PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \
97 PORT_10(290, fn, pfx##29, sfx), \
98 PORT_1(300, fn, pfx##300, sfx), PORT_1(301, fn, pfx##301, sfx), \
99 PORT_1(302, fn, pfx##302, sfx), PORT_1(303, fn, pfx##303, sfx), \
100 PORT_1(304, fn, pfx##304, sfx), PORT_1(305, fn, pfx##305, sfx), \
101 PORT_1(306, fn, pfx##306, sfx), PORT_1(307, fn, pfx##307, sfx), \
102 PORT_1(308, fn, pfx##308, sfx), \
103 /* Port320 - Port329 */ \
104 PORT_10(320, fn, pfx##32, sfx)
105
106
107 enum {
108 PINMUX_RESERVED = 0,
109
110 /* PORT0_DATA -> PORT329_DATA */
111 PINMUX_DATA_BEGIN,
112 PORT_ALL(DATA),
113 PINMUX_DATA_END,
114
115 /* PORT0_IN -> PORT329_IN */
116 PINMUX_INPUT_BEGIN,
117 PORT_ALL(IN),
118 PINMUX_INPUT_END,
119
120 /* PORT0_OUT -> PORT329_OUT */
121 PINMUX_OUTPUT_BEGIN,
122 PORT_ALL(OUT),
123 PINMUX_OUTPUT_END,
124
125 PINMUX_FUNCTION_BEGIN,
126 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT329_FN_IN */
127 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT329_FN_OUT */
128 PORT_ALL(FN0), /* PORT0_FN0 -> PORT329_FN0 */
129 PORT_ALL(FN1), /* PORT0_FN1 -> PORT329_FN1 */
130 PORT_ALL(FN2), /* PORT0_FN2 -> PORT329_FN2 */
131 PORT_ALL(FN3), /* PORT0_FN3 -> PORT329_FN3 */
132 PORT_ALL(FN4), /* PORT0_FN4 -> PORT329_FN4 */
133 PORT_ALL(FN5), /* PORT0_FN5 -> PORT329_FN5 */
134 PORT_ALL(FN6), /* PORT0_FN6 -> PORT329_FN6 */
135 PORT_ALL(FN7), /* PORT0_FN7 -> PORT329_FN7 */
136
137 MSEL1CR_31_0, MSEL1CR_31_1,
138 MSEL1CR_27_0, MSEL1CR_27_1,
139 MSEL1CR_25_0, MSEL1CR_25_1,
140 MSEL1CR_24_0, MSEL1CR_24_1,
141 MSEL1CR_22_0, MSEL1CR_22_1,
142 MSEL1CR_21_0, MSEL1CR_21_1,
143 MSEL1CR_20_0, MSEL1CR_20_1,
144 MSEL1CR_19_0, MSEL1CR_19_1,
145 MSEL1CR_18_0, MSEL1CR_18_1,
146 MSEL1CR_17_0, MSEL1CR_17_1,
147 MSEL1CR_16_0, MSEL1CR_16_1,
148 MSEL1CR_15_0, MSEL1CR_15_1,
149 MSEL1CR_14_0, MSEL1CR_14_1,
150 MSEL1CR_13_0, MSEL1CR_13_1,
151 MSEL1CR_12_0, MSEL1CR_12_1,
152 MSEL1CR_11_0, MSEL1CR_11_1,
153 MSEL1CR_10_0, MSEL1CR_10_1,
154 MSEL1CR_09_0, MSEL1CR_09_1,
155 MSEL1CR_08_0, MSEL1CR_08_1,
156 MSEL1CR_07_0, MSEL1CR_07_1,
157 MSEL1CR_06_0, MSEL1CR_06_1,
158 MSEL1CR_05_0, MSEL1CR_05_1,
159 MSEL1CR_04_0, MSEL1CR_04_1,
160 MSEL1CR_03_0, MSEL1CR_03_1,
161 MSEL1CR_02_0, MSEL1CR_02_1,
162 MSEL1CR_01_0, MSEL1CR_01_1,
163 MSEL1CR_00_0, MSEL1CR_00_1,
164
165 MSEL3CR_31_0, MSEL3CR_31_1,
166 MSEL3CR_28_0, MSEL3CR_28_1,
167 MSEL3CR_27_0, MSEL3CR_27_1,
168 MSEL3CR_26_0, MSEL3CR_26_1,
169 MSEL3CR_23_0, MSEL3CR_23_1,
170 MSEL3CR_22_0, MSEL3CR_22_1,
171 MSEL3CR_21_0, MSEL3CR_21_1,
172 MSEL3CR_20_0, MSEL3CR_20_1,
173 MSEL3CR_19_0, MSEL3CR_19_1,
174 MSEL3CR_18_0, MSEL3CR_18_1,
175 MSEL3CR_17_0, MSEL3CR_17_1,
176 MSEL3CR_16_0, MSEL3CR_16_1,
177 MSEL3CR_15_0, MSEL3CR_15_1,
178 MSEL3CR_12_0, MSEL3CR_12_1,
179 MSEL3CR_11_0, MSEL3CR_11_1,
180 MSEL3CR_10_0, MSEL3CR_10_1,
181 MSEL3CR_09_0, MSEL3CR_09_1,
182 MSEL3CR_06_0, MSEL3CR_06_1,
183 MSEL3CR_03_0, MSEL3CR_03_1,
184 MSEL3CR_01_0, MSEL3CR_01_1,
185 MSEL3CR_00_0, MSEL3CR_00_1,
186
187 MSEL4CR_30_0, MSEL4CR_30_1,
188 MSEL4CR_29_0, MSEL4CR_29_1,
189 MSEL4CR_28_0, MSEL4CR_28_1,
190 MSEL4CR_27_0, MSEL4CR_27_1,
191 MSEL4CR_26_0, MSEL4CR_26_1,
192 MSEL4CR_25_0, MSEL4CR_25_1,
193 MSEL4CR_24_0, MSEL4CR_24_1,
194 MSEL4CR_23_0, MSEL4CR_23_1,
195 MSEL4CR_22_0, MSEL4CR_22_1,
196 MSEL4CR_21_0, MSEL4CR_21_1,
197 MSEL4CR_20_0, MSEL4CR_20_1,
198 MSEL4CR_19_0, MSEL4CR_19_1,
199 MSEL4CR_18_0, MSEL4CR_18_1,
200 MSEL4CR_17_0, MSEL4CR_17_1,
201 MSEL4CR_16_0, MSEL4CR_16_1,
202 MSEL4CR_15_0, MSEL4CR_15_1,
203 MSEL4CR_14_0, MSEL4CR_14_1,
204 MSEL4CR_13_0, MSEL4CR_13_1,
205 MSEL4CR_12_0, MSEL4CR_12_1,
206 MSEL4CR_11_0, MSEL4CR_11_1,
207 MSEL4CR_10_0, MSEL4CR_10_1,
208 MSEL4CR_09_0, MSEL4CR_09_1,
209 MSEL4CR_07_0, MSEL4CR_07_1,
210 MSEL4CR_04_0, MSEL4CR_04_1,
211 MSEL4CR_01_0, MSEL4CR_01_1,
212
213 MSEL5CR_31_0, MSEL5CR_31_1,
214 MSEL5CR_30_0, MSEL5CR_30_1,
215 MSEL5CR_29_0, MSEL5CR_29_1,
216 MSEL5CR_28_0, MSEL5CR_28_1,
217 MSEL5CR_27_0, MSEL5CR_27_1,
218 MSEL5CR_26_0, MSEL5CR_26_1,
219 MSEL5CR_25_0, MSEL5CR_25_1,
220 MSEL5CR_24_0, MSEL5CR_24_1,
221 MSEL5CR_23_0, MSEL5CR_23_1,
222 MSEL5CR_22_0, MSEL5CR_22_1,
223 MSEL5CR_21_0, MSEL5CR_21_1,
224 MSEL5CR_20_0, MSEL5CR_20_1,
225 MSEL5CR_19_0, MSEL5CR_19_1,
226 MSEL5CR_18_0, MSEL5CR_18_1,
227 MSEL5CR_17_0, MSEL5CR_17_1,
228 MSEL5CR_16_0, MSEL5CR_16_1,
229 MSEL5CR_15_0, MSEL5CR_15_1,
230 MSEL5CR_14_0, MSEL5CR_14_1,
231 MSEL5CR_13_0, MSEL5CR_13_1,
232 MSEL5CR_12_0, MSEL5CR_12_1,
233 MSEL5CR_11_0, MSEL5CR_11_1,
234 MSEL5CR_10_0, MSEL5CR_10_1,
235 MSEL5CR_09_0, MSEL5CR_09_1,
236 MSEL5CR_08_0, MSEL5CR_08_1,
237 MSEL5CR_07_0, MSEL5CR_07_1,
238 MSEL5CR_06_0, MSEL5CR_06_1,
239
240 MSEL8CR_16_0, MSEL8CR_16_1,
241 MSEL8CR_01_0, MSEL8CR_01_1,
242 MSEL8CR_00_0, MSEL8CR_00_1,
243
244 PINMUX_FUNCTION_END,
245
246 PINMUX_MARK_BEGIN,
247
248
249 #define F1(a) a##_MARK
250 #define F2(a) a##_MARK
251 #define F3(a) a##_MARK
252 #define F4(a) a##_MARK
253 #define F5(a) a##_MARK
254 #define F6(a) a##_MARK
255 #define F7(a) a##_MARK
256 #define IRQ(a) IRQ##a##_MARK
257
258 F1(LCDD0), F3(PDM2_CLK_0), F7(DU0_DR0), IRQ(0), /* Port0 */
259 F1(LCDD1), F3(PDM2_DATA_1), F7(DU0_DR19), IRQ(1),
260 F1(LCDD2), F3(PDM3_CLK_2), F7(DU0_DR2), IRQ(2),
261 F1(LCDD3), F3(PDM3_DATA_3), F7(DU0_DR3), IRQ(3),
262 F1(LCDD4), F3(PDM4_CLK_4), F7(DU0_DR4), IRQ(4),
263 F1(LCDD5), F3(PDM4_DATA_5), F7(DU0_DR5), IRQ(5),
264 F1(LCDD6), F3(PDM0_OUTCLK_6), F7(DU0_DR6), IRQ(6),
265 F1(LCDD7), F3(PDM0_OUTDATA_7), F7(DU0_DR7), IRQ(7),
266 F1(LCDD8), F3(PDM1_OUTCLK_8), F7(DU0_DG0), IRQ(8),
267 F1(LCDD9), F3(PDM1_OUTDATA_9), F7(DU0_DG1), IRQ(9),
268 F1(LCDD10), F3(FSICCK), F7(DU0_DG2), IRQ(10), /* Port10 */
269 F1(LCDD11), F3(FSICISLD), F7(DU0_DG3), IRQ(11),
270 F1(LCDD12), F3(FSICOMC), F7(DU0_DG4), IRQ(12),
271 F1(LCDD13), F3(FSICOLR), F4(FSICILR), F7(DU0_DG5), IRQ(13),
272 F1(LCDD14), F3(FSICOBT), F4(FSICIBT), F7(DU0_DG6), IRQ(14),
273 F1(LCDD15), F3(FSICOSLD), F7(DU0_DG7), IRQ(15),
274 F1(LCDD16), F4(TPU1TO1), F7(DU0_DB0),
275 F1(LCDD17), F4(SF_IRQ_00), F7(DU0_DB1),
276 F1(LCDD18), F4(SF_IRQ_01), F7(DU0_DB2),
277 F1(LCDD19), F3(SCIFB3_RTS_19), F7(DU0_DB3),
278 F1(LCDD20), F3(SCIFB3_CTS_20), F7(DU0_DB4), /* Port20 */
279 F1(LCDD21), F3(SCIFB3_TXD_21), F7(DU0_DB5),
280 F1(LCDD22), F3(SCIFB3_RXD_22), F7(DU0_DB6),
281 F1(LCDD23), F3(SCIFB3_SCK_23), F7(DU0_DB7),
282 F1(LCDHSYN), F2(LCDCS), F3(SCIFB1_RTS_24),
283 F7(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N),
284 F1(LCDVSYN), F3(SCIFB1_CTS_25), F7(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N),
285 F1(LCDDCK), F2(LCDWR), F3(SCIFB1_TXD_26), F7(DU0_DOTCLKIN),
286 F1(LCDDISP), F2(LCDRS), F3(SCIFB1_RXD_27), F7(DU0_DOTCLKOUT),
287 F1(LCDRD_N), F3(SCIFB1_SCK_28), F7(DU0_DOTCLKOUTB),
288 F1(LCDLCLK), F4(SF_IRQ_02), F7(DU0_DISP_CSYNC_N_DE),
289 F1(LCDDON), F4(SF_IRQ_03), F7(DU0_ODDF_N_CLAMP), /* Port30 */
290
291 F1(SCIFA0_RTS), F5(SIM0_DET), F7(CSCIF0_RTS), /* Port32 */
292 F1(SCIFA0_CTS), F5(SIM1_DET), F7(CSCIF0_CTS),
293 F1(SCIFA0_SCK), F5(SIM0_PWRON), F7(CSCIF0_SCK),
294 F1(SCIFA1_RTS), F7(CSCIF1_RTS),
295 F1(SCIFA1_CTS), F7(CSCIF1_CTS),
296 F1(SCIFA1_SCK), F7(CSCIF1_SCK),
297 F1(SCIFB0_RTS), F3(TPU0TO1), F4(SCIFB3_RTS_38), F7(CHSCIF0_HRTS),
298 F1(SCIFB0_CTS), F3(TPU0TO2), F4(SCIFB3_CTS_39), F7(CHSCIF0_HCTS),
299 F1(SCIFB0_SCK), F3(TPU0TO3), F4(SCIFB3_SCK_40),
300 F7(CHSCIF0_HSCK), /* Port40 */
301
302 F1(PDM0_DATA), /* Port64 */
303 F1(PDM1_DATA),
304 F1(HSI_RX_WAKE), F2(SCIFB2_CTS_66), F3(MSIOF3_SYNC), F5(GenIO4),
305 IRQ(40),
306 F1(HSI_RX_READY), F2(SCIFB1_TXD_67), F5(GIO_OUT3_67), F7(CHSCIF1_HTX),
307 F1(HSI_RX_FLAG), F2(SCIFB2_TXD_68), F3(MSIOF3_TXD), F5(GIO_OUT4_68),
308 F1(HSI_RX_DATA), F2(SCIFB2_RXD_69), F3(MSIOF3_RXD), F5(GIO_OUT5_69),
309 F1(HSI_TX_FLAG), F2(SCIFB1_RTS_70), F5(GIO_OUT1_70), F6(HSIC_TSTCLK0),
310 F7(CHSCIF1_HRTS), /* Port70 */
311 F1(HSI_TX_DATA), F2(SCIFB1_CTS_71), F5(GIO_OUT2_71), F6(HSIC_TSTCLK1),
312 F7(CHSCIF1_HCTS),
313 F1(HSI_TX_WAKE), F2(SCIFB1_RXD_72), F5(GenIO8), F7(CHSCIF1_HRX),
314 F1(HSI_TX_READY), F2(SCIFB2_RTS_73), F3(MSIOF3_SCK), F5(GIO_OUT0_73),
315 F1(IRDA_OUT), F1(IRDA_IN), F1(IRDA_FIRSEL), F1(TPU0TO0),
316 F1(DIGRFEN), F1(GPS_TIMESTAMP), F1(TXP), /* Port80 */
317 F1(TXP2), F1(COEX_0), F1(COEX_1), IRQ(19), IRQ(18), /* Port85 */
318
319 F1(KEYIN0), /* Port96 */
320 F1(KEYIN1), F1(KEYIN2), F1(KEYIN3), F1(KEYIN4), /* Port100 */
321 F1(KEYIN5), F1(KEYIN6), IRQ(41), F1(KEYIN7), IRQ(42),
322 F2(KEYOUT0), F2(KEYOUT1), F2(KEYOUT2), F2(KEYOUT3),
323 F2(KEYOUT4), F2(KEYOUT5), IRQ(43), F2(KEYOUT6), IRQ(44), /* Port110 */
324 F2(KEYOUT7), F5(RFANAEN), IRQ(45),
325 F1(KEYIN8), F2(KEYOUT8), F4(SF_IRQ_04), IRQ(46),
326 F1(KEYIN9), F2(KEYOUT9), F4(SF_IRQ_05), IRQ(47),
327 F1(KEYIN10), F2(KEYOUT10), F4(SF_IRQ_06), IRQ(48),
328 F1(KEYIN11), F2(KEYOUT11), F4(SF_IRQ_07), IRQ(49),
329 F1(SCIFA0_TXD), F7(CSCIF0_TX), F1(SCIFA0_RXD), F7(CSCIF0_RX),
330 F1(SCIFA1_TXD), F7(CSCIF1_TX), F1(SCIFA1_RXD), F7(CSCIF1_RX),
331 F3(SF_PORT_1_120), F4(SCIFB3_RXD_120), F7(DU0_CDE), /* Port120 */
332 F3(SF_PORT_0_121), F4(SCIFB3_TXD_121),
333 F1(SCIFB0_TXD), F7(CHSCIF0_HTX),
334 F1(SCIFB0_RXD), F7(CHSCIF0_HRX), F3(ISP_STROBE_124),
335 F1(STP_ISD_0), F2(PDM4_CLK_125), F3(MSIOF2_TXD), F5(SIM0_VOLTSEL0),
336 F1(TS_SDEN), F2(MSIOF7_SYNC), F3(STP_ISEN_1),
337 F1(STP_ISEN_0), F2(PDM1_OUTDATA_128), F3(MSIOF2_SYNC),
338 F5(SIM1_VOLTSEL1), F1(TS_SPSYNC), F2(MSIOF7_RXD), F3(STP_ISSYNC_1),
339 F1(STP_ISSYNC_0), F2(PDM4_DATA_130), F3(MSIOF2_RXD),
340 F5(SIM0_VOLTSEL1), /* Port130 */
341 F1(STP_OPWM_0), F5(SIM1_PWRON), F1(TS_SCK), F2(MSIOF7_SCK),
342 F3(STP_ISCLK_1), F1(STP_ISCLK_0), F2(PDM1_OUTCLK_133), F3(MSIOF2_SCK),
343 F5(SIM1_VOLTSEL0), F1(TS_SDAT), F2(MSIOF7_TXD), F3(STP_ISD_1),
344 IRQ(20), /* Port160 */
345 IRQ(21), IRQ(22), IRQ(23),
346 F1(MMCD0_0), F1(MMCD0_1), F1(MMCD0_2), F1(MMCD0_3),
347 F1(MMCD0_4), F1(MMCD0_5), F1(MMCD0_6), /* Port170 */
348 F1(MMCD0_7), F1(MMCCMD0), F1(MMCCLK0), F1(MMCRST),
349 IRQ(24), IRQ(25), IRQ(26), IRQ(27),
350 F1(A10), F2(MMCD1_7), IRQ(31), /* Port192 */
351 F1(A9), F2(MMCD1_6), IRQ(32),
352 F1(A8), F2(MMCD1_5), IRQ(33),
353 F1(A7), F2(MMCD1_4), IRQ(34),
354 F1(A6), F2(MMCD1_3), IRQ(35),
355 F1(A5), F2(MMCD1_2), IRQ(36),
356 F1(A4), F2(MMCD1_1), IRQ(37),
357 F1(A3), F2(MMCD1_0), IRQ(38),
358 F1(A2), F2(MMCCMD1), IRQ(39), /* Port200 */
359 F1(A1),
360 F1(A0), F2(BS),
361 F1(CKO), F2(MMCCLK1),
362 F1(CS0_N), F5(SIM0_GPO1),
363 F1(CS2_N), F5(SIM0_GPO2),
364 F1(CS4_N), F2(VIO_VD), F5(SIM1_GPO0),
365 F1(D15), F5(GIO_OUT15),
366 F1(D14), F5(GIO_OUT14),
367 F1(D13), F5(GIO_OUT13),
368 F1(D12), F5(GIO_OUT12), /* Port210 */
369 F1(D11), F5(WGM_TXP2),
370 F1(D10), F5(WGM_GPS_TIMEM_ASK_RFCLK),
371 F1(D9), F2(VIO_D9), F5(GIO_OUT9),
372 F1(D8), F2(VIO_D8), F5(GIO_OUT8),
373 F1(D7), F2(VIO_D7), F5(GIO_OUT7),
374 F1(D6), F2(VIO_D6), F5(GIO_OUT6),
375 F1(D5), F2(VIO_D5), F5(GIO_OUT5_217),
376 F1(D4), F2(VIO_D4), F5(GIO_OUT4_218),
377 F1(D3), F2(VIO_D3), F5(GIO_OUT3_219),
378 F1(D2), F2(VIO_D2), F5(GIO_OUT2_220), /* Port220 */
379 F1(D1), F2(VIO_D1), F5(GIO_OUT1_221),
380 F1(D0), F2(VIO_D0), F5(GIO_OUT0_222),
381 F1(RDWR_224), F2(VIO_HD), F5(SIM1_GPO2),
382 F1(RD_N), F1(WAIT_N), F2(VIO_CLK), F5(SIM1_GPO1),
383 F1(WE0_N), F2(RDWR_227),
384 F1(WE1_N), F5(SIM0_GPO0),
385 F1(PWMO), F2(VIO_CKO1_229),
386 F1(SLIM_CLK), F2(VIO_CKO4_230), /* Port230 */
387 F1(SLIM_DATA), F2(VIO_CKO5_231), F2(VIO_CKO2_232), F4(SF_PORT_0_232),
388 F2(VIO_CKO3_233), F4(SF_PORT_1_233),
389 F1(FSIACK), F2(PDM3_CLK_234), F3(ISP_IRIS1_234),
390 F1(FSIAISLD), F2(PDM3_DATA_235),
391 F1(FSIAOMC), F2(PDM0_OUTCLK_236), F3(ISP_IRIS0_236),
392 F1(FSIAOLR), F2(FSIAILR), F1(FSIAOBT), F2(FSIAIBT),
393 F1(FSIAOSLD), F2(PDM0_OUTDATA_239),
394 F1(FSIBISLD), /* Port240 */
395 F1(FSIBOLR), F2(FSIBILR), F1(FSIBOMC), F3(ISP_SHUTTER1_242),
396 F1(FSIBOBT), F2(FSIBIBT), F1(FSIBOSLD), F2(FSIASPDIF),
397 F1(FSIBCK), F3(ISP_SHUTTER0_245),
398 F1(ISP_IRIS1_246), F1(ISP_IRIS0_247), F1(ISP_SHUTTER1_248),
399 F1(ISP_SHUTTER0_249), F1(ISP_STROBE_250), /* Port250 */
400 F1(MSIOF0_SYNC), F1(MSIOF0_RXD), F1(MSIOF0_SCK), F1(MSIOF0_SS2),
401 F3(VIO_CKO3_259), F1(MSIOF0_TXD), /* Port260 */
402 F2(SCIFB1_SCK_261), F7(CHSCIF1_HSCK), F2(SCIFB2_SCK_262),
403 F1(MSIOF1_SS2), F4(MSIOF5_SS2), F1(MSIOF1_TXD), F4(MSIOF5_TXD),
404 F1(MSIOF1_RXD), F4(MSIOF5_RXD), F1(MSIOF1_SS1), F4(MSIOF5_SS1),
405 F1(MSIOF0_SS1), F1(MSIOF1_SCK), F4(MSIOF5_SCK),
406 F1(MSIOF1_SYNC), F4(MSIOF5_SYNC),
407 F1(MSIOF2_SS1), F3(VIO_CKO5_270), /* Port270 */
408 F1(MSIOF2_SS2), F3(VIO_CKO2_271), F1(MSIOF3_SS2), F3(VIO_CKO1_272),
409 F1(MSIOF3_SS1), F3(VIO_CKO4_273), F1(MSIOF4_SS2), F4(TPU1TO0),
410 F1(IC_DP), F1(SIM0_RST), F1(IC_DM), F1(SIM0_BSICOMP),
411 F1(SIM0_CLK), F1(SIM0_IO), /* Port280 */
412 F1(SIM1_IO), F2(PDM2_DATA_281), F1(SIM1_CLK), F2(PDM2_CLK_282),
413 F1(SIM1_RST), F1(SDHID1_0), F3(STMDATA0_2),
414 F1(SDHID1_1), F3(STMDATA1_2), IRQ(51), /* Port290 */
415 F1(SDHID1_2), F3(STMDATA2_2), F1(SDHID1_3), F3(STMDATA3_2),
416 F1(SDHICLK1), F3(STMCLK_2), F1(SDHICMD1), F3(STMSIDI_2),
417 F1(SDHID2_0), F2(MSIOF4_TXD), F3(SCIFB2_TXD_295), F4(MSIOF6_TXD),
418 F1(SDHID2_1), F4(MSIOF6_SS2), IRQ(52),
419 F1(SDHID2_2), F2(MSIOF4_RXD), F3(SCIFB2_RXD_297), F4(MSIOF6_RXD),
420 F1(SDHID2_3), F2(MSIOF4_SYNC), F3(SCIFB2_CTS_298), F4(MSIOF6_SYNC),
421 F1(SDHICLK2), F2(MSIOF4_SCK), F3(SCIFB2_SCK_299), F4(MSIOF6_SCK),
422 F1(SDHICMD2), F2(MSIOF4_SS1), F3(SCIFB2_RTS_300),
423 F4(MSIOF6_SS1), /* Port300 */
424 F1(SDHICD0), IRQ(50), F1(SDHID0_0), F3(STMDATA0_1),
425 F1(SDHID0_1), F3(STMDATA1_1), F1(SDHID0_2), F3(STMDATA2_1),
426 F1(SDHID0_3), F3(STMDATA3_1), F1(SDHICMD0), F3(STMSIDI_1),
427 F1(SDHIWP0), F1(SDHICLK0), F3(STMCLK_1), IRQ(16), /* Port320 */
428 IRQ(17), IRQ(28), IRQ(29), IRQ(30), IRQ(53), IRQ(54),
429 IRQ(55), IRQ(56), IRQ(57),
430 PINMUX_MARK_END,
431 };
432
433 static const u16 pinmux_data[] = {
434 /* specify valid pin states for each pin in GPIO mode */
435 PINMUX_DATA_ALL(),
436
437 /* Port0 */
438 PINMUX_DATA(LCDD0_MARK, PORT0_FN1),
439 PINMUX_DATA(PDM2_CLK_0_MARK, PORT0_FN3),
440 PINMUX_DATA(DU0_DR0_MARK, PORT0_FN7),
441 PINMUX_DATA(IRQ0_MARK, PORT0_FN0),
442
443 /* Port1 */
444 PINMUX_DATA(LCDD1_MARK, PORT1_FN1),
445 PINMUX_DATA(PDM2_DATA_1_MARK, PORT1_FN3, MSEL3CR_12_0),
446 PINMUX_DATA(DU0_DR19_MARK, PORT1_FN7),
447 PINMUX_DATA(IRQ1_MARK, PORT1_FN0),
448
449 /* Port2 */
450 PINMUX_DATA(LCDD2_MARK, PORT2_FN1),
451 PINMUX_DATA(PDM3_CLK_2_MARK, PORT2_FN3),
452 PINMUX_DATA(DU0_DR2_MARK, PORT2_FN7),
453 PINMUX_DATA(IRQ2_MARK, PORT2_FN0),
454
455 /* Port3 */
456 PINMUX_DATA(LCDD3_MARK, PORT3_FN1),
457 PINMUX_DATA(PDM3_DATA_3_MARK, PORT3_FN3, MSEL3CR_12_0),
458 PINMUX_DATA(DU0_DR3_MARK, PORT3_FN7),
459 PINMUX_DATA(IRQ3_MARK, PORT3_FN0),
460
461 /* Port4 */
462 PINMUX_DATA(LCDD4_MARK, PORT4_FN1),
463 PINMUX_DATA(PDM4_CLK_4_MARK, PORT4_FN3),
464 PINMUX_DATA(DU0_DR4_MARK, PORT4_FN7),
465 PINMUX_DATA(IRQ4_MARK, PORT4_FN0),
466
467 /* Port5 */
468 PINMUX_DATA(LCDD5_MARK, PORT5_FN1),
469 PINMUX_DATA(PDM4_DATA_5_MARK, PORT5_FN3, MSEL3CR_12_0),
470 PINMUX_DATA(DU0_DR5_MARK, PORT5_FN7),
471 PINMUX_DATA(IRQ5_MARK, PORT5_FN0),
472
473 /* Port6 */
474 PINMUX_DATA(LCDD6_MARK, PORT6_FN1),
475 PINMUX_DATA(PDM0_OUTCLK_6_MARK, PORT6_FN3),
476 PINMUX_DATA(DU0_DR6_MARK, PORT6_FN7),
477 PINMUX_DATA(IRQ6_MARK, PORT6_FN0),
478
479 /* Port7 */
480 PINMUX_DATA(LCDD7_MARK, PORT7_FN1),
481 PINMUX_DATA(PDM0_OUTDATA_7_MARK, PORT7_FN3),
482 PINMUX_DATA(DU0_DR7_MARK, PORT7_FN7),
483 PINMUX_DATA(IRQ7_MARK, PORT7_FN0),
484
485 /* Port8 */
486 PINMUX_DATA(LCDD8_MARK, PORT8_FN1),
487 PINMUX_DATA(PDM1_OUTCLK_8_MARK, PORT8_FN3),
488 PINMUX_DATA(DU0_DG0_MARK, PORT8_FN7),
489 PINMUX_DATA(IRQ8_MARK, PORT8_FN0),
490
491 /* Port9 */
492 PINMUX_DATA(LCDD9_MARK, PORT9_FN1),
493 PINMUX_DATA(PDM1_OUTDATA_9_MARK, PORT9_FN3),
494 PINMUX_DATA(DU0_DG1_MARK, PORT9_FN7),
495 PINMUX_DATA(IRQ9_MARK, PORT9_FN0),
496
497 /* Port10 */
498 PINMUX_DATA(LCDD10_MARK, PORT10_FN1),
499 PINMUX_DATA(FSICCK_MARK, PORT10_FN3),
500 PINMUX_DATA(DU0_DG2_MARK, PORT10_FN7),
501 PINMUX_DATA(IRQ10_MARK, PORT10_FN0),
502
503 /* Port11 */
504 PINMUX_DATA(LCDD11_MARK, PORT11_FN1),
505 PINMUX_DATA(FSICISLD_MARK, PORT11_FN3),
506 PINMUX_DATA(DU0_DG3_MARK, PORT11_FN7),
507 PINMUX_DATA(IRQ11_MARK, PORT11_FN0),
508
509 /* Port12 */
510 PINMUX_DATA(LCDD12_MARK, PORT12_FN1),
511 PINMUX_DATA(FSICOMC_MARK, PORT12_FN3),
512 PINMUX_DATA(DU0_DG4_MARK, PORT12_FN7),
513 PINMUX_DATA(IRQ12_MARK, PORT12_FN0),
514
515 /* Port13 */
516 PINMUX_DATA(LCDD13_MARK, PORT13_FN1),
517 PINMUX_DATA(FSICOLR_MARK, PORT13_FN3),
518 PINMUX_DATA(FSICILR_MARK, PORT13_FN4),
519 PINMUX_DATA(DU0_DG5_MARK, PORT13_FN7),
520 PINMUX_DATA(IRQ13_MARK, PORT13_FN0),
521
522 /* Port14 */
523 PINMUX_DATA(LCDD14_MARK, PORT14_FN1),
524 PINMUX_DATA(FSICOBT_MARK, PORT14_FN3),
525 PINMUX_DATA(FSICIBT_MARK, PORT14_FN4),
526 PINMUX_DATA(DU0_DG6_MARK, PORT14_FN7),
527 PINMUX_DATA(IRQ14_MARK, PORT14_FN0),
528
529 /* Port15 */
530 PINMUX_DATA(LCDD15_MARK, PORT15_FN1),
531 PINMUX_DATA(FSICOSLD_MARK, PORT15_FN3),
532 PINMUX_DATA(DU0_DG7_MARK, PORT15_FN7),
533 PINMUX_DATA(IRQ15_MARK, PORT15_FN0),
534
535 /* Port16 */
536 PINMUX_DATA(LCDD16_MARK, PORT16_FN1),
537 PINMUX_DATA(TPU1TO1_MARK, PORT16_FN4),
538 PINMUX_DATA(DU0_DB0_MARK, PORT16_FN7),
539
540 /* Port17 */
541 PINMUX_DATA(LCDD17_MARK, PORT17_FN1),
542 PINMUX_DATA(SF_IRQ_00_MARK, PORT17_FN4),
543 PINMUX_DATA(DU0_DB1_MARK, PORT17_FN7),
544
545 /* Port18 */
546 PINMUX_DATA(LCDD18_MARK, PORT18_FN1),
547 PINMUX_DATA(SF_IRQ_01_MARK, PORT18_FN4),
548 PINMUX_DATA(DU0_DB2_MARK, PORT18_FN7),
549
550 /* Port19 */
551 PINMUX_DATA(LCDD19_MARK, PORT19_FN1),
552 PINMUX_DATA(SCIFB3_RTS_19_MARK, PORT19_FN3),
553 PINMUX_DATA(DU0_DB3_MARK, PORT19_FN7),
554
555 /* Port20 */
556 PINMUX_DATA(LCDD20_MARK, PORT20_FN1),
557 PINMUX_DATA(SCIFB3_CTS_20_MARK, PORT20_FN3, MSEL3CR_09_0),
558 PINMUX_DATA(DU0_DB4_MARK, PORT20_FN7),
559
560 /* Port21 */
561 PINMUX_DATA(LCDD21_MARK, PORT21_FN1),
562 PINMUX_DATA(SCIFB3_TXD_21_MARK, PORT21_FN3, MSEL3CR_09_0),
563 PINMUX_DATA(DU0_DB5_MARK, PORT21_FN7),
564
565 /* Port22 */
566 PINMUX_DATA(LCDD22_MARK, PORT22_FN1),
567 PINMUX_DATA(SCIFB3_RXD_22_MARK, PORT22_FN3, MSEL3CR_09_0),
568 PINMUX_DATA(DU0_DB6_MARK, PORT22_FN7),
569
570 /* Port23 */
571 PINMUX_DATA(LCDD23_MARK, PORT23_FN1),
572 PINMUX_DATA(SCIFB3_SCK_23_MARK, PORT23_FN3),
573 PINMUX_DATA(DU0_DB7_MARK, PORT23_FN7),
574
575 /* Port24 */
576 PINMUX_DATA(LCDHSYN_MARK, PORT24_FN1),
577 PINMUX_DATA(LCDCS_MARK, PORT24_FN2),
578 PINMUX_DATA(SCIFB1_RTS_24_MARK, PORT24_FN3),
579 PINMUX_DATA(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N_MARK, PORT24_FN7),
580
581 /* Port25 */
582 PINMUX_DATA(LCDVSYN_MARK, PORT25_FN1),
583 PINMUX_DATA(SCIFB1_CTS_25_MARK, PORT25_FN3, MSEL3CR_11_0),
584 PINMUX_DATA(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N_MARK, PORT25_FN7),
585
586 /* Port26 */
587 PINMUX_DATA(LCDDCK_MARK, PORT26_FN1),
588 PINMUX_DATA(LCDWR_MARK, PORT26_FN2),
589 PINMUX_DATA(SCIFB1_TXD_26_MARK, PORT26_FN3, MSEL3CR_11_0),
590 PINMUX_DATA(DU0_DOTCLKIN_MARK, PORT26_FN7),
591
592 /* Port27 */
593 PINMUX_DATA(LCDDISP_MARK, PORT27_FN1),
594 PINMUX_DATA(LCDRS_MARK, PORT27_FN2),
595 PINMUX_DATA(SCIFB1_RXD_27_MARK, PORT27_FN3, MSEL3CR_11_0),
596 PINMUX_DATA(DU0_DOTCLKOUT_MARK, PORT27_FN7),
597
598 /* Port28 */
599 PINMUX_DATA(LCDRD_N_MARK, PORT28_FN1),
600 PINMUX_DATA(SCIFB1_SCK_28_MARK, PORT28_FN3),
601 PINMUX_DATA(DU0_DOTCLKOUTB_MARK, PORT28_FN7),
602
603 /* Port29 */
604 PINMUX_DATA(LCDLCLK_MARK, PORT29_FN1),
605 PINMUX_DATA(SF_IRQ_02_MARK, PORT29_FN4),
606 PINMUX_DATA(DU0_DISP_CSYNC_N_DE_MARK, PORT29_FN7),
607
608 /* Port30 */
609 PINMUX_DATA(LCDDON_MARK, PORT30_FN1),
610 PINMUX_DATA(SF_IRQ_03_MARK, PORT30_FN4),
611 PINMUX_DATA(DU0_ODDF_N_CLAMP_MARK, PORT30_FN7),
612
613 /* Port32 */
614 PINMUX_DATA(SCIFA0_RTS_MARK, PORT32_FN1),
615 PINMUX_DATA(SIM0_DET_MARK, PORT32_FN5),
616 PINMUX_DATA(CSCIF0_RTS_MARK, PORT32_FN7),
617
618 /* Port33 */
619 PINMUX_DATA(SCIFA0_CTS_MARK, PORT33_FN1),
620 PINMUX_DATA(SIM1_DET_MARK, PORT33_FN5),
621 PINMUX_DATA(CSCIF0_CTS_MARK, PORT33_FN7),
622
623 /* Port34 */
624 PINMUX_DATA(SCIFA0_SCK_MARK, PORT34_FN1),
625 PINMUX_DATA(SIM0_PWRON_MARK, PORT34_FN5),
626 PINMUX_DATA(CSCIF0_SCK_MARK, PORT34_FN7),
627
628 /* Port35 */
629 PINMUX_DATA(SCIFA1_RTS_MARK, PORT35_FN1),
630 PINMUX_DATA(CSCIF1_RTS_MARK, PORT35_FN7),
631
632 /* Port36 */
633 PINMUX_DATA(SCIFA1_CTS_MARK, PORT36_FN1),
634 PINMUX_DATA(CSCIF1_CTS_MARK, PORT36_FN7),
635
636 /* Port37 */
637 PINMUX_DATA(SCIFA1_SCK_MARK, PORT37_FN1),
638 PINMUX_DATA(CSCIF1_SCK_MARK, PORT37_FN7),
639
640 /* Port38 */
641 PINMUX_DATA(SCIFB0_RTS_MARK, PORT38_FN1),
642 PINMUX_DATA(TPU0TO1_MARK, PORT38_FN3),
643 PINMUX_DATA(SCIFB3_RTS_38_MARK, PORT38_FN4),
644 PINMUX_DATA(CHSCIF0_HRTS_MARK, PORT38_FN7),
645
646 /* Port39 */
647 PINMUX_DATA(SCIFB0_CTS_MARK, PORT39_FN1),
648 PINMUX_DATA(TPU0TO2_MARK, PORT39_FN3),
649 PINMUX_DATA(SCIFB3_CTS_39_MARK, PORT39_FN4, MSEL3CR_09_1),
650 PINMUX_DATA(CHSCIF0_HCTS_MARK, PORT39_FN7),
651
652 /* Port40 */
653 PINMUX_DATA(SCIFB0_SCK_MARK, PORT40_FN1),
654 PINMUX_DATA(TPU0TO3_MARK, PORT40_FN3),
655 PINMUX_DATA(SCIFB3_SCK_40_MARK, PORT40_FN4),
656 PINMUX_DATA(CHSCIF0_HSCK_MARK, PORT40_FN7),
657
658 /* Port64 */
659 PINMUX_DATA(PDM0_DATA_MARK, PORT64_FN1),
660
661 /* Port65 */
662 PINMUX_DATA(PDM1_DATA_MARK, PORT65_FN1),
663
664 /* Port66 */
665 PINMUX_DATA(HSI_RX_WAKE_MARK, PORT66_FN1),
666 PINMUX_DATA(SCIFB2_CTS_66_MARK, PORT66_FN2, MSEL3CR_10_0),
667 PINMUX_DATA(MSIOF3_SYNC_MARK, PORT66_FN3),
668 PINMUX_DATA(GenIO4_MARK, PORT66_FN5),
669 PINMUX_DATA(IRQ40_MARK, PORT66_FN0),
670
671 /* Port67 */
672 PINMUX_DATA(HSI_RX_READY_MARK, PORT67_FN1),
673 PINMUX_DATA(SCIFB1_TXD_67_MARK, PORT67_FN2, MSEL3CR_11_1),
674 PINMUX_DATA(GIO_OUT3_67_MARK, PORT67_FN5),
675 PINMUX_DATA(CHSCIF1_HTX_MARK, PORT67_FN7),
676
677 /* Port68 */
678 PINMUX_DATA(HSI_RX_FLAG_MARK, PORT68_FN1),
679 PINMUX_DATA(SCIFB2_TXD_68_MARK, PORT68_FN2, MSEL3CR_10_0),
680 PINMUX_DATA(MSIOF3_TXD_MARK, PORT68_FN3),
681 PINMUX_DATA(GIO_OUT4_68_MARK, PORT68_FN5),
682
683 /* Port69 */
684 PINMUX_DATA(HSI_RX_DATA_MARK, PORT69_FN1),
685 PINMUX_DATA(SCIFB2_RXD_69_MARK, PORT69_FN2, MSEL3CR_10_0),
686 PINMUX_DATA(MSIOF3_RXD_MARK, PORT69_FN3),
687 PINMUX_DATA(GIO_OUT5_69_MARK, PORT69_FN5),
688
689 /* Port70 */
690 PINMUX_DATA(HSI_TX_FLAG_MARK, PORT70_FN1),
691 PINMUX_DATA(SCIFB1_RTS_70_MARK, PORT70_FN2),
692 PINMUX_DATA(GIO_OUT1_70_MARK, PORT70_FN5),
693 PINMUX_DATA(HSIC_TSTCLK0_MARK, PORT70_FN6),
694 PINMUX_DATA(CHSCIF1_HRTS_MARK, PORT70_FN7),
695
696 /* Port71 */
697 PINMUX_DATA(HSI_TX_DATA_MARK, PORT71_FN1),
698 PINMUX_DATA(SCIFB1_CTS_71_MARK, PORT71_FN2, MSEL3CR_11_1),
699 PINMUX_DATA(GIO_OUT2_71_MARK, PORT71_FN5),
700 PINMUX_DATA(HSIC_TSTCLK1_MARK, PORT71_FN6),
701 PINMUX_DATA(CHSCIF1_HCTS_MARK, PORT71_FN7),
702
703 /* Port72 */
704 PINMUX_DATA(HSI_TX_WAKE_MARK, PORT72_FN1),
705 PINMUX_DATA(SCIFB1_RXD_72_MARK, PORT72_FN2, MSEL3CR_11_1),
706 PINMUX_DATA(GenIO8_MARK, PORT72_FN5),
707 PINMUX_DATA(CHSCIF1_HRX_MARK, PORT72_FN7),
708
709 /* Port73 */
710 PINMUX_DATA(HSI_TX_READY_MARK, PORT73_FN1),
711 PINMUX_DATA(SCIFB2_RTS_73_MARK, PORT73_FN2),
712 PINMUX_DATA(MSIOF3_SCK_MARK, PORT73_FN3),
713 PINMUX_DATA(GIO_OUT0_73_MARK, PORT73_FN5),
714
715 /* Port74 - Port85 */
716 PINMUX_DATA(IRDA_OUT_MARK, PORT74_FN1),
717 PINMUX_DATA(IRDA_IN_MARK, PORT75_FN1),
718 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT76_FN1),
719 PINMUX_DATA(TPU0TO0_MARK, PORT77_FN1),
720 PINMUX_DATA(DIGRFEN_MARK, PORT78_FN1),
721 PINMUX_DATA(GPS_TIMESTAMP_MARK, PORT79_FN1),
722 PINMUX_DATA(TXP_MARK, PORT80_FN1),
723 PINMUX_DATA(TXP2_MARK, PORT81_FN1),
724 PINMUX_DATA(COEX_0_MARK, PORT82_FN1),
725 PINMUX_DATA(COEX_1_MARK, PORT83_FN1),
726 PINMUX_DATA(IRQ19_MARK, PORT84_FN0),
727 PINMUX_DATA(IRQ18_MARK, PORT85_FN0),
728
729 /* Port96 - Port101 */
730 PINMUX_DATA(KEYIN0_MARK, PORT96_FN1),
731 PINMUX_DATA(KEYIN1_MARK, PORT97_FN1),
732 PINMUX_DATA(KEYIN2_MARK, PORT98_FN1),
733 PINMUX_DATA(KEYIN3_MARK, PORT99_FN1),
734 PINMUX_DATA(KEYIN4_MARK, PORT100_FN1),
735 PINMUX_DATA(KEYIN5_MARK, PORT101_FN1),
736
737 /* Port102 */
738 PINMUX_DATA(KEYIN6_MARK, PORT102_FN1),
739 PINMUX_DATA(IRQ41_MARK, PORT102_FN0),
740
741 /* Port103 */
742 PINMUX_DATA(KEYIN7_MARK, PORT103_FN1),
743 PINMUX_DATA(IRQ42_MARK, PORT103_FN0),
744
745 /* Port104 - Port108 */
746 PINMUX_DATA(KEYOUT0_MARK, PORT104_FN2),
747 PINMUX_DATA(KEYOUT1_MARK, PORT105_FN2),
748 PINMUX_DATA(KEYOUT2_MARK, PORT106_FN2),
749 PINMUX_DATA(KEYOUT3_MARK, PORT107_FN2),
750 PINMUX_DATA(KEYOUT4_MARK, PORT108_FN2),
751
752 /* Port109 */
753 PINMUX_DATA(KEYOUT5_MARK, PORT109_FN2),
754 PINMUX_DATA(IRQ43_MARK, PORT109_FN0),
755
756 /* Port110 */
757 PINMUX_DATA(KEYOUT6_MARK, PORT110_FN2),
758 PINMUX_DATA(IRQ44_MARK, PORT110_FN0),
759
760 /* Port111 */
761 PINMUX_DATA(KEYOUT7_MARK, PORT111_FN2),
762 PINMUX_DATA(RFANAEN_MARK, PORT111_FN5),
763 PINMUX_DATA(IRQ45_MARK, PORT111_FN0),
764
765 /* Port112 */
766 PINMUX_DATA(KEYIN8_MARK, PORT112_FN1),
767 PINMUX_DATA(KEYOUT8_MARK, PORT112_FN2),
768 PINMUX_DATA(SF_IRQ_04_MARK, PORT112_FN4),
769 PINMUX_DATA(IRQ46_MARK, PORT112_FN0),
770
771 /* Port113 */
772 PINMUX_DATA(KEYIN9_MARK, PORT113_FN1),
773 PINMUX_DATA(KEYOUT9_MARK, PORT113_FN2),
774 PINMUX_DATA(SF_IRQ_05_MARK, PORT113_FN4),
775 PINMUX_DATA(IRQ47_MARK, PORT113_FN0),
776
777 /* Port114 */
778 PINMUX_DATA(KEYIN10_MARK, PORT114_FN1),
779 PINMUX_DATA(KEYOUT10_MARK, PORT114_FN2),
780 PINMUX_DATA(SF_IRQ_06_MARK, PORT114_FN4),
781 PINMUX_DATA(IRQ48_MARK, PORT114_FN0),
782
783 /* Port115 */
784 PINMUX_DATA(KEYIN11_MARK, PORT115_FN1),
785 PINMUX_DATA(KEYOUT11_MARK, PORT115_FN2),
786 PINMUX_DATA(SF_IRQ_07_MARK, PORT115_FN4),
787 PINMUX_DATA(IRQ49_MARK, PORT115_FN0),
788
789 /* Port116 */
790 PINMUX_DATA(SCIFA0_TXD_MARK, PORT116_FN1),
791 PINMUX_DATA(CSCIF0_TX_MARK, PORT116_FN7),
792
793 /* Port117 */
794 PINMUX_DATA(SCIFA0_RXD_MARK, PORT117_FN1),
795 PINMUX_DATA(CSCIF0_RX_MARK, PORT117_FN7),
796
797 /* Port118 */
798 PINMUX_DATA(SCIFA1_TXD_MARK, PORT118_FN1),
799 PINMUX_DATA(CSCIF1_TX_MARK, PORT118_FN7),
800
801 /* Port119 */
802 PINMUX_DATA(SCIFA1_RXD_MARK, PORT119_FN1),
803 PINMUX_DATA(CSCIF1_RX_MARK, PORT119_FN7),
804
805 /* Port120 */
806 PINMUX_DATA(SF_PORT_1_120_MARK, PORT120_FN3),
807 PINMUX_DATA(SCIFB3_RXD_120_MARK, PORT120_FN4, MSEL3CR_09_1),
808 PINMUX_DATA(DU0_CDE_MARK, PORT120_FN7),
809
810 /* Port121 */
811 PINMUX_DATA(SF_PORT_0_121_MARK, PORT121_FN3),
812 PINMUX_DATA(SCIFB3_TXD_121_MARK, PORT121_FN4, MSEL3CR_09_1),
813
814 /* Port122 */
815 PINMUX_DATA(SCIFB0_TXD_MARK, PORT122_FN1),
816 PINMUX_DATA(CHSCIF0_HTX_MARK, PORT122_FN7),
817
818 /* Port123 */
819 PINMUX_DATA(SCIFB0_RXD_MARK, PORT123_FN1),
820 PINMUX_DATA(CHSCIF0_HRX_MARK, PORT123_FN7),
821
822 /* Port124 */
823 PINMUX_DATA(ISP_STROBE_124_MARK, PORT124_FN3),
824
825 /* Port125 */
826 PINMUX_DATA(STP_ISD_0_MARK, PORT125_FN1),
827 PINMUX_DATA(PDM4_CLK_125_MARK, PORT125_FN2),
828 PINMUX_DATA(MSIOF2_TXD_MARK, PORT125_FN3),
829 PINMUX_DATA(SIM0_VOLTSEL0_MARK, PORT125_FN5),
830
831 /* Port126 */
832 PINMUX_DATA(TS_SDEN_MARK, PORT126_FN1),
833 PINMUX_DATA(MSIOF7_SYNC_MARK, PORT126_FN2),
834 PINMUX_DATA(STP_ISEN_1_MARK, PORT126_FN3),
835
836 /* Port128 */
837 PINMUX_DATA(STP_ISEN_0_MARK, PORT128_FN1),
838 PINMUX_DATA(PDM1_OUTDATA_128_MARK, PORT128_FN2),
839 PINMUX_DATA(MSIOF2_SYNC_MARK, PORT128_FN3),
840 PINMUX_DATA(SIM1_VOLTSEL1_MARK, PORT128_FN5),
841
842 /* Port129 */
843 PINMUX_DATA(TS_SPSYNC_MARK, PORT129_FN1),
844 PINMUX_DATA(MSIOF7_RXD_MARK, PORT129_FN2),
845 PINMUX_DATA(STP_ISSYNC_1_MARK, PORT129_FN3),
846
847 /* Port130 */
848 PINMUX_DATA(STP_ISSYNC_0_MARK, PORT130_FN1),
849 PINMUX_DATA(PDM4_DATA_130_MARK, PORT130_FN2, MSEL3CR_12_1),
850 PINMUX_DATA(MSIOF2_RXD_MARK, PORT130_FN3),
851 PINMUX_DATA(SIM0_VOLTSEL1_MARK, PORT130_FN5),
852
853 /* Port131 */
854 PINMUX_DATA(STP_OPWM_0_MARK, PORT131_FN1),
855 PINMUX_DATA(SIM1_PWRON_MARK, PORT131_FN5),
856
857 /* Port132 */
858 PINMUX_DATA(TS_SCK_MARK, PORT132_FN1),
859 PINMUX_DATA(MSIOF7_SCK_MARK, PORT132_FN2),
860 PINMUX_DATA(STP_ISCLK_1_MARK, PORT132_FN3),
861
862 /* Port133 */
863 PINMUX_DATA(STP_ISCLK_0_MARK, PORT133_FN1),
864 PINMUX_DATA(PDM1_OUTCLK_133_MARK, PORT133_FN2),
865 PINMUX_DATA(MSIOF2_SCK_MARK, PORT133_FN3),
866 PINMUX_DATA(SIM1_VOLTSEL0_MARK, PORT133_FN5),
867
868 /* Port134 */
869 PINMUX_DATA(TS_SDAT_MARK, PORT134_FN1),
870 PINMUX_DATA(MSIOF7_TXD_MARK, PORT134_FN2),
871 PINMUX_DATA(STP_ISD_1_MARK, PORT134_FN3),
872
873 /* Port160 - Port178 */
874 PINMUX_DATA(IRQ20_MARK, PORT160_FN0),
875 PINMUX_DATA(IRQ21_MARK, PORT161_FN0),
876 PINMUX_DATA(IRQ22_MARK, PORT162_FN0),
877 PINMUX_DATA(IRQ23_MARK, PORT163_FN0),
878 PINMUX_DATA(MMCD0_0_MARK, PORT164_FN1),
879 PINMUX_DATA(MMCD0_1_MARK, PORT165_FN1),
880 PINMUX_DATA(MMCD0_2_MARK, PORT166_FN1),
881 PINMUX_DATA(MMCD0_3_MARK, PORT167_FN1),
882 PINMUX_DATA(MMCD0_4_MARK, PORT168_FN1),
883 PINMUX_DATA(MMCD0_5_MARK, PORT169_FN1),
884 PINMUX_DATA(MMCD0_6_MARK, PORT170_FN1),
885 PINMUX_DATA(MMCD0_7_MARK, PORT171_FN1),
886 PINMUX_DATA(MMCCMD0_MARK, PORT172_FN1),
887 PINMUX_DATA(MMCCLK0_MARK, PORT173_FN1),
888 PINMUX_DATA(MMCRST_MARK, PORT174_FN1),
889 PINMUX_DATA(IRQ24_MARK, PORT175_FN0),
890 PINMUX_DATA(IRQ25_MARK, PORT176_FN0),
891 PINMUX_DATA(IRQ26_MARK, PORT177_FN0),
892 PINMUX_DATA(IRQ27_MARK, PORT178_FN0),
893
894 /* Port192 - Port200 FN1 */
895 PINMUX_DATA(A10_MARK, PORT192_FN1),
896 PINMUX_DATA(A9_MARK, PORT193_FN1),
897 PINMUX_DATA(A8_MARK, PORT194_FN1),
898 PINMUX_DATA(A7_MARK, PORT195_FN1),
899 PINMUX_DATA(A6_MARK, PORT196_FN1),
900 PINMUX_DATA(A5_MARK, PORT197_FN1),
901 PINMUX_DATA(A4_MARK, PORT198_FN1),
902 PINMUX_DATA(A3_MARK, PORT199_FN1),
903 PINMUX_DATA(A2_MARK, PORT200_FN1),
904
905 /* Port192 - Port200 FN2 */
906 PINMUX_DATA(MMCD1_7_MARK, PORT192_FN2),
907 PINMUX_DATA(MMCD1_6_MARK, PORT193_FN2),
908 PINMUX_DATA(MMCD1_5_MARK, PORT194_FN2),
909 PINMUX_DATA(MMCD1_4_MARK, PORT195_FN2),
910 PINMUX_DATA(MMCD1_3_MARK, PORT196_FN2),
911 PINMUX_DATA(MMCD1_2_MARK, PORT197_FN2),
912 PINMUX_DATA(MMCD1_1_MARK, PORT198_FN2),
913 PINMUX_DATA(MMCD1_0_MARK, PORT199_FN2),
914 PINMUX_DATA(MMCCMD1_MARK, PORT200_FN2),
915
916 /* Port192 - Port200 IRQ */
917 PINMUX_DATA(IRQ31_MARK, PORT192_FN0),
918 PINMUX_DATA(IRQ32_MARK, PORT193_FN0),
919 PINMUX_DATA(IRQ33_MARK, PORT194_FN0),
920 PINMUX_DATA(IRQ34_MARK, PORT195_FN0),
921 PINMUX_DATA(IRQ35_MARK, PORT196_FN0),
922 PINMUX_DATA(IRQ36_MARK, PORT197_FN0),
923 PINMUX_DATA(IRQ37_MARK, PORT198_FN0),
924 PINMUX_DATA(IRQ38_MARK, PORT199_FN0),
925 PINMUX_DATA(IRQ39_MARK, PORT200_FN0),
926
927 /* Port201 */
928 PINMUX_DATA(A1_MARK, PORT201_FN1),
929
930 /* Port202 */
931 PINMUX_DATA(A0_MARK, PORT202_FN1),
932 PINMUX_DATA(BS_MARK, PORT202_FN2),
933
934 /* Port203 */
935 PINMUX_DATA(CKO_MARK, PORT203_FN1),
936 PINMUX_DATA(MMCCLK1_MARK, PORT203_FN2),
937
938 /* Port204 */
939 PINMUX_DATA(CS0_N_MARK, PORT204_FN1),
940 PINMUX_DATA(SIM0_GPO1_MARK, PORT204_FN5),
941
942 /* Port205 */
943 PINMUX_DATA(CS2_N_MARK, PORT205_FN1),
944 PINMUX_DATA(SIM0_GPO2_MARK, PORT205_FN5),
945
946 /* Port206 */
947 PINMUX_DATA(CS4_N_MARK, PORT206_FN1),
948 PINMUX_DATA(VIO_VD_MARK, PORT206_FN2),
949 PINMUX_DATA(SIM1_GPO0_MARK, PORT206_FN5),
950
951 /* Port207 - Port212 FN1 */
952 PINMUX_DATA(D15_MARK, PORT207_FN1),
953 PINMUX_DATA(D14_MARK, PORT208_FN1),
954 PINMUX_DATA(D13_MARK, PORT209_FN1),
955 PINMUX_DATA(D12_MARK, PORT210_FN1),
956 PINMUX_DATA(D11_MARK, PORT211_FN1),
957 PINMUX_DATA(D10_MARK, PORT212_FN1),
958
959 /* Port207 - Port212 FN5 */
960 PINMUX_DATA(GIO_OUT15_MARK, PORT207_FN5),
961 PINMUX_DATA(GIO_OUT14_MARK, PORT208_FN5),
962 PINMUX_DATA(GIO_OUT13_MARK, PORT209_FN5),
963 PINMUX_DATA(GIO_OUT12_MARK, PORT210_FN5),
964 PINMUX_DATA(WGM_TXP2_MARK, PORT211_FN5),
965 PINMUX_DATA(WGM_GPS_TIMEM_ASK_RFCLK_MARK, PORT212_FN5),
966
967 /* Port213 - Port222 FN1 */
968 PINMUX_DATA(D9_MARK, PORT213_FN1),
969 PINMUX_DATA(D8_MARK, PORT214_FN1),
970 PINMUX_DATA(D7_MARK, PORT215_FN1),
971 PINMUX_DATA(D6_MARK, PORT216_FN1),
972 PINMUX_DATA(D5_MARK, PORT217_FN1),
973 PINMUX_DATA(D4_MARK, PORT218_FN1),
974 PINMUX_DATA(D3_MARK, PORT219_FN1),
975 PINMUX_DATA(D2_MARK, PORT220_FN1),
976 PINMUX_DATA(D1_MARK, PORT221_FN1),
977 PINMUX_DATA(D0_MARK, PORT222_FN1),
978
979 /* Port213 - Port222 FN2 */
980 PINMUX_DATA(VIO_D9_MARK, PORT213_FN2),
981 PINMUX_DATA(VIO_D8_MARK, PORT214_FN2),
982 PINMUX_DATA(VIO_D7_MARK, PORT215_FN2),
983 PINMUX_DATA(VIO_D6_MARK, PORT216_FN2),
984 PINMUX_DATA(VIO_D5_MARK, PORT217_FN2),
985 PINMUX_DATA(VIO_D4_MARK, PORT218_FN2),
986 PINMUX_DATA(VIO_D3_MARK, PORT219_FN2),
987 PINMUX_DATA(VIO_D2_MARK, PORT220_FN2),
988 PINMUX_DATA(VIO_D1_MARK, PORT221_FN2),
989 PINMUX_DATA(VIO_D0_MARK, PORT222_FN2),
990
991 /* Port213 - Port222 FN5 */
992 PINMUX_DATA(GIO_OUT9_MARK, PORT213_FN5),
993 PINMUX_DATA(GIO_OUT8_MARK, PORT214_FN5),
994 PINMUX_DATA(GIO_OUT7_MARK, PORT215_FN5),
995 PINMUX_DATA(GIO_OUT6_MARK, PORT216_FN5),
996 PINMUX_DATA(GIO_OUT5_217_MARK, PORT217_FN5),
997 PINMUX_DATA(GIO_OUT4_218_MARK, PORT218_FN5),
998 PINMUX_DATA(GIO_OUT3_219_MARK, PORT219_FN5),
999 PINMUX_DATA(GIO_OUT2_220_MARK, PORT220_FN5),
1000 PINMUX_DATA(GIO_OUT1_221_MARK, PORT221_FN5),
1001 PINMUX_DATA(GIO_OUT0_222_MARK, PORT222_FN5),
1002
1003 /* Port224 */
1004 PINMUX_DATA(RDWR_224_MARK, PORT224_FN1),
1005 PINMUX_DATA(VIO_HD_MARK, PORT224_FN2),
1006 PINMUX_DATA(SIM1_GPO2_MARK, PORT224_FN5),
1007
1008 /* Port225 */
1009 PINMUX_DATA(RD_N_MARK, PORT225_FN1),
1010
1011 /* Port226 */
1012 PINMUX_DATA(WAIT_N_MARK, PORT226_FN1),
1013 PINMUX_DATA(VIO_CLK_MARK, PORT226_FN2),
1014 PINMUX_DATA(SIM1_GPO1_MARK, PORT226_FN5),
1015
1016 /* Port227 */
1017 PINMUX_DATA(WE0_N_MARK, PORT227_FN1),
1018 PINMUX_DATA(RDWR_227_MARK, PORT227_FN2),
1019
1020 /* Port228 */
1021 PINMUX_DATA(WE1_N_MARK, PORT228_FN1),
1022 PINMUX_DATA(SIM0_GPO0_MARK, PORT228_FN5),
1023
1024 /* Port229 */
1025 PINMUX_DATA(PWMO_MARK, PORT229_FN1),
1026 PINMUX_DATA(VIO_CKO1_229_MARK, PORT229_FN2),
1027
1028 /* Port230 */
1029 PINMUX_DATA(SLIM_CLK_MARK, PORT230_FN1),
1030 PINMUX_DATA(VIO_CKO4_230_MARK, PORT230_FN2),
1031
1032 /* Port231 */
1033 PINMUX_DATA(SLIM_DATA_MARK, PORT231_FN1),
1034 PINMUX_DATA(VIO_CKO5_231_MARK, PORT231_FN2),
1035
1036 /* Port232 */
1037 PINMUX_DATA(VIO_CKO2_232_MARK, PORT232_FN2),
1038 PINMUX_DATA(SF_PORT_0_232_MARK, PORT232_FN4),
1039
1040 /* Port233 */
1041 PINMUX_DATA(VIO_CKO3_233_MARK, PORT233_FN2),
1042 PINMUX_DATA(SF_PORT_1_233_MARK, PORT233_FN4),
1043
1044 /* Port234 */
1045 PINMUX_DATA(FSIACK_MARK, PORT234_FN1),
1046 PINMUX_DATA(PDM3_CLK_234_MARK, PORT234_FN2),
1047 PINMUX_DATA(ISP_IRIS1_234_MARK, PORT234_FN3),
1048
1049 /* Port235 */
1050 PINMUX_DATA(FSIAISLD_MARK, PORT235_FN1),
1051 PINMUX_DATA(PDM3_DATA_235_MARK, PORT235_FN2, MSEL3CR_12_1),
1052
1053 /* Port236 */
1054 PINMUX_DATA(FSIAOMC_MARK, PORT236_FN1),
1055 PINMUX_DATA(PDM0_OUTCLK_236_MARK, PORT236_FN2),
1056 PINMUX_DATA(ISP_IRIS0_236_MARK, PORT236_FN3),
1057
1058 /* Port237 */
1059 PINMUX_DATA(FSIAOLR_MARK, PORT237_FN1),
1060 PINMUX_DATA(FSIAILR_MARK, PORT237_FN2),
1061
1062 /* Port238 */
1063 PINMUX_DATA(FSIAOBT_MARK, PORT238_FN1),
1064 PINMUX_DATA(FSIAIBT_MARK, PORT238_FN2),
1065
1066 /* Port239 */
1067 PINMUX_DATA(FSIAOSLD_MARK, PORT239_FN1),
1068 PINMUX_DATA(PDM0_OUTDATA_239_MARK, PORT239_FN2),
1069
1070 /* Port240 */
1071 PINMUX_DATA(FSIBISLD_MARK, PORT240_FN1),
1072
1073 /* Port241 */
1074 PINMUX_DATA(FSIBOLR_MARK, PORT241_FN1),
1075 PINMUX_DATA(FSIBILR_MARK, PORT241_FN2),
1076
1077 /* Port242 */
1078 PINMUX_DATA(FSIBOMC_MARK, PORT242_FN1),
1079 PINMUX_DATA(ISP_SHUTTER1_242_MARK, PORT242_FN3),
1080
1081 /* Port243 */
1082 PINMUX_DATA(FSIBOBT_MARK, PORT243_FN1),
1083 PINMUX_DATA(FSIBIBT_MARK, PORT243_FN2),
1084
1085 /* Port244 */
1086 PINMUX_DATA(FSIBOSLD_MARK, PORT244_FN1),
1087 PINMUX_DATA(FSIASPDIF_MARK, PORT244_FN2),
1088
1089 /* Port245 */
1090 PINMUX_DATA(FSIBCK_MARK, PORT245_FN1),
1091 PINMUX_DATA(ISP_SHUTTER0_245_MARK, PORT245_FN3),
1092
1093 /* Port246 - Port250 FN1 */
1094 PINMUX_DATA(ISP_IRIS1_246_MARK, PORT246_FN1),
1095 PINMUX_DATA(ISP_IRIS0_247_MARK, PORT247_FN1),
1096 PINMUX_DATA(ISP_SHUTTER1_248_MARK, PORT248_FN1),
1097 PINMUX_DATA(ISP_SHUTTER0_249_MARK, PORT249_FN1),
1098 PINMUX_DATA(ISP_STROBE_250_MARK, PORT250_FN1),
1099
1100 /* Port256 - Port258 */
1101 PINMUX_DATA(MSIOF0_SYNC_MARK, PORT256_FN1),
1102 PINMUX_DATA(MSIOF0_RXD_MARK, PORT257_FN1),
1103 PINMUX_DATA(MSIOF0_SCK_MARK, PORT258_FN1),
1104
1105 /* Port259 */
1106 PINMUX_DATA(MSIOF0_SS2_MARK, PORT259_FN1),
1107 PINMUX_DATA(VIO_CKO3_259_MARK, PORT259_FN3),
1108
1109 /* Port260 */
1110 PINMUX_DATA(MSIOF0_TXD_MARK, PORT260_FN1),
1111
1112 /* Port261 */
1113 PINMUX_DATA(SCIFB1_SCK_261_MARK, PORT261_FN2),
1114 PINMUX_DATA(CHSCIF1_HSCK_MARK, PORT261_FN7),
1115
1116 /* Port262 */
1117 PINMUX_DATA(SCIFB2_SCK_262_MARK, PORT262_FN2),
1118
1119 /* Port263 - Port266 FN1 */
1120 PINMUX_DATA(MSIOF1_SS2_MARK, PORT263_FN1),
1121 PINMUX_DATA(MSIOF1_TXD_MARK, PORT264_FN1),
1122 PINMUX_DATA(MSIOF1_RXD_MARK, PORT265_FN1),
1123 PINMUX_DATA(MSIOF1_SS1_MARK, PORT266_FN1),
1124
1125 /* Port263 - Port266 FN4 */
1126 PINMUX_DATA(MSIOF5_SS2_MARK, PORT263_FN4),
1127 PINMUX_DATA(MSIOF5_TXD_MARK, PORT264_FN4),
1128 PINMUX_DATA(MSIOF5_RXD_MARK, PORT265_FN4),
1129 PINMUX_DATA(MSIOF5_SS1_MARK, PORT266_FN4),
1130
1131 /* Port267 */
1132 PINMUX_DATA(MSIOF0_SS1_MARK, PORT267_FN1),
1133
1134 /* Port268 */
1135 PINMUX_DATA(MSIOF1_SCK_MARK, PORT268_FN1),
1136 PINMUX_DATA(MSIOF5_SCK_MARK, PORT268_FN4),
1137
1138 /* Port269 */
1139 PINMUX_DATA(MSIOF1_SYNC_MARK, PORT269_FN1),
1140 PINMUX_DATA(MSIOF5_SYNC_MARK, PORT269_FN4),
1141
1142 /* Port270 - Port273 FN1 */
1143 PINMUX_DATA(MSIOF2_SS1_MARK, PORT270_FN1),
1144 PINMUX_DATA(MSIOF2_SS2_MARK, PORT271_FN1),
1145 PINMUX_DATA(MSIOF3_SS2_MARK, PORT272_FN1),
1146 PINMUX_DATA(MSIOF3_SS1_MARK, PORT273_FN1),
1147
1148 /* Port270 - Port273 FN3 */
1149 PINMUX_DATA(VIO_CKO5_270_MARK, PORT270_FN3),
1150 PINMUX_DATA(VIO_CKO2_271_MARK, PORT271_FN3),
1151 PINMUX_DATA(VIO_CKO1_272_MARK, PORT272_FN3),
1152 PINMUX_DATA(VIO_CKO4_273_MARK, PORT273_FN3),
1153
1154 /* Port274 */
1155 PINMUX_DATA(MSIOF4_SS2_MARK, PORT274_FN1),
1156 PINMUX_DATA(TPU1TO0_MARK, PORT274_FN4),
1157
1158 /* Port275 - Port280 */
1159 PINMUX_DATA(IC_DP_MARK, PORT275_FN1),
1160 PINMUX_DATA(SIM0_RST_MARK, PORT276_FN1),
1161 PINMUX_DATA(IC_DM_MARK, PORT277_FN1),
1162 PINMUX_DATA(SIM0_BSICOMP_MARK, PORT278_FN1),
1163 PINMUX_DATA(SIM0_CLK_MARK, PORT279_FN1),
1164 PINMUX_DATA(SIM0_IO_MARK, PORT280_FN1),
1165
1166 /* Port281 */
1167 PINMUX_DATA(SIM1_IO_MARK, PORT281_FN1),
1168 PINMUX_DATA(PDM2_DATA_281_MARK, PORT281_FN2, MSEL3CR_12_1),
1169
1170 /* Port282 */
1171 PINMUX_DATA(SIM1_CLK_MARK, PORT282_FN1),
1172 PINMUX_DATA(PDM2_CLK_282_MARK, PORT282_FN2),
1173
1174 /* Port283 */
1175 PINMUX_DATA(SIM1_RST_MARK, PORT283_FN1),
1176
1177 /* Port289 */
1178 PINMUX_DATA(SDHID1_0_MARK, PORT289_FN1),
1179 PINMUX_DATA(STMDATA0_2_MARK, PORT289_FN3),
1180
1181 /* Port290 */
1182 PINMUX_DATA(SDHID1_1_MARK, PORT290_FN1),
1183 PINMUX_DATA(STMDATA1_2_MARK, PORT290_FN3),
1184 PINMUX_DATA(IRQ51_MARK, PORT290_FN0),
1185
1186 /* Port291 - Port294 FN1 */
1187 PINMUX_DATA(SDHID1_2_MARK, PORT291_FN1),
1188 PINMUX_DATA(SDHID1_3_MARK, PORT292_FN1),
1189 PINMUX_DATA(SDHICLK1_MARK, PORT293_FN1),
1190 PINMUX_DATA(SDHICMD1_MARK, PORT294_FN1),
1191
1192 /* Port291 - Port294 FN3 */
1193 PINMUX_DATA(STMDATA2_2_MARK, PORT291_FN3),
1194 PINMUX_DATA(STMDATA3_2_MARK, PORT292_FN3),
1195 PINMUX_DATA(STMCLK_2_MARK, PORT293_FN3),
1196 PINMUX_DATA(STMSIDI_2_MARK, PORT294_FN3),
1197
1198 /* Port295 */
1199 PINMUX_DATA(SDHID2_0_MARK, PORT295_FN1),
1200 PINMUX_DATA(MSIOF4_TXD_MARK, PORT295_FN2),
1201 PINMUX_DATA(SCIFB2_TXD_295_MARK, PORT295_FN3, MSEL3CR_10_1),
1202 PINMUX_DATA(MSIOF6_TXD_MARK, PORT295_FN4),
1203
1204 /* Port296 */
1205 PINMUX_DATA(SDHID2_1_MARK, PORT296_FN1),
1206 PINMUX_DATA(MSIOF6_SS2_MARK, PORT296_FN4),
1207 PINMUX_DATA(IRQ52_MARK, PORT296_FN0),
1208
1209 /* Port297 - Port300 FN1 */
1210 PINMUX_DATA(SDHID2_2_MARK, PORT297_FN1),
1211 PINMUX_DATA(SDHID2_3_MARK, PORT298_FN1),
1212 PINMUX_DATA(SDHICLK2_MARK, PORT299_FN1),
1213 PINMUX_DATA(SDHICMD2_MARK, PORT300_FN1),
1214
1215 /* Port297 - Port300 FN2 */
1216 PINMUX_DATA(MSIOF4_RXD_MARK, PORT297_FN2),
1217 PINMUX_DATA(MSIOF4_SYNC_MARK, PORT298_FN2),
1218 PINMUX_DATA(MSIOF4_SCK_MARK, PORT299_FN2),
1219 PINMUX_DATA(MSIOF4_SS1_MARK, PORT300_FN2),
1220
1221 /* Port297 - Port300 FN3 */
1222 PINMUX_DATA(SCIFB2_RXD_297_MARK, PORT297_FN3, MSEL3CR_10_1),
1223 PINMUX_DATA(SCIFB2_CTS_298_MARK, PORT298_FN3, MSEL3CR_10_1),
1224 PINMUX_DATA(SCIFB2_SCK_299_MARK, PORT299_FN3),
1225 PINMUX_DATA(SCIFB2_RTS_300_MARK, PORT300_FN3),
1226
1227 /* Port297 - Port300 FN4 */
1228 PINMUX_DATA(MSIOF6_RXD_MARK, PORT297_FN4),
1229 PINMUX_DATA(MSIOF6_SYNC_MARK, PORT298_FN4),
1230 PINMUX_DATA(MSIOF6_SCK_MARK, PORT299_FN4),
1231 PINMUX_DATA(MSIOF6_SS1_MARK, PORT300_FN4),
1232
1233 /* Port301 */
1234 PINMUX_DATA(SDHICD0_MARK, PORT301_FN1),
1235 PINMUX_DATA(IRQ50_MARK, PORT301_FN0),
1236
1237 /* Port302 - Port306 FN1 */
1238 PINMUX_DATA(SDHID0_0_MARK, PORT302_FN1),
1239 PINMUX_DATA(SDHID0_1_MARK, PORT303_FN1),
1240 PINMUX_DATA(SDHID0_2_MARK, PORT304_FN1),
1241 PINMUX_DATA(SDHID0_3_MARK, PORT305_FN1),
1242 PINMUX_DATA(SDHICMD0_MARK, PORT306_FN1),
1243
1244 /* Port302 - Port306 FN3 */
1245 PINMUX_DATA(STMDATA0_1_MARK, PORT302_FN3),
1246 PINMUX_DATA(STMDATA1_1_MARK, PORT303_FN3),
1247 PINMUX_DATA(STMDATA2_1_MARK, PORT304_FN3),
1248 PINMUX_DATA(STMDATA3_1_MARK, PORT305_FN3),
1249 PINMUX_DATA(STMSIDI_1_MARK, PORT306_FN3),
1250
1251 /* Port307 */
1252 PINMUX_DATA(SDHIWP0_MARK, PORT307_FN1),
1253
1254 /* Port308 */
1255 PINMUX_DATA(SDHICLK0_MARK, PORT308_FN1),
1256 PINMUX_DATA(STMCLK_1_MARK, PORT308_FN3),
1257
1258 /* Port320 - Port329 */
1259 PINMUX_DATA(IRQ16_MARK, PORT320_FN0),
1260 PINMUX_DATA(IRQ17_MARK, PORT321_FN0),
1261 PINMUX_DATA(IRQ28_MARK, PORT322_FN0),
1262 PINMUX_DATA(IRQ29_MARK, PORT323_FN0),
1263 PINMUX_DATA(IRQ30_MARK, PORT324_FN0),
1264 PINMUX_DATA(IRQ53_MARK, PORT325_FN0),
1265 PINMUX_DATA(IRQ54_MARK, PORT326_FN0),
1266 PINMUX_DATA(IRQ55_MARK, PORT327_FN0),
1267 PINMUX_DATA(IRQ56_MARK, PORT328_FN0),
1268 PINMUX_DATA(IRQ57_MARK, PORT329_FN0),
1269 };
1270
1271 #define __O (SH_PFC_PIN_CFG_OUTPUT)
1272 #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1273 #define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1274
1275 #define R8A73A4_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
1276 #define R8A73A4_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
1277
1278 static const struct sh_pfc_pin pinmux_pins[] = {
1279 R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1),
1280 R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3),
1281 R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5),
1282 R8A73A4_PIN_IO_PU_PD(6), R8A73A4_PIN_IO_PU_PD(7),
1283 R8A73A4_PIN_IO_PU_PD(8), R8A73A4_PIN_IO_PU_PD(9),
1284 R8A73A4_PIN_IO_PU_PD(10), R8A73A4_PIN_IO_PU_PD(11),
1285 R8A73A4_PIN_IO_PU_PD(12), R8A73A4_PIN_IO_PU_PD(13),
1286 R8A73A4_PIN_IO_PU_PD(14), R8A73A4_PIN_IO_PU_PD(15),
1287 R8A73A4_PIN_IO_PU_PD(16), R8A73A4_PIN_IO_PU_PD(17),
1288 R8A73A4_PIN_IO_PU_PD(18), R8A73A4_PIN_IO_PU_PD(19),
1289 R8A73A4_PIN_IO_PU_PD(20), R8A73A4_PIN_IO_PU_PD(21),
1290 R8A73A4_PIN_IO_PU_PD(22), R8A73A4_PIN_IO_PU_PD(23),
1291 R8A73A4_PIN_IO_PU_PD(24), R8A73A4_PIN_IO_PU_PD(25),
1292 R8A73A4_PIN_IO_PU_PD(26), R8A73A4_PIN_IO_PU_PD(27),
1293 R8A73A4_PIN_IO_PU_PD(28), R8A73A4_PIN_IO_PU_PD(29),
1294 R8A73A4_PIN_IO_PU_PD(30),
1295 R8A73A4_PIN_IO_PU_PD(32), R8A73A4_PIN_IO_PU_PD(33),
1296 R8A73A4_PIN_IO_PU_PD(34), R8A73A4_PIN_IO_PU_PD(35),
1297 R8A73A4_PIN_IO_PU_PD(36), R8A73A4_PIN_IO_PU_PD(37),
1298 R8A73A4_PIN_IO_PU_PD(38), R8A73A4_PIN_IO_PU_PD(39),
1299 R8A73A4_PIN_IO_PU_PD(40),
1300 R8A73A4_PIN_IO_PU_PD(64), R8A73A4_PIN_IO_PU_PD(65),
1301 R8A73A4_PIN_IO_PU_PD(66), R8A73A4_PIN_IO_PU_PD(67),
1302 R8A73A4_PIN_IO_PU_PD(68), R8A73A4_PIN_IO_PU_PD(69),
1303 R8A73A4_PIN_IO_PU_PD(70), R8A73A4_PIN_IO_PU_PD(71),
1304 R8A73A4_PIN_IO_PU_PD(72), R8A73A4_PIN_IO_PU_PD(73),
1305 R8A73A4_PIN_O(74), R8A73A4_PIN_IO_PU_PD(75),
1306 R8A73A4_PIN_IO_PU_PD(76), R8A73A4_PIN_IO_PU_PD(77),
1307 R8A73A4_PIN_IO_PU_PD(78), R8A73A4_PIN_IO_PU_PD(79),
1308 R8A73A4_PIN_IO_PU_PD(80), R8A73A4_PIN_IO_PU_PD(81),
1309 R8A73A4_PIN_IO_PU_PD(82), R8A73A4_PIN_IO_PU_PD(83),
1310 R8A73A4_PIN_IO_PU_PD(84), R8A73A4_PIN_IO_PU_PD(85),
1311 R8A73A4_PIN_IO_PU_PD(96), R8A73A4_PIN_IO_PU_PD(97),
1312 R8A73A4_PIN_IO_PU_PD(98), R8A73A4_PIN_IO_PU_PD(99),
1313 R8A73A4_PIN_IO_PU_PD(100), R8A73A4_PIN_IO_PU_PD(101),
1314 R8A73A4_PIN_IO_PU_PD(102), R8A73A4_PIN_IO_PU_PD(103),
1315 R8A73A4_PIN_IO_PU_PD(104), R8A73A4_PIN_IO_PU_PD(105),
1316 R8A73A4_PIN_IO_PU_PD(106), R8A73A4_PIN_IO_PU_PD(107),
1317 R8A73A4_PIN_IO_PU_PD(108), R8A73A4_PIN_IO_PU_PD(109),
1318 R8A73A4_PIN_IO_PU_PD(110), R8A73A4_PIN_IO_PU_PD(111),
1319 R8A73A4_PIN_IO_PU_PD(112), R8A73A4_PIN_IO_PU_PD(113),
1320 R8A73A4_PIN_IO_PU_PD(114), R8A73A4_PIN_IO_PU_PD(115),
1321 R8A73A4_PIN_IO_PU_PD(116), R8A73A4_PIN_IO_PU_PD(117),
1322 R8A73A4_PIN_IO_PU_PD(118), R8A73A4_PIN_IO_PU_PD(119),
1323 R8A73A4_PIN_IO_PU_PD(120), R8A73A4_PIN_IO_PU_PD(121),
1324 R8A73A4_PIN_IO_PU_PD(122), R8A73A4_PIN_IO_PU_PD(123),
1325 R8A73A4_PIN_IO_PU_PD(124), R8A73A4_PIN_IO_PU_PD(125),
1326 R8A73A4_PIN_IO_PU_PD(126),
1327 R8A73A4_PIN_IO_PU_PD(128), R8A73A4_PIN_IO_PU_PD(129),
1328 R8A73A4_PIN_IO_PU_PD(130), R8A73A4_PIN_IO_PU_PD(131),
1329 R8A73A4_PIN_IO_PU_PD(132), R8A73A4_PIN_IO_PU_PD(133),
1330 R8A73A4_PIN_IO_PU_PD(134),
1331 R8A73A4_PIN_IO_PU_PD(160), R8A73A4_PIN_IO_PU_PD(161),
1332 R8A73A4_PIN_IO_PU_PD(162), R8A73A4_PIN_IO_PU_PD(163),
1333 R8A73A4_PIN_IO_PU_PD(164), R8A73A4_PIN_IO_PU_PD(165),
1334 R8A73A4_PIN_IO_PU_PD(166), R8A73A4_PIN_IO_PU_PD(167),
1335 R8A73A4_PIN_IO_PU_PD(168), R8A73A4_PIN_IO_PU_PD(169),
1336 R8A73A4_PIN_IO_PU_PD(170), R8A73A4_PIN_IO_PU_PD(171),
1337 R8A73A4_PIN_IO_PU_PD(172), R8A73A4_PIN_IO_PU_PD(173),
1338 R8A73A4_PIN_IO_PU_PD(174), R8A73A4_PIN_IO_PU_PD(175),
1339 R8A73A4_PIN_IO_PU_PD(176), R8A73A4_PIN_IO_PU_PD(177),
1340 R8A73A4_PIN_IO_PU_PD(178),
1341 R8A73A4_PIN_IO_PU_PD(192), R8A73A4_PIN_IO_PU_PD(193),
1342 R8A73A4_PIN_IO_PU_PD(194), R8A73A4_PIN_IO_PU_PD(195),
1343 R8A73A4_PIN_IO_PU_PD(196), R8A73A4_PIN_IO_PU_PD(197),
1344 R8A73A4_PIN_IO_PU_PD(198), R8A73A4_PIN_IO_PU_PD(199),
1345 R8A73A4_PIN_IO_PU_PD(200), R8A73A4_PIN_IO_PU_PD(201),
1346 R8A73A4_PIN_IO_PU_PD(202), R8A73A4_PIN_IO_PU_PD(203),
1347 R8A73A4_PIN_IO_PU_PD(204), R8A73A4_PIN_IO_PU_PD(205),
1348 R8A73A4_PIN_IO_PU_PD(206), R8A73A4_PIN_IO_PU_PD(207),
1349 R8A73A4_PIN_IO_PU_PD(208), R8A73A4_PIN_IO_PU_PD(209),
1350 R8A73A4_PIN_IO_PU_PD(210), R8A73A4_PIN_IO_PU_PD(211),
1351 R8A73A4_PIN_IO_PU_PD(212), R8A73A4_PIN_IO_PU_PD(213),
1352 R8A73A4_PIN_IO_PU_PD(214), R8A73A4_PIN_IO_PU_PD(215),
1353 R8A73A4_PIN_IO_PU_PD(216), R8A73A4_PIN_IO_PU_PD(217),
1354 R8A73A4_PIN_IO_PU_PD(218), R8A73A4_PIN_IO_PU_PD(219),
1355 R8A73A4_PIN_IO_PU_PD(220), R8A73A4_PIN_IO_PU_PD(221),
1356 R8A73A4_PIN_IO_PU_PD(222),
1357 R8A73A4_PIN_IO_PU_PD(224), R8A73A4_PIN_IO_PU_PD(225),
1358 R8A73A4_PIN_IO_PU_PD(226), R8A73A4_PIN_IO_PU_PD(227),
1359 R8A73A4_PIN_IO_PU_PD(228), R8A73A4_PIN_IO_PU_PD(229),
1360 R8A73A4_PIN_IO_PU_PD(230), R8A73A4_PIN_IO_PU_PD(231),
1361 R8A73A4_PIN_IO_PU_PD(232), R8A73A4_PIN_IO_PU_PD(233),
1362 R8A73A4_PIN_IO_PU_PD(234), R8A73A4_PIN_IO_PU_PD(235),
1363 R8A73A4_PIN_IO_PU_PD(236), R8A73A4_PIN_IO_PU_PD(237),
1364 R8A73A4_PIN_IO_PU_PD(238), R8A73A4_PIN_IO_PU_PD(239),
1365 R8A73A4_PIN_IO_PU_PD(240), R8A73A4_PIN_IO_PU_PD(241),
1366 R8A73A4_PIN_IO_PU_PD(242), R8A73A4_PIN_IO_PU_PD(243),
1367 R8A73A4_PIN_IO_PU_PD(244), R8A73A4_PIN_IO_PU_PD(245),
1368 R8A73A4_PIN_IO_PU_PD(246), R8A73A4_PIN_IO_PU_PD(247),
1369 R8A73A4_PIN_IO_PU_PD(248), R8A73A4_PIN_IO_PU_PD(249),
1370 R8A73A4_PIN_IO_PU_PD(250),
1371 R8A73A4_PIN_IO_PU_PD(256), R8A73A4_PIN_IO_PU_PD(257),
1372 R8A73A4_PIN_IO_PU_PD(258), R8A73A4_PIN_IO_PU_PD(259),
1373 R8A73A4_PIN_IO_PU_PD(260), R8A73A4_PIN_IO_PU_PD(261),
1374 R8A73A4_PIN_IO_PU_PD(262), R8A73A4_PIN_IO_PU_PD(263),
1375 R8A73A4_PIN_IO_PU_PD(264), R8A73A4_PIN_IO_PU_PD(265),
1376 R8A73A4_PIN_IO_PU_PD(266), R8A73A4_PIN_IO_PU_PD(267),
1377 R8A73A4_PIN_IO_PU_PD(268), R8A73A4_PIN_IO_PU_PD(269),
1378 R8A73A4_PIN_IO_PU_PD(270), R8A73A4_PIN_IO_PU_PD(271),
1379 R8A73A4_PIN_IO_PU_PD(272), R8A73A4_PIN_IO_PU_PD(273),
1380 R8A73A4_PIN_IO_PU_PD(274), R8A73A4_PIN_IO_PU_PD(275),
1381 R8A73A4_PIN_IO_PU_PD(276), R8A73A4_PIN_IO_PU_PD(277),
1382 R8A73A4_PIN_IO_PU_PD(278), R8A73A4_PIN_IO_PU_PD(279),
1383 R8A73A4_PIN_IO_PU_PD(280), R8A73A4_PIN_IO_PU_PD(281),
1384 R8A73A4_PIN_IO_PU_PD(282), R8A73A4_PIN_IO_PU_PD(283),
1385 R8A73A4_PIN_O(288), R8A73A4_PIN_IO_PU_PD(289),
1386 R8A73A4_PIN_IO_PU_PD(290), R8A73A4_PIN_IO_PU_PD(291),
1387 R8A73A4_PIN_IO_PU_PD(292), R8A73A4_PIN_IO_PU_PD(293),
1388 R8A73A4_PIN_IO_PU_PD(294), R8A73A4_PIN_IO_PU_PD(295),
1389 R8A73A4_PIN_IO_PU_PD(296), R8A73A4_PIN_IO_PU_PD(297),
1390 R8A73A4_PIN_IO_PU_PD(298), R8A73A4_PIN_IO_PU_PD(299),
1391 R8A73A4_PIN_IO_PU_PD(300), R8A73A4_PIN_IO_PU_PD(301),
1392 R8A73A4_PIN_IO_PU_PD(302), R8A73A4_PIN_IO_PU_PD(303),
1393 R8A73A4_PIN_IO_PU_PD(304), R8A73A4_PIN_IO_PU_PD(305),
1394 R8A73A4_PIN_IO_PU_PD(306), R8A73A4_PIN_IO_PU_PD(307),
1395 R8A73A4_PIN_IO_PU_PD(308),
1396 R8A73A4_PIN_IO_PU_PD(320), R8A73A4_PIN_IO_PU_PD(321),
1397 R8A73A4_PIN_IO_PU_PD(322), R8A73A4_PIN_IO_PU_PD(323),
1398 R8A73A4_PIN_IO_PU_PD(324), R8A73A4_PIN_IO_PU_PD(325),
1399 R8A73A4_PIN_IO_PU_PD(326), R8A73A4_PIN_IO_PU_PD(327),
1400 R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329),
1401 };
1402
1403 /* - IRQC ------------------------------------------------------------------- */
1404 #define IRQC_PINS_MUX(pin, irq_mark) \
1405 static const unsigned int irqc_irq##irq_mark##_pins[] = { \
1406 pin, \
1407 }; \
1408 static const unsigned int irqc_irq##irq_mark##_mux[] = { \
1409 IRQ##irq_mark##_MARK, \
1410 }
1411 IRQC_PINS_MUX(0, 0);
1412 IRQC_PINS_MUX(1, 1);
1413 IRQC_PINS_MUX(2, 2);
1414 IRQC_PINS_MUX(3, 3);
1415 IRQC_PINS_MUX(4, 4);
1416 IRQC_PINS_MUX(5, 5);
1417 IRQC_PINS_MUX(6, 6);
1418 IRQC_PINS_MUX(7, 7);
1419 IRQC_PINS_MUX(8, 8);
1420 IRQC_PINS_MUX(9, 9);
1421 IRQC_PINS_MUX(10, 10);
1422 IRQC_PINS_MUX(11, 11);
1423 IRQC_PINS_MUX(12, 12);
1424 IRQC_PINS_MUX(13, 13);
1425 IRQC_PINS_MUX(14, 14);
1426 IRQC_PINS_MUX(15, 15);
1427 IRQC_PINS_MUX(66, 40);
1428 IRQC_PINS_MUX(84, 19);
1429 IRQC_PINS_MUX(85, 18);
1430 IRQC_PINS_MUX(102, 41);
1431 IRQC_PINS_MUX(103, 42);
1432 IRQC_PINS_MUX(109, 43);
1433 IRQC_PINS_MUX(110, 44);
1434 IRQC_PINS_MUX(111, 45);
1435 IRQC_PINS_MUX(112, 46);
1436 IRQC_PINS_MUX(113, 47);
1437 IRQC_PINS_MUX(114, 48);
1438 IRQC_PINS_MUX(115, 49);
1439 IRQC_PINS_MUX(160, 20);
1440 IRQC_PINS_MUX(161, 21);
1441 IRQC_PINS_MUX(162, 22);
1442 IRQC_PINS_MUX(163, 23);
1443 IRQC_PINS_MUX(175, 24);
1444 IRQC_PINS_MUX(176, 25);
1445 IRQC_PINS_MUX(177, 26);
1446 IRQC_PINS_MUX(178, 27);
1447 IRQC_PINS_MUX(192, 31);
1448 IRQC_PINS_MUX(193, 32);
1449 IRQC_PINS_MUX(194, 33);
1450 IRQC_PINS_MUX(195, 34);
1451 IRQC_PINS_MUX(196, 35);
1452 IRQC_PINS_MUX(197, 36);
1453 IRQC_PINS_MUX(198, 37);
1454 IRQC_PINS_MUX(199, 38);
1455 IRQC_PINS_MUX(200, 39);
1456 IRQC_PINS_MUX(290, 51);
1457 IRQC_PINS_MUX(296, 52);
1458 IRQC_PINS_MUX(301, 50);
1459 IRQC_PINS_MUX(320, 16);
1460 IRQC_PINS_MUX(321, 17);
1461 IRQC_PINS_MUX(322, 28);
1462 IRQC_PINS_MUX(323, 29);
1463 IRQC_PINS_MUX(324, 30);
1464 IRQC_PINS_MUX(325, 53);
1465 IRQC_PINS_MUX(326, 54);
1466 IRQC_PINS_MUX(327, 55);
1467 IRQC_PINS_MUX(328, 56);
1468 IRQC_PINS_MUX(329, 57);
1469 /* - MMCIF0 ----------------------------------------------------------------- */
1470 static const unsigned int mmc0_data1_pins[] = {
1471 /* D[0] */
1472 164,
1473 };
1474 static const unsigned int mmc0_data1_mux[] = {
1475 MMCD0_0_MARK,
1476 };
1477 static const unsigned int mmc0_data4_pins[] = {
1478 /* D[0:3] */
1479 164, 165, 166, 167,
1480 };
1481 static const unsigned int mmc0_data4_mux[] = {
1482 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
1483 };
1484 static const unsigned int mmc0_data8_pins[] = {
1485 /* D[0:7] */
1486 164, 165, 166, 167, 168, 169, 170, 171,
1487 };
1488 static const unsigned int mmc0_data8_mux[] = {
1489 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
1490 MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
1491 };
1492 static const unsigned int mmc0_ctrl_pins[] = {
1493 /* CMD, CLK */
1494 172, 173,
1495 };
1496 static const unsigned int mmc0_ctrl_mux[] = {
1497 MMCCMD0_MARK, MMCCLK0_MARK,
1498 };
1499 /* - MMCIF1 ----------------------------------------------------------------- */
1500 static const unsigned int mmc1_data1_pins[] = {
1501 /* D[0] */
1502 199,
1503 };
1504 static const unsigned int mmc1_data1_mux[] = {
1505 MMCD1_0_MARK,
1506 };
1507 static const unsigned int mmc1_data4_pins[] = {
1508 /* D[0:3] */
1509 199, 198, 197, 196,
1510 };
1511 static const unsigned int mmc1_data4_mux[] = {
1512 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
1513 };
1514 static const unsigned int mmc1_data8_pins[] = {
1515 /* D[0:7] */
1516 199, 198, 197, 196, 195, 194, 193, 192,
1517 };
1518 static const unsigned int mmc1_data8_mux[] = {
1519 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
1520 MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
1521 };
1522 static const unsigned int mmc1_ctrl_pins[] = {
1523 /* CMD, CLK */
1524 200, 203,
1525 };
1526 static const unsigned int mmc1_ctrl_mux[] = {
1527 MMCCMD1_MARK, MMCCLK1_MARK,
1528 };
1529 /* - SCIFA0 ----------------------------------------------------------------- */
1530 static const unsigned int scifa0_data_pins[] = {
1531 /* SCIFA0_RXD, SCIFA0_TXD */
1532 117, 116,
1533 };
1534 static const unsigned int scifa0_data_mux[] = {
1535 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
1536 };
1537 static const unsigned int scifa0_clk_pins[] = {
1538 /* SCIFA0_SCK */
1539 34,
1540 };
1541 static const unsigned int scifa0_clk_mux[] = {
1542 SCIFA0_SCK_MARK,
1543 };
1544 static const unsigned int scifa0_ctrl_pins[] = {
1545 /* SCIFA0_RTS, SCIFA0_CTS */
1546 32, 33,
1547 };
1548 static const unsigned int scifa0_ctrl_mux[] = {
1549 SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
1550 };
1551 /* - SCIFA1 ----------------------------------------------------------------- */
1552 static const unsigned int scifa1_data_pins[] = {
1553 /* SCIFA1_RXD, SCIFA1_TXD */
1554 119, 118,
1555 };
1556 static const unsigned int scifa1_data_mux[] = {
1557 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
1558 };
1559 static const unsigned int scifa1_clk_pins[] = {
1560 /* SCIFA1_SCK */
1561 37,
1562 };
1563 static const unsigned int scifa1_clk_mux[] = {
1564 SCIFA1_SCK_MARK,
1565 };
1566 static const unsigned int scifa1_ctrl_pins[] = {
1567 /* SCIFA1_RTS, SCIFA1_CTS */
1568 35, 36,
1569 };
1570 static const unsigned int scifa1_ctrl_mux[] = {
1571 SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
1572 };
1573 /* - SCIFB0 ----------------------------------------------------------------- */
1574 static const unsigned int scifb0_data_pins[] = {
1575 /* SCIFB0_RXD, SCIFB0_TXD */
1576 123, 122,
1577 };
1578 static const unsigned int scifb0_data_mux[] = {
1579 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
1580 };
1581 static const unsigned int scifb0_clk_pins[] = {
1582 /* SCIFB0_SCK */
1583 40,
1584 };
1585 static const unsigned int scifb0_clk_mux[] = {
1586 SCIFB0_SCK_MARK,
1587 };
1588 static const unsigned int scifb0_ctrl_pins[] = {
1589 /* SCIFB0_RTS, SCIFB0_CTS */
1590 38, 39,
1591 };
1592 static const unsigned int scifb0_ctrl_mux[] = {
1593 SCIFB0_RTS_MARK, SCIFB0_CTS_MARK,
1594 };
1595 /* - SCIFB1 ----------------------------------------------------------------- */
1596 static const unsigned int scifb1_data_pins[] = {
1597 /* SCIFB1_RXD, SCIFB1_TXD */
1598 27, 26,
1599 };
1600 static const unsigned int scifb1_data_mux[] = {
1601 SCIFB1_RXD_27_MARK, SCIFB1_TXD_26_MARK,
1602 };
1603 static const unsigned int scifb1_clk_pins[] = {
1604 /* SCIFB1_SCK */
1605 28,
1606 };
1607 static const unsigned int scifb1_clk_mux[] = {
1608 SCIFB1_SCK_28_MARK,
1609 };
1610 static const unsigned int scifb1_ctrl_pins[] = {
1611 /* SCIFB1_RTS, SCIFB1_CTS */
1612 24, 25,
1613 };
1614 static const unsigned int scifb1_ctrl_mux[] = {
1615 SCIFB1_RTS_24_MARK, SCIFB1_CTS_25_MARK,
1616 };
1617 static const unsigned int scifb1_data_b_pins[] = {
1618 /* SCIFB1_RXD, SCIFB1_TXD */
1619 72, 67,
1620 };
1621 static const unsigned int scifb1_data_b_mux[] = {
1622 SCIFB1_RXD_72_MARK, SCIFB1_TXD_67_MARK,
1623 };
1624 static const unsigned int scifb1_clk_b_pins[] = {
1625 /* SCIFB1_SCK */
1626 261,
1627 };
1628 static const unsigned int scifb1_clk_b_mux[] = {
1629 SCIFB1_SCK_261_MARK,
1630 };
1631 static const unsigned int scifb1_ctrl_b_pins[] = {
1632 /* SCIFB1_RTS, SCIFB1_CTS */
1633 70, 71,
1634 };
1635 static const unsigned int scifb1_ctrl_b_mux[] = {
1636 SCIFB1_RTS_70_MARK, SCIFB1_CTS_71_MARK,
1637 };
1638 /* - SCIFB2 ----------------------------------------------------------------- */
1639 static const unsigned int scifb2_data_pins[] = {
1640 /* SCIFB2_RXD, SCIFB2_TXD */
1641 69, 68,
1642 };
1643 static const unsigned int scifb2_data_mux[] = {
1644 SCIFB2_RXD_69_MARK, SCIFB2_TXD_68_MARK,
1645 };
1646 static const unsigned int scifb2_clk_pins[] = {
1647 /* SCIFB2_SCK */
1648 262,
1649 };
1650 static const unsigned int scifb2_clk_mux[] = {
1651 SCIFB2_SCK_262_MARK,
1652 };
1653 static const unsigned int scifb2_ctrl_pins[] = {
1654 /* SCIFB2_RTS, SCIFB2_CTS */
1655 73, 66,
1656 };
1657 static const unsigned int scifb2_ctrl_mux[] = {
1658 SCIFB2_RTS_73_MARK, SCIFB2_CTS_66_MARK,
1659 };
1660 static const unsigned int scifb2_data_b_pins[] = {
1661 /* SCIFB2_RXD, SCIFB2_TXD */
1662 297, 295,
1663 };
1664 static const unsigned int scifb2_data_b_mux[] = {
1665 SCIFB2_RXD_297_MARK, SCIFB2_TXD_295_MARK,
1666 };
1667 static const unsigned int scifb2_clk_b_pins[] = {
1668 /* SCIFB2_SCK */
1669 299,
1670 };
1671 static const unsigned int scifb2_clk_b_mux[] = {
1672 SCIFB2_SCK_299_MARK,
1673 };
1674 static const unsigned int scifb2_ctrl_b_pins[] = {
1675 /* SCIFB2_RTS, SCIFB2_CTS */
1676 300, 298,
1677 };
1678 static const unsigned int scifb2_ctrl_b_mux[] = {
1679 SCIFB2_RTS_300_MARK, SCIFB2_CTS_298_MARK,
1680 };
1681 /* - SCIFB3 ----------------------------------------------------------------- */
1682 static const unsigned int scifb3_data_pins[] = {
1683 /* SCIFB3_RXD, SCIFB3_TXD */
1684 22, 21,
1685 };
1686 static const unsigned int scifb3_data_mux[] = {
1687 SCIFB3_RXD_22_MARK, SCIFB3_TXD_21_MARK,
1688 };
1689 static const unsigned int scifb3_clk_pins[] = {
1690 /* SCIFB3_SCK */
1691 23,
1692 };
1693 static const unsigned int scifb3_clk_mux[] = {
1694 SCIFB3_SCK_23_MARK,
1695 };
1696 static const unsigned int scifb3_ctrl_pins[] = {
1697 /* SCIFB3_RTS, SCIFB3_CTS */
1698 19, 20,
1699 };
1700 static const unsigned int scifb3_ctrl_mux[] = {
1701 SCIFB3_RTS_19_MARK, SCIFB3_CTS_20_MARK,
1702 };
1703 static const unsigned int scifb3_data_b_pins[] = {
1704 /* SCIFB3_RXD, SCIFB3_TXD */
1705 120, 121,
1706 };
1707 static const unsigned int scifb3_data_b_mux[] = {
1708 SCIFB3_RXD_120_MARK, SCIFB3_TXD_121_MARK,
1709 };
1710 static const unsigned int scifb3_clk_b_pins[] = {
1711 /* SCIFB3_SCK */
1712 40,
1713 };
1714 static const unsigned int scifb3_clk_b_mux[] = {
1715 SCIFB3_SCK_40_MARK,
1716 };
1717 static const unsigned int scifb3_ctrl_b_pins[] = {
1718 /* SCIFB3_RTS, SCIFB3_CTS */
1719 38, 39,
1720 };
1721 static const unsigned int scifb3_ctrl_b_mux[] = {
1722 SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK,
1723 };
1724 /* - SDHI0 ------------------------------------------------------------------ */
1725 static const unsigned int sdhi0_data1_pins[] = {
1726 /* D0 */
1727 302,
1728 };
1729 static const unsigned int sdhi0_data1_mux[] = {
1730 SDHID0_0_MARK,
1731 };
1732 static const unsigned int sdhi0_data4_pins[] = {
1733 /* D[0:3] */
1734 302, 303, 304, 305,
1735 };
1736 static const unsigned int sdhi0_data4_mux[] = {
1737 SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
1738 };
1739 static const unsigned int sdhi0_ctrl_pins[] = {
1740 /* CLK, CMD */
1741 308, 306,
1742 };
1743 static const unsigned int sdhi0_ctrl_mux[] = {
1744 SDHICLK0_MARK, SDHICMD0_MARK,
1745 };
1746 static const unsigned int sdhi0_cd_pins[] = {
1747 /* CD */
1748 301,
1749 };
1750 static const unsigned int sdhi0_cd_mux[] = {
1751 SDHICD0_MARK,
1752 };
1753 static const unsigned int sdhi0_wp_pins[] = {
1754 /* WP */
1755 307,
1756 };
1757 static const unsigned int sdhi0_wp_mux[] = {
1758 SDHIWP0_MARK,
1759 };
1760 /* - SDHI1 ------------------------------------------------------------------ */
1761 static const unsigned int sdhi1_data1_pins[] = {
1762 /* D0 */
1763 289,
1764 };
1765 static const unsigned int sdhi1_data1_mux[] = {
1766 SDHID1_0_MARK,
1767 };
1768 static const unsigned int sdhi1_data4_pins[] = {
1769 /* D[0:3] */
1770 289, 290, 291, 292,
1771 };
1772 static const unsigned int sdhi1_data4_mux[] = {
1773 SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
1774 };
1775 static const unsigned int sdhi1_ctrl_pins[] = {
1776 /* CLK, CMD */
1777 293, 294,
1778 };
1779 static const unsigned int sdhi1_ctrl_mux[] = {
1780 SDHICLK1_MARK, SDHICMD1_MARK,
1781 };
1782 /* - SDHI2 ------------------------------------------------------------------ */
1783 static const unsigned int sdhi2_data1_pins[] = {
1784 /* D0 */
1785 295,
1786 };
1787 static const unsigned int sdhi2_data1_mux[] = {
1788 SDHID2_0_MARK,
1789 };
1790 static const unsigned int sdhi2_data4_pins[] = {
1791 /* D[0:3] */
1792 295, 296, 297, 298,
1793 };
1794 static const unsigned int sdhi2_data4_mux[] = {
1795 SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
1796 };
1797 static const unsigned int sdhi2_ctrl_pins[] = {
1798 /* CLK, CMD */
1799 299, 300,
1800 };
1801 static const unsigned int sdhi2_ctrl_mux[] = {
1802 SDHICLK2_MARK, SDHICMD2_MARK,
1803 };
1804
1805 static const struct sh_pfc_pin_group pinmux_groups[] = {
1806 SH_PFC_PIN_GROUP(irqc_irq0),
1807 SH_PFC_PIN_GROUP(irqc_irq1),
1808 SH_PFC_PIN_GROUP(irqc_irq2),
1809 SH_PFC_PIN_GROUP(irqc_irq3),
1810 SH_PFC_PIN_GROUP(irqc_irq4),
1811 SH_PFC_PIN_GROUP(irqc_irq5),
1812 SH_PFC_PIN_GROUP(irqc_irq6),
1813 SH_PFC_PIN_GROUP(irqc_irq7),
1814 SH_PFC_PIN_GROUP(irqc_irq8),
1815 SH_PFC_PIN_GROUP(irqc_irq9),
1816 SH_PFC_PIN_GROUP(irqc_irq10),
1817 SH_PFC_PIN_GROUP(irqc_irq11),
1818 SH_PFC_PIN_GROUP(irqc_irq12),
1819 SH_PFC_PIN_GROUP(irqc_irq13),
1820 SH_PFC_PIN_GROUP(irqc_irq14),
1821 SH_PFC_PIN_GROUP(irqc_irq15),
1822 SH_PFC_PIN_GROUP(irqc_irq16),
1823 SH_PFC_PIN_GROUP(irqc_irq17),
1824 SH_PFC_PIN_GROUP(irqc_irq18),
1825 SH_PFC_PIN_GROUP(irqc_irq19),
1826 SH_PFC_PIN_GROUP(irqc_irq20),
1827 SH_PFC_PIN_GROUP(irqc_irq21),
1828 SH_PFC_PIN_GROUP(irqc_irq22),
1829 SH_PFC_PIN_GROUP(irqc_irq23),
1830 SH_PFC_PIN_GROUP(irqc_irq24),
1831 SH_PFC_PIN_GROUP(irqc_irq25),
1832 SH_PFC_PIN_GROUP(irqc_irq26),
1833 SH_PFC_PIN_GROUP(irqc_irq27),
1834 SH_PFC_PIN_GROUP(irqc_irq28),
1835 SH_PFC_PIN_GROUP(irqc_irq29),
1836 SH_PFC_PIN_GROUP(irqc_irq30),
1837 SH_PFC_PIN_GROUP(irqc_irq31),
1838 SH_PFC_PIN_GROUP(irqc_irq32),
1839 SH_PFC_PIN_GROUP(irqc_irq33),
1840 SH_PFC_PIN_GROUP(irqc_irq34),
1841 SH_PFC_PIN_GROUP(irqc_irq35),
1842 SH_PFC_PIN_GROUP(irqc_irq36),
1843 SH_PFC_PIN_GROUP(irqc_irq37),
1844 SH_PFC_PIN_GROUP(irqc_irq38),
1845 SH_PFC_PIN_GROUP(irqc_irq39),
1846 SH_PFC_PIN_GROUP(irqc_irq40),
1847 SH_PFC_PIN_GROUP(irqc_irq41),
1848 SH_PFC_PIN_GROUP(irqc_irq42),
1849 SH_PFC_PIN_GROUP(irqc_irq43),
1850 SH_PFC_PIN_GROUP(irqc_irq44),
1851 SH_PFC_PIN_GROUP(irqc_irq45),
1852 SH_PFC_PIN_GROUP(irqc_irq46),
1853 SH_PFC_PIN_GROUP(irqc_irq47),
1854 SH_PFC_PIN_GROUP(irqc_irq48),
1855 SH_PFC_PIN_GROUP(irqc_irq49),
1856 SH_PFC_PIN_GROUP(irqc_irq50),
1857 SH_PFC_PIN_GROUP(irqc_irq51),
1858 SH_PFC_PIN_GROUP(irqc_irq52),
1859 SH_PFC_PIN_GROUP(irqc_irq53),
1860 SH_PFC_PIN_GROUP(irqc_irq54),
1861 SH_PFC_PIN_GROUP(irqc_irq55),
1862 SH_PFC_PIN_GROUP(irqc_irq56),
1863 SH_PFC_PIN_GROUP(irqc_irq57),
1864 SH_PFC_PIN_GROUP(mmc0_data1),
1865 SH_PFC_PIN_GROUP(mmc0_data4),
1866 SH_PFC_PIN_GROUP(mmc0_data8),
1867 SH_PFC_PIN_GROUP(mmc0_ctrl),
1868 SH_PFC_PIN_GROUP(mmc1_data1),
1869 SH_PFC_PIN_GROUP(mmc1_data4),
1870 SH_PFC_PIN_GROUP(mmc1_data8),
1871 SH_PFC_PIN_GROUP(mmc1_ctrl),
1872 SH_PFC_PIN_GROUP(scifa0_data),
1873 SH_PFC_PIN_GROUP(scifa0_clk),
1874 SH_PFC_PIN_GROUP(scifa0_ctrl),
1875 SH_PFC_PIN_GROUP(scifa1_data),
1876 SH_PFC_PIN_GROUP(scifa1_clk),
1877 SH_PFC_PIN_GROUP(scifa1_ctrl),
1878 SH_PFC_PIN_GROUP(scifb0_data),
1879 SH_PFC_PIN_GROUP(scifb0_clk),
1880 SH_PFC_PIN_GROUP(scifb0_ctrl),
1881 SH_PFC_PIN_GROUP(scifb1_data),
1882 SH_PFC_PIN_GROUP(scifb1_clk),
1883 SH_PFC_PIN_GROUP(scifb1_ctrl),
1884 SH_PFC_PIN_GROUP(scifb1_data_b),
1885 SH_PFC_PIN_GROUP(scifb1_clk_b),
1886 SH_PFC_PIN_GROUP(scifb1_ctrl_b),
1887 SH_PFC_PIN_GROUP(scifb2_data),
1888 SH_PFC_PIN_GROUP(scifb2_clk),
1889 SH_PFC_PIN_GROUP(scifb2_ctrl),
1890 SH_PFC_PIN_GROUP(scifb2_data_b),
1891 SH_PFC_PIN_GROUP(scifb2_clk_b),
1892 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
1893 SH_PFC_PIN_GROUP(scifb3_data),
1894 SH_PFC_PIN_GROUP(scifb3_clk),
1895 SH_PFC_PIN_GROUP(scifb3_ctrl),
1896 SH_PFC_PIN_GROUP(scifb3_data_b),
1897 SH_PFC_PIN_GROUP(scifb3_clk_b),
1898 SH_PFC_PIN_GROUP(scifb3_ctrl_b),
1899 SH_PFC_PIN_GROUP(sdhi0_data1),
1900 SH_PFC_PIN_GROUP(sdhi0_data4),
1901 SH_PFC_PIN_GROUP(sdhi0_ctrl),
1902 SH_PFC_PIN_GROUP(sdhi0_cd),
1903 SH_PFC_PIN_GROUP(sdhi0_wp),
1904 SH_PFC_PIN_GROUP(sdhi1_data1),
1905 SH_PFC_PIN_GROUP(sdhi1_data4),
1906 SH_PFC_PIN_GROUP(sdhi1_ctrl),
1907 SH_PFC_PIN_GROUP(sdhi2_data1),
1908 SH_PFC_PIN_GROUP(sdhi2_data4),
1909 SH_PFC_PIN_GROUP(sdhi2_ctrl),
1910 };
1911
1912 static const char * const irqc_groups[] = {
1913 "irqc_irq0",
1914 "irqc_irq1",
1915 "irqc_irq2",
1916 "irqc_irq3",
1917 "irqc_irq4",
1918 "irqc_irq5",
1919 "irqc_irq6",
1920 "irqc_irq7",
1921 "irqc_irq8",
1922 "irqc_irq9",
1923 "irqc_irq10",
1924 "irqc_irq11",
1925 "irqc_irq12",
1926 "irqc_irq13",
1927 "irqc_irq14",
1928 "irqc_irq15",
1929 "irqc_irq16",
1930 "irqc_irq17",
1931 "irqc_irq18",
1932 "irqc_irq19",
1933 "irqc_irq20",
1934 "irqc_irq21",
1935 "irqc_irq22",
1936 "irqc_irq23",
1937 "irqc_irq24",
1938 "irqc_irq25",
1939 "irqc_irq26",
1940 "irqc_irq27",
1941 "irqc_irq28",
1942 "irqc_irq29",
1943 "irqc_irq30",
1944 "irqc_irq31",
1945 "irqc_irq32",
1946 "irqc_irq33",
1947 "irqc_irq34",
1948 "irqc_irq35",
1949 "irqc_irq36",
1950 "irqc_irq37",
1951 "irqc_irq38",
1952 "irqc_irq39",
1953 "irqc_irq40",
1954 "irqc_irq41",
1955 "irqc_irq42",
1956 "irqc_irq43",
1957 "irqc_irq44",
1958 "irqc_irq45",
1959 "irqc_irq46",
1960 "irqc_irq47",
1961 "irqc_irq48",
1962 "irqc_irq49",
1963 "irqc_irq50",
1964 "irqc_irq51",
1965 "irqc_irq52",
1966 "irqc_irq53",
1967 "irqc_irq54",
1968 "irqc_irq55",
1969 "irqc_irq56",
1970 "irqc_irq57",
1971 };
1972
1973 static const char * const mmc0_groups[] = {
1974 "mmc0_data1",
1975 "mmc0_data4",
1976 "mmc0_data8",
1977 "mmc0_ctrl",
1978 };
1979
1980 static const char * const mmc1_groups[] = {
1981 "mmc1_data1",
1982 "mmc1_data4",
1983 "mmc1_data8",
1984 "mmc1_ctrl",
1985 };
1986
1987 static const char * const scifa0_groups[] = {
1988 "scifa0_data",
1989 "scifa0_clk",
1990 "scifa0_ctrl",
1991 };
1992
1993 static const char * const scifa1_groups[] = {
1994 "scifa1_data",
1995 "scifa1_clk",
1996 "scifa1_ctrl",
1997 };
1998
1999 static const char * const scifb0_groups[] = {
2000 "scifb0_data",
2001 "scifb0_clk",
2002 "scifb0_ctrl",
2003 };
2004
2005 static const char * const scifb1_groups[] = {
2006 "scifb1_data",
2007 "scifb1_clk",
2008 "scifb1_ctrl",
2009 "scifb1_data_b",
2010 "scifb1_clk_b",
2011 "scifb1_ctrl_b",
2012 };
2013
2014 static const char * const scifb2_groups[] = {
2015 "scifb2_data",
2016 "scifb2_clk",
2017 "scifb2_ctrl",
2018 "scifb2_data_b",
2019 "scifb2_clk_b",
2020 "scifb2_ctrl_b",
2021 };
2022
2023 static const char * const scifb3_groups[] = {
2024 "scifb3_data",
2025 "scifb3_clk",
2026 "scifb3_ctrl",
2027 "scifb3_data_b",
2028 "scifb3_clk_b",
2029 "scifb3_ctrl_b",
2030 };
2031
2032 static const char * const sdhi0_groups[] = {
2033 "sdhi0_data1",
2034 "sdhi0_data4",
2035 "sdhi0_ctrl",
2036 "sdhi0_cd",
2037 "sdhi0_wp",
2038 };
2039
2040 static const char * const sdhi1_groups[] = {
2041 "sdhi1_data1",
2042 "sdhi1_data4",
2043 "sdhi1_ctrl",
2044 };
2045
2046 static const char * const sdhi2_groups[] = {
2047 "sdhi2_data1",
2048 "sdhi2_data4",
2049 "sdhi2_ctrl",
2050 };
2051
2052 static const struct sh_pfc_function pinmux_functions[] = {
2053 SH_PFC_FUNCTION(irqc),
2054 SH_PFC_FUNCTION(mmc0),
2055 SH_PFC_FUNCTION(mmc1),
2056 SH_PFC_FUNCTION(scifa0),
2057 SH_PFC_FUNCTION(scifa1),
2058 SH_PFC_FUNCTION(scifb0),
2059 SH_PFC_FUNCTION(scifb1),
2060 SH_PFC_FUNCTION(scifb2),
2061 SH_PFC_FUNCTION(scifb3),
2062 SH_PFC_FUNCTION(sdhi0),
2063 SH_PFC_FUNCTION(sdhi1),
2064 SH_PFC_FUNCTION(sdhi2),
2065 };
2066
2067 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2068 PORTCR(0, 0xe6050000),
2069 PORTCR(1, 0xe6050001),
2070 PORTCR(2, 0xe6050002),
2071 PORTCR(3, 0xe6050003),
2072 PORTCR(4, 0xe6050004),
2073 PORTCR(5, 0xe6050005),
2074 PORTCR(6, 0xe6050006),
2075 PORTCR(7, 0xe6050007),
2076 PORTCR(8, 0xe6050008),
2077 PORTCR(9, 0xe6050009),
2078 PORTCR(10, 0xe605000A),
2079 PORTCR(11, 0xe605000B),
2080 PORTCR(12, 0xe605000C),
2081 PORTCR(13, 0xe605000D),
2082 PORTCR(14, 0xe605000E),
2083 PORTCR(15, 0xe605000F),
2084 PORTCR(16, 0xe6050010),
2085 PORTCR(17, 0xe6050011),
2086 PORTCR(18, 0xe6050012),
2087 PORTCR(19, 0xe6050013),
2088 PORTCR(20, 0xe6050014),
2089 PORTCR(21, 0xe6050015),
2090 PORTCR(22, 0xe6050016),
2091 PORTCR(23, 0xe6050017),
2092 PORTCR(24, 0xe6050018),
2093 PORTCR(25, 0xe6050019),
2094 PORTCR(26, 0xe605001A),
2095 PORTCR(27, 0xe605001B),
2096 PORTCR(28, 0xe605001C),
2097 PORTCR(29, 0xe605001D),
2098 PORTCR(30, 0xe605001E),
2099 PORTCR(32, 0xe6051020),
2100 PORTCR(33, 0xe6051021),
2101 PORTCR(34, 0xe6051022),
2102 PORTCR(35, 0xe6051023),
2103 PORTCR(36, 0xe6051024),
2104 PORTCR(37, 0xe6051025),
2105 PORTCR(38, 0xe6051026),
2106 PORTCR(39, 0xe6051027),
2107 PORTCR(40, 0xe6051028),
2108 PORTCR(64, 0xe6050040),
2109 PORTCR(65, 0xe6050041),
2110 PORTCR(66, 0xe6050042),
2111 PORTCR(67, 0xe6050043),
2112 PORTCR(68, 0xe6050044),
2113 PORTCR(69, 0xe6050045),
2114 PORTCR(70, 0xe6050046),
2115 PORTCR(71, 0xe6050047),
2116 PORTCR(72, 0xe6050048),
2117 PORTCR(73, 0xe6050049),
2118 PORTCR(74, 0xe605004A),
2119 PORTCR(75, 0xe605004B),
2120 PORTCR(76, 0xe605004C),
2121 PORTCR(77, 0xe605004D),
2122 PORTCR(78, 0xe605004E),
2123 PORTCR(79, 0xe605004F),
2124 PORTCR(80, 0xe6050050),
2125 PORTCR(81, 0xe6050051),
2126 PORTCR(82, 0xe6050052),
2127 PORTCR(83, 0xe6050053),
2128 PORTCR(84, 0xe6050054),
2129 PORTCR(85, 0xe6050055),
2130 PORTCR(96, 0xe6051060),
2131 PORTCR(97, 0xe6051061),
2132 PORTCR(98, 0xe6051062),
2133 PORTCR(99, 0xe6051063),
2134 PORTCR(100, 0xe6051064),
2135 PORTCR(101, 0xe6051065),
2136 PORTCR(102, 0xe6051066),
2137 PORTCR(103, 0xe6051067),
2138 PORTCR(104, 0xe6051068),
2139 PORTCR(105, 0xe6051069),
2140 PORTCR(106, 0xe605106A),
2141 PORTCR(107, 0xe605106B),
2142 PORTCR(108, 0xe605106C),
2143 PORTCR(109, 0xe605106D),
2144 PORTCR(110, 0xe605106E),
2145 PORTCR(111, 0xe605106F),
2146 PORTCR(112, 0xe6051070),
2147 PORTCR(113, 0xe6051071),
2148 PORTCR(114, 0xe6051072),
2149 PORTCR(115, 0xe6051073),
2150 PORTCR(116, 0xe6051074),
2151 PORTCR(117, 0xe6051075),
2152 PORTCR(118, 0xe6051076),
2153 PORTCR(119, 0xe6051077),
2154 PORTCR(120, 0xe6051078),
2155 PORTCR(121, 0xe6051079),
2156 PORTCR(122, 0xe605107A),
2157 PORTCR(123, 0xe605107B),
2158 PORTCR(124, 0xe605107C),
2159 PORTCR(125, 0xe605107D),
2160 PORTCR(126, 0xe605107E),
2161 PORTCR(128, 0xe6051080),
2162 PORTCR(129, 0xe6051081),
2163 PORTCR(130, 0xe6051082),
2164 PORTCR(131, 0xe6051083),
2165 PORTCR(132, 0xe6051084),
2166 PORTCR(133, 0xe6051085),
2167 PORTCR(134, 0xe6051086),
2168 PORTCR(160, 0xe60520A0),
2169 PORTCR(161, 0xe60520A1),
2170 PORTCR(162, 0xe60520A2),
2171 PORTCR(163, 0xe60520A3),
2172 PORTCR(164, 0xe60520A4),
2173 PORTCR(165, 0xe60520A5),
2174 PORTCR(166, 0xe60520A6),
2175 PORTCR(167, 0xe60520A7),
2176 PORTCR(168, 0xe60520A8),
2177 PORTCR(169, 0xe60520A9),
2178 PORTCR(170, 0xe60520AA),
2179 PORTCR(171, 0xe60520AB),
2180 PORTCR(172, 0xe60520AC),
2181 PORTCR(173, 0xe60520AD),
2182 PORTCR(174, 0xe60520AE),
2183 PORTCR(175, 0xe60520AF),
2184 PORTCR(176, 0xe60520B0),
2185 PORTCR(177, 0xe60520B1),
2186 PORTCR(178, 0xe60520B2),
2187 PORTCR(192, 0xe60520C0),
2188 PORTCR(193, 0xe60520C1),
2189 PORTCR(194, 0xe60520C2),
2190 PORTCR(195, 0xe60520C3),
2191 PORTCR(196, 0xe60520C4),
2192 PORTCR(197, 0xe60520C5),
2193 PORTCR(198, 0xe60520C6),
2194 PORTCR(199, 0xe60520C7),
2195 PORTCR(200, 0xe60520C8),
2196 PORTCR(201, 0xe60520C9),
2197 PORTCR(202, 0xe60520CA),
2198 PORTCR(203, 0xe60520CB),
2199 PORTCR(204, 0xe60520CC),
2200 PORTCR(205, 0xe60520CD),
2201 PORTCR(206, 0xe60520CE),
2202 PORTCR(207, 0xe60520CF),
2203 PORTCR(208, 0xe60520D0),
2204 PORTCR(209, 0xe60520D1),
2205 PORTCR(210, 0xe60520D2),
2206 PORTCR(211, 0xe60520D3),
2207 PORTCR(212, 0xe60520D4),
2208 PORTCR(213, 0xe60520D5),
2209 PORTCR(214, 0xe60520D6),
2210 PORTCR(215, 0xe60520D7),
2211 PORTCR(216, 0xe60520D8),
2212 PORTCR(217, 0xe60520D9),
2213 PORTCR(218, 0xe60520DA),
2214 PORTCR(219, 0xe60520DB),
2215 PORTCR(220, 0xe60520DC),
2216 PORTCR(221, 0xe60520DD),
2217 PORTCR(222, 0xe60520DE),
2218 PORTCR(224, 0xe60520E0),
2219 PORTCR(225, 0xe60520E1),
2220 PORTCR(226, 0xe60520E2),
2221 PORTCR(227, 0xe60520E3),
2222 PORTCR(228, 0xe60520E4),
2223 PORTCR(229, 0xe60520E5),
2224 PORTCR(230, 0xe60520e6),
2225 PORTCR(231, 0xe60520E7),
2226 PORTCR(232, 0xe60520E8),
2227 PORTCR(233, 0xe60520E9),
2228 PORTCR(234, 0xe60520EA),
2229 PORTCR(235, 0xe60520EB),
2230 PORTCR(236, 0xe60520EC),
2231 PORTCR(237, 0xe60520ED),
2232 PORTCR(238, 0xe60520EE),
2233 PORTCR(239, 0xe60520EF),
2234 PORTCR(240, 0xe60520F0),
2235 PORTCR(241, 0xe60520F1),
2236 PORTCR(242, 0xe60520F2),
2237 PORTCR(243, 0xe60520F3),
2238 PORTCR(244, 0xe60520F4),
2239 PORTCR(245, 0xe60520F5),
2240 PORTCR(246, 0xe60520F6),
2241 PORTCR(247, 0xe60520F7),
2242 PORTCR(248, 0xe60520F8),
2243 PORTCR(249, 0xe60520F9),
2244 PORTCR(250, 0xe60520FA),
2245 PORTCR(256, 0xe6052100),
2246 PORTCR(257, 0xe6052101),
2247 PORTCR(258, 0xe6052102),
2248 PORTCR(259, 0xe6052103),
2249 PORTCR(260, 0xe6052104),
2250 PORTCR(261, 0xe6052105),
2251 PORTCR(262, 0xe6052106),
2252 PORTCR(263, 0xe6052107),
2253 PORTCR(264, 0xe6052108),
2254 PORTCR(265, 0xe6052109),
2255 PORTCR(266, 0xe605210A),
2256 PORTCR(267, 0xe605210B),
2257 PORTCR(268, 0xe605210C),
2258 PORTCR(269, 0xe605210D),
2259 PORTCR(270, 0xe605210E),
2260 PORTCR(271, 0xe605210F),
2261 PORTCR(272, 0xe6052110),
2262 PORTCR(273, 0xe6052111),
2263 PORTCR(274, 0xe6052112),
2264 PORTCR(275, 0xe6052113),
2265 PORTCR(276, 0xe6052114),
2266 PORTCR(277, 0xe6052115),
2267 PORTCR(278, 0xe6052116),
2268 PORTCR(279, 0xe6052117),
2269 PORTCR(280, 0xe6052118),
2270 PORTCR(281, 0xe6052119),
2271 PORTCR(282, 0xe605211A),
2272 PORTCR(283, 0xe605211B),
2273 PORTCR(288, 0xe6053120),
2274 PORTCR(289, 0xe6053121),
2275 PORTCR(290, 0xe6053122),
2276 PORTCR(291, 0xe6053123),
2277 PORTCR(292, 0xe6053124),
2278 PORTCR(293, 0xe6053125),
2279 PORTCR(294, 0xe6053126),
2280 PORTCR(295, 0xe6053127),
2281 PORTCR(296, 0xe6053128),
2282 PORTCR(297, 0xe6053129),
2283 PORTCR(298, 0xe605312A),
2284 PORTCR(299, 0xe605312B),
2285 PORTCR(300, 0xe605312C),
2286 PORTCR(301, 0xe605312D),
2287 PORTCR(302, 0xe605312E),
2288 PORTCR(303, 0xe605312F),
2289 PORTCR(304, 0xe6053130),
2290 PORTCR(305, 0xe6053131),
2291 PORTCR(306, 0xe6053132),
2292 PORTCR(307, 0xe6053133),
2293 PORTCR(308, 0xe6053134),
2294 PORTCR(320, 0xe6053140),
2295 PORTCR(321, 0xe6053141),
2296 PORTCR(322, 0xe6053142),
2297 PORTCR(323, 0xe6053143),
2298 PORTCR(324, 0xe6053144),
2299 PORTCR(325, 0xe6053145),
2300 PORTCR(326, 0xe6053146),
2301 PORTCR(327, 0xe6053147),
2302 PORTCR(328, 0xe6053148),
2303 PORTCR(329, 0xe6053149),
2304
2305 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
2306 MSEL1CR_31_0, MSEL1CR_31_1,
2307 0, 0,
2308 0, 0,
2309 0, 0,
2310 MSEL1CR_27_0, MSEL1CR_27_1,
2311 0, 0,
2312 MSEL1CR_25_0, MSEL1CR_25_1,
2313 MSEL1CR_24_0, MSEL1CR_24_1,
2314 0, 0,
2315 MSEL1CR_22_0, MSEL1CR_22_1,
2316 MSEL1CR_21_0, MSEL1CR_21_1,
2317 MSEL1CR_20_0, MSEL1CR_20_1,
2318 MSEL1CR_19_0, MSEL1CR_19_1,
2319 MSEL1CR_18_0, MSEL1CR_18_1,
2320 MSEL1CR_17_0, MSEL1CR_17_1,
2321 MSEL1CR_16_0, MSEL1CR_16_1,
2322 MSEL1CR_15_0, MSEL1CR_15_1,
2323 MSEL1CR_14_0, MSEL1CR_14_1,
2324 MSEL1CR_13_0, MSEL1CR_13_1,
2325 MSEL1CR_12_0, MSEL1CR_12_1,
2326 MSEL1CR_11_0, MSEL1CR_11_1,
2327 MSEL1CR_10_0, MSEL1CR_10_1,
2328 MSEL1CR_09_0, MSEL1CR_09_1,
2329 MSEL1CR_08_0, MSEL1CR_08_1,
2330 MSEL1CR_07_0, MSEL1CR_07_1,
2331 MSEL1CR_06_0, MSEL1CR_06_1,
2332 MSEL1CR_05_0, MSEL1CR_05_1,
2333 MSEL1CR_04_0, MSEL1CR_04_1,
2334 MSEL1CR_03_0, MSEL1CR_03_1,
2335 MSEL1CR_02_0, MSEL1CR_02_1,
2336 MSEL1CR_01_0, MSEL1CR_01_1,
2337 MSEL1CR_00_0, MSEL1CR_00_1,
2338 }
2339 },
2340 { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
2341 MSEL3CR_31_0, MSEL3CR_31_1,
2342 0, 0,
2343 0, 0,
2344 MSEL3CR_28_0, MSEL3CR_28_1,
2345 MSEL3CR_27_0, MSEL3CR_27_1,
2346 MSEL3CR_26_0, MSEL3CR_26_1,
2347 0, 0,
2348 0, 0,
2349 MSEL3CR_23_0, MSEL3CR_23_1,
2350 MSEL3CR_22_0, MSEL3CR_22_1,
2351 MSEL3CR_21_0, MSEL3CR_21_1,
2352 MSEL3CR_20_0, MSEL3CR_20_1,
2353 MSEL3CR_19_0, MSEL3CR_19_1,
2354 MSEL3CR_18_0, MSEL3CR_18_1,
2355 MSEL3CR_17_0, MSEL3CR_17_1,
2356 MSEL3CR_16_0, MSEL3CR_16_1,
2357 MSEL3CR_15_0, MSEL3CR_15_1,
2358 0, 0,
2359 0, 0,
2360 MSEL3CR_12_0, MSEL3CR_12_1,
2361 MSEL3CR_11_0, MSEL3CR_11_1,
2362 MSEL3CR_10_0, MSEL3CR_10_1,
2363 MSEL3CR_09_0, MSEL3CR_09_1,
2364 0, 0,
2365 0, 0,
2366 MSEL3CR_06_0, MSEL3CR_06_1,
2367 0, 0,
2368 0, 0,
2369 MSEL3CR_03_0, MSEL3CR_03_1,
2370 0, 0,
2371 MSEL3CR_01_0, MSEL3CR_01_1,
2372 MSEL3CR_00_0, MSEL3CR_00_1,
2373 }
2374 },
2375 { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
2376 0, 0,
2377 MSEL4CR_30_0, MSEL4CR_30_1,
2378 MSEL4CR_29_0, MSEL4CR_29_1,
2379 MSEL4CR_28_0, MSEL4CR_28_1,
2380 MSEL4CR_27_0, MSEL4CR_27_1,
2381 MSEL4CR_26_0, MSEL4CR_26_1,
2382 MSEL4CR_25_0, MSEL4CR_25_1,
2383 MSEL4CR_24_0, MSEL4CR_24_1,
2384 MSEL4CR_23_0, MSEL4CR_23_1,
2385 MSEL4CR_22_0, MSEL4CR_22_1,
2386 MSEL4CR_21_0, MSEL4CR_21_1,
2387 MSEL4CR_20_0, MSEL4CR_20_1,
2388 MSEL4CR_19_0, MSEL4CR_19_1,
2389 MSEL4CR_18_0, MSEL4CR_18_1,
2390 MSEL4CR_17_0, MSEL4CR_17_1,
2391 MSEL4CR_16_0, MSEL4CR_16_1,
2392 MSEL4CR_15_0, MSEL4CR_15_1,
2393 MSEL4CR_14_0, MSEL4CR_14_1,
2394 MSEL4CR_13_0, MSEL4CR_13_1,
2395 MSEL4CR_12_0, MSEL4CR_12_1,
2396 MSEL4CR_11_0, MSEL4CR_11_1,
2397 MSEL4CR_10_0, MSEL4CR_10_1,
2398 MSEL4CR_09_0, MSEL4CR_09_1,
2399 0, 0,
2400 MSEL4CR_07_0, MSEL4CR_07_1,
2401 0, 0,
2402 0, 0,
2403 MSEL4CR_04_0, MSEL4CR_04_1,
2404 0, 0,
2405 0, 0,
2406 MSEL4CR_01_0, MSEL4CR_01_1,
2407 0, 0,
2408 }
2409 },
2410 { PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1) {
2411 MSEL5CR_31_0, MSEL5CR_31_1,
2412 MSEL5CR_30_0, MSEL5CR_30_1,
2413 MSEL5CR_29_0, MSEL5CR_29_1,
2414 MSEL5CR_28_0, MSEL5CR_28_1,
2415 MSEL5CR_27_0, MSEL5CR_27_1,
2416 MSEL5CR_26_0, MSEL5CR_26_1,
2417 MSEL5CR_25_0, MSEL5CR_25_1,
2418 MSEL5CR_24_0, MSEL5CR_24_1,
2419 MSEL5CR_23_0, MSEL5CR_23_1,
2420 MSEL5CR_22_0, MSEL5CR_22_1,
2421 MSEL5CR_21_0, MSEL5CR_21_1,
2422 MSEL5CR_20_0, MSEL5CR_20_1,
2423 MSEL5CR_19_0, MSEL5CR_19_1,
2424 MSEL5CR_18_0, MSEL5CR_18_1,
2425 MSEL5CR_17_0, MSEL5CR_17_1,
2426 MSEL5CR_16_0, MSEL5CR_16_1,
2427 MSEL5CR_15_0, MSEL5CR_15_1,
2428 MSEL5CR_14_0, MSEL5CR_14_1,
2429 MSEL5CR_13_0, MSEL5CR_13_1,
2430 MSEL5CR_12_0, MSEL5CR_12_1,
2431 MSEL5CR_11_0, MSEL5CR_11_1,
2432 MSEL5CR_10_0, MSEL5CR_10_1,
2433 MSEL5CR_09_0, MSEL5CR_09_1,
2434 MSEL5CR_08_0, MSEL5CR_08_1,
2435 MSEL5CR_07_0, MSEL5CR_07_1,
2436 MSEL5CR_06_0, MSEL5CR_06_1,
2437 0, 0,
2438 0, 0,
2439 0, 0,
2440 0, 0,
2441 0, 0,
2442 0, 0,
2443 }
2444 },
2445 { PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1) {
2446 0, 0,
2447 0, 0,
2448 0, 0,
2449 0, 0,
2450 0, 0,
2451 0, 0,
2452 0, 0,
2453 0, 0,
2454 0, 0,
2455 0, 0,
2456 0, 0,
2457 0, 0,
2458 0, 0,
2459 0, 0,
2460 0, 0,
2461 MSEL8CR_16_0, MSEL8CR_16_1,
2462 0, 0,
2463 0, 0,
2464 0, 0,
2465 0, 0,
2466 0, 0,
2467 0, 0,
2468 0, 0,
2469 0, 0,
2470 0, 0,
2471 0, 0,
2472 0, 0,
2473 0, 0,
2474 0, 0,
2475 0, 0,
2476 MSEL8CR_01_0, MSEL8CR_01_1,
2477 MSEL8CR_00_0, MSEL8CR_00_1,
2478 }
2479 },
2480 { },
2481 };
2482
2483 static const struct pinmux_data_reg pinmux_data_regs[] = {
2484
2485 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
2486 0, PORT30_DATA, PORT29_DATA, PORT28_DATA,
2487 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
2488 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
2489 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
2490 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
2491 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
2492 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
2493 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA,
2494 }
2495 },
2496 { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
2497 0, 0, 0, 0,
2498 0, 0, 0, 0,
2499 0, 0, 0, 0,
2500 0, 0, 0, 0,
2501 0, 0, 0, 0,
2502 0, 0, 0, PORT40_DATA,
2503 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
2504 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
2505 }
2506 },
2507 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32) {
2508 0, 0, 0, 0,
2509 0, 0, 0, 0,
2510 0, 0, PORT85_DATA, PORT84_DATA,
2511 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
2512 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
2513 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
2514 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
2515 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
2516 }
2517 },
2518 { PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) {
2519 0, PORT126_DATA, PORT125_DATA, PORT124_DATA,
2520 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
2521 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
2522 PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
2523 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
2524 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
2525 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
2526 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA,
2527 }
2528 },
2529 { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) {
2530 0, 0, 0, 0,
2531 0, 0, 0, 0,
2532 0, 0, 0, 0,
2533 0, 0, 0, 0,
2534 0, 0, 0, 0,
2535 0, 0, 0, 0,
2536 0, PORT134_DATA, PORT133_DATA, PORT132_DATA,
2537 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
2538 }
2539 },
2540 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) {
2541 0, 0, 0, 0,
2542 0, 0, 0, 0,
2543 0, 0, 0, 0,
2544 0, PORT178_DATA, PORT177_DATA, PORT176_DATA,
2545 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
2546 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
2547 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
2548 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
2549 }
2550 },
2551 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) {
2552 0, PORT222_DATA, PORT221_DATA, PORT220_DATA,
2553 PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
2554 PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
2555 PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
2556 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
2557 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
2558 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
2559 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA,
2560 }
2561 },
2562 { PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32) {
2563 0, 0, 0, 0,
2564 0, PORT250_DATA, PORT249_DATA, PORT248_DATA,
2565 PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
2566 PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
2567 PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
2568 PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
2569 PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
2570 PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA,
2571 }
2572 },
2573 { PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32) {
2574 0, 0, 0, 0,
2575 PORT283_DATA, PORT282_DATA, PORT281_DATA, PORT280_DATA,
2576 PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
2577 PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
2578 PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
2579 PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
2580 PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
2581 PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA,
2582 }
2583 },
2584 { PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32) {
2585 0, 0, 0, 0,
2586 0, 0, 0, 0,
2587 0, 0, 0, PORT308_DATA,
2588 PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
2589 PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
2590 PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
2591 PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
2592 PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA,
2593 }
2594 },
2595 { PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32) {
2596 0, 0, 0, 0,
2597 0, 0, 0, 0,
2598 0, 0, 0, 0,
2599 0, 0, 0, 0,
2600 0, 0, 0, 0,
2601 0, 0, PORT329_DATA, PORT328_DATA,
2602 PORT327_DATA, PORT326_DATA, PORT325_DATA, PORT324_DATA,
2603 PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA,
2604 }
2605 },
2606 { },
2607 };
2608
2609 static const struct pinmux_irq pinmux_irqs[] = {
2610 PINMUX_IRQ(irq_pin(0), 0),
2611 PINMUX_IRQ(irq_pin(1), 1),
2612 PINMUX_IRQ(irq_pin(2), 2),
2613 PINMUX_IRQ(irq_pin(3), 3),
2614 PINMUX_IRQ(irq_pin(4), 4),
2615 PINMUX_IRQ(irq_pin(5), 5),
2616 PINMUX_IRQ(irq_pin(6), 6),
2617 PINMUX_IRQ(irq_pin(7), 7),
2618 PINMUX_IRQ(irq_pin(8), 8),
2619 PINMUX_IRQ(irq_pin(9), 9),
2620 PINMUX_IRQ(irq_pin(10), 10),
2621 PINMUX_IRQ(irq_pin(11), 11),
2622 PINMUX_IRQ(irq_pin(12), 12),
2623 PINMUX_IRQ(irq_pin(13), 13),
2624 PINMUX_IRQ(irq_pin(14), 14),
2625 PINMUX_IRQ(irq_pin(15), 15),
2626 PINMUX_IRQ(irq_pin(16), 320),
2627 PINMUX_IRQ(irq_pin(17), 321),
2628 PINMUX_IRQ(irq_pin(18), 85),
2629 PINMUX_IRQ(irq_pin(19), 84),
2630 PINMUX_IRQ(irq_pin(20), 160),
2631 PINMUX_IRQ(irq_pin(21), 161),
2632 PINMUX_IRQ(irq_pin(22), 162),
2633 PINMUX_IRQ(irq_pin(23), 163),
2634 PINMUX_IRQ(irq_pin(24), 175),
2635 PINMUX_IRQ(irq_pin(25), 176),
2636 PINMUX_IRQ(irq_pin(26), 177),
2637 PINMUX_IRQ(irq_pin(27), 178),
2638 PINMUX_IRQ(irq_pin(28), 322),
2639 PINMUX_IRQ(irq_pin(29), 323),
2640 PINMUX_IRQ(irq_pin(30), 324),
2641 PINMUX_IRQ(irq_pin(31), 192),
2642 PINMUX_IRQ(irq_pin(32), 193),
2643 PINMUX_IRQ(irq_pin(33), 194),
2644 PINMUX_IRQ(irq_pin(34), 195),
2645 PINMUX_IRQ(irq_pin(35), 196),
2646 PINMUX_IRQ(irq_pin(36), 197),
2647 PINMUX_IRQ(irq_pin(37), 198),
2648 PINMUX_IRQ(irq_pin(38), 199),
2649 PINMUX_IRQ(irq_pin(39), 200),
2650 PINMUX_IRQ(irq_pin(40), 66),
2651 PINMUX_IRQ(irq_pin(41), 102),
2652 PINMUX_IRQ(irq_pin(42), 103),
2653 PINMUX_IRQ(irq_pin(43), 109),
2654 PINMUX_IRQ(irq_pin(44), 110),
2655 PINMUX_IRQ(irq_pin(45), 111),
2656 PINMUX_IRQ(irq_pin(46), 112),
2657 PINMUX_IRQ(irq_pin(47), 113),
2658 PINMUX_IRQ(irq_pin(48), 114),
2659 PINMUX_IRQ(irq_pin(49), 115),
2660 PINMUX_IRQ(irq_pin(50), 301),
2661 PINMUX_IRQ(irq_pin(51), 290),
2662 PINMUX_IRQ(irq_pin(52), 296),
2663 PINMUX_IRQ(irq_pin(53), 325),
2664 PINMUX_IRQ(irq_pin(54), 326),
2665 PINMUX_IRQ(irq_pin(55), 327),
2666 PINMUX_IRQ(irq_pin(56), 328),
2667 PINMUX_IRQ(irq_pin(57), 329),
2668 };
2669
2670 #define PORTCR_PULMD_OFF (0 << 6)
2671 #define PORTCR_PULMD_DOWN (2 << 6)
2672 #define PORTCR_PULMD_UP (3 << 6)
2673 #define PORTCR_PULMD_MASK (3 << 6)
2674
2675 static const unsigned int r8a73a4_portcr_offsets[] = {
2676 0x00000000, 0x00001000, 0x00000000, 0x00001000,
2677 0x00001000, 0x00002000, 0x00002000, 0x00002000,
2678 0x00002000, 0x00003000, 0x00003000,
2679 };
2680
2681 static unsigned int r8a73a4_pinmux_get_bias(struct sh_pfc *pfc,
2682 unsigned int pin)
2683 {
2684 void __iomem *addr;
2685
2686 addr = pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
2687
2688 switch (ioread8(addr) & PORTCR_PULMD_MASK) {
2689 case PORTCR_PULMD_UP:
2690 return PIN_CONFIG_BIAS_PULL_UP;
2691 case PORTCR_PULMD_DOWN:
2692 return PIN_CONFIG_BIAS_PULL_DOWN;
2693 case PORTCR_PULMD_OFF:
2694 default:
2695 return PIN_CONFIG_BIAS_DISABLE;
2696 }
2697 }
2698
2699 static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
2700 unsigned int bias)
2701 {
2702 void __iomem *addr;
2703 u32 value;
2704
2705 addr = pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
2706 value = ioread8(addr) & ~PORTCR_PULMD_MASK;
2707
2708 switch (bias) {
2709 case PIN_CONFIG_BIAS_PULL_UP:
2710 value |= PORTCR_PULMD_UP;
2711 break;
2712 case PIN_CONFIG_BIAS_PULL_DOWN:
2713 value |= PORTCR_PULMD_DOWN;
2714 break;
2715 }
2716
2717 iowrite8(value, addr);
2718 }
2719
2720 static const struct sh_pfc_soc_operations r8a73a4_pinmux_ops = {
2721 .get_bias = r8a73a4_pinmux_get_bias,
2722 .set_bias = r8a73a4_pinmux_set_bias,
2723 };
2724
2725 const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
2726 .name = "r8a73a4_pfc",
2727 .ops = &r8a73a4_pinmux_ops,
2728
2729 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2730 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2731 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2732
2733 .pins = pinmux_pins,
2734 .nr_pins = ARRAY_SIZE(pinmux_pins),
2735
2736 .groups = pinmux_groups,
2737 .nr_groups = ARRAY_SIZE(pinmux_groups),
2738 .functions = pinmux_functions,
2739 .nr_functions = ARRAY_SIZE(pinmux_functions),
2740
2741 .cfg_regs = pinmux_config_regs,
2742 .data_regs = pinmux_data_regs,
2743
2744 .gpio_data = pinmux_data,
2745 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2746
2747 .gpio_irq = pinmux_irqs,
2748 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
2749 };
Linux kernel - Deliverables
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