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58fbe6b1bae0dda9ee522aaf598359bc47598f1d
[deliverable/linux.git] / drivers / pinctrl / sh-pfc / pfc-r8a7740.c
1 /*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of the
10 * License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21 #include <linux/kernel.h>
22 #include <mach/r8a7740.h>
23 #include <mach/irqs.h>
24
25 #include "sh_pfc.h"
26
27 #define CPU_ALL_PORT(fn, pfx, sfx) \
28 PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
29 PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \
30 PORT_10(fn, pfx##20, sfx), \
31 PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx)
32
33 #define IRQC_PIN_MUX(irq, pin) \
34 static const unsigned int intc_irq##irq##_pins[] = { \
35 pin, \
36 }; \
37 static const unsigned int intc_irq##irq##_mux[] = { \
38 IRQ##irq##_MARK, \
39 }
40
41 #define IRQC_PINS_MUX(irq, idx, pin) \
42 static const unsigned int intc_irq##irq##_##idx##_pins[] = { \
43 pin, \
44 }; \
45 static const unsigned int intc_irq##irq##_##idx##_mux[] = { \
46 IRQ##irq##_PORT##pin##_MARK, \
47 }
48
49 enum {
50 PINMUX_RESERVED = 0,
51
52 /* PORT0_DATA -> PORT211_DATA */
53 PINMUX_DATA_BEGIN,
54 PORT_ALL(DATA),
55 PINMUX_DATA_END,
56
57 /* PORT0_IN -> PORT211_IN */
58 PINMUX_INPUT_BEGIN,
59 PORT_ALL(IN),
60 PINMUX_INPUT_END,
61
62 /* PORT0_IN_PU -> PORT211_IN_PU */
63 PINMUX_INPUT_PULLUP_BEGIN,
64 PORT_ALL(IN_PU),
65 PINMUX_INPUT_PULLUP_END,
66
67 /* PORT0_IN_PD -> PORT211_IN_PD */
68 PINMUX_INPUT_PULLDOWN_BEGIN,
69 PORT_ALL(IN_PD),
70 PINMUX_INPUT_PULLDOWN_END,
71
72 /* PORT0_OUT -> PORT211_OUT */
73 PINMUX_OUTPUT_BEGIN,
74 PORT_ALL(OUT),
75 PINMUX_OUTPUT_END,
76
77 PINMUX_FUNCTION_BEGIN,
78 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT211_FN_IN */
79 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT211_FN_OUT */
80 PORT_ALL(FN0), /* PORT0_FN0 -> PORT211_FN0 */
81 PORT_ALL(FN1), /* PORT0_FN1 -> PORT211_FN1 */
82 PORT_ALL(FN2), /* PORT0_FN2 -> PORT211_FN2 */
83 PORT_ALL(FN3), /* PORT0_FN3 -> PORT211_FN3 */
84 PORT_ALL(FN4), /* PORT0_FN4 -> PORT211_FN4 */
85 PORT_ALL(FN5), /* PORT0_FN5 -> PORT211_FN5 */
86 PORT_ALL(FN6), /* PORT0_FN6 -> PORT211_FN6 */
87 PORT_ALL(FN7), /* PORT0_FN7 -> PORT211_FN7 */
88
89 MSEL1CR_31_0, MSEL1CR_31_1,
90 MSEL1CR_30_0, MSEL1CR_30_1,
91 MSEL1CR_29_0, MSEL1CR_29_1,
92 MSEL1CR_28_0, MSEL1CR_28_1,
93 MSEL1CR_27_0, MSEL1CR_27_1,
94 MSEL1CR_26_0, MSEL1CR_26_1,
95 MSEL1CR_16_0, MSEL1CR_16_1,
96 MSEL1CR_15_0, MSEL1CR_15_1,
97 MSEL1CR_14_0, MSEL1CR_14_1,
98 MSEL1CR_13_0, MSEL1CR_13_1,
99 MSEL1CR_12_0, MSEL1CR_12_1,
100 MSEL1CR_9_0, MSEL1CR_9_1,
101 MSEL1CR_7_0, MSEL1CR_7_1,
102 MSEL1CR_6_0, MSEL1CR_6_1,
103 MSEL1CR_5_0, MSEL1CR_5_1,
104 MSEL1CR_4_0, MSEL1CR_4_1,
105 MSEL1CR_3_0, MSEL1CR_3_1,
106 MSEL1CR_2_0, MSEL1CR_2_1,
107 MSEL1CR_0_0, MSEL1CR_0_1,
108
109 MSEL3CR_15_0, MSEL3CR_15_1, /* Trace / Debug ? */
110 MSEL3CR_6_0, MSEL3CR_6_1,
111
112 MSEL4CR_19_0, MSEL4CR_19_1,
113 MSEL4CR_18_0, MSEL4CR_18_1,
114 MSEL4CR_15_0, MSEL4CR_15_1,
115 MSEL4CR_10_0, MSEL4CR_10_1,
116 MSEL4CR_6_0, MSEL4CR_6_1,
117 MSEL4CR_4_0, MSEL4CR_4_1,
118 MSEL4CR_1_0, MSEL4CR_1_1,
119
120 MSEL5CR_31_0, MSEL5CR_31_1, /* irq/fiq output */
121 MSEL5CR_30_0, MSEL5CR_30_1,
122 MSEL5CR_29_0, MSEL5CR_29_1,
123 MSEL5CR_27_0, MSEL5CR_27_1,
124 MSEL5CR_25_0, MSEL5CR_25_1,
125 MSEL5CR_23_0, MSEL5CR_23_1,
126 MSEL5CR_21_0, MSEL5CR_21_1,
127 MSEL5CR_19_0, MSEL5CR_19_1,
128 MSEL5CR_17_0, MSEL5CR_17_1,
129 MSEL5CR_15_0, MSEL5CR_15_1,
130 MSEL5CR_14_0, MSEL5CR_14_1,
131 MSEL5CR_13_0, MSEL5CR_13_1,
132 MSEL5CR_12_0, MSEL5CR_12_1,
133 MSEL5CR_11_0, MSEL5CR_11_1,
134 MSEL5CR_10_0, MSEL5CR_10_1,
135 MSEL5CR_8_0, MSEL5CR_8_1,
136 MSEL5CR_7_0, MSEL5CR_7_1,
137 MSEL5CR_6_0, MSEL5CR_6_1,
138 MSEL5CR_5_0, MSEL5CR_5_1,
139 MSEL5CR_4_0, MSEL5CR_4_1,
140 MSEL5CR_3_0, MSEL5CR_3_1,
141 MSEL5CR_2_0, MSEL5CR_2_1,
142 MSEL5CR_0_0, MSEL5CR_0_1,
143 PINMUX_FUNCTION_END,
144
145 PINMUX_MARK_BEGIN,
146
147 /* IRQ */
148 IRQ0_PORT2_MARK, IRQ0_PORT13_MARK,
149 IRQ1_MARK,
150 IRQ2_PORT11_MARK, IRQ2_PORT12_MARK,
151 IRQ3_PORT10_MARK, IRQ3_PORT14_MARK,
152 IRQ4_PORT15_MARK, IRQ4_PORT172_MARK,
153 IRQ5_PORT0_MARK, IRQ5_PORT1_MARK,
154 IRQ6_PORT121_MARK, IRQ6_PORT173_MARK,
155 IRQ7_PORT120_MARK, IRQ7_PORT209_MARK,
156 IRQ8_MARK,
157 IRQ9_PORT118_MARK, IRQ9_PORT210_MARK,
158 IRQ10_MARK,
159 IRQ11_MARK,
160 IRQ12_PORT42_MARK, IRQ12_PORT97_MARK,
161 IRQ13_PORT64_MARK, IRQ13_PORT98_MARK,
162 IRQ14_PORT63_MARK, IRQ14_PORT99_MARK,
163 IRQ15_PORT62_MARK, IRQ15_PORT100_MARK,
164 IRQ16_PORT68_MARK, IRQ16_PORT211_MARK,
165 IRQ17_MARK,
166 IRQ18_MARK,
167 IRQ19_MARK,
168 IRQ20_MARK,
169 IRQ21_MARK,
170 IRQ22_MARK,
171 IRQ23_MARK,
172 IRQ24_MARK,
173 IRQ25_MARK,
174 IRQ26_PORT58_MARK, IRQ26_PORT81_MARK,
175 IRQ27_PORT57_MARK, IRQ27_PORT168_MARK,
176 IRQ28_PORT56_MARK, IRQ28_PORT169_MARK,
177 IRQ29_PORT50_MARK, IRQ29_PORT170_MARK,
178 IRQ30_PORT49_MARK, IRQ30_PORT171_MARK,
179 IRQ31_PORT41_MARK, IRQ31_PORT167_MARK,
180
181 /* Function */
182
183 /* DBGT */
184 DBGMDT2_MARK, DBGMDT1_MARK, DBGMDT0_MARK,
185 DBGMD10_MARK, DBGMD11_MARK, DBGMD20_MARK,
186 DBGMD21_MARK,
187
188 /* FSI-A */
189 FSIAISLD_PORT0_MARK, /* FSIAISLD Port 0/5 */
190 FSIAISLD_PORT5_MARK,
191 FSIASPDIF_PORT9_MARK, /* FSIASPDIF Port 9/18 */
192 FSIASPDIF_PORT18_MARK,
193 FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK,
194 FSIAOBT_MARK, FSIAOSLD_MARK, FSIAOMC_MARK,
195 FSIACK_MARK, FSIAILR_MARK, FSIAIBT_MARK,
196
197 /* FSI-B */
198 FSIBCK_MARK,
199
200 /* FMSI */
201 FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
202 FMSISLD_PORT6_MARK,
203 FMSIILR_MARK, FMSIIBT_MARK, FMSIOLR_MARK, FMSIOBT_MARK,
204 FMSICK_MARK, FMSOILR_MARK, FMSOIBT_MARK, FMSOOLR_MARK,
205 FMSOOBT_MARK, FMSOSLD_MARK, FMSOCK_MARK,
206
207 /* SCIFA0 */
208 SCIFA0_SCK_MARK, SCIFA0_CTS_MARK, SCIFA0_RTS_MARK,
209 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
210
211 /* SCIFA1 */
212 SCIFA1_CTS_MARK, SCIFA1_SCK_MARK, SCIFA1_RXD_MARK,
213 SCIFA1_TXD_MARK, SCIFA1_RTS_MARK,
214
215 /* SCIFA2 */
216 SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
217 SCIFA2_SCK_PORT199_MARK,
218 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
219 SCIFA2_CTS_MARK, SCIFA2_RTS_MARK,
220
221 /* SCIFA3 */
222 SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
223 SCIFA3_SCK_PORT116_MARK,
224 SCIFA3_CTS_PORT117_MARK,
225 SCIFA3_RXD_PORT174_MARK,
226 SCIFA3_TXD_PORT175_MARK,
227
228 SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
229 SCIFA3_SCK_PORT158_MARK,
230 SCIFA3_CTS_PORT162_MARK,
231 SCIFA3_RXD_PORT159_MARK,
232 SCIFA3_TXD_PORT160_MARK,
233
234 /* SCIFA4 */
235 SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
236 SCIFA4_TXD_PORT13_MARK,
237
238 SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
239 SCIFA4_TXD_PORT203_MARK,
240
241 SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
242 SCIFA4_TXD_PORT93_MARK,
243
244 SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
245 SCIFA4_SCK_PORT205_MARK,
246
247 /* SCIFA5 */
248 SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
249 SCIFA5_RXD_PORT10_MARK,
250
251 SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
252 SCIFA5_TXD_PORT208_MARK,
253
254 SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
255 SCIFA5_RXD_PORT92_MARK,
256
257 SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
258 SCIFA5_SCK_PORT206_MARK,
259
260 /* SCIFA6 */
261 SCIFA6_SCK_MARK, SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
262
263 /* SCIFA7 */
264 SCIFA7_TXD_MARK, SCIFA7_RXD_MARK,
265
266 /* SCIFAB */
267 SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
268 SCIFB_RXD_PORT191_MARK,
269 SCIFB_TXD_PORT192_MARK,
270 SCIFB_RTS_PORT186_MARK,
271 SCIFB_CTS_PORT187_MARK,
272
273 SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
274 SCIFB_RXD_PORT3_MARK,
275 SCIFB_TXD_PORT4_MARK,
276 SCIFB_RTS_PORT172_MARK,
277 SCIFB_CTS_PORT173_MARK,
278
279 /* LCD0 */
280 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
281 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
282 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
283 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
284 LCD0_D16_MARK, LCD0_D17_MARK,
285 LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
286 LCD0_DCK_MARK, LCD0_VSYN_MARK, /* for RGB */
287 LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */
288 LCD0_WR_MARK, LCD0_RD_MARK, /* for SYS */
289 LCD0_CS_MARK, LCD0_RS_MARK, /* for SYS */
290
291 LCD0_D21_PORT158_MARK, LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
292 LCD0_D22_PORT160_MARK, LCD0_D20_PORT161_MARK,
293 LCD0_D19_PORT162_MARK, LCD0_D18_PORT163_MARK,
294 LCD0_LCLK_PORT165_MARK,
295
296 LCD0_D18_PORT40_MARK, LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
297 LCD0_D23_PORT1_MARK, LCD0_D21_PORT2_MARK,
298 LCD0_D20_PORT3_MARK, LCD0_D19_PORT4_MARK,
299 LCD0_LCLK_PORT102_MARK,
300
301 /* LCD1 */
302 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
303 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
304 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
305 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
306 LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
307 LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
308 LCD1_DON_MARK, LCD1_VCPWC_MARK,
309 LCD1_LCLK_MARK, LCD1_VEPWC_MARK,
310
311 LCD1_DCK_MARK, LCD1_VSYN_MARK, /* for RGB */
312 LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */
313 LCD1_RS_MARK, LCD1_CS_MARK, /* for SYS */
314 LCD1_RD_MARK, LCD1_WR_MARK, /* for SYS */
315
316 /* RSPI */
317 RSPI_SSL0_A_MARK, RSPI_SSL1_A_MARK, RSPI_SSL2_A_MARK,
318 RSPI_SSL3_A_MARK, RSPI_CK_A_MARK, RSPI_MOSI_A_MARK,
319 RSPI_MISO_A_MARK,
320
321 /* VIO CKO */
322 VIO_CKO1_MARK, /* needs fixup */
323 VIO_CKO2_MARK,
324 VIO_CKO_1_MARK,
325 VIO_CKO_MARK,
326
327 /* VIO0 */
328 VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
329 VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
330 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
331 VIO0_D12_MARK, VIO0_VD_MARK, VIO0_HD_MARK, VIO0_CLK_MARK,
332 VIO0_FIELD_MARK,
333
334 VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
335 VIO0_D14_PORT25_MARK,
336 VIO0_D15_PORT24_MARK,
337
338 VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
339 VIO0_D14_PORT95_MARK,
340 VIO0_D15_PORT96_MARK,
341
342 /* VIO1 */
343 VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
344 VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
345 VIO1_VD_MARK, VIO1_HD_MARK, VIO1_CLK_MARK, VIO1_FIELD_MARK,
346
347 /* TPU0 */
348 TPU0TO0_MARK, TPU0TO1_MARK, TPU0TO3_MARK,
349 TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
350 TPU0TO2_PORT202_MARK,
351
352 /* SSP1 0 */
353 STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK,
354 STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK,
355 STP0_IPEN_MARK, STP0_IPCLK_MARK, STP0_IPSYNC_MARK,
356
357 /* SSP1 1 */
358 STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK,
359 STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK,
360 STP1_IPSYNC_MARK,
361
362 STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
363 STP1_IPEN_PORT187_MARK,
364
365 STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
366 STP1_IPEN_PORT193_MARK,
367
368 /* SIM */
369 SIM_RST_MARK, SIM_CLK_MARK,
370 SIM_D_PORT22_MARK, /* SIM_D Port 22/199 */
371 SIM_D_PORT199_MARK,
372
373 /* SDHI0 */
374 SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
375 SDHI0_CD_MARK, SDHI0_WP_MARK, SDHI0_CMD_MARK, SDHI0_CLK_MARK,
376
377 /* SDHI1 */
378 SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
379 SDHI1_CD_MARK, SDHI1_WP_MARK, SDHI1_CMD_MARK, SDHI1_CLK_MARK,
380
381 /* SDHI2 */
382 SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
383 SDHI2_CLK_MARK, SDHI2_CMD_MARK,
384
385 SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
386 SDHI2_WP_PORT25_MARK,
387
388 SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
389 SDHI2_CD_PORT202_MARK,
390
391 /* MSIOF2 */
392 MSIOF2_TXD_MARK, MSIOF2_RXD_MARK, MSIOF2_TSCK_MARK,
393 MSIOF2_SS2_MARK, MSIOF2_TSYNC_MARK, MSIOF2_SS1_MARK,
394 MSIOF2_MCK1_MARK, MSIOF2_MCK0_MARK, MSIOF2_RSYNC_MARK,
395 MSIOF2_RSCK_MARK,
396
397 /* KEYSC */
398 KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
399 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
400 KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
401
402 KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
403 KEYIN1_PORT44_MARK,
404 KEYIN2_PORT45_MARK,
405 KEYIN3_PORT46_MARK,
406
407 KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
408 KEYIN1_PORT57_MARK,
409 KEYIN2_PORT56_MARK,
410 KEYIN3_PORT55_MARK,
411
412 /* VOU */
413 DV_D0_MARK, DV_D1_MARK, DV_D2_MARK, DV_D3_MARK,
414 DV_D4_MARK, DV_D5_MARK, DV_D6_MARK, DV_D7_MARK,
415 DV_D8_MARK, DV_D9_MARK, DV_D10_MARK, DV_D11_MARK,
416 DV_D12_MARK, DV_D13_MARK, DV_D14_MARK, DV_D15_MARK,
417 DV_CLK_MARK, DV_VSYNC_MARK, DV_HSYNC_MARK,
418
419 /* MEMC */
420 MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, MEMC_AD3_MARK,
421 MEMC_AD4_MARK, MEMC_AD5_MARK, MEMC_AD6_MARK, MEMC_AD7_MARK,
422 MEMC_AD8_MARK, MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK,
423 MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK,
424 MEMC_CS0_MARK, MEMC_INT_MARK, MEMC_NWE_MARK, MEMC_NOE_MARK,
425
426 MEMC_CS1_MARK, /* MSEL4CR_6_0 */
427 MEMC_ADV_MARK,
428 MEMC_WAIT_MARK,
429 MEMC_BUSCLK_MARK,
430
431 MEMC_A1_MARK, /* MSEL4CR_6_1 */
432 MEMC_DREQ0_MARK,
433 MEMC_DREQ1_MARK,
434 MEMC_A0_MARK,
435
436 /* MMC */
437 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK,
438 MMC0_D3_PORT71_MARK, MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK,
439 MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, MMC0_CLK_PORT66_MARK,
440 MMC0_CMD_PORT67_MARK, /* MSEL4CR_15_0 */
441
442 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK,
443 MMC1_D3_PORT146_MARK, MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK,
444 MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, MMC1_CLK_PORT103_MARK,
445 MMC1_CMD_PORT104_MARK, /* MSEL4CR_15_1 */
446
447 /* MSIOF0 */
448 MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, MSIOF0_RXD_MARK,
449 MSIOF0_TXD_MARK, MSIOF0_MCK0_MARK, MSIOF0_MCK1_MARK,
450 MSIOF0_RSYNC_MARK, MSIOF0_RSCK_MARK, MSIOF0_TSCK_MARK,
451 MSIOF0_TSYNC_MARK,
452
453 /* MSIOF1 */
454 MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK,
455 MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
456
457 MSIOF1_SS2_PORT116_MARK, MSIOF1_SS1_PORT117_MARK,
458 MSIOF1_RXD_PORT118_MARK, MSIOF1_TXD_PORT119_MARK,
459 MSIOF1_TSYNC_PORT120_MARK,
460 MSIOF1_TSCK_PORT121_MARK, /* MSEL4CR_10_0 */
461
462 MSIOF1_SS1_PORT67_MARK, MSIOF1_TSCK_PORT72_MARK,
463 MSIOF1_TSYNC_PORT73_MARK, MSIOF1_TXD_PORT74_MARK,
464 MSIOF1_RXD_PORT75_MARK,
465 MSIOF1_SS2_PORT202_MARK, /* MSEL4CR_10_1 */
466
467 /* GPIO */
468 GPO0_MARK, GPI0_MARK, GPO1_MARK, GPI1_MARK,
469
470 /* USB0 */
471 USB0_OCI_MARK, USB0_PPON_MARK, VBUS_MARK,
472
473 /* USB1 */
474 USB1_OCI_MARK, USB1_PPON_MARK,
475
476 /* BBIF1 */
477 BBIF1_RXD_MARK, BBIF1_TXD_MARK, BBIF1_TSYNC_MARK,
478 BBIF1_TSCK_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK,
479 BBIF1_FLOW_MARK, BBIF1_RX_FLOW_N_MARK,
480
481 /* BBIF2 */
482 BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
483 BBIF2_RXD2_PORT60_MARK,
484 BBIF2_TSYNC2_PORT6_MARK,
485 BBIF2_TSCK2_PORT59_MARK,
486
487 BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
488 BBIF2_TXD2_PORT183_MARK,
489 BBIF2_TSCK2_PORT89_MARK,
490 BBIF2_TSYNC2_PORT184_MARK,
491
492 /* BSC / FLCTL / PCMCIA */
493 CS0_MARK, CS2_MARK, CS4_MARK,
494 CS5B_MARK, CS6A_MARK,
495 CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
496 CS5A_PORT19_MARK,
497 IOIS16_MARK, /* ? */
498
499 A0_MARK, A1_MARK, A2_MARK, A3_MARK,
500 A4_FOE_MARK, /* share with FLCTL */
501 A5_FCDE_MARK, /* share with FLCTL */
502 A6_MARK, A7_MARK, A8_MARK, A9_MARK,
503 A10_MARK, A11_MARK, A12_MARK, A13_MARK,
504 A14_MARK, A15_MARK, A16_MARK, A17_MARK,
505 A18_MARK, A19_MARK, A20_MARK, A21_MARK,
506 A22_MARK, A23_MARK, A24_MARK, A25_MARK,
507 A26_MARK,
508
509 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, /* share with FLCTL */
510 D3_NAF3_MARK, D4_NAF4_MARK, D5_NAF5_MARK, /* share with FLCTL */
511 D6_NAF6_MARK, D7_NAF7_MARK, D8_NAF8_MARK, /* share with FLCTL */
512 D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */
513 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */
514 D15_NAF15_MARK, /* share with FLCTL */
515 D16_MARK, D17_MARK, D18_MARK, D19_MARK,
516 D20_MARK, D21_MARK, D22_MARK, D23_MARK,
517 D24_MARK, D25_MARK, D26_MARK, D27_MARK,
518 D28_MARK, D29_MARK, D30_MARK, D31_MARK,
519
520 WE0_FWE_MARK, /* share with FLCTL */
521 WE1_MARK,
522 WE2_ICIORD_MARK, /* share with PCMCIA */
523 WE3_ICIOWR_MARK, /* share with PCMCIA */
524 CKO_MARK, BS_MARK, RDWR_MARK,
525 RD_FSC_MARK, /* share with FLCTL */
526 WAIT_PORT177_MARK, /* WAIT Port 90/177 */
527 WAIT_PORT90_MARK,
528
529 FCE0_MARK, FCE1_MARK, FRB_MARK, /* FLCTL */
530
531 /* IRDA */
532 IRDA_FIRSEL_MARK, IRDA_IN_MARK, IRDA_OUT_MARK,
533
534 /* ATAPI */
535 IDE_D0_MARK, IDE_D1_MARK, IDE_D2_MARK, IDE_D3_MARK,
536 IDE_D4_MARK, IDE_D5_MARK, IDE_D6_MARK, IDE_D7_MARK,
537 IDE_D8_MARK, IDE_D9_MARK, IDE_D10_MARK, IDE_D11_MARK,
538 IDE_D12_MARK, IDE_D13_MARK, IDE_D14_MARK, IDE_D15_MARK,
539 IDE_A0_MARK, IDE_A1_MARK, IDE_A2_MARK, IDE_CS0_MARK,
540 IDE_CS1_MARK, IDE_IOWR_MARK, IDE_IORD_MARK, IDE_IORDY_MARK,
541 IDE_INT_MARK, IDE_RST_MARK, IDE_DIRECTION_MARK,
542 IDE_EXBUF_ENB_MARK, IDE_IODACK_MARK, IDE_IODREQ_MARK,
543
544 /* RMII */
545 RMII_CRS_DV_MARK, RMII_RX_ER_MARK, RMII_RXD0_MARK,
546 RMII_RXD1_MARK, RMII_TX_EN_MARK, RMII_TXD0_MARK,
547 RMII_MDC_MARK, RMII_TXD1_MARK, RMII_MDIO_MARK,
548 RMII_REF50CK_MARK, /* for RMII */
549 RMII_REF125CK_MARK, /* for GMII */
550
551 /* GEther */
552 ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_ETXD0_MARK, ET_ETXD1_MARK,
553 ET_ETXD2_MARK, ET_ETXD3_MARK,
554 ET_ETXD4_MARK, ET_ETXD5_MARK, /* for GEther */
555 ET_ETXD6_MARK, ET_ETXD7_MARK, /* for GEther */
556 ET_COL_MARK, ET_TX_ER_MARK, ET_RX_CLK_MARK, ET_RX_DV_MARK,
557 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
558 ET_ERXD4_MARK, ET_ERXD5_MARK, /* for GEther */
559 ET_ERXD6_MARK, ET_ERXD7_MARK, /* for GEther */
560 ET_RX_ER_MARK, ET_CRS_MARK, ET_MDC_MARK, ET_MDIO_MARK,
561 ET_LINK_MARK, ET_PHY_INT_MARK, ET_WOL_MARK, ET_GTX_CLK_MARK,
562
563 /* DMA0 */
564 DREQ0_MARK, DACK0_MARK,
565
566 /* DMA1 */
567 DREQ1_MARK, DACK1_MARK,
568
569 /* SYSC */
570 RESETOUTS_MARK, RESETP_PULLUP_MARK, RESETP_PLAIN_MARK,
571
572 /* IRREM */
573 IROUT_MARK,
574
575 /* SDENC */
576 SDENC_CPG_MARK, SDENC_DV_CLKI_MARK,
577
578 /* HDMI */
579 HDMI_HPD_MARK, HDMI_CEC_MARK,
580
581 /* DEBUG */
582 EDEBGREQ_PULLUP_MARK, /* for JTAG */
583 EDEBGREQ_PULLDOWN_MARK,
584
585 TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */
586 TRACEAUD_FROM_LCDC0_MARK,
587 TRACEAUD_FROM_MEMC_MARK,
588
589 PINMUX_MARK_END,
590 };
591
592 static const pinmux_enum_t pinmux_data[] = {
593 /* specify valid pin states for each pin in GPIO mode */
594
595 /* I/O and Pull U/D */
596 PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1),
597 PORT_DATA_IO_PD(2), PORT_DATA_IO_PD(3),
598 PORT_DATA_IO_PD(4), PORT_DATA_IO_PD(5),
599 PORT_DATA_IO_PD(6), PORT_DATA_IO(7),
600 PORT_DATA_IO(8), PORT_DATA_IO(9),
601
602 PORT_DATA_IO_PD(10), PORT_DATA_IO_PD(11),
603 PORT_DATA_IO_PD(12), PORT_DATA_IO_PU_PD(13),
604 PORT_DATA_IO_PD(14), PORT_DATA_IO_PD(15),
605 PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17),
606 PORT_DATA_IO(18), PORT_DATA_IO_PU(19),
607
608 PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PD(21),
609 PORT_DATA_IO_PU_PD(22), PORT_DATA_IO(23),
610 PORT_DATA_IO_PU(24), PORT_DATA_IO_PU(25),
611 PORT_DATA_IO_PU(26), PORT_DATA_IO_PU(27),
612 PORT_DATA_IO_PU(28), PORT_DATA_IO_PU(29),
613
614 PORT_DATA_IO_PU(30), PORT_DATA_IO_PD(31),
615 PORT_DATA_IO_PD(32), PORT_DATA_IO_PD(33),
616 PORT_DATA_IO_PD(34), PORT_DATA_IO_PU(35),
617 PORT_DATA_IO_PU(36), PORT_DATA_IO_PD(37),
618 PORT_DATA_IO_PU(38), PORT_DATA_IO_PD(39),
619
620 PORT_DATA_IO_PU_PD(40), PORT_DATA_IO_PD(41),
621 PORT_DATA_IO_PD(42), PORT_DATA_IO_PU_PD(43),
622 PORT_DATA_IO_PU_PD(44), PORT_DATA_IO_PU_PD(45),
623 PORT_DATA_IO_PU_PD(46), PORT_DATA_IO_PU_PD(47),
624 PORT_DATA_IO_PU_PD(48), PORT_DATA_IO_PU_PD(49),
625
626 PORT_DATA_IO_PU_PD(50), PORT_DATA_IO_PD(51),
627 PORT_DATA_IO_PD(52), PORT_DATA_IO_PD(53),
628 PORT_DATA_IO_PD(54), PORT_DATA_IO_PU_PD(55),
629 PORT_DATA_IO_PU_PD(56), PORT_DATA_IO_PU_PD(57),
630 PORT_DATA_IO_PU_PD(58), PORT_DATA_IO_PU_PD(59),
631
632 PORT_DATA_IO_PU_PD(60), PORT_DATA_IO_PD(61),
633 PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63),
634 PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65),
635 PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67),
636 PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69),
637
638 PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71),
639 PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73),
640 PORT_DATA_IO_PU_PD(74), PORT_DATA_IO_PU_PD(75),
641 PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77),
642 PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79),
643
644 PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81),
645 PORT_DATA_IO(82), PORT_DATA_IO_PU_PD(83),
646 PORT_DATA_IO(84), PORT_DATA_IO_PD(85),
647 PORT_DATA_IO_PD(86), PORT_DATA_IO_PD(87),
648 PORT_DATA_IO_PD(88), PORT_DATA_IO_PD(89),
649
650 PORT_DATA_IO_PD(90), PORT_DATA_IO_PU_PD(91),
651 PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93),
652 PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95),
653 PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97),
654 PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99),
655
656 PORT_DATA_IO_PU_PD(100), PORT_DATA_IO(101),
657 PORT_DATA_IO_PU(102), PORT_DATA_IO_PU_PD(103),
658 PORT_DATA_IO_PU(104), PORT_DATA_IO_PU(105),
659 PORT_DATA_IO_PU_PD(106), PORT_DATA_IO(107),
660 PORT_DATA_IO(108), PORT_DATA_IO(109),
661
662 PORT_DATA_IO(110), PORT_DATA_IO(111),
663 PORT_DATA_IO(112), PORT_DATA_IO(113),
664 PORT_DATA_IO_PU_PD(114), PORT_DATA_IO(115),
665 PORT_DATA_IO_PD(116), PORT_DATA_IO_PD(117),
666 PORT_DATA_IO_PD(118), PORT_DATA_IO_PD(119),
667
668 PORT_DATA_IO_PD(120), PORT_DATA_IO_PD(121),
669 PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123),
670 PORT_DATA_IO_PD(124), PORT_DATA_IO(125),
671 PORT_DATA_IO(126), PORT_DATA_IO(127),
672 PORT_DATA_IO(128), PORT_DATA_IO(129),
673
674 PORT_DATA_IO(130), PORT_DATA_IO(131),
675 PORT_DATA_IO(132), PORT_DATA_IO(133),
676 PORT_DATA_IO(134), PORT_DATA_IO(135),
677 PORT_DATA_IO(136), PORT_DATA_IO(137),
678 PORT_DATA_IO(138), PORT_DATA_IO(139),
679
680 PORT_DATA_IO(140), PORT_DATA_IO(141),
681 PORT_DATA_IO_PU(142), PORT_DATA_IO_PU(143),
682 PORT_DATA_IO_PU(144), PORT_DATA_IO_PU(145),
683 PORT_DATA_IO_PU(146), PORT_DATA_IO_PU(147),
684 PORT_DATA_IO_PU(148), PORT_DATA_IO_PU(149),
685
686 PORT_DATA_IO_PU(150), PORT_DATA_IO_PU(151),
687 PORT_DATA_IO_PU(152), PORT_DATA_IO_PU(153),
688 PORT_DATA_IO_PU(154), PORT_DATA_IO_PU(155),
689 PORT_DATA_IO_PU(156), PORT_DATA_IO_PU(157),
690 PORT_DATA_IO_PD(158), PORT_DATA_IO_PD(159),
691
692 PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PD(161),
693 PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163),
694 PORT_DATA_IO_PD(164), PORT_DATA_IO_PD(165),
695 PORT_DATA_IO_PU(166), PORT_DATA_IO_PU(167),
696 PORT_DATA_IO_PU(168), PORT_DATA_IO_PU(169),
697
698 PORT_DATA_IO_PU(170), PORT_DATA_IO_PU(171),
699 PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173),
700 PORT_DATA_IO_PD(174), PORT_DATA_IO_PD(175),
701 PORT_DATA_IO_PU(176), PORT_DATA_IO_PU_PD(177),
702 PORT_DATA_IO_PU(178), PORT_DATA_IO_PD(179),
703
704 PORT_DATA_IO_PD(180), PORT_DATA_IO_PU(181),
705 PORT_DATA_IO_PU(182), PORT_DATA_IO(183),
706 PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185),
707 PORT_DATA_IO_PD(186), PORT_DATA_IO_PD(187),
708 PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189),
709
710 PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191),
711 PORT_DATA_IO_PD(192), PORT_DATA_IO_PU_PD(193),
712 PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PD(195),
713 PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PD(197),
714 PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199),
715
716 PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU(201),
717 PORT_DATA_IO_PU_PD(202), PORT_DATA_IO(203),
718 PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205),
719 PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207),
720 PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PD(209),
721
722 PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),
723
724 /* Port0 */
725 PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1),
726 PINMUX_DATA(FSIAISLD_PORT0_MARK, PORT0_FN2, MSEL5CR_3_0),
727 PINMUX_DATA(FSIAOSLD1_MARK, PORT0_FN3),
728 PINMUX_DATA(LCD0_D22_PORT0_MARK, PORT0_FN4, MSEL5CR_6_0),
729 PINMUX_DATA(SCIFA7_RXD_MARK, PORT0_FN6),
730 PINMUX_DATA(LCD1_D4_MARK, PORT0_FN7),
731 PINMUX_DATA(IRQ5_PORT0_MARK, PORT0_FN0, MSEL1CR_5_0),
732
733 /* Port1 */
734 PINMUX_DATA(DBGMDT1_MARK, PORT1_FN1),
735 PINMUX_DATA(FMSISLD_PORT1_MARK, PORT1_FN2, MSEL5CR_5_0),
736 PINMUX_DATA(FSIAOSLD2_MARK, PORT1_FN3),
737 PINMUX_DATA(LCD0_D23_PORT1_MARK, PORT1_FN4, MSEL5CR_6_0),
738 PINMUX_DATA(SCIFA7_TXD_MARK, PORT1_FN6),
739 PINMUX_DATA(LCD1_D3_MARK, PORT1_FN7),
740 PINMUX_DATA(IRQ5_PORT1_MARK, PORT1_FN0, MSEL1CR_5_1),
741
742 /* Port2 */
743 PINMUX_DATA(DBGMDT0_MARK, PORT2_FN1),
744 PINMUX_DATA(SCIFB_SCK_PORT2_MARK, PORT2_FN2, MSEL5CR_17_1),
745 PINMUX_DATA(LCD0_D21_PORT2_MARK, PORT2_FN4, MSEL5CR_6_0),
746 PINMUX_DATA(LCD1_D2_MARK, PORT2_FN7),
747 PINMUX_DATA(IRQ0_PORT2_MARK, PORT2_FN0, MSEL1CR_0_1),
748
749 /* Port3 */
750 PINMUX_DATA(DBGMD21_MARK, PORT3_FN1),
751 PINMUX_DATA(SCIFB_RXD_PORT3_MARK, PORT3_FN2, MSEL5CR_17_1),
752 PINMUX_DATA(LCD0_D20_PORT3_MARK, PORT3_FN4, MSEL5CR_6_0),
753 PINMUX_DATA(LCD1_D1_MARK, PORT3_FN7),
754
755 /* Port4 */
756 PINMUX_DATA(DBGMD20_MARK, PORT4_FN1),
757 PINMUX_DATA(SCIFB_TXD_PORT4_MARK, PORT4_FN2, MSEL5CR_17_1),
758 PINMUX_DATA(LCD0_D19_PORT4_MARK, PORT4_FN4, MSEL5CR_6_0),
759 PINMUX_DATA(LCD1_D0_MARK, PORT4_FN7),
760
761 /* Port5 */
762 PINMUX_DATA(DBGMD11_MARK, PORT5_FN1),
763 PINMUX_DATA(BBIF2_TXD2_PORT5_MARK, PORT5_FN2, MSEL5CR_0_0),
764 PINMUX_DATA(FSIAISLD_PORT5_MARK, PORT5_FN4, MSEL5CR_3_1),
765 PINMUX_DATA(RSPI_SSL0_A_MARK, PORT5_FN6),
766 PINMUX_DATA(LCD1_VCPWC_MARK, PORT5_FN7),
767
768 /* Port6 */
769 PINMUX_DATA(DBGMD10_MARK, PORT6_FN1),
770 PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK, PORT6_FN2, MSEL5CR_0_0),
771 PINMUX_DATA(FMSISLD_PORT6_MARK, PORT6_FN4, MSEL5CR_5_1),
772 PINMUX_DATA(RSPI_SSL1_A_MARK, PORT6_FN6),
773 PINMUX_DATA(LCD1_VEPWC_MARK, PORT6_FN7),
774
775 /* Port7 */
776 PINMUX_DATA(FSIAOLR_MARK, PORT7_FN1),
777
778 /* Port8 */
779 PINMUX_DATA(FSIAOBT_MARK, PORT8_FN1),
780
781 /* Port9 */
782 PINMUX_DATA(FSIAOSLD_MARK, PORT9_FN1),
783 PINMUX_DATA(FSIASPDIF_PORT9_MARK, PORT9_FN2, MSEL5CR_4_0),
784
785 /* Port10 */
786 PINMUX_DATA(FSIAOMC_MARK, PORT10_FN1),
787 PINMUX_DATA(SCIFA5_RXD_PORT10_MARK, PORT10_FN3, MSEL5CR_14_0, MSEL5CR_15_0),
788 PINMUX_DATA(IRQ3_PORT10_MARK, PORT10_FN0, MSEL1CR_3_0),
789
790 /* Port11 */
791 PINMUX_DATA(FSIACK_MARK, PORT11_FN1),
792 PINMUX_DATA(FSIBCK_MARK, PORT11_FN2),
793 PINMUX_DATA(IRQ2_PORT11_MARK, PORT11_FN0, MSEL1CR_2_0),
794
795 /* Port12 */
796 PINMUX_DATA(FSIAILR_MARK, PORT12_FN1),
797 PINMUX_DATA(SCIFA4_RXD_PORT12_MARK, PORT12_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
798 PINMUX_DATA(LCD1_RS_MARK, PORT12_FN6),
799 PINMUX_DATA(LCD1_DISP_MARK, PORT12_FN7),
800 PINMUX_DATA(IRQ2_PORT12_MARK, PORT12_FN0, MSEL1CR_2_1),
801
802 /* Port13 */
803 PINMUX_DATA(FSIAIBT_MARK, PORT13_FN1),
804 PINMUX_DATA(SCIFA4_TXD_PORT13_MARK, PORT13_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
805 PINMUX_DATA(LCD1_RD_MARK, PORT13_FN7),
806 PINMUX_DATA(IRQ0_PORT13_MARK, PORT13_FN0, MSEL1CR_0_0),
807
808 /* Port14 */
809 PINMUX_DATA(FMSOILR_MARK, PORT14_FN1),
810 PINMUX_DATA(FMSIILR_MARK, PORT14_FN2),
811 PINMUX_DATA(VIO_CKO1_MARK, PORT14_FN3),
812 PINMUX_DATA(LCD1_D23_MARK, PORT14_FN7),
813 PINMUX_DATA(IRQ3_PORT14_MARK, PORT14_FN0, MSEL1CR_3_1),
814
815 /* Port15 */
816 PINMUX_DATA(FMSOIBT_MARK, PORT15_FN1),
817 PINMUX_DATA(FMSIIBT_MARK, PORT15_FN2),
818 PINMUX_DATA(VIO_CKO2_MARK, PORT15_FN3),
819 PINMUX_DATA(LCD1_D22_MARK, PORT15_FN7),
820 PINMUX_DATA(IRQ4_PORT15_MARK, PORT15_FN0, MSEL1CR_4_0),
821
822 /* Port16 */
823 PINMUX_DATA(FMSOOLR_MARK, PORT16_FN1),
824 PINMUX_DATA(FMSIOLR_MARK, PORT16_FN2),
825
826 /* Port17 */
827 PINMUX_DATA(FMSOOBT_MARK, PORT17_FN1),
828 PINMUX_DATA(FMSIOBT_MARK, PORT17_FN2),
829
830 /* Port18 */
831 PINMUX_DATA(FMSOSLD_MARK, PORT18_FN1),
832 PINMUX_DATA(FSIASPDIF_PORT18_MARK, PORT18_FN2, MSEL5CR_4_1),
833
834 /* Port19 */
835 PINMUX_DATA(FMSICK_MARK, PORT19_FN1),
836 PINMUX_DATA(CS5A_PORT19_MARK, PORT19_FN7, MSEL5CR_2_1),
837 PINMUX_DATA(IRQ10_MARK, PORT19_FN0),
838
839 /* Port20 */
840 PINMUX_DATA(FMSOCK_MARK, PORT20_FN1),
841 PINMUX_DATA(SCIFA5_TXD_PORT20_MARK, PORT20_FN3, MSEL5CR_15_0, MSEL5CR_14_0),
842 PINMUX_DATA(IRQ1_MARK, PORT20_FN0),
843
844 /* Port21 */
845 PINMUX_DATA(SCIFA1_CTS_MARK, PORT21_FN1),
846 PINMUX_DATA(SCIFA4_SCK_PORT21_MARK, PORT21_FN2, MSEL5CR_10_0),
847 PINMUX_DATA(TPU0TO1_MARK, PORT21_FN4),
848 PINMUX_DATA(VIO1_FIELD_MARK, PORT21_FN5),
849 PINMUX_DATA(STP0_IPD5_MARK, PORT21_FN6),
850 PINMUX_DATA(LCD1_D10_MARK, PORT21_FN7),
851
852 /* Port22 */
853 PINMUX_DATA(SCIFA2_SCK_PORT22_MARK, PORT22_FN1, MSEL5CR_7_0),
854 PINMUX_DATA(SIM_D_PORT22_MARK, PORT22_FN4, MSEL5CR_21_0),
855 PINMUX_DATA(VIO0_D13_PORT22_MARK, PORT22_FN7, MSEL5CR_27_1),
856
857 /* Port23 */
858 PINMUX_DATA(SCIFA1_RTS_MARK, PORT23_FN1),
859 PINMUX_DATA(SCIFA5_SCK_PORT23_MARK, PORT23_FN3, MSEL5CR_13_0),
860 PINMUX_DATA(TPU0TO0_MARK, PORT23_FN4),
861 PINMUX_DATA(VIO_CKO_1_MARK, PORT23_FN5),
862 PINMUX_DATA(STP0_IPD2_MARK, PORT23_FN6),
863 PINMUX_DATA(LCD1_D7_MARK, PORT23_FN7),
864
865 /* Port24 */
866 PINMUX_DATA(VIO0_D15_PORT24_MARK, PORT24_FN1, MSEL5CR_27_0),
867 PINMUX_DATA(VIO1_D7_MARK, PORT24_FN5),
868 PINMUX_DATA(SCIFA6_SCK_MARK, PORT24_FN6),
869 PINMUX_DATA(SDHI2_CD_PORT24_MARK, PORT24_FN7, MSEL5CR_19_0),
870
871 /* Port25 */
872 PINMUX_DATA(VIO0_D14_PORT25_MARK, PORT25_FN1, MSEL5CR_27_0),
873 PINMUX_DATA(VIO1_D6_MARK, PORT25_FN5),
874 PINMUX_DATA(SCIFA6_RXD_MARK, PORT25_FN6),
875 PINMUX_DATA(SDHI2_WP_PORT25_MARK, PORT25_FN7, MSEL5CR_19_0),
876
877 /* Port26 */
878 PINMUX_DATA(VIO0_D13_PORT26_MARK, PORT26_FN1, MSEL5CR_27_0),
879 PINMUX_DATA(VIO1_D5_MARK, PORT26_FN5),
880 PINMUX_DATA(SCIFA6_TXD_MARK, PORT26_FN6),
881
882 /* Port27 - Port39 Function */
883 PINMUX_DATA(VIO0_D7_MARK, PORT27_FN1),
884 PINMUX_DATA(VIO0_D6_MARK, PORT28_FN1),
885 PINMUX_DATA(VIO0_D5_MARK, PORT29_FN1),
886 PINMUX_DATA(VIO0_D4_MARK, PORT30_FN1),
887 PINMUX_DATA(VIO0_D3_MARK, PORT31_FN1),
888 PINMUX_DATA(VIO0_D2_MARK, PORT32_FN1),
889 PINMUX_DATA(VIO0_D1_MARK, PORT33_FN1),
890 PINMUX_DATA(VIO0_D0_MARK, PORT34_FN1),
891 PINMUX_DATA(VIO0_CLK_MARK, PORT35_FN1),
892 PINMUX_DATA(VIO_CKO_MARK, PORT36_FN1),
893 PINMUX_DATA(VIO0_HD_MARK, PORT37_FN1),
894 PINMUX_DATA(VIO0_FIELD_MARK, PORT38_FN1),
895 PINMUX_DATA(VIO0_VD_MARK, PORT39_FN1),
896
897 /* Port38 IRQ */
898 PINMUX_DATA(IRQ25_MARK, PORT38_FN0),
899
900 /* Port40 */
901 PINMUX_DATA(LCD0_D18_PORT40_MARK, PORT40_FN4, MSEL5CR_6_0),
902 PINMUX_DATA(RSPI_CK_A_MARK, PORT40_FN6),
903 PINMUX_DATA(LCD1_LCLK_MARK, PORT40_FN7),
904
905 /* Port41 */
906 PINMUX_DATA(LCD0_D17_MARK, PORT41_FN1),
907 PINMUX_DATA(MSIOF2_SS1_MARK, PORT41_FN2),
908 PINMUX_DATA(IRQ31_PORT41_MARK, PORT41_FN0, MSEL1CR_31_1),
909
910 /* Port42 */
911 PINMUX_DATA(LCD0_D16_MARK, PORT42_FN1),
912 PINMUX_DATA(MSIOF2_MCK1_MARK, PORT42_FN2),
913 PINMUX_DATA(IRQ12_PORT42_MARK, PORT42_FN0, MSEL1CR_12_1),
914
915 /* Port43 */
916 PINMUX_DATA(LCD0_D15_MARK, PORT43_FN1),
917 PINMUX_DATA(MSIOF2_MCK0_MARK, PORT43_FN2),
918 PINMUX_DATA(KEYIN0_PORT43_MARK, PORT43_FN3, MSEL4CR_18_0),
919 PINMUX_DATA(DV_D15_MARK, PORT43_FN6),
920
921 /* Port44 */
922 PINMUX_DATA(LCD0_D14_MARK, PORT44_FN1),
923 PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT44_FN2),
924 PINMUX_DATA(KEYIN1_PORT44_MARK, PORT44_FN3, MSEL4CR_18_0),
925 PINMUX_DATA(DV_D14_MARK, PORT44_FN6),
926
927 /* Port45 */
928 PINMUX_DATA(LCD0_D13_MARK, PORT45_FN1),
929 PINMUX_DATA(MSIOF2_RSCK_MARK, PORT45_FN2),
930 PINMUX_DATA(KEYIN2_PORT45_MARK, PORT45_FN3, MSEL4CR_18_0),
931 PINMUX_DATA(DV_D13_MARK, PORT45_FN6),
932
933 /* Port46 */
934 PINMUX_DATA(LCD0_D12_MARK, PORT46_FN1),
935 PINMUX_DATA(KEYIN3_PORT46_MARK, PORT46_FN3, MSEL4CR_18_0),
936 PINMUX_DATA(DV_D12_MARK, PORT46_FN6),
937
938 /* Port47 */
939 PINMUX_DATA(LCD0_D11_MARK, PORT47_FN1),
940 PINMUX_DATA(KEYIN4_MARK, PORT47_FN3),
941 PINMUX_DATA(DV_D11_MARK, PORT47_FN6),
942
943 /* Port48 */
944 PINMUX_DATA(LCD0_D10_MARK, PORT48_FN1),
945 PINMUX_DATA(KEYIN5_MARK, PORT48_FN3),
946 PINMUX_DATA(DV_D10_MARK, PORT48_FN6),
947
948 /* Port49 */
949 PINMUX_DATA(LCD0_D9_MARK, PORT49_FN1),
950 PINMUX_DATA(KEYIN6_MARK, PORT49_FN3),
951 PINMUX_DATA(DV_D9_MARK, PORT49_FN6),
952 PINMUX_DATA(IRQ30_PORT49_MARK, PORT49_FN0, MSEL1CR_30_1),
953
954 /* Port50 */
955 PINMUX_DATA(LCD0_D8_MARK, PORT50_FN1),
956 PINMUX_DATA(KEYIN7_MARK, PORT50_FN3),
957 PINMUX_DATA(DV_D8_MARK, PORT50_FN6),
958 PINMUX_DATA(IRQ29_PORT50_MARK, PORT50_FN0, MSEL1CR_29_1),
959
960 /* Port51 */
961 PINMUX_DATA(LCD0_D7_MARK, PORT51_FN1),
962 PINMUX_DATA(KEYOUT0_MARK, PORT51_FN3),
963 PINMUX_DATA(DV_D7_MARK, PORT51_FN6),
964
965 /* Port52 */
966 PINMUX_DATA(LCD0_D6_MARK, PORT52_FN1),
967 PINMUX_DATA(KEYOUT1_MARK, PORT52_FN3),
968 PINMUX_DATA(DV_D6_MARK, PORT52_FN6),
969
970 /* Port53 */
971 PINMUX_DATA(LCD0_D5_MARK, PORT53_FN1),
972 PINMUX_DATA(KEYOUT2_MARK, PORT53_FN3),
973 PINMUX_DATA(DV_D5_MARK, PORT53_FN6),
974
975 /* Port54 */
976 PINMUX_DATA(LCD0_D4_MARK, PORT54_FN1),
977 PINMUX_DATA(KEYOUT3_MARK, PORT54_FN3),
978 PINMUX_DATA(DV_D4_MARK, PORT54_FN6),
979
980 /* Port55 */
981 PINMUX_DATA(LCD0_D3_MARK, PORT55_FN1),
982 PINMUX_DATA(KEYOUT4_MARK, PORT55_FN3),
983 PINMUX_DATA(KEYIN3_PORT55_MARK, PORT55_FN4, MSEL4CR_18_1),
984 PINMUX_DATA(DV_D3_MARK, PORT55_FN6),
985
986 /* Port56 */
987 PINMUX_DATA(LCD0_D2_MARK, PORT56_FN1),
988 PINMUX_DATA(KEYOUT5_MARK, PORT56_FN3),
989 PINMUX_DATA(KEYIN2_PORT56_MARK, PORT56_FN4, MSEL4CR_18_1),
990 PINMUX_DATA(DV_D2_MARK, PORT56_FN6),
991 PINMUX_DATA(IRQ28_PORT56_MARK, PORT56_FN0, MSEL1CR_28_1),
992
993 /* Port57 */
994 PINMUX_DATA(LCD0_D1_MARK, PORT57_FN1),
995 PINMUX_DATA(KEYOUT6_MARK, PORT57_FN3),
996 PINMUX_DATA(KEYIN1_PORT57_MARK, PORT57_FN4, MSEL4CR_18_1),
997 PINMUX_DATA(DV_D1_MARK, PORT57_FN6),
998 PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1),
999
1000 /* Port58 */
1001 PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1, MSEL3CR_6_0),
1002 PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3),
1003 PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1),
1004 PINMUX_DATA(DV_D0_MARK, PORT58_FN6),
1005 PINMUX_DATA(IRQ26_PORT58_MARK, PORT58_FN0, MSEL1CR_26_1),
1006
1007 /* Port59 */
1008 PINMUX_DATA(LCD0_VCPWC_MARK, PORT59_FN1),
1009 PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK, PORT59_FN2, MSEL5CR_0_0),
1010 PINMUX_DATA(RSPI_MOSI_A_MARK, PORT59_FN6),
1011
1012 /* Port60 */
1013 PINMUX_DATA(LCD0_VEPWC_MARK, PORT60_FN1),
1014 PINMUX_DATA(BBIF2_RXD2_PORT60_MARK, PORT60_FN2, MSEL5CR_0_0),
1015 PINMUX_DATA(RSPI_MISO_A_MARK, PORT60_FN6),
1016
1017 /* Port61 */
1018 PINMUX_DATA(LCD0_DON_MARK, PORT61_FN1),
1019 PINMUX_DATA(MSIOF2_TXD_MARK, PORT61_FN2),
1020
1021 /* Port62 */
1022 PINMUX_DATA(LCD0_DCK_MARK, PORT62_FN1),
1023 PINMUX_DATA(LCD0_WR_MARK, PORT62_FN4),
1024 PINMUX_DATA(DV_CLK_MARK, PORT62_FN6),
1025 PINMUX_DATA(IRQ15_PORT62_MARK, PORT62_FN0, MSEL1CR_15_1),
1026
1027 /* Port63 */
1028 PINMUX_DATA(LCD0_VSYN_MARK, PORT63_FN1),
1029 PINMUX_DATA(DV_VSYNC_MARK, PORT63_FN6),
1030 PINMUX_DATA(IRQ14_PORT63_MARK, PORT63_FN0, MSEL1CR_14_1),
1031
1032 /* Port64 */
1033 PINMUX_DATA(LCD0_HSYN_MARK, PORT64_FN1),
1034 PINMUX_DATA(LCD0_CS_MARK, PORT64_FN4),
1035 PINMUX_DATA(DV_HSYNC_MARK, PORT64_FN6),
1036 PINMUX_DATA(IRQ13_PORT64_MARK, PORT64_FN0, MSEL1CR_13_1),
1037
1038 /* Port65 */
1039 PINMUX_DATA(LCD0_DISP_MARK, PORT65_FN1),
1040 PINMUX_DATA(MSIOF2_TSCK_MARK, PORT65_FN2),
1041 PINMUX_DATA(LCD0_RS_MARK, PORT65_FN4),
1042
1043 /* Port66 */
1044 PINMUX_DATA(MEMC_INT_MARK, PORT66_FN1),
1045 PINMUX_DATA(TPU0TO2_PORT66_MARK, PORT66_FN3, MSEL5CR_25_0),
1046 PINMUX_DATA(MMC0_CLK_PORT66_MARK, PORT66_FN4, MSEL4CR_15_0),
1047 PINMUX_DATA(SDHI1_CLK_MARK, PORT66_FN6),
1048
1049 /* Port67 - Port73 Function1 */
1050 PINMUX_DATA(MEMC_CS0_MARK, PORT67_FN1),
1051 PINMUX_DATA(MEMC_AD8_MARK, PORT68_FN1),
1052 PINMUX_DATA(MEMC_AD9_MARK, PORT69_FN1),
1053 PINMUX_DATA(MEMC_AD10_MARK, PORT70_FN1),
1054 PINMUX_DATA(MEMC_AD11_MARK, PORT71_FN1),
1055 PINMUX_DATA(MEMC_AD12_MARK, PORT72_FN1),
1056 PINMUX_DATA(MEMC_AD13_MARK, PORT73_FN1),
1057
1058 /* Port67 - Port73 Function2 */
1059 PINMUX_DATA(MSIOF1_SS1_PORT67_MARK, PORT67_FN2, MSEL4CR_10_1),
1060 PINMUX_DATA(MSIOF1_RSCK_MARK, PORT68_FN2),
1061 PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT69_FN2),
1062 PINMUX_DATA(MSIOF1_MCK0_MARK, PORT70_FN2),
1063 PINMUX_DATA(MSIOF1_MCK1_MARK, PORT71_FN2),
1064 PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK, PORT72_FN2, MSEL4CR_10_1),
1065 PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK, PORT73_FN2, MSEL4CR_10_1),
1066
1067 /* Port67 - Port73 Function4 */
1068 PINMUX_DATA(MMC0_CMD_PORT67_MARK, PORT67_FN4, MSEL4CR_15_0),
1069 PINMUX_DATA(MMC0_D0_PORT68_MARK, PORT68_FN4, MSEL4CR_15_0),
1070 PINMUX_DATA(MMC0_D1_PORT69_MARK, PORT69_FN4, MSEL4CR_15_0),
1071 PINMUX_DATA(MMC0_D2_PORT70_MARK, PORT70_FN4, MSEL4CR_15_0),
1072 PINMUX_DATA(MMC0_D3_PORT71_MARK, PORT71_FN4, MSEL4CR_15_0),
1073 PINMUX_DATA(MMC0_D4_PORT72_MARK, PORT72_FN4, MSEL4CR_15_0),
1074 PINMUX_DATA(MMC0_D5_PORT73_MARK, PORT73_FN4, MSEL4CR_15_0),
1075
1076 /* Port67 - Port73 Function6 */
1077 PINMUX_DATA(SDHI1_CMD_MARK, PORT67_FN6),
1078 PINMUX_DATA(SDHI1_D0_MARK, PORT68_FN6),
1079 PINMUX_DATA(SDHI1_D1_MARK, PORT69_FN6),
1080 PINMUX_DATA(SDHI1_D2_MARK, PORT70_FN6),
1081 PINMUX_DATA(SDHI1_D3_MARK, PORT71_FN6),
1082 PINMUX_DATA(SDHI1_CD_MARK, PORT72_FN6),
1083 PINMUX_DATA(SDHI1_WP_MARK, PORT73_FN6),
1084
1085 /* Port67 - Port71 IRQ */
1086 PINMUX_DATA(IRQ20_MARK, PORT67_FN0),
1087 PINMUX_DATA(IRQ16_PORT68_MARK, PORT68_FN0, MSEL1CR_16_0),
1088 PINMUX_DATA(IRQ17_MARK, PORT69_FN0),
1089 PINMUX_DATA(IRQ18_MARK, PORT70_FN0),
1090 PINMUX_DATA(IRQ19_MARK, PORT71_FN0),
1091
1092 /* Port74 */
1093 PINMUX_DATA(MEMC_AD14_MARK, PORT74_FN1),
1094 PINMUX_DATA(MSIOF1_TXD_PORT74_MARK, PORT74_FN2, MSEL4CR_10_1),
1095 PINMUX_DATA(MMC0_D6_PORT74_MARK, PORT74_FN4, MSEL4CR_15_0),
1096 PINMUX_DATA(STP1_IPD7_MARK, PORT74_FN6),
1097 PINMUX_DATA(LCD1_D21_MARK, PORT74_FN7),
1098
1099 /* Port75 */
1100 PINMUX_DATA(MEMC_AD15_MARK, PORT75_FN1),
1101 PINMUX_DATA(MSIOF1_RXD_PORT75_MARK, PORT75_FN2, MSEL4CR_10_1),
1102 PINMUX_DATA(MMC0_D7_PORT75_MARK, PORT75_FN4, MSEL4CR_15_0),
1103 PINMUX_DATA(STP1_IPD6_MARK, PORT75_FN6),
1104 PINMUX_DATA(LCD1_D20_MARK, PORT75_FN7),
1105
1106 /* Port76 - Port80 Function */
1107 PINMUX_DATA(SDHI0_CMD_MARK, PORT76_FN1),
1108 PINMUX_DATA(SDHI0_D0_MARK, PORT77_FN1),
1109 PINMUX_DATA(SDHI0_D1_MARK, PORT78_FN1),
1110 PINMUX_DATA(SDHI0_D2_MARK, PORT79_FN1),
1111 PINMUX_DATA(SDHI0_D3_MARK, PORT80_FN1),
1112
1113 /* Port81 */
1114 PINMUX_DATA(SDHI0_CD_MARK, PORT81_FN1),
1115 PINMUX_DATA(IRQ26_PORT81_MARK, PORT81_FN0, MSEL1CR_26_0),
1116
1117 /* Port82 - Port88 Function */
1118 PINMUX_DATA(SDHI0_CLK_MARK, PORT82_FN1),
1119 PINMUX_DATA(SDHI0_WP_MARK, PORT83_FN1),
1120 PINMUX_DATA(RESETOUTS_MARK, PORT84_FN1),
1121 PINMUX_DATA(USB0_PPON_MARK, PORT85_FN1),
1122 PINMUX_DATA(USB0_OCI_MARK, PORT86_FN1),
1123 PINMUX_DATA(USB1_PPON_MARK, PORT87_FN1),
1124 PINMUX_DATA(USB1_OCI_MARK, PORT88_FN1),
1125
1126 /* Port89 */
1127 PINMUX_DATA(DREQ0_MARK, PORT89_FN1),
1128 PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK, PORT89_FN2, MSEL5CR_0_1),
1129 PINMUX_DATA(RSPI_SSL3_A_MARK, PORT89_FN6),
1130
1131 /* Port90 */
1132 PINMUX_DATA(DACK0_MARK, PORT90_FN1),
1133 PINMUX_DATA(BBIF2_RXD2_PORT90_MARK, PORT90_FN2, MSEL5CR_0_1),
1134 PINMUX_DATA(RSPI_SSL2_A_MARK, PORT90_FN6),
1135 PINMUX_DATA(WAIT_PORT90_MARK, PORT90_FN7, MSEL5CR_2_1),
1136
1137 /* Port91 */
1138 PINMUX_DATA(MEMC_AD0_MARK, PORT91_FN1),
1139 PINMUX_DATA(BBIF1_RXD_MARK, PORT91_FN2),
1140 PINMUX_DATA(SCIFA5_TXD_PORT91_MARK, PORT91_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
1141 PINMUX_DATA(LCD1_D5_MARK, PORT91_FN7),
1142
1143 /* Port92 */
1144 PINMUX_DATA(MEMC_AD1_MARK, PORT92_FN1),
1145 PINMUX_DATA(BBIF1_TSYNC_MARK, PORT92_FN2),
1146 PINMUX_DATA(SCIFA5_RXD_PORT92_MARK, PORT92_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
1147 PINMUX_DATA(STP0_IPD1_MARK, PORT92_FN6),
1148 PINMUX_DATA(LCD1_D6_MARK, PORT92_FN7),
1149
1150 /* Port93 */
1151 PINMUX_DATA(MEMC_AD2_MARK, PORT93_FN1),
1152 PINMUX_DATA(BBIF1_TSCK_MARK, PORT93_FN2),
1153 PINMUX_DATA(SCIFA4_TXD_PORT93_MARK, PORT93_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
1154 PINMUX_DATA(STP0_IPD3_MARK, PORT93_FN6),
1155 PINMUX_DATA(LCD1_D8_MARK, PORT93_FN7),
1156
1157 /* Port94 */
1158 PINMUX_DATA(MEMC_AD3_MARK, PORT94_FN1),
1159 PINMUX_DATA(BBIF1_TXD_MARK, PORT94_FN2),
1160 PINMUX_DATA(SCIFA4_RXD_PORT94_MARK, PORT94_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
1161 PINMUX_DATA(STP0_IPD4_MARK, PORT94_FN6),
1162 PINMUX_DATA(LCD1_D9_MARK, PORT94_FN7),
1163
1164 /* Port95 */
1165 PINMUX_DATA(MEMC_CS1_MARK, PORT95_FN1, MSEL4CR_6_0),
1166 PINMUX_DATA(MEMC_A1_MARK, PORT95_FN1, MSEL4CR_6_1),
1167
1168 PINMUX_DATA(SCIFA2_CTS_MARK, PORT95_FN2),
1169 PINMUX_DATA(SIM_RST_MARK, PORT95_FN4),
1170 PINMUX_DATA(VIO0_D14_PORT95_MARK, PORT95_FN7, MSEL5CR_27_1),
1171 PINMUX_DATA(IRQ22_MARK, PORT95_FN0),
1172
1173 /* Port96 */
1174 PINMUX_DATA(MEMC_ADV_MARK, PORT96_FN1, MSEL4CR_6_0),
1175 PINMUX_DATA(MEMC_DREQ0_MARK, PORT96_FN1, MSEL4CR_6_1),
1176
1177 PINMUX_DATA(SCIFA2_RTS_MARK, PORT96_FN2),
1178 PINMUX_DATA(SIM_CLK_MARK, PORT96_FN4),
1179 PINMUX_DATA(VIO0_D15_PORT96_MARK, PORT96_FN7, MSEL5CR_27_1),
1180 PINMUX_DATA(IRQ23_MARK, PORT96_FN0),
1181
1182 /* Port97 */
1183 PINMUX_DATA(MEMC_AD4_MARK, PORT97_FN1),
1184 PINMUX_DATA(BBIF1_RSCK_MARK, PORT97_FN2),
1185 PINMUX_DATA(LCD1_CS_MARK, PORT97_FN6),
1186 PINMUX_DATA(LCD1_HSYN_MARK, PORT97_FN7),
1187 PINMUX_DATA(IRQ12_PORT97_MARK, PORT97_FN0, MSEL1CR_12_0),
1188
1189 /* Port98 */
1190 PINMUX_DATA(MEMC_AD5_MARK, PORT98_FN1),
1191 PINMUX_DATA(BBIF1_RSYNC_MARK, PORT98_FN2),
1192 PINMUX_DATA(LCD1_VSYN_MARK, PORT98_FN7),
1193 PINMUX_DATA(IRQ13_PORT98_MARK, PORT98_FN0, MSEL1CR_13_0),
1194
1195 /* Port99 */
1196 PINMUX_DATA(MEMC_AD6_MARK, PORT99_FN1),
1197 PINMUX_DATA(BBIF1_FLOW_MARK, PORT99_FN2),
1198 PINMUX_DATA(LCD1_WR_MARK, PORT99_FN6),
1199 PINMUX_DATA(LCD1_DCK_MARK, PORT99_FN7),
1200 PINMUX_DATA(IRQ14_PORT99_MARK, PORT99_FN0, MSEL1CR_14_0),
1201
1202 /* Port100 */
1203 PINMUX_DATA(MEMC_AD7_MARK, PORT100_FN1),
1204 PINMUX_DATA(BBIF1_RX_FLOW_N_MARK, PORT100_FN2),
1205 PINMUX_DATA(LCD1_DON_MARK, PORT100_FN7),
1206 PINMUX_DATA(IRQ15_PORT100_MARK, PORT100_FN0, MSEL1CR_15_0),
1207
1208 /* Port101 */
1209 PINMUX_DATA(FCE0_MARK, PORT101_FN1),
1210
1211 /* Port102 */
1212 PINMUX_DATA(FRB_MARK, PORT102_FN1),
1213 PINMUX_DATA(LCD0_LCLK_PORT102_MARK, PORT102_FN4, MSEL5CR_6_0),
1214
1215 /* Port103 */
1216 PINMUX_DATA(CS5B_MARK, PORT103_FN1),
1217 PINMUX_DATA(FCE1_MARK, PORT103_FN2),
1218 PINMUX_DATA(MMC1_CLK_PORT103_MARK, PORT103_FN3, MSEL4CR_15_1),
1219
1220 /* Port104 */
1221 PINMUX_DATA(CS6A_MARK, PORT104_FN1),
1222 PINMUX_DATA(MMC1_CMD_PORT104_MARK, PORT104_FN3, MSEL4CR_15_1),
1223 PINMUX_DATA(IRQ11_MARK, PORT104_FN0),
1224
1225 /* Port105 */
1226 PINMUX_DATA(CS5A_PORT105_MARK, PORT105_FN1, MSEL5CR_2_0),
1227 PINMUX_DATA(SCIFA3_RTS_PORT105_MARK, PORT105_FN4, MSEL5CR_8_0),
1228
1229 /* Port106 */
1230 PINMUX_DATA(IOIS16_MARK, PORT106_FN1),
1231 PINMUX_DATA(IDE_EXBUF_ENB_MARK, PORT106_FN6),
1232
1233 /* Port107 - Port115 Function */
1234 PINMUX_DATA(WE3_ICIOWR_MARK, PORT107_FN1),
1235 PINMUX_DATA(WE2_ICIORD_MARK, PORT108_FN1),
1236 PINMUX_DATA(CS0_MARK, PORT109_FN1),
1237 PINMUX_DATA(CS2_MARK, PORT110_FN1),
1238 PINMUX_DATA(CS4_MARK, PORT111_FN1),
1239 PINMUX_DATA(WE1_MARK, PORT112_FN1),
1240 PINMUX_DATA(WE0_FWE_MARK, PORT113_FN1),
1241 PINMUX_DATA(RDWR_MARK, PORT114_FN1),
1242 PINMUX_DATA(RD_FSC_MARK, PORT115_FN1),
1243
1244 /* Port116 */
1245 PINMUX_DATA(A25_MARK, PORT116_FN1),
1246 PINMUX_DATA(MSIOF0_SS2_MARK, PORT116_FN2),
1247 PINMUX_DATA(MSIOF1_SS2_PORT116_MARK, PORT116_FN3, MSEL4CR_10_0),
1248 PINMUX_DATA(SCIFA3_SCK_PORT116_MARK, PORT116_FN4, MSEL5CR_8_0),
1249 PINMUX_DATA(GPO1_MARK, PORT116_FN5),
1250
1251 /* Port117 */
1252 PINMUX_DATA(A24_MARK, PORT117_FN1),
1253 PINMUX_DATA(MSIOF0_SS1_MARK, PORT117_FN2),
1254 PINMUX_DATA(MSIOF1_SS1_PORT117_MARK, PORT117_FN3, MSEL4CR_10_0),
1255 PINMUX_DATA(SCIFA3_CTS_PORT117_MARK, PORT117_FN4, MSEL5CR_8_0),
1256 PINMUX_DATA(GPO0_MARK, PORT117_FN5),
1257
1258 /* Port118 */
1259 PINMUX_DATA(A23_MARK, PORT118_FN1),
1260 PINMUX_DATA(MSIOF0_MCK1_MARK, PORT118_FN2),
1261 PINMUX_DATA(MSIOF1_RXD_PORT118_MARK, PORT118_FN3, MSEL4CR_10_0),
1262 PINMUX_DATA(GPI1_MARK, PORT118_FN5),
1263 PINMUX_DATA(IRQ9_PORT118_MARK, PORT118_FN0, MSEL1CR_9_0),
1264
1265 /* Port119 */
1266 PINMUX_DATA(A22_MARK, PORT119_FN1),
1267 PINMUX_DATA(MSIOF0_MCK0_MARK, PORT119_FN2),
1268 PINMUX_DATA(MSIOF1_TXD_PORT119_MARK, PORT119_FN3, MSEL4CR_10_0),
1269 PINMUX_DATA(GPI0_MARK, PORT119_FN5),
1270 PINMUX_DATA(IRQ8_MARK, PORT119_FN0),
1271
1272 /* Port120 */
1273 PINMUX_DATA(A21_MARK, PORT120_FN1),
1274 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2),
1275 PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0),
1276 PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_1),
1277
1278 /* Port121 */
1279 PINMUX_DATA(A20_MARK, PORT121_FN1),
1280 PINMUX_DATA(MSIOF0_RSCK_MARK, PORT121_FN2),
1281 PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK, PORT121_FN3, MSEL4CR_10_0),
1282 PINMUX_DATA(IRQ6_PORT121_MARK, PORT121_FN0, MSEL1CR_6_0),
1283
1284 /* Port122 */
1285 PINMUX_DATA(A19_MARK, PORT122_FN1),
1286 PINMUX_DATA(MSIOF0_RXD_MARK, PORT122_FN2),
1287
1288 /* Port123 */
1289 PINMUX_DATA(A18_MARK, PORT123_FN1),
1290 PINMUX_DATA(MSIOF0_TSCK_MARK, PORT123_FN2),
1291
1292 /* Port124 */
1293 PINMUX_DATA(A17_MARK, PORT124_FN1),
1294 PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT124_FN2),
1295
1296 /* Port125 - Port141 Function */
1297 PINMUX_DATA(A16_MARK, PORT125_FN1),
1298 PINMUX_DATA(A15_MARK, PORT126_FN1),
1299 PINMUX_DATA(A14_MARK, PORT127_FN1),
1300 PINMUX_DATA(A13_MARK, PORT128_FN1),
1301 PINMUX_DATA(A12_MARK, PORT129_FN1),
1302 PINMUX_DATA(A11_MARK, PORT130_FN1),
1303 PINMUX_DATA(A10_MARK, PORT131_FN1),
1304 PINMUX_DATA(A9_MARK, PORT132_FN1),
1305 PINMUX_DATA(A8_MARK, PORT133_FN1),
1306 PINMUX_DATA(A7_MARK, PORT134_FN1),
1307 PINMUX_DATA(A6_MARK, PORT135_FN1),
1308 PINMUX_DATA(A5_FCDE_MARK, PORT136_FN1),
1309 PINMUX_DATA(A4_FOE_MARK, PORT137_FN1),
1310 PINMUX_DATA(A3_MARK, PORT138_FN1),
1311 PINMUX_DATA(A2_MARK, PORT139_FN1),
1312 PINMUX_DATA(A1_MARK, PORT140_FN1),
1313 PINMUX_DATA(CKO_MARK, PORT141_FN1),
1314
1315 /* Port142 - Port157 Function1 */
1316 PINMUX_DATA(D15_NAF15_MARK, PORT142_FN1),
1317 PINMUX_DATA(D14_NAF14_MARK, PORT143_FN1),
1318 PINMUX_DATA(D13_NAF13_MARK, PORT144_FN1),
1319 PINMUX_DATA(D12_NAF12_MARK, PORT145_FN1),
1320 PINMUX_DATA(D11_NAF11_MARK, PORT146_FN1),
1321 PINMUX_DATA(D10_NAF10_MARK, PORT147_FN1),
1322 PINMUX_DATA(D9_NAF9_MARK, PORT148_FN1),
1323 PINMUX_DATA(D8_NAF8_MARK, PORT149_FN1),
1324 PINMUX_DATA(D7_NAF7_MARK, PORT150_FN1),
1325 PINMUX_DATA(D6_NAF6_MARK, PORT151_FN1),
1326 PINMUX_DATA(D5_NAF5_MARK, PORT152_FN1),
1327 PINMUX_DATA(D4_NAF4_MARK, PORT153_FN1),
1328 PINMUX_DATA(D3_NAF3_MARK, PORT154_FN1),
1329 PINMUX_DATA(D2_NAF2_MARK, PORT155_FN1),
1330 PINMUX_DATA(D1_NAF1_MARK, PORT156_FN1),
1331 PINMUX_DATA(D0_NAF0_MARK, PORT157_FN1),
1332
1333 /* Port142 - Port149 Function3 */
1334 PINMUX_DATA(MMC1_D7_PORT142_MARK, PORT142_FN3, MSEL4CR_15_1),
1335 PINMUX_DATA(MMC1_D6_PORT143_MARK, PORT143_FN3, MSEL4CR_15_1),
1336 PINMUX_DATA(MMC1_D5_PORT144_MARK, PORT144_FN3, MSEL4CR_15_1),
1337 PINMUX_DATA(MMC1_D4_PORT145_MARK, PORT145_FN3, MSEL4CR_15_1),
1338 PINMUX_DATA(MMC1_D3_PORT146_MARK, PORT146_FN3, MSEL4CR_15_1),
1339 PINMUX_DATA(MMC1_D2_PORT147_MARK, PORT147_FN3, MSEL4CR_15_1),
1340 PINMUX_DATA(MMC1_D1_PORT148_MARK, PORT148_FN3, MSEL4CR_15_1),
1341 PINMUX_DATA(MMC1_D0_PORT149_MARK, PORT149_FN3, MSEL4CR_15_1),
1342
1343 /* Port158 */
1344 PINMUX_DATA(D31_MARK, PORT158_FN1),
1345 PINMUX_DATA(SCIFA3_SCK_PORT158_MARK, PORT158_FN2, MSEL5CR_8_1),
1346 PINMUX_DATA(RMII_REF125CK_MARK, PORT158_FN3),
1347 PINMUX_DATA(LCD0_D21_PORT158_MARK, PORT158_FN4, MSEL5CR_6_1),
1348 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT158_FN5),
1349 PINMUX_DATA(IDE_D15_MARK, PORT158_FN6),
1350
1351 /* Port159 */
1352 PINMUX_DATA(D30_MARK, PORT159_FN1),
1353 PINMUX_DATA(SCIFA3_RXD_PORT159_MARK, PORT159_FN2, MSEL5CR_8_1),
1354 PINMUX_DATA(RMII_REF50CK_MARK, PORT159_FN3),
1355 PINMUX_DATA(LCD0_D23_PORT159_MARK, PORT159_FN4, MSEL5CR_6_1),
1356 PINMUX_DATA(IDE_D14_MARK, PORT159_FN6),
1357
1358 /* Port160 */
1359 PINMUX_DATA(D29_MARK, PORT160_FN1),
1360 PINMUX_DATA(SCIFA3_TXD_PORT160_MARK, PORT160_FN2, MSEL5CR_8_1),
1361 PINMUX_DATA(LCD0_D22_PORT160_MARK, PORT160_FN4, MSEL5CR_6_1),
1362 PINMUX_DATA(VIO1_HD_MARK, PORT160_FN5),
1363 PINMUX_DATA(IDE_D13_MARK, PORT160_FN6),
1364
1365 /* Port161 */
1366 PINMUX_DATA(D28_MARK, PORT161_FN1),
1367 PINMUX_DATA(SCIFA3_RTS_PORT161_MARK, PORT161_FN2, MSEL5CR_8_1),
1368 PINMUX_DATA(ET_RX_DV_MARK, PORT161_FN3),
1369 PINMUX_DATA(LCD0_D20_PORT161_MARK, PORT161_FN4, MSEL5CR_6_1),
1370 PINMUX_DATA(IRDA_IN_MARK, PORT161_FN5),
1371 PINMUX_DATA(IDE_D12_MARK, PORT161_FN6),
1372
1373 /* Port162 */
1374 PINMUX_DATA(D27_MARK, PORT162_FN1),
1375 PINMUX_DATA(SCIFA3_CTS_PORT162_MARK, PORT162_FN2, MSEL5CR_8_1),
1376 PINMUX_DATA(LCD0_D19_PORT162_MARK, PORT162_FN4, MSEL5CR_6_1),
1377 PINMUX_DATA(IRDA_OUT_MARK, PORT162_FN5),
1378 PINMUX_DATA(IDE_D11_MARK, PORT162_FN6),
1379
1380 /* Port163 */
1381 PINMUX_DATA(D26_MARK, PORT163_FN1),
1382 PINMUX_DATA(MSIOF2_SS2_MARK, PORT163_FN2),
1383 PINMUX_DATA(ET_COL_MARK, PORT163_FN3),
1384 PINMUX_DATA(LCD0_D18_PORT163_MARK, PORT163_FN4, MSEL5CR_6_1),
1385 PINMUX_DATA(IROUT_MARK, PORT163_FN5),
1386 PINMUX_DATA(IDE_D10_MARK, PORT163_FN6),
1387
1388 /* Port164 */
1389 PINMUX_DATA(D25_MARK, PORT164_FN1),
1390 PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT164_FN2),
1391 PINMUX_DATA(ET_PHY_INT_MARK, PORT164_FN3),
1392 PINMUX_DATA(LCD0_RD_MARK, PORT164_FN4),
1393 PINMUX_DATA(IDE_D9_MARK, PORT164_FN6),
1394
1395 /* Port165 */
1396 PINMUX_DATA(D24_MARK, PORT165_FN1),
1397 PINMUX_DATA(MSIOF2_RXD_MARK, PORT165_FN2),
1398 PINMUX_DATA(LCD0_LCLK_PORT165_MARK, PORT165_FN4, MSEL5CR_6_1),
1399 PINMUX_DATA(IDE_D8_MARK, PORT165_FN6),
1400
1401 /* Port166 - Port171 Function1 */
1402 PINMUX_DATA(D21_MARK, PORT166_FN1),
1403 PINMUX_DATA(D20_MARK, PORT167_FN1),
1404 PINMUX_DATA(D19_MARK, PORT168_FN1),
1405 PINMUX_DATA(D18_MARK, PORT169_FN1),
1406 PINMUX_DATA(D17_MARK, PORT170_FN1),
1407 PINMUX_DATA(D16_MARK, PORT171_FN1),
1408
1409 /* Port166 - Port171 Function3 */
1410 PINMUX_DATA(ET_ETXD5_MARK, PORT166_FN3),
1411 PINMUX_DATA(ET_ETXD4_MARK, PORT167_FN3),
1412 PINMUX_DATA(ET_ETXD3_MARK, PORT168_FN3),
1413 PINMUX_DATA(ET_ETXD2_MARK, PORT169_FN3),
1414 PINMUX_DATA(ET_ETXD1_MARK, PORT170_FN3),
1415 PINMUX_DATA(ET_ETXD0_MARK, PORT171_FN3),
1416
1417 /* Port166 - Port171 Function6 */
1418 PINMUX_DATA(IDE_D5_MARK, PORT166_FN6),
1419 PINMUX_DATA(IDE_D4_MARK, PORT167_FN6),
1420 PINMUX_DATA(IDE_D3_MARK, PORT168_FN6),
1421 PINMUX_DATA(IDE_D2_MARK, PORT169_FN6),
1422 PINMUX_DATA(IDE_D1_MARK, PORT170_FN6),
1423 PINMUX_DATA(IDE_D0_MARK, PORT171_FN6),
1424
1425 /* Port167 - Port171 IRQ */
1426 PINMUX_DATA(IRQ31_PORT167_MARK, PORT167_FN0, MSEL1CR_31_0),
1427 PINMUX_DATA(IRQ27_PORT168_MARK, PORT168_FN0, MSEL1CR_27_0),
1428 PINMUX_DATA(IRQ28_PORT169_MARK, PORT169_FN0, MSEL1CR_28_0),
1429 PINMUX_DATA(IRQ29_PORT170_MARK, PORT170_FN0, MSEL1CR_29_0),
1430 PINMUX_DATA(IRQ30_PORT171_MARK, PORT171_FN0, MSEL1CR_30_0),
1431
1432 /* Port172 */
1433 PINMUX_DATA(D23_MARK, PORT172_FN1),
1434 PINMUX_DATA(SCIFB_RTS_PORT172_MARK, PORT172_FN2, MSEL5CR_17_1),
1435 PINMUX_DATA(ET_ETXD7_MARK, PORT172_FN3),
1436 PINMUX_DATA(IDE_D7_MARK, PORT172_FN6),
1437 PINMUX_DATA(IRQ4_PORT172_MARK, PORT172_FN0, MSEL1CR_4_1),
1438
1439 /* Port173 */
1440 PINMUX_DATA(D22_MARK, PORT173_FN1),
1441 PINMUX_DATA(SCIFB_CTS_PORT173_MARK, PORT173_FN2, MSEL5CR_17_1),
1442 PINMUX_DATA(ET_ETXD6_MARK, PORT173_FN3),
1443 PINMUX_DATA(IDE_D6_MARK, PORT173_FN6),
1444 PINMUX_DATA(IRQ6_PORT173_MARK, PORT173_FN0, MSEL1CR_6_1),
1445
1446 /* Port174 */
1447 PINMUX_DATA(A26_MARK, PORT174_FN1),
1448 PINMUX_DATA(MSIOF0_TXD_MARK, PORT174_FN2),
1449 PINMUX_DATA(ET_RX_CLK_MARK, PORT174_FN3),
1450 PINMUX_DATA(SCIFA3_RXD_PORT174_MARK, PORT174_FN4, MSEL5CR_8_0),
1451
1452 /* Port175 */
1453 PINMUX_DATA(A0_MARK, PORT175_FN1),
1454 PINMUX_DATA(BS_MARK, PORT175_FN2),
1455 PINMUX_DATA(ET_WOL_MARK, PORT175_FN3),
1456 PINMUX_DATA(SCIFA3_TXD_PORT175_MARK, PORT175_FN4, MSEL5CR_8_0),
1457
1458 /* Port176 */
1459 PINMUX_DATA(ET_GTX_CLK_MARK, PORT176_FN3),
1460
1461 /* Port177 */
1462 PINMUX_DATA(WAIT_PORT177_MARK, PORT177_FN1, MSEL5CR_2_0),
1463 PINMUX_DATA(ET_LINK_MARK, PORT177_FN3),
1464 PINMUX_DATA(IDE_IOWR_MARK, PORT177_FN6),
1465 PINMUX_DATA(SDHI2_WP_PORT177_MARK, PORT177_FN7, MSEL5CR_19_1),
1466
1467 /* Port178 */
1468 PINMUX_DATA(VIO0_D12_MARK, PORT178_FN1),
1469 PINMUX_DATA(VIO1_D4_MARK, PORT178_FN5),
1470 PINMUX_DATA(IDE_IORD_MARK, PORT178_FN6),
1471
1472 /* Port179 */
1473 PINMUX_DATA(VIO0_D11_MARK, PORT179_FN1),
1474 PINMUX_DATA(VIO1_D3_MARK, PORT179_FN5),
1475 PINMUX_DATA(IDE_IORDY_MARK, PORT179_FN6),
1476
1477 /* Port180 */
1478 PINMUX_DATA(VIO0_D10_MARK, PORT180_FN1),
1479 PINMUX_DATA(TPU0TO3_MARK, PORT180_FN4),
1480 PINMUX_DATA(VIO1_D2_MARK, PORT180_FN5),
1481 PINMUX_DATA(IDE_INT_MARK, PORT180_FN6),
1482 PINMUX_DATA(IRQ24_MARK, PORT180_FN0),
1483
1484 /* Port181 */
1485 PINMUX_DATA(VIO0_D9_MARK, PORT181_FN1),
1486 PINMUX_DATA(VIO1_D1_MARK, PORT181_FN5),
1487 PINMUX_DATA(IDE_RST_MARK, PORT181_FN6),
1488
1489 /* Port182 */
1490 PINMUX_DATA(VIO0_D8_MARK, PORT182_FN1),
1491 PINMUX_DATA(VIO1_D0_MARK, PORT182_FN5),
1492 PINMUX_DATA(IDE_DIRECTION_MARK, PORT182_FN6),
1493
1494 /* Port183 */
1495 PINMUX_DATA(DREQ1_MARK, PORT183_FN1),
1496 PINMUX_DATA(BBIF2_TXD2_PORT183_MARK, PORT183_FN2, MSEL5CR_0_1),
1497 PINMUX_DATA(ET_TX_EN_MARK, PORT183_FN3),
1498
1499 /* Port184 */
1500 PINMUX_DATA(DACK1_MARK, PORT184_FN1),
1501 PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK, PORT184_FN2, MSEL5CR_0_1),
1502 PINMUX_DATA(ET_TX_CLK_MARK, PORT184_FN3),
1503
1504 /* Port185 - Port192 Function1 */
1505 PINMUX_DATA(SCIFA1_SCK_MARK, PORT185_FN1),
1506 PINMUX_DATA(SCIFB_RTS_PORT186_MARK, PORT186_FN1, MSEL5CR_17_0),
1507 PINMUX_DATA(SCIFB_CTS_PORT187_MARK, PORT187_FN1, MSEL5CR_17_0),
1508 PINMUX_DATA(SCIFA0_SCK_MARK, PORT188_FN1),
1509 PINMUX_DATA(SCIFB_SCK_PORT190_MARK, PORT190_FN1, MSEL5CR_17_0),
1510 PINMUX_DATA(SCIFB_RXD_PORT191_MARK, PORT191_FN1, MSEL5CR_17_0),
1511 PINMUX_DATA(SCIFB_TXD_PORT192_MARK, PORT192_FN1, MSEL5CR_17_0),
1512
1513 /* Port185 - Port192 Function3 */
1514 PINMUX_DATA(ET_ERXD0_MARK, PORT185_FN3),
1515 PINMUX_DATA(ET_ERXD1_MARK, PORT186_FN3),
1516 PINMUX_DATA(ET_ERXD2_MARK, PORT187_FN3),
1517 PINMUX_DATA(ET_ERXD3_MARK, PORT188_FN3),
1518 PINMUX_DATA(ET_ERXD4_MARK, PORT189_FN3),
1519 PINMUX_DATA(ET_ERXD5_MARK, PORT190_FN3),
1520 PINMUX_DATA(ET_ERXD6_MARK, PORT191_FN3),
1521 PINMUX_DATA(ET_ERXD7_MARK, PORT192_FN3),
1522
1523 /* Port185 - Port192 Function6 */
1524 PINMUX_DATA(STP1_IPCLK_MARK, PORT185_FN6),
1525 PINMUX_DATA(STP1_IPD0_PORT186_MARK, PORT186_FN6, MSEL5CR_23_0),
1526 PINMUX_DATA(STP1_IPEN_PORT187_MARK, PORT187_FN6, MSEL5CR_23_0),
1527 PINMUX_DATA(STP1_IPSYNC_MARK, PORT188_FN6),
1528 PINMUX_DATA(STP0_IPCLK_MARK, PORT189_FN6),
1529 PINMUX_DATA(STP0_IPD0_MARK, PORT190_FN6),
1530 PINMUX_DATA(STP0_IPEN_MARK, PORT191_FN6),
1531 PINMUX_DATA(STP0_IPSYNC_MARK, PORT192_FN6),
1532
1533 /* Port193 */
1534 PINMUX_DATA(SCIFA0_CTS_MARK, PORT193_FN1),
1535 PINMUX_DATA(RMII_CRS_DV_MARK, PORT193_FN3),
1536 PINMUX_DATA(STP1_IPEN_PORT193_MARK, PORT193_FN6, MSEL5CR_23_1), /* ? */
1537 PINMUX_DATA(LCD1_D17_MARK, PORT193_FN7),
1538
1539 /* Port194 */
1540 PINMUX_DATA(SCIFA0_RTS_MARK, PORT194_FN1),
1541 PINMUX_DATA(RMII_RX_ER_MARK, PORT194_FN3),
1542 PINMUX_DATA(STP1_IPD0_PORT194_MARK, PORT194_FN6, MSEL5CR_23_1), /* ? */
1543 PINMUX_DATA(LCD1_D16_MARK, PORT194_FN7),
1544
1545 /* Port195 */
1546 PINMUX_DATA(SCIFA1_RXD_MARK, PORT195_FN1),
1547 PINMUX_DATA(RMII_RXD0_MARK, PORT195_FN3),
1548 PINMUX_DATA(STP1_IPD3_MARK, PORT195_FN6),
1549 PINMUX_DATA(LCD1_D15_MARK, PORT195_FN7),
1550
1551 /* Port196 */
1552 PINMUX_DATA(SCIFA1_TXD_MARK, PORT196_FN1),
1553 PINMUX_DATA(RMII_RXD1_MARK, PORT196_FN3),
1554 PINMUX_DATA(STP1_IPD2_MARK, PORT196_FN6),
1555 PINMUX_DATA(LCD1_D14_MARK, PORT196_FN7),
1556
1557 /* Port197 */
1558 PINMUX_DATA(SCIFA0_RXD_MARK, PORT197_FN1),
1559 PINMUX_DATA(VIO1_CLK_MARK, PORT197_FN5),
1560 PINMUX_DATA(STP1_IPD5_MARK, PORT197_FN6),
1561 PINMUX_DATA(LCD1_D19_MARK, PORT197_FN7),
1562
1563 /* Port198 */
1564 PINMUX_DATA(SCIFA0_TXD_MARK, PORT198_FN1),
1565 PINMUX_DATA(VIO1_VD_MARK, PORT198_FN5),
1566 PINMUX_DATA(STP1_IPD4_MARK, PORT198_FN6),
1567 PINMUX_DATA(LCD1_D18_MARK, PORT198_FN7),
1568
1569 /* Port199 */
1570 PINMUX_DATA(MEMC_NWE_MARK, PORT199_FN1),
1571 PINMUX_DATA(SCIFA2_SCK_PORT199_MARK, PORT199_FN2, MSEL5CR_7_1),
1572 PINMUX_DATA(RMII_TX_EN_MARK, PORT199_FN3),
1573 PINMUX_DATA(SIM_D_PORT199_MARK, PORT199_FN4, MSEL5CR_21_1),
1574 PINMUX_DATA(STP1_IPD1_MARK, PORT199_FN6),
1575 PINMUX_DATA(LCD1_D13_MARK, PORT199_FN7),
1576
1577 /* Port200 */
1578 PINMUX_DATA(MEMC_NOE_MARK, PORT200_FN1),
1579 PINMUX_DATA(SCIFA2_RXD_MARK, PORT200_FN2),
1580 PINMUX_DATA(RMII_TXD0_MARK, PORT200_FN3),
1581 PINMUX_DATA(STP0_IPD7_MARK, PORT200_FN6),
1582 PINMUX_DATA(LCD1_D12_MARK, PORT200_FN7),
1583
1584 /* Port201 */
1585 PINMUX_DATA(MEMC_WAIT_MARK, PORT201_FN1, MSEL4CR_6_0),
1586 PINMUX_DATA(MEMC_DREQ1_MARK, PORT201_FN1, MSEL4CR_6_1),
1587
1588 PINMUX_DATA(SCIFA2_TXD_MARK, PORT201_FN2),
1589 PINMUX_DATA(RMII_TXD1_MARK, PORT201_FN3),
1590 PINMUX_DATA(STP0_IPD6_MARK, PORT201_FN6),
1591 PINMUX_DATA(LCD1_D11_MARK, PORT201_FN7),
1592
1593 /* Port202 */
1594 PINMUX_DATA(MEMC_BUSCLK_MARK, PORT202_FN1, MSEL4CR_6_0),
1595 PINMUX_DATA(MEMC_A0_MARK, PORT202_FN1, MSEL4CR_6_1),
1596
1597 PINMUX_DATA(MSIOF1_SS2_PORT202_MARK, PORT202_FN2, MSEL4CR_10_1),
1598 PINMUX_DATA(RMII_MDC_MARK, PORT202_FN3),
1599 PINMUX_DATA(TPU0TO2_PORT202_MARK, PORT202_FN4, MSEL5CR_25_1),
1600 PINMUX_DATA(IDE_CS0_MARK, PORT202_FN6),
1601 PINMUX_DATA(SDHI2_CD_PORT202_MARK, PORT202_FN7, MSEL5CR_19_1),
1602 PINMUX_DATA(IRQ21_MARK, PORT202_FN0),
1603
1604 /* Port203 - Port208 Function1 */
1605 PINMUX_DATA(SDHI2_CLK_MARK, PORT203_FN1),
1606 PINMUX_DATA(SDHI2_CMD_MARK, PORT204_FN1),
1607 PINMUX_DATA(SDHI2_D0_MARK, PORT205_FN1),
1608 PINMUX_DATA(SDHI2_D1_MARK, PORT206_FN1),
1609 PINMUX_DATA(SDHI2_D2_MARK, PORT207_FN1),
1610 PINMUX_DATA(SDHI2_D3_MARK, PORT208_FN1),
1611
1612 /* Port203 - Port208 Function3 */
1613 PINMUX_DATA(ET_TX_ER_MARK, PORT203_FN3),
1614 PINMUX_DATA(ET_RX_ER_MARK, PORT204_FN3),
1615 PINMUX_DATA(ET_CRS_MARK, PORT205_FN3),
1616 PINMUX_DATA(ET_MDC_MARK, PORT206_FN3),
1617 PINMUX_DATA(ET_MDIO_MARK, PORT207_FN3),
1618 PINMUX_DATA(RMII_MDIO_MARK, PORT208_FN3),
1619
1620 /* Port203 - Port208 Function6 */
1621 PINMUX_DATA(IDE_A2_MARK, PORT203_FN6),
1622 PINMUX_DATA(IDE_A1_MARK, PORT204_FN6),
1623 PINMUX_DATA(IDE_A0_MARK, PORT205_FN6),
1624 PINMUX_DATA(IDE_IODACK_MARK, PORT206_FN6),
1625 PINMUX_DATA(IDE_IODREQ_MARK, PORT207_FN6),
1626 PINMUX_DATA(IDE_CS1_MARK, PORT208_FN6),
1627
1628 /* Port203 - Port208 Function7 */
1629 PINMUX_DATA(SCIFA4_TXD_PORT203_MARK, PORT203_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
1630 PINMUX_DATA(SCIFA4_RXD_PORT204_MARK, PORT204_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
1631 PINMUX_DATA(SCIFA4_SCK_PORT205_MARK, PORT205_FN7, MSEL5CR_10_1),
1632 PINMUX_DATA(SCIFA5_SCK_PORT206_MARK, PORT206_FN7, MSEL5CR_13_1),
1633 PINMUX_DATA(SCIFA5_RXD_PORT207_MARK, PORT207_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
1634 PINMUX_DATA(SCIFA5_TXD_PORT208_MARK, PORT208_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
1635
1636 /* Port209 */
1637 PINMUX_DATA(VBUS_MARK, PORT209_FN1),
1638 PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_0),
1639
1640 /* Port210 */
1641 PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1),
1642 PINMUX_DATA(HDMI_HPD_MARK, PORT210_FN1),
1643
1644 /* Port211 */
1645 PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1),
1646 PINMUX_DATA(HDMI_CEC_MARK, PORT211_FN1),
1647
1648 /* SDENC */
1649 PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0),
1650 PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
1651
1652 /* SYSC */
1653 PINMUX_DATA(RESETP_PULLUP_MARK, MSEL4CR_4_0),
1654 PINMUX_DATA(RESETP_PLAIN_MARK, MSEL4CR_4_1),
1655
1656 /* DEBUG */
1657 PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK, MSEL4CR_1_0),
1658 PINMUX_DATA(EDEBGREQ_PULLUP_MARK, MSEL4CR_1_1),
1659
1660 PINMUX_DATA(TRACEAUD_FROM_VIO_MARK, MSEL5CR_30_0, MSEL5CR_29_0),
1661 PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK, MSEL5CR_30_0, MSEL5CR_29_1),
1662 PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
1663 };
1664
1665 static struct sh_pfc_pin pinmux_pins[] = {
1666 GPIO_PORT_ALL(),
1667 };
1668
1669 /* - BSC -------------------------------------------------------------------- */
1670 static const unsigned int bsc_data8_pins[] = {
1671 /* D[0:7] */
1672 157, 156, 155, 154, 153, 152, 151, 150,
1673 };
1674 static const unsigned int bsc_data8_mux[] = {
1675 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1676 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1677 };
1678 static const unsigned int bsc_data16_pins[] = {
1679 /* D[0:15] */
1680 157, 156, 155, 154, 153, 152, 151, 150,
1681 149, 148, 147, 146, 145, 144, 143, 142,
1682 };
1683 static const unsigned int bsc_data16_mux[] = {
1684 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1685 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1686 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1687 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1688 };
1689 static const unsigned int bsc_data32_pins[] = {
1690 /* D[0:31] */
1691 157, 156, 155, 154, 153, 152, 151, 150,
1692 149, 148, 147, 146, 145, 144, 143, 142,
1693 171, 170, 169, 168, 167, 166, 173, 172,
1694 165, 164, 163, 162, 161, 160, 159, 158,
1695 };
1696 static const unsigned int bsc_data32_mux[] = {
1697 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1698 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1699 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1700 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1701 D16_MARK, D17_MARK, D18_MARK, D19_MARK,
1702 D20_MARK, D21_MARK, D22_MARK, D23_MARK,
1703 D24_MARK, D25_MARK, D26_MARK, D27_MARK,
1704 D28_MARK, D29_MARK, D30_MARK, D31_MARK,
1705 };
1706 static const unsigned int bsc_cs0_pins[] = {
1707 /* CS */
1708 109,
1709 };
1710 static const unsigned int bsc_cs0_mux[] = {
1711 CS0_MARK,
1712 };
1713 static const unsigned int bsc_cs2_pins[] = {
1714 /* CS */
1715 110,
1716 };
1717 static const unsigned int bsc_cs2_mux[] = {
1718 CS2_MARK,
1719 };
1720 static const unsigned int bsc_cs4_pins[] = {
1721 /* CS */
1722 111,
1723 };
1724 static const unsigned int bsc_cs4_mux[] = {
1725 CS4_MARK,
1726 };
1727 static const unsigned int bsc_cs5a_0_pins[] = {
1728 /* CS */
1729 105,
1730 };
1731 static const unsigned int bsc_cs5a_0_mux[] = {
1732 CS5A_PORT105_MARK,
1733 };
1734 static const unsigned int bsc_cs5a_1_pins[] = {
1735 /* CS */
1736 19,
1737 };
1738 static const unsigned int bsc_cs5a_1_mux[] = {
1739 CS5A_PORT19_MARK,
1740 };
1741 static const unsigned int bsc_cs5b_pins[] = {
1742 /* CS */
1743 103,
1744 };
1745 static const unsigned int bsc_cs5b_mux[] = {
1746 CS5B_MARK,
1747 };
1748 static const unsigned int bsc_cs6a_pins[] = {
1749 /* CS */
1750 104,
1751 };
1752 static const unsigned int bsc_cs6a_mux[] = {
1753 CS6A_MARK,
1754 };
1755 static const unsigned int bsc_rd_we8_pins[] = {
1756 /* RD, WE[0] */
1757 115, 113,
1758 };
1759 static const unsigned int bsc_rd_we8_mux[] = {
1760 RD_FSC_MARK, WE0_FWE_MARK,
1761 };
1762 static const unsigned int bsc_rd_we16_pins[] = {
1763 /* RD, WE[0:1] */
1764 115, 113, 112,
1765 };
1766 static const unsigned int bsc_rd_we16_mux[] = {
1767 RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
1768 };
1769 static const unsigned int bsc_rd_we32_pins[] = {
1770 /* RD, WE[0:3] */
1771 115, 113, 112, 108, 107,
1772 };
1773 static const unsigned int bsc_rd_we32_mux[] = {
1774 RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK,
1775 };
1776 static const unsigned int bsc_bs_pins[] = {
1777 /* BS */
1778 175,
1779 };
1780 static const unsigned int bsc_bs_mux[] = {
1781 BS_MARK,
1782 };
1783 static const unsigned int bsc_rdwr_pins[] = {
1784 /* RDWR */
1785 114,
1786 };
1787 static const unsigned int bsc_rdwr_mux[] = {
1788 RDWR_MARK,
1789 };
1790 /* - CEU0 ------------------------------------------------------------------- */
1791 static const unsigned int ceu0_data_0_7_pins[] = {
1792 /* D[0:7] */
1793 34, 33, 32, 31, 30, 29, 28, 27,
1794 };
1795 static const unsigned int ceu0_data_0_7_mux[] = {
1796 VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
1797 VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
1798 };
1799 static const unsigned int ceu0_data_8_15_0_pins[] = {
1800 /* D[8:15] */
1801 182, 181, 180, 179, 178, 26, 25, 24,
1802 };
1803 static const unsigned int ceu0_data_8_15_0_mux[] = {
1804 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
1805 VIO0_D12_MARK, VIO0_D13_PORT26_MARK, VIO0_D14_PORT25_MARK,
1806 VIO0_D15_PORT24_MARK,
1807 };
1808 static const unsigned int ceu0_data_8_15_1_pins[] = {
1809 /* D[8:15] */
1810 182, 181, 180, 179, 178, 22, 95, 96,
1811 };
1812 static const unsigned int ceu0_data_8_15_1_mux[] = {
1813 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
1814 VIO0_D12_MARK, VIO0_D13_PORT22_MARK, VIO0_D14_PORT95_MARK,
1815 VIO0_D15_PORT96_MARK,
1816 };
1817 static const unsigned int ceu0_clk_0_pins[] = {
1818 /* CKO */
1819 36,
1820 };
1821 static const unsigned int ceu0_clk_0_mux[] = {
1822 VIO_CKO_MARK,
1823 };
1824 static const unsigned int ceu0_clk_1_pins[] = {
1825 /* CKO */
1826 14,
1827 };
1828 static const unsigned int ceu0_clk_1_mux[] = {
1829 VIO_CKO1_MARK,
1830 };
1831 static const unsigned int ceu0_clk_2_pins[] = {
1832 /* CKO */
1833 15,
1834 };
1835 static const unsigned int ceu0_clk_2_mux[] = {
1836 VIO_CKO2_MARK,
1837 };
1838 static const unsigned int ceu0_sync_pins[] = {
1839 /* CLK, VD, HD */
1840 35, 39, 37,
1841 };
1842 static const unsigned int ceu0_sync_mux[] = {
1843 VIO0_CLK_MARK, VIO0_VD_MARK, VIO0_HD_MARK,
1844 };
1845 static const unsigned int ceu0_field_pins[] = {
1846 /* FIELD */
1847 38,
1848 };
1849 static const unsigned int ceu0_field_mux[] = {
1850 VIO0_FIELD_MARK,
1851 };
1852 /* - CEU1 ------------------------------------------------------------------- */
1853 static const unsigned int ceu1_data_pins[] = {
1854 /* D[0:7] */
1855 182, 181, 180, 179, 178, 26, 25, 24,
1856 };
1857 static const unsigned int ceu1_data_mux[] = {
1858 VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
1859 VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
1860 };
1861 static const unsigned int ceu1_clk_pins[] = {
1862 /* CKO */
1863 23,
1864 };
1865 static const unsigned int ceu1_clk_mux[] = {
1866 VIO_CKO_1_MARK,
1867 };
1868 static const unsigned int ceu1_sync_pins[] = {
1869 /* CLK, VD, HD */
1870 197, 198, 160,
1871 };
1872 static const unsigned int ceu1_sync_mux[] = {
1873 VIO1_CLK_MARK, VIO1_VD_MARK, VIO1_HD_MARK,
1874 };
1875 static const unsigned int ceu1_field_pins[] = {
1876 /* FIELD */
1877 21,
1878 };
1879 static const unsigned int ceu1_field_mux[] = {
1880 VIO1_FIELD_MARK,
1881 };
1882 /* - FSIA ------------------------------------------------------------------- */
1883 static const unsigned int fsia_mclk_in_pins[] = {
1884 /* CK */
1885 11,
1886 };
1887 static const unsigned int fsia_mclk_in_mux[] = {
1888 FSIACK_MARK,
1889 };
1890 static const unsigned int fsia_mclk_out_pins[] = {
1891 /* OMC */
1892 10,
1893 };
1894 static const unsigned int fsia_mclk_out_mux[] = {
1895 FSIAOMC_MARK,
1896 };
1897 static const unsigned int fsia_sclk_in_pins[] = {
1898 /* ILR, IBT */
1899 12, 13,
1900 };
1901 static const unsigned int fsia_sclk_in_mux[] = {
1902 FSIAILR_MARK, FSIAIBT_MARK,
1903 };
1904 static const unsigned int fsia_sclk_out_pins[] = {
1905 /* OLR, OBT */
1906 7, 8,
1907 };
1908 static const unsigned int fsia_sclk_out_mux[] = {
1909 FSIAOLR_MARK, FSIAOBT_MARK,
1910 };
1911 static const unsigned int fsia_data_in_0_pins[] = {
1912 /* ISLD */
1913 0,
1914 };
1915 static const unsigned int fsia_data_in_0_mux[] = {
1916 FSIAISLD_PORT0_MARK,
1917 };
1918 static const unsigned int fsia_data_in_1_pins[] = {
1919 /* ISLD */
1920 5,
1921 };
1922 static const unsigned int fsia_data_in_1_mux[] = {
1923 FSIAISLD_PORT5_MARK,
1924 };
1925 static const unsigned int fsia_data_out_0_pins[] = {
1926 /* OSLD */
1927 9,
1928 };
1929 static const unsigned int fsia_data_out_0_mux[] = {
1930 FSIAOSLD_MARK,
1931 };
1932 static const unsigned int fsia_data_out_1_pins[] = {
1933 /* OSLD */
1934 0,
1935 };
1936 static const unsigned int fsia_data_out_1_mux[] = {
1937 FSIAOSLD1_MARK,
1938 };
1939 static const unsigned int fsia_data_out_2_pins[] = {
1940 /* OSLD */
1941 1,
1942 };
1943 static const unsigned int fsia_data_out_2_mux[] = {
1944 FSIAOSLD2_MARK,
1945 };
1946 static const unsigned int fsia_spdif_0_pins[] = {
1947 /* SPDIF */
1948 9,
1949 };
1950 static const unsigned int fsia_spdif_0_mux[] = {
1951 FSIASPDIF_PORT9_MARK,
1952 };
1953 static const unsigned int fsia_spdif_1_pins[] = {
1954 /* SPDIF */
1955 18,
1956 };
1957 static const unsigned int fsia_spdif_1_mux[] = {
1958 FSIASPDIF_PORT18_MARK,
1959 };
1960 /* - FSIB ------------------------------------------------------------------- */
1961 static const unsigned int fsib_mclk_in_pins[] = {
1962 /* CK */
1963 11,
1964 };
1965 static const unsigned int fsib_mclk_in_mux[] = {
1966 FSIBCK_MARK,
1967 };
1968 /* - GETHER ----------------------------------------------------------------- */
1969 static const unsigned int gether_rmii_pins[] = {
1970 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */
1971 195, 196, 194, 193, 200, 201, 199, 159, 202, 208,
1972 };
1973 static const unsigned int gether_rmii_mux[] = {
1974 RMII_RXD0_MARK, RMII_RXD1_MARK, RMII_RX_ER_MARK, RMII_CRS_DV_MARK,
1975 RMII_TXD0_MARK, RMII_TXD1_MARK, RMII_TX_EN_MARK, RMII_REF50CK_MARK,
1976 RMII_MDC_MARK, RMII_MDIO_MARK,
1977 };
1978 static const unsigned int gether_mii_pins[] = {
1979 /* RXD[0:3], RX_CLK, RX_DV, RX_ER
1980 * TXD[0:3], TX_CLK, TX_EN, TX_ER
1981 * CRS, COL, MDC, MDIO,
1982 */
1983 185, 186, 187, 188, 174, 161, 204,
1984 171, 170, 169, 168, 184, 183, 203,
1985 205, 163, 206, 207,
1986 };
1987 static const unsigned int gether_mii_mux[] = {
1988 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
1989 ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
1990 ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
1991 ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
1992 ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
1993 };
1994 static const unsigned int gether_gmii_pins[] = {
1995 /* RXD[0:7], RX_CLK, RX_DV, RX_ER
1996 * TXD[0:7], GTX_CLK, TX_CLK, TX_EN, TX_ER
1997 * CRS, COL, MDC, MDIO, REF125CK_MARK,
1998 */
1999 185, 186, 187, 188, 189, 190, 191, 192, 174, 161, 204,
2000 171, 170, 169, 168, 167, 166, 173, 172, 176, 184, 183, 203,
2001 205, 163, 206, 207,
2002 };
2003 static const unsigned int gether_gmii_mux[] = {
2004 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
2005 ET_ERXD4_MARK, ET_ERXD5_MARK, ET_ERXD6_MARK, ET_ERXD7_MARK,
2006 ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
2007 ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
2008 ET_ETXD4_MARK, ET_ETXD5_MARK, ET_ETXD6_MARK, ET_ETXD7_MARK,
2009 ET_GTX_CLK_MARK, ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
2010 ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
2011 RMII_REF125CK_MARK,
2012 };
2013 static const unsigned int gether_int_pins[] = {
2014 /* PHY_INT */
2015 164,
2016 };
2017 static const unsigned int gether_int_mux[] = {
2018 ET_PHY_INT_MARK,
2019 };
2020 static const unsigned int gether_link_pins[] = {
2021 /* LINK */
2022 177,
2023 };
2024 static const unsigned int gether_link_mux[] = {
2025 ET_LINK_MARK,
2026 };
2027 static const unsigned int gether_wol_pins[] = {
2028 /* WOL */
2029 175,
2030 };
2031 static const unsigned int gether_wol_mux[] = {
2032 ET_WOL_MARK,
2033 };
2034 /* - HDMI ------------------------------------------------------------------- */
2035 static const unsigned int hdmi_pins[] = {
2036 /* HPD, CEC */
2037 210, 211,
2038 };
2039 static const unsigned int hdmi_mux[] = {
2040 HDMI_HPD_MARK, HDMI_CEC_MARK,
2041 };
2042 /* - INTC ------------------------------------------------------------------- */
2043 IRQC_PINS_MUX(0, 0, 2);
2044 IRQC_PINS_MUX(0, 1, 13);
2045 IRQC_PIN_MUX(1, 20);
2046 IRQC_PINS_MUX(2, 0, 11);
2047 IRQC_PINS_MUX(2, 1, 12);
2048 IRQC_PINS_MUX(3, 0, 10);
2049 IRQC_PINS_MUX(3, 1, 14);
2050 IRQC_PINS_MUX(4, 0, 15);
2051 IRQC_PINS_MUX(4, 1, 172);
2052 IRQC_PINS_MUX(5, 0, 0);
2053 IRQC_PINS_MUX(5, 1, 1);
2054 IRQC_PINS_MUX(6, 0, 121);
2055 IRQC_PINS_MUX(6, 1, 173);
2056 IRQC_PINS_MUX(7, 0, 120);
2057 IRQC_PINS_MUX(7, 1, 209);
2058 IRQC_PIN_MUX(8, 119);
2059 IRQC_PINS_MUX(9, 0, 118);
2060 IRQC_PINS_MUX(9, 1, 210);
2061 IRQC_PIN_MUX(10, 19);
2062 IRQC_PIN_MUX(11, 104);
2063 IRQC_PINS_MUX(12, 0, 42);
2064 IRQC_PINS_MUX(12, 1, 97);
2065 IRQC_PINS_MUX(13, 0, 64);
2066 IRQC_PINS_MUX(13, 1, 98);
2067 IRQC_PINS_MUX(14, 0, 63);
2068 IRQC_PINS_MUX(14, 1, 99);
2069 IRQC_PINS_MUX(15, 0, 62);
2070 IRQC_PINS_MUX(15, 1, 100);
2071 IRQC_PINS_MUX(16, 0, 68);
2072 IRQC_PINS_MUX(16, 1, 211);
2073 IRQC_PIN_MUX(17, 69);
2074 IRQC_PIN_MUX(18, 70);
2075 IRQC_PIN_MUX(19, 71);
2076 IRQC_PIN_MUX(20, 67);
2077 IRQC_PIN_MUX(21, 202);
2078 IRQC_PIN_MUX(22, 95);
2079 IRQC_PIN_MUX(23, 96);
2080 IRQC_PIN_MUX(24, 180);
2081 IRQC_PIN_MUX(25, 38);
2082 IRQC_PINS_MUX(26, 0, 58);
2083 IRQC_PINS_MUX(26, 1, 81);
2084 IRQC_PINS_MUX(27, 0, 57);
2085 IRQC_PINS_MUX(27, 1, 168);
2086 IRQC_PINS_MUX(28, 0, 56);
2087 IRQC_PINS_MUX(28, 1, 169);
2088 IRQC_PINS_MUX(29, 0, 50);
2089 IRQC_PINS_MUX(29, 1, 170);
2090 IRQC_PINS_MUX(30, 0, 49);
2091 IRQC_PINS_MUX(30, 1, 171);
2092 IRQC_PINS_MUX(31, 0, 41);
2093 IRQC_PINS_MUX(31, 1, 167);
2094
2095 /* - LCD0 ------------------------------------------------------------------- */
2096 static const unsigned int lcd0_data8_pins[] = {
2097 /* D[0:7] */
2098 58, 57, 56, 55, 54, 53, 52, 51,
2099 };
2100 static const unsigned int lcd0_data8_mux[] = {
2101 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2102 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2103 };
2104 static const unsigned int lcd0_data9_pins[] = {
2105 /* D[0:8] */
2106 58, 57, 56, 55, 54, 53, 52, 51,
2107 50,
2108 };
2109 static const unsigned int lcd0_data9_mux[] = {
2110 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2111 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2112 LCD0_D8_MARK,
2113 };
2114 static const unsigned int lcd0_data12_pins[] = {
2115 /* D[0:11] */
2116 58, 57, 56, 55, 54, 53, 52, 51,
2117 50, 49, 48, 47,
2118 };
2119 static const unsigned int lcd0_data12_mux[] = {
2120 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2121 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2122 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2123 };
2124 static const unsigned int lcd0_data16_pins[] = {
2125 /* D[0:15] */
2126 58, 57, 56, 55, 54, 53, 52, 51,
2127 50, 49, 48, 47, 46, 45, 44, 43,
2128 };
2129 static const unsigned int lcd0_data16_mux[] = {
2130 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2131 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2132 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2133 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2134 };
2135 static const unsigned int lcd0_data18_pins[] = {
2136 /* D[0:17] */
2137 58, 57, 56, 55, 54, 53, 52, 51,
2138 50, 49, 48, 47, 46, 45, 44, 43,
2139 42, 41,
2140 };
2141 static const unsigned int lcd0_data18_mux[] = {
2142 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2143 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2144 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2145 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2146 LCD0_D16_MARK, LCD0_D17_MARK,
2147 };
2148 static const unsigned int lcd0_data24_0_pins[] = {
2149 /* D[0:23] */
2150 58, 57, 56, 55, 54, 53, 52, 51,
2151 50, 49, 48, 47, 46, 45, 44, 43,
2152 42, 41, 40, 4, 3, 2, 0, 1,
2153 };
2154 static const unsigned int lcd0_data24_0_mux[] = {
2155 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2156 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2157 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2158 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2159 LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT40_MARK, LCD0_D19_PORT4_MARK,
2160 LCD0_D20_PORT3_MARK, LCD0_D21_PORT2_MARK, LCD0_D22_PORT0_MARK,
2161 LCD0_D23_PORT1_MARK,
2162 };
2163 static const unsigned int lcd0_data24_1_pins[] = {
2164 /* D[0:23] */
2165 58, 57, 56, 55, 54, 53, 52, 51,
2166 50, 49, 48, 47, 46, 45, 44, 43,
2167 42, 41, 163, 162, 161, 158, 160, 159,
2168 };
2169 static const unsigned int lcd0_data24_1_mux[] = {
2170 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2171 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2172 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2173 LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK,
2174 LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK,
2175 LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK,
2176 };
2177 static const unsigned int lcd0_display_pins[] = {
2178 /* DON, VCPWC, VEPWC */
2179 61, 59, 60,
2180 };
2181 static const unsigned int lcd0_display_mux[] = {
2182 LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
2183 };
2184 static const unsigned int lcd0_lclk_0_pins[] = {
2185 /* LCLK */
2186 102,
2187 };
2188 static const unsigned int lcd0_lclk_0_mux[] = {
2189 LCD0_LCLK_PORT102_MARK,
2190 };
2191 static const unsigned int lcd0_lclk_1_pins[] = {
2192 /* LCLK */
2193 165,
2194 };
2195 static const unsigned int lcd0_lclk_1_mux[] = {
2196 LCD0_LCLK_PORT165_MARK,
2197 };
2198 static const unsigned int lcd0_sync_pins[] = {
2199 /* VSYN, HSYN, DCK, DISP */
2200 63, 64, 62, 65,
2201 };
2202 static const unsigned int lcd0_sync_mux[] = {
2203 LCD0_VSYN_MARK, LCD0_HSYN_MARK, LCD0_DCK_MARK, LCD0_DISP_MARK,
2204 };
2205 static const unsigned int lcd0_sys_pins[] = {
2206 /* CS, WR, RD, RS */
2207 64, 62, 164, 65,
2208 };
2209 static const unsigned int lcd0_sys_mux[] = {
2210 LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK,
2211 };
2212 /* - LCD1 ------------------------------------------------------------------- */
2213 static const unsigned int lcd1_data8_pins[] = {
2214 /* D[0:7] */
2215 4, 3, 2, 1, 0, 91, 92, 23,
2216 };
2217 static const unsigned int lcd1_data8_mux[] = {
2218 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2219 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2220 };
2221 static const unsigned int lcd1_data9_pins[] = {
2222 /* D[0:8] */
2223 4, 3, 2, 1, 0, 91, 92, 23,
2224 93,
2225 };
2226 static const unsigned int lcd1_data9_mux[] = {
2227 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2228 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2229 LCD1_D8_MARK,
2230 };
2231 static const unsigned int lcd1_data12_pins[] = {
2232 /* D[0:12] */
2233 4, 3, 2, 1, 0, 91, 92, 23,
2234 93, 94, 21, 201,
2235 };
2236 static const unsigned int lcd1_data12_mux[] = {
2237 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2238 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2239 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2240 };
2241 static const unsigned int lcd1_data16_pins[] = {
2242 /* D[0:15] */
2243 4, 3, 2, 1, 0, 91, 92, 23,
2244 93, 94, 21, 201, 200, 199, 196, 195,
2245 };
2246 static const unsigned int lcd1_data16_mux[] = {
2247 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2248 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2249 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2250 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2251 };
2252 static const unsigned int lcd1_data18_pins[] = {
2253 /* D[0:17] */
2254 4, 3, 2, 1, 0, 91, 92, 23,
2255 93, 94, 21, 201, 200, 199, 196, 195,
2256 194, 193,
2257 };
2258 static const unsigned int lcd1_data18_mux[] = {
2259 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2260 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2261 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2262 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2263 LCD1_D16_MARK, LCD1_D17_MARK,
2264 };
2265 static const unsigned int lcd1_data24_pins[] = {
2266 /* D[0:23] */
2267 4, 3, 2, 1, 0, 91, 92, 23,
2268 93, 94, 21, 201, 200, 199, 196, 195,
2269 194, 193, 198, 197, 75, 74, 15, 14,
2270 };
2271 static const unsigned int lcd1_data24_mux[] = {
2272 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2273 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2274 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2275 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2276 LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
2277 LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
2278 };
2279 static const unsigned int lcd1_display_pins[] = {
2280 /* DON, VCPWC, VEPWC */
2281 100, 5, 6,
2282 };
2283 static const unsigned int lcd1_display_mux[] = {
2284 LCD1_DON_MARK, LCD1_VCPWC_MARK, LCD1_VEPWC_MARK,
2285 };
2286 static const unsigned int lcd1_lclk_pins[] = {
2287 /* LCLK */
2288 40,
2289 };
2290 static const unsigned int lcd1_lclk_mux[] = {
2291 LCD1_LCLK_MARK,
2292 };
2293 static const unsigned int lcd1_sync_pins[] = {
2294 /* VSYN, HSYN, DCK, DISP */
2295 98, 97, 99, 12,
2296 };
2297 static const unsigned int lcd1_sync_mux[] = {
2298 LCD1_VSYN_MARK, LCD1_HSYN_MARK, LCD1_DCK_MARK, LCD1_DISP_MARK,
2299 };
2300 static const unsigned int lcd1_sys_pins[] = {
2301 /* CS, WR, RD, RS */
2302 97, 99, 13, 12,
2303 };
2304 static const unsigned int lcd1_sys_mux[] = {
2305 LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
2306 };
2307 /* - MMCIF ------------------------------------------------------------------ */
2308 static const unsigned int mmc0_data1_0_pins[] = {
2309 /* D[0] */
2310 68,
2311 };
2312 static const unsigned int mmc0_data1_0_mux[] = {
2313 MMC0_D0_PORT68_MARK,
2314 };
2315 static const unsigned int mmc0_data4_0_pins[] = {
2316 /* D[0:3] */
2317 68, 69, 70, 71,
2318 };
2319 static const unsigned int mmc0_data4_0_mux[] = {
2320 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
2321 };
2322 static const unsigned int mmc0_data8_0_pins[] = {
2323 /* D[0:7] */
2324 68, 69, 70, 71, 72, 73, 74, 75,
2325 };
2326 static const unsigned int mmc0_data8_0_mux[] = {
2327 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
2328 MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
2329 };
2330 static const unsigned int mmc0_ctrl_0_pins[] = {
2331 /* CMD, CLK */
2332 67, 66,
2333 };
2334 static const unsigned int mmc0_ctrl_0_mux[] = {
2335 MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
2336 };
2337
2338 static const unsigned int mmc0_data1_1_pins[] = {
2339 /* D[0] */
2340 149,
2341 };
2342 static const unsigned int mmc0_data1_1_mux[] = {
2343 MMC1_D0_PORT149_MARK,
2344 };
2345 static const unsigned int mmc0_data4_1_pins[] = {
2346 /* D[0:3] */
2347 149, 148, 147, 146,
2348 };
2349 static const unsigned int mmc0_data4_1_mux[] = {
2350 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
2351 };
2352 static const unsigned int mmc0_data8_1_pins[] = {
2353 /* D[0:7] */
2354 149, 148, 147, 146, 145, 144, 143, 142,
2355 };
2356 static const unsigned int mmc0_data8_1_mux[] = {
2357 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
2358 MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
2359 };
2360 static const unsigned int mmc0_ctrl_1_pins[] = {
2361 /* CMD, CLK */
2362 104, 103,
2363 };
2364 static const unsigned int mmc0_ctrl_1_mux[] = {
2365 MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
2366 };
2367 /* - SCIFA0 ----------------------------------------------------------------- */
2368 static const unsigned int scifa0_data_pins[] = {
2369 /* RXD, TXD */
2370 197, 198,
2371 };
2372 static const unsigned int scifa0_data_mux[] = {
2373 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2374 };
2375 static const unsigned int scifa0_clk_pins[] = {
2376 /* SCK */
2377 188,
2378 };
2379 static const unsigned int scifa0_clk_mux[] = {
2380 SCIFA0_SCK_MARK,
2381 };
2382 static const unsigned int scifa0_ctrl_pins[] = {
2383 /* RTS, CTS */
2384 194, 193,
2385 };
2386 static const unsigned int scifa0_ctrl_mux[] = {
2387 SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
2388 };
2389 /* - SCIFA1 ----------------------------------------------------------------- */
2390 static const unsigned int scifa1_data_pins[] = {
2391 /* RXD, TXD */
2392 195, 196,
2393 };
2394 static const unsigned int scifa1_data_mux[] = {
2395 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2396 };
2397 static const unsigned int scifa1_clk_pins[] = {
2398 /* SCK */
2399 185,
2400 };
2401 static const unsigned int scifa1_clk_mux[] = {
2402 SCIFA1_SCK_MARK,
2403 };
2404 static const unsigned int scifa1_ctrl_pins[] = {
2405 /* RTS, CTS */
2406 23, 21,
2407 };
2408 static const unsigned int scifa1_ctrl_mux[] = {
2409 SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
2410 };
2411 /* - SCIFA2 ----------------------------------------------------------------- */
2412 static const unsigned int scifa2_data_pins[] = {
2413 /* RXD, TXD */
2414 200, 201,
2415 };
2416 static const unsigned int scifa2_data_mux[] = {
2417 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2418 };
2419 static const unsigned int scifa2_clk_0_pins[] = {
2420 /* SCK */
2421 22,
2422 };
2423 static const unsigned int scifa2_clk_0_mux[] = {
2424 SCIFA2_SCK_PORT22_MARK,
2425 };
2426 static const unsigned int scifa2_clk_1_pins[] = {
2427 /* SCK */
2428 199,
2429 };
2430 static const unsigned int scifa2_clk_1_mux[] = {
2431 SCIFA2_SCK_PORT199_MARK,
2432 };
2433 static const unsigned int scifa2_ctrl_pins[] = {
2434 /* RTS, CTS */
2435 96, 95,
2436 };
2437 static const unsigned int scifa2_ctrl_mux[] = {
2438 SCIFA2_RTS_MARK, SCIFA2_CTS_MARK,
2439 };
2440 /* - SCIFA3 ----------------------------------------------------------------- */
2441 static const unsigned int scifa3_data_0_pins[] = {
2442 /* RXD, TXD */
2443 174, 175,
2444 };
2445 static const unsigned int scifa3_data_0_mux[] = {
2446 SCIFA3_RXD_PORT174_MARK, SCIFA3_TXD_PORT175_MARK,
2447 };
2448 static const unsigned int scifa3_clk_0_pins[] = {
2449 /* SCK */
2450 116,
2451 };
2452 static const unsigned int scifa3_clk_0_mux[] = {
2453 SCIFA3_SCK_PORT116_MARK,
2454 };
2455 static const unsigned int scifa3_ctrl_0_pins[] = {
2456 /* RTS, CTS */
2457 105, 117,
2458 };
2459 static const unsigned int scifa3_ctrl_0_mux[] = {
2460 SCIFA3_RTS_PORT105_MARK, SCIFA3_CTS_PORT117_MARK,
2461 };
2462 static const unsigned int scifa3_data_1_pins[] = {
2463 /* RXD, TXD */
2464 159, 160,
2465 };
2466 static const unsigned int scifa3_data_1_mux[] = {
2467 SCIFA3_RXD_PORT159_MARK, SCIFA3_TXD_PORT160_MARK,
2468 };
2469 static const unsigned int scifa3_clk_1_pins[] = {
2470 /* SCK */
2471 158,
2472 };
2473 static const unsigned int scifa3_clk_1_mux[] = {
2474 SCIFA3_SCK_PORT158_MARK,
2475 };
2476 static const unsigned int scifa3_ctrl_1_pins[] = {
2477 /* RTS, CTS */
2478 161, 162,
2479 };
2480 static const unsigned int scifa3_ctrl_1_mux[] = {
2481 SCIFA3_RTS_PORT161_MARK, SCIFA3_CTS_PORT162_MARK,
2482 };
2483 /* - SCIFA4 ----------------------------------------------------------------- */
2484 static const unsigned int scifa4_data_0_pins[] = {
2485 /* RXD, TXD */
2486 12, 13,
2487 };
2488 static const unsigned int scifa4_data_0_mux[] = {
2489 SCIFA4_RXD_PORT12_MARK, SCIFA4_TXD_PORT13_MARK,
2490 };
2491 static const unsigned int scifa4_data_1_pins[] = {
2492 /* RXD, TXD */
2493 204, 203,
2494 };
2495 static const unsigned int scifa4_data_1_mux[] = {
2496 SCIFA4_RXD_PORT204_MARK, SCIFA4_TXD_PORT203_MARK,
2497 };
2498 static const unsigned int scifa4_data_2_pins[] = {
2499 /* RXD, TXD */
2500 94, 93,
2501 };
2502 static const unsigned int scifa4_data_2_mux[] = {
2503 SCIFA4_RXD_PORT94_MARK, SCIFA4_TXD_PORT93_MARK,
2504 };
2505 static const unsigned int scifa4_clk_0_pins[] = {
2506 /* SCK */
2507 21,
2508 };
2509 static const unsigned int scifa4_clk_0_mux[] = {
2510 SCIFA4_SCK_PORT21_MARK,
2511 };
2512 static const unsigned int scifa4_clk_1_pins[] = {
2513 /* SCK */
2514 205,
2515 };
2516 static const unsigned int scifa4_clk_1_mux[] = {
2517 SCIFA4_SCK_PORT205_MARK,
2518 };
2519 /* - SCIFA5 ----------------------------------------------------------------- */
2520 static const unsigned int scifa5_data_0_pins[] = {
2521 /* RXD, TXD */
2522 10, 20,
2523 };
2524 static const unsigned int scifa5_data_0_mux[] = {
2525 SCIFA5_RXD_PORT10_MARK, SCIFA5_TXD_PORT20_MARK,
2526 };
2527 static const unsigned int scifa5_data_1_pins[] = {
2528 /* RXD, TXD */
2529 207, 208,
2530 };
2531 static const unsigned int scifa5_data_1_mux[] = {
2532 SCIFA5_RXD_PORT207_MARK, SCIFA5_TXD_PORT208_MARK,
2533 };
2534 static const unsigned int scifa5_data_2_pins[] = {
2535 /* RXD, TXD */
2536 92, 91,
2537 };
2538 static const unsigned int scifa5_data_2_mux[] = {
2539 SCIFA5_RXD_PORT92_MARK, SCIFA5_TXD_PORT91_MARK,
2540 };
2541 static const unsigned int scifa5_clk_0_pins[] = {
2542 /* SCK */
2543 23,
2544 };
2545 static const unsigned int scifa5_clk_0_mux[] = {
2546 SCIFA5_SCK_PORT23_MARK,
2547 };
2548 static const unsigned int scifa5_clk_1_pins[] = {
2549 /* SCK */
2550 206,
2551 };
2552 static const unsigned int scifa5_clk_1_mux[] = {
2553 SCIFA5_SCK_PORT206_MARK,
2554 };
2555 /* - SCIFA6 ----------------------------------------------------------------- */
2556 static const unsigned int scifa6_data_pins[] = {
2557 /* RXD, TXD */
2558 25, 26,
2559 };
2560 static const unsigned int scifa6_data_mux[] = {
2561 SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
2562 };
2563 static const unsigned int scifa6_clk_pins[] = {
2564 /* SCK */
2565 24,
2566 };
2567 static const unsigned int scifa6_clk_mux[] = {
2568 SCIFA6_SCK_MARK,
2569 };
2570 /* - SCIFA7 ----------------------------------------------------------------- */
2571 static const unsigned int scifa7_data_pins[] = {
2572 /* RXD, TXD */
2573 0, 1,
2574 };
2575 static const unsigned int scifa7_data_mux[] = {
2576 SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
2577 };
2578 /* - SCIFB ------------------------------------------------------------------ */
2579 static const unsigned int scifb_data_0_pins[] = {
2580 /* RXD, TXD */
2581 191, 192,
2582 };
2583 static const unsigned int scifb_data_0_mux[] = {
2584 SCIFB_RXD_PORT191_MARK, SCIFB_TXD_PORT192_MARK,
2585 };
2586 static const unsigned int scifb_clk_0_pins[] = {
2587 /* SCK */
2588 190,
2589 };
2590 static const unsigned int scifb_clk_0_mux[] = {
2591 SCIFB_SCK_PORT190_MARK,
2592 };
2593 static const unsigned int scifb_ctrl_0_pins[] = {
2594 /* RTS, CTS */
2595 186, 187,
2596 };
2597 static const unsigned int scifb_ctrl_0_mux[] = {
2598 SCIFB_RTS_PORT186_MARK, SCIFB_CTS_PORT187_MARK,
2599 };
2600 static const unsigned int scifb_data_1_pins[] = {
2601 /* RXD, TXD */
2602 3, 4,
2603 };
2604 static const unsigned int scifb_data_1_mux[] = {
2605 SCIFB_RXD_PORT3_MARK, SCIFB_TXD_PORT4_MARK,
2606 };
2607 static const unsigned int scifb_clk_1_pins[] = {
2608 /* SCK */
2609 2,
2610 };
2611 static const unsigned int scifb_clk_1_mux[] = {
2612 SCIFB_SCK_PORT2_MARK,
2613 };
2614 static const unsigned int scifb_ctrl_1_pins[] = {
2615 /* RTS, CTS */
2616 172, 173,
2617 };
2618 static const unsigned int scifb_ctrl_1_mux[] = {
2619 SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK,
2620 };
2621 /* - SDHI0 ------------------------------------------------------------------ */
2622 static const unsigned int sdhi0_data1_pins[] = {
2623 /* D0 */
2624 77,
2625 };
2626 static const unsigned int sdhi0_data1_mux[] = {
2627 SDHI0_D0_MARK,
2628 };
2629 static const unsigned int sdhi0_data4_pins[] = {
2630 /* D[0:3] */
2631 77, 78, 79, 80,
2632 };
2633 static const unsigned int sdhi0_data4_mux[] = {
2634 SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
2635 };
2636 static const unsigned int sdhi0_ctrl_pins[] = {
2637 /* CMD, CLK */
2638 76, 82,
2639 };
2640 static const unsigned int sdhi0_ctrl_mux[] = {
2641 SDHI0_CMD_MARK, SDHI0_CLK_MARK,
2642 };
2643 static const unsigned int sdhi0_cd_pins[] = {
2644 /* CD */
2645 81,
2646 };
2647 static const unsigned int sdhi0_cd_mux[] = {
2648 SDHI0_CD_MARK,
2649 };
2650 static const unsigned int sdhi0_wp_pins[] = {
2651 /* WP */
2652 83,
2653 };
2654 static const unsigned int sdhi0_wp_mux[] = {
2655 SDHI0_WP_MARK,
2656 };
2657 /* - SDHI1 ------------------------------------------------------------------ */
2658 static const unsigned int sdhi1_data1_pins[] = {
2659 /* D0 */
2660 68,
2661 };
2662 static const unsigned int sdhi1_data1_mux[] = {
2663 SDHI1_D0_MARK,
2664 };
2665 static const unsigned int sdhi1_data4_pins[] = {
2666 /* D[0:3] */
2667 68, 69, 70, 71,
2668 };
2669 static const unsigned int sdhi1_data4_mux[] = {
2670 SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
2671 };
2672 static const unsigned int sdhi1_ctrl_pins[] = {
2673 /* CMD, CLK */
2674 67, 66,
2675 };
2676 static const unsigned int sdhi1_ctrl_mux[] = {
2677 SDHI1_CMD_MARK, SDHI1_CLK_MARK,
2678 };
2679 static const unsigned int sdhi1_cd_pins[] = {
2680 /* CD */
2681 72,
2682 };
2683 static const unsigned int sdhi1_cd_mux[] = {
2684 SDHI1_CD_MARK,
2685 };
2686 static const unsigned int sdhi1_wp_pins[] = {
2687 /* WP */
2688 73,
2689 };
2690 static const unsigned int sdhi1_wp_mux[] = {
2691 SDHI1_WP_MARK,
2692 };
2693 /* - SDHI2 ------------------------------------------------------------------ */
2694 static const unsigned int sdhi2_data1_pins[] = {
2695 /* D0 */
2696 205,
2697 };
2698 static const unsigned int sdhi2_data1_mux[] = {
2699 SDHI2_D0_MARK,
2700 };
2701 static const unsigned int sdhi2_data4_pins[] = {
2702 /* D[0:3] */
2703 205, 206, 207, 208,
2704 };
2705 static const unsigned int sdhi2_data4_mux[] = {
2706 SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
2707 };
2708 static const unsigned int sdhi2_ctrl_pins[] = {
2709 /* CMD, CLK */
2710 204, 203,
2711 };
2712 static const unsigned int sdhi2_ctrl_mux[] = {
2713 SDHI2_CMD_MARK, SDHI2_CLK_MARK,
2714 };
2715 static const unsigned int sdhi2_cd_0_pins[] = {
2716 /* CD */
2717 202,
2718 };
2719 static const unsigned int sdhi2_cd_0_mux[] = {
2720 SDHI2_CD_PORT202_MARK,
2721 };
2722 static const unsigned int sdhi2_wp_0_pins[] = {
2723 /* WP */
2724 177,
2725 };
2726 static const unsigned int sdhi2_wp_0_mux[] = {
2727 SDHI2_WP_PORT177_MARK,
2728 };
2729 static const unsigned int sdhi2_cd_1_pins[] = {
2730 /* CD */
2731 24,
2732 };
2733 static const unsigned int sdhi2_cd_1_mux[] = {
2734 SDHI2_CD_PORT24_MARK,
2735 };
2736 static const unsigned int sdhi2_wp_1_pins[] = {
2737 /* WP */
2738 25,
2739 };
2740 static const unsigned int sdhi2_wp_1_mux[] = {
2741 SDHI2_WP_PORT25_MARK,
2742 };
2743
2744 static const struct sh_pfc_pin_group pinmux_groups[] = {
2745 SH_PFC_PIN_GROUP(bsc_data8),
2746 SH_PFC_PIN_GROUP(bsc_data16),
2747 SH_PFC_PIN_GROUP(bsc_data32),
2748 SH_PFC_PIN_GROUP(bsc_cs0),
2749 SH_PFC_PIN_GROUP(bsc_cs2),
2750 SH_PFC_PIN_GROUP(bsc_cs4),
2751 SH_PFC_PIN_GROUP(bsc_cs5a_0),
2752 SH_PFC_PIN_GROUP(bsc_cs5a_1),
2753 SH_PFC_PIN_GROUP(bsc_cs5b),
2754 SH_PFC_PIN_GROUP(bsc_cs6a),
2755 SH_PFC_PIN_GROUP(bsc_rd_we8),
2756 SH_PFC_PIN_GROUP(bsc_rd_we16),
2757 SH_PFC_PIN_GROUP(bsc_rd_we32),
2758 SH_PFC_PIN_GROUP(bsc_bs),
2759 SH_PFC_PIN_GROUP(bsc_rdwr),
2760 SH_PFC_PIN_GROUP(ceu0_data_0_7),
2761 SH_PFC_PIN_GROUP(ceu0_data_8_15_0),
2762 SH_PFC_PIN_GROUP(ceu0_data_8_15_1),
2763 SH_PFC_PIN_GROUP(ceu0_clk_0),
2764 SH_PFC_PIN_GROUP(ceu0_clk_1),
2765 SH_PFC_PIN_GROUP(ceu0_clk_2),
2766 SH_PFC_PIN_GROUP(ceu0_sync),
2767 SH_PFC_PIN_GROUP(ceu0_field),
2768 SH_PFC_PIN_GROUP(ceu1_data),
2769 SH_PFC_PIN_GROUP(ceu1_clk),
2770 SH_PFC_PIN_GROUP(ceu1_sync),
2771 SH_PFC_PIN_GROUP(ceu1_field),
2772 SH_PFC_PIN_GROUP(fsia_mclk_in),
2773 SH_PFC_PIN_GROUP(fsia_mclk_out),
2774 SH_PFC_PIN_GROUP(fsia_sclk_in),
2775 SH_PFC_PIN_GROUP(fsia_sclk_out),
2776 SH_PFC_PIN_GROUP(fsia_data_in_0),
2777 SH_PFC_PIN_GROUP(fsia_data_in_1),
2778 SH_PFC_PIN_GROUP(fsia_data_out_0),
2779 SH_PFC_PIN_GROUP(fsia_data_out_1),
2780 SH_PFC_PIN_GROUP(fsia_data_out_2),
2781 SH_PFC_PIN_GROUP(fsia_spdif_0),
2782 SH_PFC_PIN_GROUP(fsia_spdif_1),
2783 SH_PFC_PIN_GROUP(fsib_mclk_in),
2784 SH_PFC_PIN_GROUP(gether_rmii),
2785 SH_PFC_PIN_GROUP(gether_mii),
2786 SH_PFC_PIN_GROUP(gether_gmii),
2787 SH_PFC_PIN_GROUP(gether_int),
2788 SH_PFC_PIN_GROUP(gether_link),
2789 SH_PFC_PIN_GROUP(gether_wol),
2790 SH_PFC_PIN_GROUP(hdmi),
2791 SH_PFC_PIN_GROUP(intc_irq0_0),
2792 SH_PFC_PIN_GROUP(intc_irq0_1),
2793 SH_PFC_PIN_GROUP(intc_irq1),
2794 SH_PFC_PIN_GROUP(intc_irq2_0),
2795 SH_PFC_PIN_GROUP(intc_irq2_1),
2796 SH_PFC_PIN_GROUP(intc_irq3_0),
2797 SH_PFC_PIN_GROUP(intc_irq3_1),
2798 SH_PFC_PIN_GROUP(intc_irq4_0),
2799 SH_PFC_PIN_GROUP(intc_irq4_1),
2800 SH_PFC_PIN_GROUP(intc_irq5_0),
2801 SH_PFC_PIN_GROUP(intc_irq5_1),
2802 SH_PFC_PIN_GROUP(intc_irq6_0),
2803 SH_PFC_PIN_GROUP(intc_irq6_1),
2804 SH_PFC_PIN_GROUP(intc_irq7_0),
2805 SH_PFC_PIN_GROUP(intc_irq7_1),
2806 SH_PFC_PIN_GROUP(intc_irq8),
2807 SH_PFC_PIN_GROUP(intc_irq9_0),
2808 SH_PFC_PIN_GROUP(intc_irq9_1),
2809 SH_PFC_PIN_GROUP(intc_irq10),
2810 SH_PFC_PIN_GROUP(intc_irq11),
2811 SH_PFC_PIN_GROUP(intc_irq12_0),
2812 SH_PFC_PIN_GROUP(intc_irq12_1),
2813 SH_PFC_PIN_GROUP(intc_irq13_0),
2814 SH_PFC_PIN_GROUP(intc_irq13_1),
2815 SH_PFC_PIN_GROUP(intc_irq14_0),
2816 SH_PFC_PIN_GROUP(intc_irq14_1),
2817 SH_PFC_PIN_GROUP(intc_irq15_0),
2818 SH_PFC_PIN_GROUP(intc_irq15_1),
2819 SH_PFC_PIN_GROUP(intc_irq16_0),
2820 SH_PFC_PIN_GROUP(intc_irq16_1),
2821 SH_PFC_PIN_GROUP(intc_irq17),
2822 SH_PFC_PIN_GROUP(intc_irq18),
2823 SH_PFC_PIN_GROUP(intc_irq19),
2824 SH_PFC_PIN_GROUP(intc_irq20),
2825 SH_PFC_PIN_GROUP(intc_irq21),
2826 SH_PFC_PIN_GROUP(intc_irq22),
2827 SH_PFC_PIN_GROUP(intc_irq23),
2828 SH_PFC_PIN_GROUP(intc_irq24),
2829 SH_PFC_PIN_GROUP(intc_irq25),
2830 SH_PFC_PIN_GROUP(intc_irq26_0),
2831 SH_PFC_PIN_GROUP(intc_irq26_1),
2832 SH_PFC_PIN_GROUP(intc_irq27_0),
2833 SH_PFC_PIN_GROUP(intc_irq27_1),
2834 SH_PFC_PIN_GROUP(intc_irq28_0),
2835 SH_PFC_PIN_GROUP(intc_irq28_1),
2836 SH_PFC_PIN_GROUP(intc_irq29_0),
2837 SH_PFC_PIN_GROUP(intc_irq29_1),
2838 SH_PFC_PIN_GROUP(intc_irq30_0),
2839 SH_PFC_PIN_GROUP(intc_irq30_1),
2840 SH_PFC_PIN_GROUP(intc_irq31_0),
2841 SH_PFC_PIN_GROUP(intc_irq31_1),
2842 SH_PFC_PIN_GROUP(lcd0_data8),
2843 SH_PFC_PIN_GROUP(lcd0_data9),
2844 SH_PFC_PIN_GROUP(lcd0_data12),
2845 SH_PFC_PIN_GROUP(lcd0_data16),
2846 SH_PFC_PIN_GROUP(lcd0_data18),
2847 SH_PFC_PIN_GROUP(lcd0_data24_0),
2848 SH_PFC_PIN_GROUP(lcd0_data24_1),
2849 SH_PFC_PIN_GROUP(lcd0_display),
2850 SH_PFC_PIN_GROUP(lcd0_lclk_0),
2851 SH_PFC_PIN_GROUP(lcd0_lclk_1),
2852 SH_PFC_PIN_GROUP(lcd0_sync),
2853 SH_PFC_PIN_GROUP(lcd0_sys),
2854 SH_PFC_PIN_GROUP(lcd1_data8),
2855 SH_PFC_PIN_GROUP(lcd1_data9),
2856 SH_PFC_PIN_GROUP(lcd1_data12),
2857 SH_PFC_PIN_GROUP(lcd1_data16),
2858 SH_PFC_PIN_GROUP(lcd1_data18),
2859 SH_PFC_PIN_GROUP(lcd1_data24),
2860 SH_PFC_PIN_GROUP(lcd1_display),
2861 SH_PFC_PIN_GROUP(lcd1_lclk),
2862 SH_PFC_PIN_GROUP(lcd1_sync),
2863 SH_PFC_PIN_GROUP(lcd1_sys),
2864 SH_PFC_PIN_GROUP(mmc0_data1_0),
2865 SH_PFC_PIN_GROUP(mmc0_data4_0),
2866 SH_PFC_PIN_GROUP(mmc0_data8_0),
2867 SH_PFC_PIN_GROUP(mmc0_ctrl_0),
2868 SH_PFC_PIN_GROUP(mmc0_data1_1),
2869 SH_PFC_PIN_GROUP(mmc0_data4_1),
2870 SH_PFC_PIN_GROUP(mmc0_data8_1),
2871 SH_PFC_PIN_GROUP(mmc0_ctrl_1),
2872 SH_PFC_PIN_GROUP(scifa0_data),
2873 SH_PFC_PIN_GROUP(scifa0_clk),
2874 SH_PFC_PIN_GROUP(scifa0_ctrl),
2875 SH_PFC_PIN_GROUP(scifa1_data),
2876 SH_PFC_PIN_GROUP(scifa1_clk),
2877 SH_PFC_PIN_GROUP(scifa1_ctrl),
2878 SH_PFC_PIN_GROUP(scifa2_data),
2879 SH_PFC_PIN_GROUP(scifa2_clk_0),
2880 SH_PFC_PIN_GROUP(scifa2_clk_1),
2881 SH_PFC_PIN_GROUP(scifa2_ctrl),
2882 SH_PFC_PIN_GROUP(scifa3_data_0),
2883 SH_PFC_PIN_GROUP(scifa3_clk_0),
2884 SH_PFC_PIN_GROUP(scifa3_ctrl_0),
2885 SH_PFC_PIN_GROUP(scifa3_data_1),
2886 SH_PFC_PIN_GROUP(scifa3_clk_1),
2887 SH_PFC_PIN_GROUP(scifa3_ctrl_1),
2888 SH_PFC_PIN_GROUP(scifa4_data_0),
2889 SH_PFC_PIN_GROUP(scifa4_data_1),
2890 SH_PFC_PIN_GROUP(scifa4_data_2),
2891 SH_PFC_PIN_GROUP(scifa4_clk_0),
2892 SH_PFC_PIN_GROUP(scifa4_clk_1),
2893 SH_PFC_PIN_GROUP(scifa5_data_0),
2894 SH_PFC_PIN_GROUP(scifa5_data_1),
2895 SH_PFC_PIN_GROUP(scifa5_data_2),
2896 SH_PFC_PIN_GROUP(scifa5_clk_0),
2897 SH_PFC_PIN_GROUP(scifa5_clk_1),
2898 SH_PFC_PIN_GROUP(scifa6_data),
2899 SH_PFC_PIN_GROUP(scifa6_clk),
2900 SH_PFC_PIN_GROUP(scifa7_data),
2901 SH_PFC_PIN_GROUP(scifb_data_0),
2902 SH_PFC_PIN_GROUP(scifb_clk_0),
2903 SH_PFC_PIN_GROUP(scifb_ctrl_0),
2904 SH_PFC_PIN_GROUP(scifb_data_1),
2905 SH_PFC_PIN_GROUP(scifb_clk_1),
2906 SH_PFC_PIN_GROUP(scifb_ctrl_1),
2907 SH_PFC_PIN_GROUP(sdhi0_data1),
2908 SH_PFC_PIN_GROUP(sdhi0_data4),
2909 SH_PFC_PIN_GROUP(sdhi0_ctrl),
2910 SH_PFC_PIN_GROUP(sdhi0_cd),
2911 SH_PFC_PIN_GROUP(sdhi0_wp),
2912 SH_PFC_PIN_GROUP(sdhi1_data1),
2913 SH_PFC_PIN_GROUP(sdhi1_data4),
2914 SH_PFC_PIN_GROUP(sdhi1_ctrl),
2915 SH_PFC_PIN_GROUP(sdhi1_cd),
2916 SH_PFC_PIN_GROUP(sdhi1_wp),
2917 SH_PFC_PIN_GROUP(sdhi2_data1),
2918 SH_PFC_PIN_GROUP(sdhi2_data4),
2919 SH_PFC_PIN_GROUP(sdhi2_ctrl),
2920 SH_PFC_PIN_GROUP(sdhi2_cd_0),
2921 SH_PFC_PIN_GROUP(sdhi2_wp_0),
2922 SH_PFC_PIN_GROUP(sdhi2_cd_1),
2923 SH_PFC_PIN_GROUP(sdhi2_wp_1),
2924 };
2925
2926 static const char * const bsc_groups[] = {
2927 "bsc_data8",
2928 "bsc_data16",
2929 "bsc_data32",
2930 "bsc_cs0",
2931 "bsc_cs2",
2932 "bsc_cs4",
2933 "bsc_cs5a_0",
2934 "bsc_cs5a_1",
2935 "bsc_cs5b",
2936 "bsc_cs6a",
2937 "bsc_rd_we8",
2938 "bsc_rd_we16",
2939 "bsc_rd_we32",
2940 "bsc_bs",
2941 "bsc_rdwr",
2942 };
2943
2944 static const char * const ceu0_groups[] = {
2945 "ceu0_data_0_7",
2946 "ceu0_data_8_15_0",
2947 "ceu0_data_8_15_1",
2948 "ceu0_clk_0",
2949 "ceu0_clk_1",
2950 "ceu0_clk_2",
2951 "ceu0_sync",
2952 "ceu0_field",
2953 };
2954
2955 static const char * const ceu1_groups[] = {
2956 "ceu1_data",
2957 "ceu1_clk",
2958 "ceu1_sync",
2959 "ceu1_field",
2960 };
2961
2962 static const char * const fsia_groups[] = {
2963 "fsia_mclk_in",
2964 "fsia_mclk_out",
2965 "fsia_sclk_in",
2966 "fsia_sclk_out",
2967 "fsia_data_in_0",
2968 "fsia_data_in_1",
2969 "fsia_data_out_0",
2970 "fsia_data_out_1",
2971 "fsia_data_out_2",
2972 "fsia_spdif_0",
2973 "fsia_spdif_1",
2974 };
2975
2976 static const char * const fsib_groups[] = {
2977 "fsib_mclk_in",
2978 };
2979
2980 static const char * const gether_groups[] = {
2981 "gether_rmii",
2982 "gether_mii",
2983 "gether_gmii",
2984 "gether_int",
2985 "gether_link",
2986 "gether_wol",
2987 };
2988
2989 static const char * const hdmi_groups[] = {
2990 "hdmi",
2991 };
2992
2993 static const char * const intc_groups[] = {
2994 "intc_irq0_0",
2995 "intc_irq0_1",
2996 "intc_irq1",
2997 "intc_irq2_0",
2998 "intc_irq2_1",
2999 "intc_irq3_0",
3000 "intc_irq3_1",
3001 "intc_irq4_0",
3002 "intc_irq4_1",
3003 "intc_irq5_0",
3004 "intc_irq5_1",
3005 "intc_irq6_0",
3006 "intc_irq6_1",
3007 "intc_irq7_0",
3008 "intc_irq7_1",
3009 "intc_irq8",
3010 "intc_irq9_0",
3011 "intc_irq9_1",
3012 "intc_irq10",
3013 "intc_irq11",
3014 "intc_irq12_0",
3015 "intc_irq12_1",
3016 "intc_irq13_0",
3017 "intc_irq13_1",
3018 "intc_irq14_0",
3019 "intc_irq14_1",
3020 "intc_irq15_0",
3021 "intc_irq15_1",
3022 "intc_irq16_0",
3023 "intc_irq16_1",
3024 "intc_irq17",
3025 "intc_irq18",
3026 "intc_irq19",
3027 "intc_irq20",
3028 "intc_irq21",
3029 "intc_irq22",
3030 "intc_irq23",
3031 "intc_irq24",
3032 "intc_irq25",
3033 "intc_irq26_0",
3034 "intc_irq26_1",
3035 "intc_irq27_0",
3036 "intc_irq27_1",
3037 "intc_irq28_0",
3038 "intc_irq28_1",
3039 "intc_irq29_0",
3040 "intc_irq29_1",
3041 "intc_irq30_0",
3042 "intc_irq30_1",
3043 "intc_irq31_0",
3044 "intc_irq31_1",
3045 };
3046
3047 static const char * const lcd0_groups[] = {
3048 "lcd0_data8",
3049 "lcd0_data9",
3050 "lcd0_data12",
3051 "lcd0_data16",
3052 "lcd0_data18",
3053 "lcd0_data24_0",
3054 "lcd0_data24_1",
3055 "lcd0_display",
3056 "lcd0_lclk_0",
3057 "lcd0_lclk_1",
3058 "lcd0_sync",
3059 "lcd0_sys",
3060 };
3061
3062 static const char * const lcd1_groups[] = {
3063 "lcd1_data8",
3064 "lcd1_data9",
3065 "lcd1_data12",
3066 "lcd1_data16",
3067 "lcd1_data18",
3068 "lcd1_data24",
3069 "lcd1_display",
3070 "lcd1_lclk",
3071 "lcd1_sync",
3072 "lcd1_sys",
3073 };
3074
3075 static const char * const mmc0_groups[] = {
3076 "mmc0_data1_0",
3077 "mmc0_data4_0",
3078 "mmc0_data8_0",
3079 "mmc0_ctrl_0",
3080 "mmc0_data1_1",
3081 "mmc0_data4_1",
3082 "mmc0_data8_1",
3083 "mmc0_ctrl_1",
3084 };
3085
3086 static const char * const scifa0_groups[] = {
3087 "scifa0_data",
3088 "scifa0_clk",
3089 "scifa0_ctrl",
3090 };
3091
3092 static const char * const scifa1_groups[] = {
3093 "scifa1_data",
3094 "scifa1_clk",
3095 "scifa1_ctrl",
3096 };
3097
3098 static const char * const scifa2_groups[] = {
3099 "scifa2_data",
3100 "scifa2_clk_0",
3101 "scifa2_clk_1",
3102 "scifa2_ctrl",
3103 };
3104
3105 static const char * const scifa3_groups[] = {
3106 "scifa3_data_0",
3107 "scifa3_clk_0",
3108 "scifa3_ctrl_0",
3109 "scifa3_data_1",
3110 "scifa3_clk_1",
3111 "scifa3_ctrl_1",
3112 };
3113
3114 static const char * const scifa4_groups[] = {
3115 "scifa4_data_0",
3116 "scifa4_data_1",
3117 "scifa4_data_2",
3118 "scifa4_clk_0",
3119 "scifa4_clk_1",
3120 };
3121
3122 static const char * const scifa5_groups[] = {
3123 "scifa5_data_0",
3124 "scifa5_data_1",
3125 "scifa5_data_2",
3126 "scifa5_clk_0",
3127 "scifa5_clk_1",
3128 };
3129
3130 static const char * const scifa6_groups[] = {
3131 "scifa6_data",
3132 "scifa6_clk",
3133 };
3134
3135 static const char * const scifa7_groups[] = {
3136 "scifa7_data",
3137 };
3138
3139 static const char * const scifb_groups[] = {
3140 "scifb_data_0",
3141 "scifb_clk_0",
3142 "scifb_ctrl_0",
3143 "scifb_data_1",
3144 "scifb_clk_1",
3145 "scifb_ctrl_1",
3146 };
3147
3148 static const char * const sdhi0_groups[] = {
3149 "sdhi0_data1",
3150 "sdhi0_data4",
3151 "sdhi0_ctrl",
3152 "sdhi0_cd",
3153 "sdhi0_wp",
3154 };
3155
3156 static const char * const sdhi1_groups[] = {
3157 "sdhi1_data1",
3158 "sdhi1_data4",
3159 "sdhi1_ctrl",
3160 "sdhi1_cd",
3161 "sdhi1_wp",
3162 };
3163
3164 static const char * const sdhi2_groups[] = {
3165 "sdhi2_data1",
3166 "sdhi2_data4",
3167 "sdhi2_ctrl",
3168 "sdhi2_cd_0",
3169 "sdhi2_wp_0",
3170 "sdhi2_cd_1",
3171 "sdhi2_wp_1",
3172 };
3173
3174 static const struct sh_pfc_function pinmux_functions[] = {
3175 SH_PFC_FUNCTION(bsc),
3176 SH_PFC_FUNCTION(ceu0),
3177 SH_PFC_FUNCTION(ceu1),
3178 SH_PFC_FUNCTION(fsia),
3179 SH_PFC_FUNCTION(fsib),
3180 SH_PFC_FUNCTION(gether),
3181 SH_PFC_FUNCTION(hdmi),
3182 SH_PFC_FUNCTION(intc),
3183 SH_PFC_FUNCTION(lcd0),
3184 SH_PFC_FUNCTION(lcd1),
3185 SH_PFC_FUNCTION(mmc0),
3186 SH_PFC_FUNCTION(scifa0),
3187 SH_PFC_FUNCTION(scifa1),
3188 SH_PFC_FUNCTION(scifa2),
3189 SH_PFC_FUNCTION(scifa3),
3190 SH_PFC_FUNCTION(scifa4),
3191 SH_PFC_FUNCTION(scifa5),
3192 SH_PFC_FUNCTION(scifa6),
3193 SH_PFC_FUNCTION(scifa7),
3194 SH_PFC_FUNCTION(scifb),
3195 SH_PFC_FUNCTION(sdhi0),
3196 SH_PFC_FUNCTION(sdhi1),
3197 SH_PFC_FUNCTION(sdhi2),
3198 };
3199
3200 #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
3201
3202 static const struct pinmux_func pinmux_func_gpios[] = {
3203 /* Function */
3204
3205 /* DBGT */
3206 GPIO_FN(DBGMDT2), GPIO_FN(DBGMDT1), GPIO_FN(DBGMDT0),
3207 GPIO_FN(DBGMD10), GPIO_FN(DBGMD11), GPIO_FN(DBGMD20),
3208 GPIO_FN(DBGMD21),
3209
3210 /* FSI-A */
3211 GPIO_FN(FSIAISLD_PORT0), /* FSIAISLD Port 0/5 */
3212 GPIO_FN(FSIAISLD_PORT5),
3213 GPIO_FN(FSIASPDIF_PORT9), /* FSIASPDIF Port 9/18 */
3214 GPIO_FN(FSIASPDIF_PORT18),
3215 GPIO_FN(FSIAOSLD1), GPIO_FN(FSIAOSLD2), GPIO_FN(FSIAOLR),
3216 GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD), GPIO_FN(FSIAOMC),
3217 GPIO_FN(FSIACK), GPIO_FN(FSIAILR), GPIO_FN(FSIAIBT),
3218
3219 /* FSI-B */
3220 GPIO_FN(FSIBCK),
3221
3222 /* FMSI */
3223 GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */
3224 GPIO_FN(FMSISLD_PORT6),
3225 GPIO_FN(FMSIILR), GPIO_FN(FMSIIBT), GPIO_FN(FMSIOLR),
3226 GPIO_FN(FMSIOBT), GPIO_FN(FMSICK), GPIO_FN(FMSOILR),
3227 GPIO_FN(FMSOIBT), GPIO_FN(FMSOOLR), GPIO_FN(FMSOOBT),
3228 GPIO_FN(FMSOSLD), GPIO_FN(FMSOCK),
3229
3230 /* RSPI */
3231 GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A),
3232 GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A),
3233 GPIO_FN(RSPI_MISO_A),
3234
3235 /* VIO CKO */
3236 GPIO_FN(VIO_CKO1),
3237 GPIO_FN(VIO_CKO2),
3238 GPIO_FN(VIO_CKO_1),
3239 GPIO_FN(VIO_CKO),
3240
3241 /* VIO0 */
3242 GPIO_FN(VIO0_D0), GPIO_FN(VIO0_D1), GPIO_FN(VIO0_D2),
3243 GPIO_FN(VIO0_D3), GPIO_FN(VIO0_D4), GPIO_FN(VIO0_D5),
3244 GPIO_FN(VIO0_D6), GPIO_FN(VIO0_D7), GPIO_FN(VIO0_D8),
3245 GPIO_FN(VIO0_D9), GPIO_FN(VIO0_D10), GPIO_FN(VIO0_D11),
3246 GPIO_FN(VIO0_D12), GPIO_FN(VIO0_VD), GPIO_FN(VIO0_HD),
3247 GPIO_FN(VIO0_CLK), GPIO_FN(VIO0_FIELD),
3248
3249 GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */
3250 GPIO_FN(VIO0_D14_PORT25),
3251 GPIO_FN(VIO0_D15_PORT24),
3252
3253 GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */
3254 GPIO_FN(VIO0_D14_PORT95),
3255 GPIO_FN(VIO0_D15_PORT96),
3256
3257 /* VIO1 */
3258 GPIO_FN(VIO1_D0), GPIO_FN(VIO1_D1), GPIO_FN(VIO1_D2),
3259 GPIO_FN(VIO1_D3), GPIO_FN(VIO1_D4), GPIO_FN(VIO1_D5),
3260 GPIO_FN(VIO1_D6), GPIO_FN(VIO1_D7), GPIO_FN(VIO1_VD),
3261 GPIO_FN(VIO1_HD), GPIO_FN(VIO1_CLK), GPIO_FN(VIO1_FIELD),
3262
3263 /* TPU0 */
3264 GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO3),
3265 GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */
3266 GPIO_FN(TPU0TO2_PORT202),
3267
3268 /* SSP1 0 */
3269 GPIO_FN(STP0_IPD0), GPIO_FN(STP0_IPD1), GPIO_FN(STP0_IPD2),
3270 GPIO_FN(STP0_IPD3), GPIO_FN(STP0_IPD4), GPIO_FN(STP0_IPD5),
3271 GPIO_FN(STP0_IPD6), GPIO_FN(STP0_IPD7), GPIO_FN(STP0_IPEN),
3272 GPIO_FN(STP0_IPCLK), GPIO_FN(STP0_IPSYNC),
3273
3274 /* SSP1 1 */
3275 GPIO_FN(STP1_IPD1), GPIO_FN(STP1_IPD2), GPIO_FN(STP1_IPD3),
3276 GPIO_FN(STP1_IPD4), GPIO_FN(STP1_IPD5), GPIO_FN(STP1_IPD6),
3277 GPIO_FN(STP1_IPD7), GPIO_FN(STP1_IPCLK), GPIO_FN(STP1_IPSYNC),
3278
3279 GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */
3280 GPIO_FN(STP1_IPEN_PORT187),
3281
3282 GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */
3283 GPIO_FN(STP1_IPEN_PORT193),
3284
3285 /* SIM */
3286 GPIO_FN(SIM_RST), GPIO_FN(SIM_CLK),
3287 GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */
3288 GPIO_FN(SIM_D_PORT199),
3289
3290 /* MSIOF2 */
3291 GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK),
3292 GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1),
3293 GPIO_FN(MSIOF2_MCK1), GPIO_FN(MSIOF2_MCK0), GPIO_FN(MSIOF2_RSYNC),
3294 GPIO_FN(MSIOF2_RSCK),
3295
3296 /* KEYSC */
3297 GPIO_FN(KEYIN4), GPIO_FN(KEYIN5),
3298 GPIO_FN(KEYIN6), GPIO_FN(KEYIN7),
3299 GPIO_FN(KEYOUT0), GPIO_FN(KEYOUT1), GPIO_FN(KEYOUT2),
3300 GPIO_FN(KEYOUT3), GPIO_FN(KEYOUT4), GPIO_FN(KEYOUT5),
3301 GPIO_FN(KEYOUT6), GPIO_FN(KEYOUT7),
3302
3303 GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */
3304 GPIO_FN(KEYIN1_PORT44),
3305 GPIO_FN(KEYIN2_PORT45),
3306 GPIO_FN(KEYIN3_PORT46),
3307
3308 GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */
3309 GPIO_FN(KEYIN1_PORT57),
3310 GPIO_FN(KEYIN2_PORT56),
3311 GPIO_FN(KEYIN3_PORT55),
3312
3313 /* VOU */
3314 GPIO_FN(DV_D0), GPIO_FN(DV_D1), GPIO_FN(DV_D2),
3315 GPIO_FN(DV_D3), GPIO_FN(DV_D4), GPIO_FN(DV_D5),
3316 GPIO_FN(DV_D6), GPIO_FN(DV_D7), GPIO_FN(DV_D8),
3317 GPIO_FN(DV_D9), GPIO_FN(DV_D10), GPIO_FN(DV_D11),
3318 GPIO_FN(DV_D12), GPIO_FN(DV_D13), GPIO_FN(DV_D14),
3319 GPIO_FN(DV_D15), GPIO_FN(DV_CLK),
3320 GPIO_FN(DV_VSYNC), GPIO_FN(DV_HSYNC),
3321
3322 /* MEMC */
3323 GPIO_FN(MEMC_AD0), GPIO_FN(MEMC_AD1), GPIO_FN(MEMC_AD2),
3324 GPIO_FN(MEMC_AD3), GPIO_FN(MEMC_AD4), GPIO_FN(MEMC_AD5),
3325 GPIO_FN(MEMC_AD6), GPIO_FN(MEMC_AD7), GPIO_FN(MEMC_AD8),
3326 GPIO_FN(MEMC_AD9), GPIO_FN(MEMC_AD10), GPIO_FN(MEMC_AD11),
3327 GPIO_FN(MEMC_AD12), GPIO_FN(MEMC_AD13), GPIO_FN(MEMC_AD14),
3328 GPIO_FN(MEMC_AD15), GPIO_FN(MEMC_CS0), GPIO_FN(MEMC_INT),
3329 GPIO_FN(MEMC_NWE), GPIO_FN(MEMC_NOE), GPIO_FN(MEMC_CS1),
3330 GPIO_FN(MEMC_A1), GPIO_FN(MEMC_ADV), GPIO_FN(MEMC_DREQ0),
3331 GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK),
3332 GPIO_FN(MEMC_A0),
3333
3334 /* MSIOF0 */
3335 GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD),
3336 GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1),
3337 GPIO_FN(MSIOF0_RSYNC), GPIO_FN(MSIOF0_RSCK), GPIO_FN(MSIOF0_TSCK),
3338 GPIO_FN(MSIOF0_TSYNC),
3339
3340 /* MSIOF1 */
3341 GPIO_FN(MSIOF1_RSCK), GPIO_FN(MSIOF1_RSYNC),
3342 GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1),
3343
3344 GPIO_FN(MSIOF1_SS2_PORT116), GPIO_FN(MSIOF1_SS1_PORT117),
3345 GPIO_FN(MSIOF1_RXD_PORT118), GPIO_FN(MSIOF1_TXD_PORT119),
3346 GPIO_FN(MSIOF1_TSYNC_PORT120),
3347 GPIO_FN(MSIOF1_TSCK_PORT121), /* MSEL4CR_10_0 */
3348
3349 GPIO_FN(MSIOF1_SS1_PORT67), GPIO_FN(MSIOF1_TSCK_PORT72),
3350 GPIO_FN(MSIOF1_TSYNC_PORT73), GPIO_FN(MSIOF1_TXD_PORT74),
3351 GPIO_FN(MSIOF1_RXD_PORT75),
3352 GPIO_FN(MSIOF1_SS2_PORT202), /* MSEL4CR_10_1 */
3353
3354 /* GPIO */
3355 GPIO_FN(GPO0), GPIO_FN(GPI0),
3356 GPIO_FN(GPO1), GPIO_FN(GPI1),
3357
3358 /* USB0 */
3359 GPIO_FN(USB0_OCI), GPIO_FN(USB0_PPON), GPIO_FN(VBUS),
3360
3361 /* USB1 */
3362 GPIO_FN(USB1_OCI), GPIO_FN(USB1_PPON),
3363
3364 /* BBIF1 */
3365 GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_TSYNC),
3366 GPIO_FN(BBIF1_TSCK), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC),
3367 GPIO_FN(BBIF1_FLOW), GPIO_FN(BBIF1_RX_FLOW_N),
3368
3369 /* BBIF2 */
3370 GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */
3371 GPIO_FN(BBIF2_RXD2_PORT60),
3372 GPIO_FN(BBIF2_TSYNC2_PORT6),
3373 GPIO_FN(BBIF2_TSCK2_PORT59),
3374
3375 GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */
3376 GPIO_FN(BBIF2_TXD2_PORT183),
3377 GPIO_FN(BBIF2_TSCK2_PORT89),
3378 GPIO_FN(BBIF2_TSYNC2_PORT184),
3379
3380 /* FLCTL / PCMCIA */
3381 GPIO_FN(IOIS16), /* ? */
3382
3383 GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), GPIO_FN(A3),
3384 GPIO_FN(A4_FOE), GPIO_FN(A5_FCDE), /* share with FLCTL */
3385 GPIO_FN(A6), GPIO_FN(A7), GPIO_FN(A8), GPIO_FN(A9),
3386 GPIO_FN(A10), GPIO_FN(A11), GPIO_FN(A12), GPIO_FN(A13),
3387 GPIO_FN(A14), GPIO_FN(A15), GPIO_FN(A16), GPIO_FN(A17),
3388 GPIO_FN(A18), GPIO_FN(A19), GPIO_FN(A20), GPIO_FN(A21),
3389 GPIO_FN(A22), GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25),
3390 GPIO_FN(A26),
3391
3392 GPIO_FN(CKO),
3393 GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */
3394 GPIO_FN(WAIT_PORT90),
3395
3396 GPIO_FN(FCE0), GPIO_FN(FCE1), GPIO_FN(FRB), /* FLCTL */
3397
3398 /* IRDA */
3399 GPIO_FN(IRDA_FIRSEL), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_OUT),
3400
3401 /* ATAPI */
3402 GPIO_FN(IDE_D0), GPIO_FN(IDE_D1), GPIO_FN(IDE_D2),
3403 GPIO_FN(IDE_D3), GPIO_FN(IDE_D4), GPIO_FN(IDE_D5),
3404 GPIO_FN(IDE_D6), GPIO_FN(IDE_D7), GPIO_FN(IDE_D8),
3405 GPIO_FN(IDE_D9), GPIO_FN(IDE_D10), GPIO_FN(IDE_D11),
3406 GPIO_FN(IDE_D12), GPIO_FN(IDE_D13), GPIO_FN(IDE_D14),
3407 GPIO_FN(IDE_D15), GPIO_FN(IDE_A0), GPIO_FN(IDE_A1),
3408 GPIO_FN(IDE_A2), GPIO_FN(IDE_CS0), GPIO_FN(IDE_CS1),
3409 GPIO_FN(IDE_IOWR), GPIO_FN(IDE_IORD), GPIO_FN(IDE_IORDY),
3410 GPIO_FN(IDE_INT), GPIO_FN(IDE_RST), GPIO_FN(IDE_DIRECTION),
3411 GPIO_FN(IDE_EXBUF_ENB), GPIO_FN(IDE_IODACK), GPIO_FN(IDE_IODREQ),
3412
3413 /* DMA0 */
3414 GPIO_FN(DREQ0), GPIO_FN(DACK0),
3415
3416 /* DMA1 */
3417 GPIO_FN(DREQ1), GPIO_FN(DACK1),
3418
3419 /* SYSC */
3420 GPIO_FN(RESETOUTS),
3421
3422 /* IRREM */
3423 GPIO_FN(IROUT),
3424
3425 /* SDENC */
3426 GPIO_FN(SDENC_CPG),
3427 GPIO_FN(SDENC_DV_CLKI),
3428
3429 /* HDMI */
3430 GPIO_FN(HDMI_HPD),
3431 GPIO_FN(HDMI_CEC),
3432
3433 /* SYSC */
3434 GPIO_FN(RESETP_PULLUP),
3435 GPIO_FN(RESETP_PLAIN),
3436
3437 /* DEBUG */
3438 GPIO_FN(EDEBGREQ_PULLDOWN),
3439 GPIO_FN(EDEBGREQ_PULLUP),
3440
3441 GPIO_FN(TRACEAUD_FROM_VIO),
3442 GPIO_FN(TRACEAUD_FROM_LCDC0),
3443 GPIO_FN(TRACEAUD_FROM_MEMC),
3444 };
3445
3446 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3447 PORTCR(0, 0xe6050000), /* PORT0CR */
3448 PORTCR(1, 0xe6050001), /* PORT1CR */
3449 PORTCR(2, 0xe6050002), /* PORT2CR */
3450 PORTCR(3, 0xe6050003), /* PORT3CR */
3451 PORTCR(4, 0xe6050004), /* PORT4CR */
3452 PORTCR(5, 0xe6050005), /* PORT5CR */
3453 PORTCR(6, 0xe6050006), /* PORT6CR */
3454 PORTCR(7, 0xe6050007), /* PORT7CR */
3455 PORTCR(8, 0xe6050008), /* PORT8CR */
3456 PORTCR(9, 0xe6050009), /* PORT9CR */
3457 PORTCR(10, 0xe605000a), /* PORT10CR */
3458 PORTCR(11, 0xe605000b), /* PORT11CR */
3459 PORTCR(12, 0xe605000c), /* PORT12CR */
3460 PORTCR(13, 0xe605000d), /* PORT13CR */
3461 PORTCR(14, 0xe605000e), /* PORT14CR */
3462 PORTCR(15, 0xe605000f), /* PORT15CR */
3463 PORTCR(16, 0xe6050010), /* PORT16CR */
3464 PORTCR(17, 0xe6050011), /* PORT17CR */
3465 PORTCR(18, 0xe6050012), /* PORT18CR */
3466 PORTCR(19, 0xe6050013), /* PORT19CR */
3467 PORTCR(20, 0xe6050014), /* PORT20CR */
3468 PORTCR(21, 0xe6050015), /* PORT21CR */
3469 PORTCR(22, 0xe6050016), /* PORT22CR */
3470 PORTCR(23, 0xe6050017), /* PORT23CR */
3471 PORTCR(24, 0xe6050018), /* PORT24CR */
3472 PORTCR(25, 0xe6050019), /* PORT25CR */
3473 PORTCR(26, 0xe605001a), /* PORT26CR */
3474 PORTCR(27, 0xe605001b), /* PORT27CR */
3475 PORTCR(28, 0xe605001c), /* PORT28CR */
3476 PORTCR(29, 0xe605001d), /* PORT29CR */
3477 PORTCR(30, 0xe605001e), /* PORT30CR */
3478 PORTCR(31, 0xe605001f), /* PORT31CR */
3479 PORTCR(32, 0xe6050020), /* PORT32CR */
3480 PORTCR(33, 0xe6050021), /* PORT33CR */
3481 PORTCR(34, 0xe6050022), /* PORT34CR */
3482 PORTCR(35, 0xe6050023), /* PORT35CR */
3483 PORTCR(36, 0xe6050024), /* PORT36CR */
3484 PORTCR(37, 0xe6050025), /* PORT37CR */
3485 PORTCR(38, 0xe6050026), /* PORT38CR */
3486 PORTCR(39, 0xe6050027), /* PORT39CR */
3487 PORTCR(40, 0xe6050028), /* PORT40CR */
3488 PORTCR(41, 0xe6050029), /* PORT41CR */
3489 PORTCR(42, 0xe605002a), /* PORT42CR */
3490 PORTCR(43, 0xe605002b), /* PORT43CR */
3491 PORTCR(44, 0xe605002c), /* PORT44CR */
3492 PORTCR(45, 0xe605002d), /* PORT45CR */
3493 PORTCR(46, 0xe605002e), /* PORT46CR */
3494 PORTCR(47, 0xe605002f), /* PORT47CR */
3495 PORTCR(48, 0xe6050030), /* PORT48CR */
3496 PORTCR(49, 0xe6050031), /* PORT49CR */
3497 PORTCR(50, 0xe6050032), /* PORT50CR */
3498 PORTCR(51, 0xe6050033), /* PORT51CR */
3499 PORTCR(52, 0xe6050034), /* PORT52CR */
3500 PORTCR(53, 0xe6050035), /* PORT53CR */
3501 PORTCR(54, 0xe6050036), /* PORT54CR */
3502 PORTCR(55, 0xe6050037), /* PORT55CR */
3503 PORTCR(56, 0xe6050038), /* PORT56CR */
3504 PORTCR(57, 0xe6050039), /* PORT57CR */
3505 PORTCR(58, 0xe605003a), /* PORT58CR */
3506 PORTCR(59, 0xe605003b), /* PORT59CR */
3507 PORTCR(60, 0xe605003c), /* PORT60CR */
3508 PORTCR(61, 0xe605003d), /* PORT61CR */
3509 PORTCR(62, 0xe605003e), /* PORT62CR */
3510 PORTCR(63, 0xe605003f), /* PORT63CR */
3511 PORTCR(64, 0xe6050040), /* PORT64CR */
3512 PORTCR(65, 0xe6050041), /* PORT65CR */
3513 PORTCR(66, 0xe6050042), /* PORT66CR */
3514 PORTCR(67, 0xe6050043), /* PORT67CR */
3515 PORTCR(68, 0xe6050044), /* PORT68CR */
3516 PORTCR(69, 0xe6050045), /* PORT69CR */
3517 PORTCR(70, 0xe6050046), /* PORT70CR */
3518 PORTCR(71, 0xe6050047), /* PORT71CR */
3519 PORTCR(72, 0xe6050048), /* PORT72CR */
3520 PORTCR(73, 0xe6050049), /* PORT73CR */
3521 PORTCR(74, 0xe605004a), /* PORT74CR */
3522 PORTCR(75, 0xe605004b), /* PORT75CR */
3523 PORTCR(76, 0xe605004c), /* PORT76CR */
3524 PORTCR(77, 0xe605004d), /* PORT77CR */
3525 PORTCR(78, 0xe605004e), /* PORT78CR */
3526 PORTCR(79, 0xe605004f), /* PORT79CR */
3527 PORTCR(80, 0xe6050050), /* PORT80CR */
3528 PORTCR(81, 0xe6050051), /* PORT81CR */
3529 PORTCR(82, 0xe6050052), /* PORT82CR */
3530 PORTCR(83, 0xe6050053), /* PORT83CR */
3531
3532 PORTCR(84, 0xe6051054), /* PORT84CR */
3533 PORTCR(85, 0xe6051055), /* PORT85CR */
3534 PORTCR(86, 0xe6051056), /* PORT86CR */
3535 PORTCR(87, 0xe6051057), /* PORT87CR */
3536 PORTCR(88, 0xe6051058), /* PORT88CR */
3537 PORTCR(89, 0xe6051059), /* PORT89CR */
3538 PORTCR(90, 0xe605105a), /* PORT90CR */
3539 PORTCR(91, 0xe605105b), /* PORT91CR */
3540 PORTCR(92, 0xe605105c), /* PORT92CR */
3541 PORTCR(93, 0xe605105d), /* PORT93CR */
3542 PORTCR(94, 0xe605105e), /* PORT94CR */
3543 PORTCR(95, 0xe605105f), /* PORT95CR */
3544 PORTCR(96, 0xe6051060), /* PORT96CR */
3545 PORTCR(97, 0xe6051061), /* PORT97CR */
3546 PORTCR(98, 0xe6051062), /* PORT98CR */
3547 PORTCR(99, 0xe6051063), /* PORT99CR */
3548 PORTCR(100, 0xe6051064), /* PORT100CR */
3549 PORTCR(101, 0xe6051065), /* PORT101CR */
3550 PORTCR(102, 0xe6051066), /* PORT102CR */
3551 PORTCR(103, 0xe6051067), /* PORT103CR */
3552 PORTCR(104, 0xe6051068), /* PORT104CR */
3553 PORTCR(105, 0xe6051069), /* PORT105CR */
3554 PORTCR(106, 0xe605106a), /* PORT106CR */
3555 PORTCR(107, 0xe605106b), /* PORT107CR */
3556 PORTCR(108, 0xe605106c), /* PORT108CR */
3557 PORTCR(109, 0xe605106d), /* PORT109CR */
3558 PORTCR(110, 0xe605106e), /* PORT110CR */
3559 PORTCR(111, 0xe605106f), /* PORT111CR */
3560 PORTCR(112, 0xe6051070), /* PORT112CR */
3561 PORTCR(113, 0xe6051071), /* PORT113CR */
3562 PORTCR(114, 0xe6051072), /* PORT114CR */
3563
3564 PORTCR(115, 0xe6052073), /* PORT115CR */
3565 PORTCR(116, 0xe6052074), /* PORT116CR */
3566 PORTCR(117, 0xe6052075), /* PORT117CR */
3567 PORTCR(118, 0xe6052076), /* PORT118CR */
3568 PORTCR(119, 0xe6052077), /* PORT119CR */
3569 PORTCR(120, 0xe6052078), /* PORT120CR */
3570 PORTCR(121, 0xe6052079), /* PORT121CR */
3571 PORTCR(122, 0xe605207a), /* PORT122CR */
3572 PORTCR(123, 0xe605207b), /* PORT123CR */
3573 PORTCR(124, 0xe605207c), /* PORT124CR */
3574 PORTCR(125, 0xe605207d), /* PORT125CR */
3575 PORTCR(126, 0xe605207e), /* PORT126CR */
3576 PORTCR(127, 0xe605207f), /* PORT127CR */
3577 PORTCR(128, 0xe6052080), /* PORT128CR */
3578 PORTCR(129, 0xe6052081), /* PORT129CR */
3579 PORTCR(130, 0xe6052082), /* PORT130CR */
3580 PORTCR(131, 0xe6052083), /* PORT131CR */
3581 PORTCR(132, 0xe6052084), /* PORT132CR */
3582 PORTCR(133, 0xe6052085), /* PORT133CR */
3583 PORTCR(134, 0xe6052086), /* PORT134CR */
3584 PORTCR(135, 0xe6052087), /* PORT135CR */
3585 PORTCR(136, 0xe6052088), /* PORT136CR */
3586 PORTCR(137, 0xe6052089), /* PORT137CR */
3587 PORTCR(138, 0xe605208a), /* PORT138CR */
3588 PORTCR(139, 0xe605208b), /* PORT139CR */
3589 PORTCR(140, 0xe605208c), /* PORT140CR */
3590 PORTCR(141, 0xe605208d), /* PORT141CR */
3591 PORTCR(142, 0xe605208e), /* PORT142CR */
3592 PORTCR(143, 0xe605208f), /* PORT143CR */
3593 PORTCR(144, 0xe6052090), /* PORT144CR */
3594 PORTCR(145, 0xe6052091), /* PORT145CR */
3595 PORTCR(146, 0xe6052092), /* PORT146CR */
3596 PORTCR(147, 0xe6052093), /* PORT147CR */
3597 PORTCR(148, 0xe6052094), /* PORT148CR */
3598 PORTCR(149, 0xe6052095), /* PORT149CR */
3599 PORTCR(150, 0xe6052096), /* PORT150CR */
3600 PORTCR(151, 0xe6052097), /* PORT151CR */
3601 PORTCR(152, 0xe6052098), /* PORT152CR */
3602 PORTCR(153, 0xe6052099), /* PORT153CR */
3603 PORTCR(154, 0xe605209a), /* PORT154CR */
3604 PORTCR(155, 0xe605209b), /* PORT155CR */
3605 PORTCR(156, 0xe605209c), /* PORT156CR */
3606 PORTCR(157, 0xe605209d), /* PORT157CR */
3607 PORTCR(158, 0xe605209e), /* PORT158CR */
3608 PORTCR(159, 0xe605209f), /* PORT159CR */
3609 PORTCR(160, 0xe60520a0), /* PORT160CR */
3610 PORTCR(161, 0xe60520a1), /* PORT161CR */
3611 PORTCR(162, 0xe60520a2), /* PORT162CR */
3612 PORTCR(163, 0xe60520a3), /* PORT163CR */
3613 PORTCR(164, 0xe60520a4), /* PORT164CR */
3614 PORTCR(165, 0xe60520a5), /* PORT165CR */
3615 PORTCR(166, 0xe60520a6), /* PORT166CR */
3616 PORTCR(167, 0xe60520a7), /* PORT167CR */
3617 PORTCR(168, 0xe60520a8), /* PORT168CR */
3618 PORTCR(169, 0xe60520a9), /* PORT169CR */
3619 PORTCR(170, 0xe60520aa), /* PORT170CR */
3620 PORTCR(171, 0xe60520ab), /* PORT171CR */
3621 PORTCR(172, 0xe60520ac), /* PORT172CR */
3622 PORTCR(173, 0xe60520ad), /* PORT173CR */
3623 PORTCR(174, 0xe60520ae), /* PORT174CR */
3624 PORTCR(175, 0xe60520af), /* PORT175CR */
3625 PORTCR(176, 0xe60520b0), /* PORT176CR */
3626 PORTCR(177, 0xe60520b1), /* PORT177CR */
3627 PORTCR(178, 0xe60520b2), /* PORT178CR */
3628 PORTCR(179, 0xe60520b3), /* PORT179CR */
3629 PORTCR(180, 0xe60520b4), /* PORT180CR */
3630 PORTCR(181, 0xe60520b5), /* PORT181CR */
3631 PORTCR(182, 0xe60520b6), /* PORT182CR */
3632 PORTCR(183, 0xe60520b7), /* PORT183CR */
3633 PORTCR(184, 0xe60520b8), /* PORT184CR */
3634 PORTCR(185, 0xe60520b9), /* PORT185CR */
3635 PORTCR(186, 0xe60520ba), /* PORT186CR */
3636 PORTCR(187, 0xe60520bb), /* PORT187CR */
3637 PORTCR(188, 0xe60520bc), /* PORT188CR */
3638 PORTCR(189, 0xe60520bd), /* PORT189CR */
3639 PORTCR(190, 0xe60520be), /* PORT190CR */
3640 PORTCR(191, 0xe60520bf), /* PORT191CR */
3641 PORTCR(192, 0xe60520c0), /* PORT192CR */
3642 PORTCR(193, 0xe60520c1), /* PORT193CR */
3643 PORTCR(194, 0xe60520c2), /* PORT194CR */
3644 PORTCR(195, 0xe60520c3), /* PORT195CR */
3645 PORTCR(196, 0xe60520c4), /* PORT196CR */
3646 PORTCR(197, 0xe60520c5), /* PORT197CR */
3647 PORTCR(198, 0xe60520c6), /* PORT198CR */
3648 PORTCR(199, 0xe60520c7), /* PORT199CR */
3649 PORTCR(200, 0xe60520c8), /* PORT200CR */
3650 PORTCR(201, 0xe60520c9), /* PORT201CR */
3651 PORTCR(202, 0xe60520ca), /* PORT202CR */
3652 PORTCR(203, 0xe60520cb), /* PORT203CR */
3653 PORTCR(204, 0xe60520cc), /* PORT204CR */
3654 PORTCR(205, 0xe60520cd), /* PORT205CR */
3655 PORTCR(206, 0xe60520ce), /* PORT206CR */
3656 PORTCR(207, 0xe60520cf), /* PORT207CR */
3657 PORTCR(208, 0xe60520d0), /* PORT208CR */
3658 PORTCR(209, 0xe60520d1), /* PORT209CR */
3659
3660 PORTCR(210, 0xe60530d2), /* PORT210CR */
3661 PORTCR(211, 0xe60530d3), /* PORT211CR */
3662
3663 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
3664 MSEL1CR_31_0, MSEL1CR_31_1,
3665 MSEL1CR_30_0, MSEL1CR_30_1,
3666 MSEL1CR_29_0, MSEL1CR_29_1,
3667 MSEL1CR_28_0, MSEL1CR_28_1,
3668 MSEL1CR_27_0, MSEL1CR_27_1,
3669 MSEL1CR_26_0, MSEL1CR_26_1,
3670 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3671 0, 0, 0, 0, 0, 0, 0, 0,
3672 MSEL1CR_16_0, MSEL1CR_16_1,
3673 MSEL1CR_15_0, MSEL1CR_15_1,
3674 MSEL1CR_14_0, MSEL1CR_14_1,
3675 MSEL1CR_13_0, MSEL1CR_13_1,
3676 MSEL1CR_12_0, MSEL1CR_12_1,
3677 0, 0, 0, 0,
3678 MSEL1CR_9_0, MSEL1CR_9_1,
3679 0, 0,
3680 MSEL1CR_7_0, MSEL1CR_7_1,
3681 MSEL1CR_6_0, MSEL1CR_6_1,
3682 MSEL1CR_5_0, MSEL1CR_5_1,
3683 MSEL1CR_4_0, MSEL1CR_4_1,
3684 MSEL1CR_3_0, MSEL1CR_3_1,
3685 MSEL1CR_2_0, MSEL1CR_2_1,
3686 0, 0,
3687 MSEL1CR_0_0, MSEL1CR_0_1,
3688 }
3689 },
3690 { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
3691 0, 0, 0, 0, 0, 0, 0, 0,
3692 0, 0, 0, 0, 0, 0, 0, 0,
3693 0, 0, 0, 0, 0, 0, 0, 0,
3694 0, 0, 0, 0, 0, 0, 0, 0,
3695 MSEL3CR_15_0, MSEL3CR_15_1,
3696 0, 0, 0, 0, 0, 0, 0, 0,
3697 0, 0, 0, 0, 0, 0, 0, 0,
3698 MSEL3CR_6_0, MSEL3CR_6_1,
3699 0, 0, 0, 0, 0, 0, 0, 0,
3700 0, 0, 0, 0,
3701 }
3702 },
3703 { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
3704 0, 0, 0, 0, 0, 0, 0, 0,
3705 0, 0, 0, 0, 0, 0, 0, 0,
3706 0, 0, 0, 0, 0, 0, 0, 0,
3707 MSEL4CR_19_0, MSEL4CR_19_1,
3708 MSEL4CR_18_0, MSEL4CR_18_1,
3709 0, 0, 0, 0,
3710 MSEL4CR_15_0, MSEL4CR_15_1,
3711 0, 0, 0, 0, 0, 0, 0, 0,
3712 MSEL4CR_10_0, MSEL4CR_10_1,
3713 0, 0, 0, 0, 0, 0,
3714 MSEL4CR_6_0, MSEL4CR_6_1,
3715 0, 0,
3716 MSEL4CR_4_0, MSEL4CR_4_1,
3717 0, 0, 0, 0,
3718 MSEL4CR_1_0, MSEL4CR_1_1,
3719 0, 0,
3720 }
3721 },
3722 { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {
3723 MSEL5CR_31_0, MSEL5CR_31_1,
3724 MSEL5CR_30_0, MSEL5CR_30_1,
3725 MSEL5CR_29_0, MSEL5CR_29_1,
3726 0, 0,
3727 MSEL5CR_27_0, MSEL5CR_27_1,
3728 0, 0,
3729 MSEL5CR_25_0, MSEL5CR_25_1,
3730 0, 0,
3731 MSEL5CR_23_0, MSEL5CR_23_1,
3732 0, 0,
3733 MSEL5CR_21_0, MSEL5CR_21_1,
3734 0, 0,
3735 MSEL5CR_19_0, MSEL5CR_19_1,
3736 0, 0,
3737 MSEL5CR_17_0, MSEL5CR_17_1,
3738 0, 0,
3739 MSEL5CR_15_0, MSEL5CR_15_1,
3740 MSEL5CR_14_0, MSEL5CR_14_1,
3741 MSEL5CR_13_0, MSEL5CR_13_1,
3742 MSEL5CR_12_0, MSEL5CR_12_1,
3743 MSEL5CR_11_0, MSEL5CR_11_1,
3744 MSEL5CR_10_0, MSEL5CR_10_1,
3745 0, 0,
3746 MSEL5CR_8_0, MSEL5CR_8_1,
3747 MSEL5CR_7_0, MSEL5CR_7_1,
3748 MSEL5CR_6_0, MSEL5CR_6_1,
3749 MSEL5CR_5_0, MSEL5CR_5_1,
3750 MSEL5CR_4_0, MSEL5CR_4_1,
3751 MSEL5CR_3_0, MSEL5CR_3_1,
3752 MSEL5CR_2_0, MSEL5CR_2_1,
3753 0, 0,
3754 MSEL5CR_0_0, MSEL5CR_0_1,
3755 }
3756 },
3757 { },
3758 };
3759
3760 static const struct pinmux_data_reg pinmux_data_regs[] = {
3761 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
3762 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
3763 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
3764 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
3765 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
3766 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
3767 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
3768 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
3769 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
3770 },
3771 { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) {
3772 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
3773 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
3774 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
3775 PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
3776 PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
3777 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
3778 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
3779 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
3780 },
3781 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) {
3782 0, 0, 0, 0,
3783 0, 0, 0, 0,
3784 0, 0, 0, 0,
3785 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
3786 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
3787 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
3788 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
3789 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
3790 },
3791 { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) {
3792 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
3793 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
3794 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
3795 0, 0, 0, 0,
3796 0, 0, 0, 0,
3797 0, 0, 0, 0,
3798 0, 0, 0, 0,
3799 0, 0, 0, 0 }
3800 },
3801 { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) {
3802 0, 0, 0, 0,
3803 0, 0, 0, 0,
3804 0, 0, 0, 0,
3805 0, PORT114_DATA, PORT113_DATA, PORT112_DATA,
3806 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
3807 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
3808 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
3809 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
3810 },
3811 { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) {
3812 PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
3813 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
3814 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
3815 PORT115_DATA, 0, 0, 0,
3816 0, 0, 0, 0,
3817 0, 0, 0, 0,
3818 0, 0, 0, 0,
3819 0, 0, 0, 0 }
3820 },
3821 { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) {
3822 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
3823 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
3824 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
3825 PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
3826 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
3827 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
3828 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
3829 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
3830 },
3831 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) {
3832 PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
3833 PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
3834 PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
3835 PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
3836 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
3837 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
3838 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
3839 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
3840 },
3841 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) {
3842 0, 0, 0, 0,
3843 0, 0, 0, 0,
3844 0, 0, 0, 0,
3845 0, 0, PORT209_DATA, PORT208_DATA,
3846 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
3847 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
3848 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
3849 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
3850 },
3851 { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) {
3852 0, 0, 0, 0,
3853 0, 0, 0, 0,
3854 0, 0, 0, 0,
3855 PORT211_DATA, PORT210_DATA, 0, 0,
3856 0, 0, 0, 0,
3857 0, 0, 0, 0,
3858 0, 0, 0, 0,
3859 0, 0, 0, 0 }
3860 },
3861 { },
3862 };
3863
3864 static const struct pinmux_irq pinmux_irqs[] = {
3865 PINMUX_IRQ(irq_pin(0), GPIO_PORT2, GPIO_PORT13), /* IRQ0A */
3866 PINMUX_IRQ(irq_pin(1), GPIO_PORT20), /* IRQ1A */
3867 PINMUX_IRQ(irq_pin(2), GPIO_PORT11, GPIO_PORT12), /* IRQ2A */
3868 PINMUX_IRQ(irq_pin(3), GPIO_PORT10, GPIO_PORT14), /* IRQ3A */
3869 PINMUX_IRQ(irq_pin(4), GPIO_PORT15, GPIO_PORT172),/* IRQ4A */
3870 PINMUX_IRQ(irq_pin(5), GPIO_PORT0, GPIO_PORT1), /* IRQ5A */
3871 PINMUX_IRQ(irq_pin(6), GPIO_PORT121, GPIO_PORT173),/* IRQ6A */
3872 PINMUX_IRQ(irq_pin(7), GPIO_PORT120, GPIO_PORT209),/* IRQ7A */
3873 PINMUX_IRQ(irq_pin(8), GPIO_PORT119), /* IRQ8A */
3874 PINMUX_IRQ(irq_pin(9), GPIO_PORT118, GPIO_PORT210),/* IRQ9A */
3875 PINMUX_IRQ(irq_pin(10), GPIO_PORT19), /* IRQ10A */
3876 PINMUX_IRQ(irq_pin(11), GPIO_PORT104), /* IRQ11A */
3877 PINMUX_IRQ(irq_pin(12), GPIO_PORT42, GPIO_PORT97), /* IRQ12A */
3878 PINMUX_IRQ(irq_pin(13), GPIO_PORT64, GPIO_PORT98), /* IRQ13A */
3879 PINMUX_IRQ(irq_pin(14), GPIO_PORT63, GPIO_PORT99), /* IRQ14A */
3880 PINMUX_IRQ(irq_pin(15), GPIO_PORT62, GPIO_PORT100),/* IRQ15A */
3881 PINMUX_IRQ(irq_pin(16), GPIO_PORT68, GPIO_PORT211),/* IRQ16A */
3882 PINMUX_IRQ(irq_pin(17), GPIO_PORT69), /* IRQ17A */
3883 PINMUX_IRQ(irq_pin(18), GPIO_PORT70), /* IRQ18A */
3884 PINMUX_IRQ(irq_pin(19), GPIO_PORT71), /* IRQ19A */
3885 PINMUX_IRQ(irq_pin(20), GPIO_PORT67), /* IRQ20A */
3886 PINMUX_IRQ(irq_pin(21), GPIO_PORT202), /* IRQ21A */
3887 PINMUX_IRQ(irq_pin(22), GPIO_PORT95), /* IRQ22A */
3888 PINMUX_IRQ(irq_pin(23), GPIO_PORT96), /* IRQ23A */
3889 PINMUX_IRQ(irq_pin(24), GPIO_PORT180), /* IRQ24A */
3890 PINMUX_IRQ(irq_pin(25), GPIO_PORT38), /* IRQ25A */
3891 PINMUX_IRQ(irq_pin(26), GPIO_PORT58, GPIO_PORT81), /* IRQ26A */
3892 PINMUX_IRQ(irq_pin(27), GPIO_PORT57, GPIO_PORT168),/* IRQ27A */
3893 PINMUX_IRQ(irq_pin(28), GPIO_PORT56, GPIO_PORT169),/* IRQ28A */
3894 PINMUX_IRQ(irq_pin(29), GPIO_PORT50, GPIO_PORT170),/* IRQ29A */
3895 PINMUX_IRQ(irq_pin(30), GPIO_PORT49, GPIO_PORT171),/* IRQ30A */
3896 PINMUX_IRQ(irq_pin(31), GPIO_PORT41, GPIO_PORT167),/* IRQ31A */
3897 };
3898
3899 const struct sh_pfc_soc_info r8a7740_pinmux_info = {
3900 .name = "r8a7740_pfc",
3901 .input = { PINMUX_INPUT_BEGIN,
3902 PINMUX_INPUT_END },
3903 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
3904 PINMUX_INPUT_PULLUP_END },
3905 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN,
3906 PINMUX_INPUT_PULLDOWN_END },
3907 .output = { PINMUX_OUTPUT_BEGIN,
3908 PINMUX_OUTPUT_END },
3909 .function = { PINMUX_FUNCTION_BEGIN,
3910 PINMUX_FUNCTION_END },
3911
3912 .pins = pinmux_pins,
3913 .nr_pins = ARRAY_SIZE(pinmux_pins),
3914 .groups = pinmux_groups,
3915 .nr_groups = ARRAY_SIZE(pinmux_groups),
3916 .functions = pinmux_functions,
3917 .nr_functions = ARRAY_SIZE(pinmux_functions),
3918
3919 .func_gpios = pinmux_func_gpios,
3920 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
3921
3922 .cfg_regs = pinmux_config_regs,
3923 .data_regs = pinmux_data_regs,
3924
3925 .gpio_data = pinmux_data,
3926 .gpio_data_size = ARRAY_SIZE(pinmux_data),
3927
3928 .gpio_irq = pinmux_irqs,
3929 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
3930 };
Linux kernel - Deliverables
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