2 * R8A7790 processor support
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Magnus Damm
6 * Copyright (C) 2012 Renesas Solutions Corp.
7 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; version 2 of the
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <linux/kernel.h>
25 #include <linux/platform_data/gpio-rcar.h>
30 #define PORT_GP_30(bank, fn, sfx) \
31 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
32 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
33 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
34 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
35 PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
36 PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
37 PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
38 PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
39 PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
40 PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
41 PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
42 PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
43 PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \
44 PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \
45 PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx)
47 #define CPU_ALL_PORT(fn, sfx) \
48 PORT_GP_32(0, fn, sfx), \
49 PORT_GP_30(1, fn, sfx), \
50 PORT_GP_30(2, fn, sfx), \
51 PORT_GP_32(3, fn, sfx), \
52 PORT_GP_32(4, fn, sfx), \
53 PORT_GP_32(5, fn, sfx)
62 PINMUX_FUNCTION_BEGIN
,
66 FN_IP0_2_0
, FN_IP0_5_3
, FN_IP0_8_6
, FN_IP0_11_9
, FN_IP0_15_12
,
67 FN_IP0_19_16
, FN_IP0_22_20
, FN_IP0_26_23
, FN_IP0_30_27
,
68 FN_IP1_3_0
, FN_IP1_7_4
, FN_IP1_11_8
, FN_IP1_14_12
,
69 FN_IP1_17_15
, FN_IP1_21_18
, FN_IP1_25_22
, FN_IP1_27_26
,
70 FN_IP1_29_28
, FN_IP2_2_0
, FN_IP2_5_3
, FN_IP2_8_6
, FN_IP2_11_9
,
71 FN_IP2_14_12
, FN_IP2_17_15
, FN_IP2_21_18
, FN_IP2_25_22
,
72 FN_IP2_28_26
, FN_IP3_3_0
, FN_IP3_7_4
, FN_IP3_11_8
,
73 FN_IP3_14_12
, FN_IP3_17_15
,
76 FN_IP3_19_18
, FN_IP3_22_20
, FN_IP3_25_23
, FN_IP3_28_26
,
77 FN_IP3_31_29
, FN_IP4_2_0
, FN_IP4_5_3
, FN_IP4_8_6
, FN_IP4_11_9
,
78 FN_IP4_14_12
, FN_IP4_17_15
, FN_IP4_20_18
, FN_IP4_23_21
,
79 FN_IP4_26_24
, FN_IP4_29_27
, FN_IP5_2_0
, FN_IP5_5_3
, FN_IP5_9_6
,
80 FN_IP5_12_10
, FN_IP5_14_13
, FN_IP5_17_15
, FN_IP5_20_18
,
81 FN_IP5_23_21
, FN_IP5_26_24
, FN_IP5_29_27
, FN_IP6_2_0
,
82 FN_IP6_5_3
, FN_IP6_8_6
, FN_IP6_10_9
, FN_IP6_13_11
,
85 FN_IP7_28_27
, FN_IP7_30_29
, FN_IP8_1_0
, FN_IP8_3_2
, FN_IP8_5_4
,
86 FN_IP8_7_6
, FN_IP8_9_8
, FN_IP8_11_10
, FN_IP8_13_12
, FN_IP8_15_14
,
87 FN_IP8_17_16
, FN_IP8_19_18
, FN_IP8_21_20
, FN_IP8_23_22
,
88 FN_IP8_25_24
, FN_IP8_26
, FN_IP8_27
, FN_VI1_DATA7_VI1_B7
,
89 FN_IP6_16_14
, FN_IP6_19_17
, FN_IP6_22_20
, FN_IP6_25_23
,
90 FN_IP6_28_26
, FN_IP6_31_29
, FN_IP7_2_0
, FN_IP7_5_3
, FN_IP7_7_6
,
91 FN_IP7_9_8
, FN_IP7_12_10
, FN_IP7_15_13
,
94 FN_IP8_28
, FN_IP8_30_29
, FN_IP9_1_0
, FN_IP9_3_2
, FN_IP9_5_4
,
95 FN_IP9_7_6
, FN_IP9_11_8
, FN_IP9_15_12
, FN_IP9_17_16
, FN_IP9_19_18
,
96 FN_IP9_21_20
, FN_IP9_23_22
, FN_IP9_25_24
, FN_IP9_27_26
,
97 FN_IP9_31_28
, FN_IP10_3_0
, FN_IP10_6_4
, FN_IP10_10_7
, FN_IP10_14_11
,
98 FN_IP10_18_15
, FN_IP10_22_19
, FN_IP10_25_23
, FN_IP10_29_26
,
99 FN_IP11_3_0
, FN_IP11_4
, FN_IP11_6_5
, FN_IP11_8_7
, FN_IP11_10_9
,
100 FN_IP11_12_11
, FN_IP11_14_13
, FN_IP11_17_15
, FN_IP11_21_18
,
103 FN_IP11_23_22
, FN_IP11_26_24
, FN_IP11_29_27
, FN_IP11_31_30
,
104 FN_IP12_1_0
, FN_IP12_3_2
, FN_IP12_5_4
, FN_IP12_7_6
, FN_IP12_10_8
,
105 FN_IP12_13_11
, FN_IP12_16_14
, FN_IP12_19_17
, FN_IP12_22_20
,
106 FN_IP12_24_23
, FN_IP12_27_25
, FN_IP12_30_28
, FN_IP13_2_0
,
107 FN_IP13_6_3
, FN_IP13_9_7
, FN_IP13_12_10
, FN_IP13_15_13
,
108 FN_IP13_18_16
, FN_IP13_22_19
, FN_IP13_25_23
, FN_IP13_28_26
,
109 FN_IP13_30_29
, FN_IP14_2_0
, FN_IP14_5_3
, FN_IP14_8_6
, FN_IP14_11_9
,
110 FN_IP14_15_12
, FN_IP14_18_16
,
113 FN_IP14_21_19
, FN_IP14_24_22
, FN_IP14_27_25
, FN_IP14_30_28
,
114 FN_IP15_2_0
, FN_IP15_5_3
, FN_IP15_8_6
, FN_IP15_11_9
, FN_IP15_13_12
,
115 FN_IP15_15_14
, FN_IP15_17_16
, FN_IP15_19_18
, FN_IP15_22_20
,
116 FN_IP15_25_23
, FN_IP15_27_26
, FN_IP15_29_28
, FN_IP16_2_0
,
117 FN_IP16_5_3
, FN_USB0_PWEN
, FN_USB0_OVC_VBUS
, FN_IP16_6
, FN_IP16_7
,
118 FN_USB2_PWEN
, FN_USB2_OVC
, FN_AVS1
, FN_AVS2
, FN_DU_DOTCLKIN0
,
119 FN_IP7_26_25
, FN_DU_DOTCLKIN2
, FN_IP7_18_16
, FN_IP7_21_19
, FN_IP7_24_22
,
122 FN_D0
, FN_MSIOF3_SCK_B
, FN_VI3_DATA0
, FN_VI0_G4
, FN_VI0_G4_B
,
123 FN_D1
, FN_MSIOF3_SYNC_B
, FN_VI3_DATA1
, FN_VI0_G5
,
124 FN_VI0_G5_B
, FN_D2
, FN_MSIOF3_RXD_B
, FN_VI3_DATA2
,
125 FN_VI0_G6
, FN_VI0_G6_B
, FN_D3
, FN_MSIOF3_TXD_B
,
126 FN_VI3_DATA3
, FN_VI0_G7
, FN_VI0_G7_B
, FN_D4
,
127 FN_SCIFB1_RXD_F
, FN_SCIFB0_RXD_C
, FN_VI3_DATA4
,
128 FN_VI0_R0
, FN_VI0_R0_B
, FN_RX0_B
, FN_D5
,
129 FN_SCIFB1_TXD_F
, FN_SCIFB0_TXD_C
, FN_VI3_DATA5
,
130 FN_VI0_R1
, FN_VI0_R1_B
, FN_TX0_B
, FN_D6
,
131 FN_IIC2_SCL_C
, FN_VI3_DATA6
, FN_VI0_R2
, FN_VI0_R2_B
,
132 FN_I2C2_SCL_C
, FN_D7
, FN_AD_DI_B
, FN_IIC2_SDA_C
,
133 FN_VI3_DATA7
, FN_VI0_R3
, FN_VI0_R3_B
, FN_I2C2_SDA_C
, FN_TCLK1
,
134 FN_D8
, FN_SCIFA1_SCK_C
, FN_AVB_TXD0
,
135 FN_VI0_G0
, FN_VI0_G0_B
, FN_VI2_DATA0_VI2_B0
,
138 FN_D9
, FN_SCIFA1_RXD_C
, FN_AVB_TXD1
,
139 FN_VI0_G1
, FN_VI0_G1_B
, FN_VI2_DATA1_VI2_B1
, FN_D10
,
140 FN_SCIFA1_TXD_C
, FN_AVB_TXD2
,
141 FN_VI0_G2
, FN_VI0_G2_B
, FN_VI2_DATA2_VI2_B2
, FN_D11
,
142 FN_SCIFA1_CTS_N_C
, FN_AVB_TXD3
,
143 FN_VI0_G3
, FN_VI0_G3_B
, FN_VI2_DATA3_VI2_B3
,
144 FN_D12
, FN_SCIFA1_RTS_N_C
, FN_AVB_TXD4
,
145 FN_VI0_HSYNC_N
, FN_VI0_HSYNC_N_B
, FN_VI2_DATA4_VI2_B4
,
146 FN_D13
, FN_AVB_TXD5
, FN_VI0_VSYNC_N
,
147 FN_VI0_VSYNC_N_B
, FN_VI2_DATA5_VI2_B5
, FN_D14
,
148 FN_SCIFB1_RXD_C
, FN_AVB_TXD6
, FN_RX1_B
,
149 FN_VI0_CLKENB
, FN_VI0_CLKENB_B
, FN_VI2_DATA6_VI2_B6
,
150 FN_D15
, FN_SCIFB1_TXD_C
, FN_AVB_TXD7
, FN_TX1_B
,
151 FN_VI0_FIELD
, FN_VI0_FIELD_B
, FN_VI2_DATA7_VI2_B7
,
152 FN_A0
, FN_PWM3
, FN_A1
, FN_PWM4
,
155 FN_A2
, FN_PWM5
, FN_MSIOF1_SS1_B
, FN_A3
,
156 FN_PWM6
, FN_MSIOF1_SS2_B
, FN_A4
, FN_MSIOF1_TXD_B
,
157 FN_TPU0TO0
, FN_A5
, FN_SCIFA1_TXD_B
, FN_TPU0TO1
,
158 FN_A6
, FN_SCIFA1_RTS_N_B
, FN_TPU0TO2
, FN_A7
,
159 FN_SCIFA1_SCK_B
, FN_AUDIO_CLKOUT_B
, FN_TPU0TO3
,
160 FN_A8
, FN_SCIFA1_RXD_B
, FN_SSI_SCK5_B
, FN_VI0_R4
,
161 FN_VI0_R4_B
, FN_SCIFB2_RXD_C
, FN_RX2_B
, FN_VI2_DATA0_VI2_B0_B
,
162 FN_A9
, FN_SCIFA1_CTS_N_B
, FN_SSI_WS5_B
, FN_VI0_R5
,
163 FN_VI0_R5_B
, FN_SCIFB2_TXD_C
, FN_TX2_B
, FN_VI2_DATA1_VI2_B1_B
,
164 FN_A10
, FN_SSI_SDATA5_B
, FN_MSIOF2_SYNC
, FN_VI0_R6
,
165 FN_VI0_R6_B
, FN_VI2_DATA2_VI2_B2_B
,
168 FN_A11
, FN_SCIFB2_CTS_N_B
, FN_MSIOF2_SCK
, FN_VI1_R0
,
169 FN_VI1_R0_B
, FN_VI2_G0
, FN_VI2_DATA3_VI2_B3_B
,
170 FN_A12
, FN_SCIFB2_RXD_B
, FN_MSIOF2_TXD
, FN_VI1_R1
,
171 FN_VI1_R1_B
, FN_VI2_G1
, FN_VI2_DATA4_VI2_B4_B
,
172 FN_A13
, FN_SCIFB2_RTS_N_B
, FN_EX_WAIT2
,
173 FN_MSIOF2_RXD
, FN_VI1_R2
, FN_VI1_R2_B
, FN_VI2_G2
,
174 FN_VI2_DATA5_VI2_B5_B
, FN_A14
, FN_SCIFB2_TXD_B
,
175 FN_ATACS11_N
, FN_MSIOF2_SS1
, FN_A15
, FN_SCIFB2_SCK_B
,
176 FN_ATARD1_N
, FN_MSIOF2_SS2
, FN_A16
, FN_ATAWR1_N
,
177 FN_A17
, FN_AD_DO_B
, FN_ATADIR1_N
, FN_A18
,
178 FN_AD_CLK_B
, FN_ATAG1_N
, FN_A19
, FN_AD_NCS_N_B
,
179 FN_ATACS01_N
, FN_EX_WAIT0_B
, FN_A20
, FN_SPCLK
,
180 FN_VI1_R3
, FN_VI1_R3_B
, FN_VI2_G4
,
183 FN_A21
, FN_MOSI_IO0
, FN_VI1_R4
, FN_VI1_R4_B
, FN_VI2_G5
,
184 FN_A22
, FN_MISO_IO1
, FN_VI1_R5
, FN_VI1_R5_B
,
185 FN_VI2_G6
, FN_A23
, FN_IO2
, FN_VI1_G7
,
186 FN_VI1_G7_B
, FN_VI2_G7
, FN_A24
, FN_IO3
,
187 FN_VI1_R7
, FN_VI1_R7_B
, FN_VI2_CLKENB
,
188 FN_VI2_CLKENB_B
, FN_A25
, FN_SSL
, FN_VI1_G6
,
189 FN_VI1_G6_B
, FN_VI2_FIELD
, FN_VI2_FIELD_B
, FN_CS0_N
,
190 FN_VI1_R6
, FN_VI1_R6_B
, FN_VI2_G3
, FN_MSIOF0_SS2_B
,
191 FN_CS1_N_A26
, FN_SPEEDIN
, FN_VI0_R7
, FN_VI0_R7_B
,
192 FN_VI2_CLK
, FN_VI2_CLK_B
, FN_EX_CS0_N
, FN_HRX1_B
,
193 FN_VI1_G5
, FN_VI1_G5_B
, FN_VI2_R0
, FN_HTX0_B
,
194 FN_MSIOF0_SS1_B
, FN_EX_CS1_N
, FN_GPS_CLK
,
195 FN_HCTS1_N_B
, FN_VI1_FIELD
, FN_VI1_FIELD_B
,
196 FN_VI2_R1
, FN_EX_CS2_N
, FN_GPS_SIGN
, FN_HRTS1_N_B
,
197 FN_VI3_CLKENB
, FN_VI1_G0
, FN_VI1_G0_B
, FN_VI2_R2
,
200 FN_EX_CS3_N
, FN_GPS_MAG
, FN_VI3_FIELD
, FN_VI1_G1
, FN_VI1_G1_B
,
201 FN_VI2_R3
, FN_EX_CS4_N
, FN_MSIOF1_SCK_B
, FN_VI3_HSYNC_N
,
202 FN_VI2_HSYNC_N
, FN_IIC1_SCL
, FN_VI2_HSYNC_N_B
,
203 FN_INTC_EN0_N
, FN_I2C1_SCL
, FN_EX_CS5_N
, FN_CAN0_RX
,
204 FN_MSIOF1_RXD_B
, FN_VI3_VSYNC_N
, FN_VI1_G2
,
205 FN_VI1_G2_B
, FN_VI2_R4
, FN_IIC1_SDA
, FN_INTC_EN1_N
,
206 FN_I2C1_SDA
, FN_BS_N
, FN_IETX
, FN_HTX1_B
,
207 FN_CAN1_TX
, FN_DRACK0
, FN_IETX_C
, FN_RD_N
,
208 FN_CAN0_TX
, FN_SCIFA0_SCK_B
, FN_RD_WR_N
, FN_VI1_G3
,
209 FN_VI1_G3_B
, FN_VI2_R5
, FN_SCIFA0_RXD_B
,
210 FN_INTC_IRQ4_N
, FN_WE0_N
, FN_IECLK
, FN_CAN_CLK
,
211 FN_VI2_VSYNC_N
, FN_SCIFA0_TXD_B
, FN_VI2_VSYNC_N_B
,
212 FN_WE1_N
, FN_IERX
, FN_CAN1_RX
, FN_VI1_G4
,
213 FN_VI1_G4_B
, FN_VI2_R6
, FN_SCIFA0_CTS_N_B
,
214 FN_IERX_C
, FN_EX_WAIT0
, FN_IRQ3
, FN_INTC_IRQ3_N
,
215 FN_VI3_CLK
, FN_SCIFA0_RTS_N_B
, FN_HRX0_B
,
216 FN_MSIOF0_SCK_B
, FN_DREQ0_N
, FN_VI1_HSYNC_N
,
217 FN_VI1_HSYNC_N_B
, FN_VI2_R7
, FN_SSI_SCK78_C
,
221 FN_DACK0
, FN_IRQ0
, FN_INTC_IRQ0_N
, FN_SSI_SCK6_B
,
222 FN_VI1_VSYNC_N
, FN_VI1_VSYNC_N_B
, FN_SSI_WS78_C
,
223 FN_DREQ1_N
, FN_VI1_CLKENB
, FN_VI1_CLKENB_B
,
224 FN_SSI_SDATA7_C
, FN_SSI_SCK78_B
, FN_DACK1
, FN_IRQ1
,
225 FN_INTC_IRQ1_N
, FN_SSI_WS6_B
, FN_SSI_SDATA8_C
,
226 FN_DREQ2_N
, FN_HSCK1_B
, FN_HCTS0_N_B
,
227 FN_MSIOF0_TXD_B
, FN_DACK2
, FN_IRQ2
, FN_INTC_IRQ2_N
,
228 FN_SSI_SDATA6_B
, FN_HRTS0_N_B
, FN_MSIOF0_RXD_B
,
229 FN_ETH_CRS_DV
, FN_STP_ISCLK_0_B
,
230 FN_TS_SDEN0_D
, FN_GLO_Q0_C
, FN_IIC2_SCL_E
,
231 FN_I2C2_SCL_E
, FN_ETH_RX_ER
,
232 FN_STP_ISD_0_B
, FN_TS_SPSYNC0_D
, FN_GLO_Q1_C
,
233 FN_IIC2_SDA_E
, FN_I2C2_SDA_E
, FN_ETH_RXD0
,
234 FN_STP_ISEN_0_B
, FN_TS_SDAT0_D
, FN_GLO_I0_C
,
235 FN_SCIFB1_SCK_G
, FN_SCK1_E
, FN_ETH_RXD1
,
236 FN_HRX0_E
, FN_STP_ISSYNC_0_B
,
237 FN_TS_SCK0_D
, FN_GLO_I1_C
, FN_SCIFB1_RXD_G
,
238 FN_RX1_E
, FN_ETH_LINK
, FN_HTX0_E
,
239 FN_STP_IVCXO27_0_B
, FN_SCIFB1_TXD_G
, FN_TX1_E
,
240 FN_ETH_REF_CLK
, FN_HCTS0_N_E
,
241 FN_STP_IVCXO27_1_B
, FN_HRX0_F
,
244 FN_ETH_MDIO
, FN_HRTS0_N_E
,
245 FN_SIM0_D_C
, FN_HCTS0_N_F
, FN_ETH_TXD1
,
246 FN_HTX0_F
, FN_BPFCLK_G
,
247 FN_ETH_TX_EN
, FN_SIM0_CLK_C
,
248 FN_HRTS0_N_F
, FN_ETH_MAGIC
,
249 FN_SIM0_RST_C
, FN_ETH_TXD0
,
250 FN_STP_ISCLK_1_B
, FN_TS_SDEN1_C
, FN_GLO_SCLK_C
,
251 FN_ETH_MDC
, FN_STP_ISD_1_B
,
252 FN_TS_SPSYNC1_C
, FN_GLO_SDATA_C
, FN_PWM0
,
253 FN_SCIFA2_SCK_C
, FN_STP_ISEN_1_B
, FN_TS_SDAT1_C
,
254 FN_GLO_SS_C
, FN_PWM1
, FN_SCIFA2_TXD_C
,
255 FN_STP_ISSYNC_1_B
, FN_TS_SCK1_C
, FN_GLO_RFON_C
,
256 FN_PCMOE_N
, FN_PWM2
, FN_PWMFSW0
, FN_SCIFA2_RXD_C
,
257 FN_PCMWE_N
, FN_IECLK_C
, FN_DU_DOTCLKIN1
,
258 FN_AUDIO_CLKC
, FN_AUDIO_CLKOUT_C
, FN_VI0_CLK
,
259 FN_ATACS00_N
, FN_AVB_RXD1
,
260 FN_VI0_DATA0_VI0_B0
, FN_ATACS10_N
, FN_AVB_RXD2
,
263 FN_VI0_DATA1_VI0_B1
, FN_ATARD0_N
, FN_AVB_RXD3
,
264 FN_VI0_DATA2_VI0_B2
, FN_ATAWR0_N
,
265 FN_AVB_RXD4
, FN_VI0_DATA3_VI0_B3
, FN_ATADIR0_N
,
266 FN_AVB_RXD5
, FN_VI0_DATA4_VI0_B4
, FN_ATAG0_N
,
267 FN_AVB_RXD6
, FN_VI0_DATA5_VI0_B5
, FN_EX_WAIT1
,
268 FN_AVB_RXD7
, FN_VI0_DATA6_VI0_B6
, FN_AVB_RX_ER
,
269 FN_VI0_DATA7_VI0_B7
, FN_AVB_RX_CLK
,
270 FN_VI1_CLK
, FN_AVB_RX_DV
,
271 FN_VI1_DATA0_VI1_B0
, FN_SCIFA1_SCK_D
,
272 FN_AVB_CRS
, FN_VI1_DATA1_VI1_B1
,
273 FN_SCIFA1_RXD_D
, FN_AVB_MDC
,
274 FN_VI1_DATA2_VI1_B2
, FN_SCIFA1_TXD_D
, FN_AVB_MDIO
,
275 FN_VI1_DATA3_VI1_B3
, FN_SCIFA1_CTS_N_D
,
276 FN_AVB_GTX_CLK
, FN_VI1_DATA4_VI1_B4
, FN_SCIFA1_RTS_N_D
,
277 FN_AVB_MAGIC
, FN_VI1_DATA5_VI1_B5
,
278 FN_AVB_PHY_INT
, FN_VI1_DATA6_VI1_B6
, FN_AVB_GTXREFCLK
,
279 FN_SD0_CLK
, FN_VI1_DATA0_VI1_B0_B
, FN_SD0_CMD
,
280 FN_SCIFB1_SCK_B
, FN_VI1_DATA1_VI1_B1_B
,
283 FN_SD0_DAT0
, FN_SCIFB1_RXD_B
, FN_VI1_DATA2_VI1_B2_B
,
284 FN_SD0_DAT1
, FN_SCIFB1_TXD_B
, FN_VI1_DATA3_VI1_B3_B
,
285 FN_SD0_DAT2
, FN_SCIFB1_CTS_N_B
, FN_VI1_DATA4_VI1_B4_B
,
286 FN_SD0_DAT3
, FN_SCIFB1_RTS_N_B
, FN_VI1_DATA5_VI1_B5_B
,
287 FN_SD0_CD
, FN_MMC0_D6
, FN_TS_SDEN0_B
, FN_USB0_EXTP
,
288 FN_GLO_SCLK
, FN_VI1_DATA6_VI1_B6_B
, FN_IIC1_SCL_B
,
289 FN_I2C1_SCL_B
, FN_VI2_DATA6_VI2_B6_B
, FN_SD0_WP
,
290 FN_MMC0_D7
, FN_TS_SPSYNC0_B
, FN_USB0_IDIN
,
291 FN_GLO_SDATA
, FN_VI1_DATA7_VI1_B7_B
, FN_IIC1_SDA_B
,
292 FN_I2C1_SDA_B
, FN_VI2_DATA7_VI2_B7_B
, FN_SD1_CLK
,
293 FN_AVB_TX_EN
, FN_SD1_CMD
,
294 FN_AVB_TX_ER
, FN_SCIFB0_SCK_B
,
295 FN_SD1_DAT0
, FN_AVB_TX_CLK
,
296 FN_SCIFB0_RXD_B
, FN_SD1_DAT1
, FN_AVB_LINK
,
297 FN_SCIFB0_TXD_B
, FN_SD1_DAT2
,
298 FN_AVB_COL
, FN_SCIFB0_CTS_N_B
,
299 FN_SD1_DAT3
, FN_AVB_RXD0
,
300 FN_SCIFB0_RTS_N_B
, FN_SD1_CD
, FN_MMC1_D6
,
301 FN_TS_SDEN1
, FN_USB1_EXTP
, FN_GLO_SS
, FN_VI0_CLK_B
,
302 FN_IIC2_SCL_D
, FN_I2C2_SCL_D
, FN_SIM0_CLK_B
,
306 FN_SD1_WP
, FN_MMC1_D7
, FN_TS_SPSYNC1
, FN_USB1_IDIN
,
307 FN_GLO_RFON
, FN_VI1_CLK_B
, FN_IIC2_SDA_D
, FN_I2C2_SDA_D
,
308 FN_SIM0_D_B
, FN_SD2_CLK
, FN_MMC0_CLK
, FN_SIM0_CLK
,
309 FN_VI0_DATA0_VI0_B0_B
, FN_TS_SDEN0_C
, FN_GLO_SCLK_B
,
310 FN_VI3_DATA0_B
, FN_SD2_CMD
, FN_MMC0_CMD
, FN_SIM0_D
,
311 FN_VI0_DATA1_VI0_B1_B
, FN_SCIFB1_SCK_E
, FN_SCK1_D
,
312 FN_TS_SPSYNC0_C
, FN_GLO_SDATA_B
, FN_VI3_DATA1_B
,
313 FN_SD2_DAT0
, FN_MMC0_D0
, FN_FMCLK_B
,
314 FN_VI0_DATA2_VI0_B2_B
, FN_SCIFB1_RXD_E
, FN_RX1_D
,
315 FN_TS_SDAT0_C
, FN_GLO_SS_B
, FN_VI3_DATA2_B
,
316 FN_SD2_DAT1
, FN_MMC0_D1
, FN_FMIN_B
,
317 FN_VI0_DATA3_VI0_B3_B
, FN_SCIFB1_TXD_E
, FN_TX1_D
,
318 FN_TS_SCK0_C
, FN_GLO_RFON_B
, FN_VI3_DATA3_B
,
319 FN_SD2_DAT2
, FN_MMC0_D2
, FN_BPFCLK_B
,
320 FN_VI0_DATA4_VI0_B4_B
, FN_HRX0_D
, FN_TS_SDEN1_B
,
321 FN_GLO_Q0_B
, FN_VI3_DATA4_B
, FN_SD2_DAT3
,
322 FN_MMC0_D3
, FN_SIM0_RST
, FN_VI0_DATA5_VI0_B5_B
,
323 FN_HTX0_D
, FN_TS_SPSYNC1_B
, FN_GLO_Q1_B
,
324 FN_VI3_DATA5_B
, FN_SD2_CD
, FN_MMC0_D4
,
325 FN_TS_SDAT0_B
, FN_USB2_EXTP
, FN_GLO_I0
,
326 FN_VI0_DATA6_VI0_B6_B
, FN_HCTS0_N_D
, FN_TS_SDAT1_B
,
327 FN_GLO_I0_B
, FN_VI3_DATA6_B
,
330 FN_SD2_WP
, FN_MMC0_D5
, FN_TS_SCK0_B
, FN_USB2_IDIN
,
331 FN_GLO_I1
, FN_VI0_DATA7_VI0_B7_B
, FN_HRTS0_N_D
,
332 FN_TS_SCK1_B
, FN_GLO_I1_B
, FN_VI3_DATA7_B
,
333 FN_SD3_CLK
, FN_MMC1_CLK
, FN_SD3_CMD
, FN_MMC1_CMD
,
334 FN_MTS_N
, FN_SD3_DAT0
, FN_MMC1_D0
, FN_STM_N
,
335 FN_SD3_DAT1
, FN_MMC1_D1
, FN_MDATA
, FN_SD3_DAT2
,
336 FN_MMC1_D2
, FN_SDATA
, FN_SD3_DAT3
, FN_MMC1_D3
,
337 FN_SCKZ
, FN_SD3_CD
, FN_MMC1_D4
, FN_TS_SDAT1
,
338 FN_VSP
, FN_GLO_Q0
, FN_SIM0_RST_B
, FN_SD3_WP
,
339 FN_MMC1_D5
, FN_TS_SCK1
, FN_GLO_Q1
, FN_FMIN_C
,
340 FN_FMIN_E
, FN_FMIN_F
,
341 FN_MLB_CLK
, FN_IIC2_SCL_B
, FN_I2C2_SCL_B
,
342 FN_MLB_SIG
, FN_SCIFB1_RXD_D
, FN_RX1_C
, FN_IIC2_SDA_B
,
343 FN_I2C2_SDA_B
, FN_MLB_DAT
,
344 FN_SCIFB1_TXD_D
, FN_TX1_C
, FN_BPFCLK_C
,
345 FN_SSI_SCK0129
, FN_CAN_CLK_B
,
349 FN_SSI_WS0129
, FN_CAN0_TX_B
, FN_MOUT1
,
350 FN_SSI_SDATA0
, FN_CAN0_RX_B
, FN_MOUT2
,
351 FN_SSI_SDATA1
, FN_CAN1_TX_B
, FN_MOUT5
,
352 FN_SSI_SDATA2
, FN_CAN1_RX_B
, FN_SSI_SCK1
, FN_MOUT6
,
353 FN_SSI_SCK34
, FN_STP_OPWM_0
, FN_SCIFB0_SCK
,
354 FN_MSIOF1_SCK
, FN_CAN_DEBUG_HW_TRIGGER
, FN_SSI_WS34
,
355 FN_STP_IVCXO27_0
, FN_SCIFB0_RXD
, FN_MSIOF1_SYNC
,
356 FN_CAN_STEP0
, FN_SSI_SDATA3
, FN_STP_ISCLK_0
,
357 FN_SCIFB0_TXD
, FN_MSIOF1_SS1
, FN_CAN_TXCLK
,
358 FN_SSI_SCK4
, FN_STP_ISD_0
, FN_SCIFB0_CTS_N
,
359 FN_MSIOF1_SS2
, FN_SSI_SCK5_C
, FN_CAN_DEBUGOUT0
,
360 FN_SSI_WS4
, FN_STP_ISEN_0
, FN_SCIFB0_RTS_N
,
361 FN_MSIOF1_TXD
, FN_SSI_WS5_C
, FN_CAN_DEBUGOUT1
,
362 FN_SSI_SDATA4
, FN_STP_ISSYNC_0
, FN_MSIOF1_RXD
,
363 FN_CAN_DEBUGOUT2
, FN_SSI_SCK5
, FN_SCIFB1_SCK
,
364 FN_IERX_B
, FN_DU2_EXHSYNC_DU2_HSYNC
, FN_QSTH_QHS
,
365 FN_CAN_DEBUGOUT3
, FN_SSI_WS5
, FN_SCIFB1_RXD
,
366 FN_IECLK_B
, FN_DU2_EXVSYNC_DU2_VSYNC
, FN_QSTB_QHE
,
370 FN_SSI_SDATA5
, FN_SCIFB1_TXD
, FN_IETX_B
, FN_DU2_DR2
,
371 FN_LCDOUT2
, FN_CAN_DEBUGOUT5
, FN_SSI_SCK6
,
372 FN_SCIFB1_CTS_N
, FN_BPFCLK_D
,
373 FN_DU2_DR3
, FN_LCDOUT3
, FN_CAN_DEBUGOUT6
,
374 FN_BPFCLK_F
, FN_SSI_WS6
,
375 FN_SCIFB1_RTS_N
, FN_CAN0_TX_D
, FN_DU2_DR4
,
376 FN_LCDOUT4
, FN_CAN_DEBUGOUT7
, FN_SSI_SDATA6
,
377 FN_FMIN_D
, FN_DU2_DR5
, FN_LCDOUT5
,
378 FN_CAN_DEBUGOUT8
, FN_SSI_SCK78
, FN_STP_IVCXO27_1
,
379 FN_SCK1
, FN_SCIFA1_SCK
, FN_DU2_DR6
, FN_LCDOUT6
,
380 FN_CAN_DEBUGOUT9
, FN_SSI_WS78
, FN_STP_ISCLK_1
,
381 FN_SCIFB2_SCK
, FN_SCIFA2_CTS_N
, FN_DU2_DR7
,
382 FN_LCDOUT7
, FN_CAN_DEBUGOUT10
, FN_SSI_SDATA7
,
383 FN_STP_ISD_1
, FN_SCIFB2_RXD
, FN_SCIFA2_RTS_N
,
384 FN_TCLK2
, FN_QSTVA_QVS
, FN_CAN_DEBUGOUT11
,
385 FN_BPFCLK_E
, FN_SSI_SDATA7_B
,
386 FN_FMIN_G
, FN_SSI_SDATA8
,
387 FN_STP_ISEN_1
, FN_SCIFB2_TXD
, FN_CAN0_TX_C
,
388 FN_CAN_DEBUGOUT12
, FN_SSI_SDATA8_B
, FN_SSI_SDATA9
,
389 FN_STP_ISSYNC_1
, FN_SCIFB2_CTS_N
, FN_SSI_WS1
,
390 FN_SSI_SDATA5_C
, FN_CAN_DEBUGOUT13
, FN_AUDIO_CLKA
,
391 FN_SCIFB2_RTS_N
, FN_CAN_DEBUGOUT14
,
394 FN_AUDIO_CLKB
, FN_SCIF_CLK
, FN_CAN0_RX_D
,
395 FN_DVC_MUTE
, FN_CAN0_RX_C
, FN_CAN_DEBUGOUT15
,
396 FN_REMOCON
, FN_SCIFA0_SCK
, FN_HSCK1
, FN_SCK0
,
397 FN_MSIOF3_SS2
, FN_DU2_DG2
, FN_LCDOUT10
, FN_IIC1_SDA_C
,
398 FN_I2C1_SDA_C
, FN_SCIFA0_RXD
, FN_HRX1
, FN_RX0
,
399 FN_DU2_DR0
, FN_LCDOUT0
, FN_SCIFA0_TXD
, FN_HTX1
,
400 FN_TX0
, FN_DU2_DR1
, FN_LCDOUT1
, FN_SCIFA0_CTS_N
,
401 FN_HCTS1_N
, FN_CTS0_N
, FN_MSIOF3_SYNC
, FN_DU2_DG3
,
402 FN_LCDOUT11
, FN_PWM0_B
, FN_IIC1_SCL_C
, FN_I2C1_SCL_C
,
403 FN_SCIFA0_RTS_N
, FN_HRTS1_N
, FN_RTS0_N
,
404 FN_MSIOF3_SS1
, FN_DU2_DG0
, FN_LCDOUT8
, FN_PWM1_B
,
405 FN_SCIFA1_RXD
, FN_AD_DI
, FN_RX1
,
406 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE
, FN_QCPV_QDE
,
407 FN_SCIFA1_TXD
, FN_AD_DO
, FN_TX1
, FN_DU2_DG1
,
408 FN_LCDOUT9
, FN_SCIFA1_CTS_N
, FN_AD_CLK
,
409 FN_CTS1_N
, FN_MSIOF3_RXD
, FN_DU0_DOTCLKOUT
, FN_QCLK
,
410 FN_SCIFA1_RTS_N
, FN_AD_NCS_N
, FN_RTS1_N
,
411 FN_MSIOF3_TXD
, FN_DU1_DOTCLKOUT
, FN_QSTVB_QVE
,
415 FN_SCIFA2_SCK
, FN_FMCLK
, FN_SCK2
, FN_MSIOF3_SCK
, FN_DU2_DG7
,
416 FN_LCDOUT15
, FN_SCIF_CLK_B
, FN_SCIFA2_RXD
, FN_FMIN
,
417 FN_TX2
, FN_DU2_DB0
, FN_LCDOUT16
, FN_IIC2_SCL
, FN_I2C2_SCL
,
418 FN_SCIFA2_TXD
, FN_BPFCLK
, FN_RX2
, FN_DU2_DB1
, FN_LCDOUT17
,
419 FN_IIC2_SDA
, FN_I2C2_SDA
, FN_HSCK0
, FN_TS_SDEN0
,
420 FN_DU2_DG4
, FN_LCDOUT12
, FN_HCTS0_N_C
, FN_HRX0
,
421 FN_DU2_DB2
, FN_LCDOUT18
, FN_HTX0
, FN_DU2_DB3
,
422 FN_LCDOUT19
, FN_HCTS0_N
, FN_SSI_SCK9
, FN_DU2_DB4
,
423 FN_LCDOUT20
, FN_HRTS0_N
, FN_SSI_WS9
, FN_DU2_DB5
,
424 FN_LCDOUT21
, FN_MSIOF0_SCK
, FN_TS_SDAT0
, FN_ADICLK
,
425 FN_DU2_DB6
, FN_LCDOUT22
, FN_MSIOF0_SYNC
, FN_TS_SCK0
,
426 FN_SSI_SCK2
, FN_ADIDATA
, FN_DU2_DB7
, FN_LCDOUT23
,
427 FN_HRX0_C
, FN_MSIOF0_SS1
, FN_ADICHS0
,
428 FN_DU2_DG5
, FN_LCDOUT13
, FN_MSIOF0_TXD
, FN_ADICHS1
,
429 FN_DU2_DG6
, FN_LCDOUT14
,
432 FN_MSIOF0_SS2
, FN_AUDIO_CLKOUT
, FN_ADICHS2
,
433 FN_DU2_DISP
, FN_QPOLA
, FN_HTX0_C
, FN_SCIFA2_TXD_B
,
434 FN_MSIOF0_RXD
, FN_TS_SPSYNC0
, FN_SSI_WS2
,
435 FN_ADICS_SAMP
, FN_DU2_CDE
, FN_QPOLB
, FN_SCIFA2_RXD_B
,
436 FN_USB1_PWEN
, FN_AUDIO_CLKOUT_D
, FN_USB1_OVC
,
439 FN_SEL_SCIF1_0
, FN_SEL_SCIF1_1
, FN_SEL_SCIF1_2
, FN_SEL_SCIF1_3
,
441 FN_SEL_SCIFB_0
, FN_SEL_SCIFB_1
, FN_SEL_SCIFB_2
,
442 FN_SEL_SCIFB2_0
, FN_SEL_SCIFB2_1
, FN_SEL_SCIFB2_2
,
443 FN_SEL_SCIFB1_0
, FN_SEL_SCIFB1_1
, FN_SEL_SCIFB1_2
, FN_SEL_SCIFB1_3
,
445 FN_SEL_SCIFB1_5
, FN_SEL_SCIFB1_6
,
446 FN_SEL_SCIFA1_0
, FN_SEL_SCIFA1_1
, FN_SEL_SCIFA1_2
, FN_SEL_SCIFA1_3
,
447 FN_SEL_SCIF0_0
, FN_SEL_SCIF0_1
,
448 FN_SEL_SCFA_0
, FN_SEL_SCFA_1
,
449 FN_SEL_SOF1_0
, FN_SEL_SOF1_1
,
450 FN_SEL_SSI7_0
, FN_SEL_SSI7_1
, FN_SEL_SSI7_2
,
451 FN_SEL_SSI6_0
, FN_SEL_SSI6_1
,
452 FN_SEL_SSI5_0
, FN_SEL_SSI5_1
, FN_SEL_SSI5_2
,
453 FN_SEL_VI3_0
, FN_SEL_VI3_1
,
454 FN_SEL_VI2_0
, FN_SEL_VI2_1
,
455 FN_SEL_VI1_0
, FN_SEL_VI1_1
,
456 FN_SEL_VI0_0
, FN_SEL_VI0_1
,
457 FN_SEL_TSIF1_0
, FN_SEL_TSIF1_1
, FN_SEL_TSIF1_2
,
458 FN_SEL_LBS_0
, FN_SEL_LBS_1
,
459 FN_SEL_TSIF0_0
, FN_SEL_TSIF0_1
, FN_SEL_TSIF0_2
, FN_SEL_TSIF0_3
,
460 FN_SEL_SOF3_0
, FN_SEL_SOF3_1
,
461 FN_SEL_SOF0_0
, FN_SEL_SOF0_1
,
463 FN_SEL_TMU1_0
, FN_SEL_TMU1_1
,
464 FN_SEL_HSCIF1_0
, FN_SEL_HSCIF1_1
,
465 FN_SEL_SCIFCLK_0
, FN_SEL_SCIFCLK_1
,
466 FN_SEL_CAN0_0
, FN_SEL_CAN0_1
, FN_SEL_CAN0_2
, FN_SEL_CAN0_3
,
467 FN_SEL_CANCLK_0
, FN_SEL_CANCLK_1
,
468 FN_SEL_SCIFA2_0
, FN_SEL_SCIFA2_1
, FN_SEL_SCIFA2_2
,
469 FN_SEL_CAN1_0
, FN_SEL_CAN1_1
,
470 FN_SEL_SCIF2_0
, FN_SEL_SCIF2_1
,
471 FN_SEL_ADI_0
, FN_SEL_ADI_1
,
472 FN_SEL_SSP_0
, FN_SEL_SSP_1
,
473 FN_SEL_FM_0
, FN_SEL_FM_1
, FN_SEL_FM_2
, FN_SEL_FM_3
,
474 FN_SEL_FM_4
, FN_SEL_FM_5
, FN_SEL_FM_6
,
475 FN_SEL_HSCIF0_0
, FN_SEL_HSCIF0_1
, FN_SEL_HSCIF0_2
, FN_SEL_HSCIF0_3
,
476 FN_SEL_HSCIF0_4
, FN_SEL_HSCIF0_5
,
477 FN_SEL_GPS_0
, FN_SEL_GPS_1
, FN_SEL_GPS_2
,
478 FN_SEL_SIM_0
, FN_SEL_SIM_1
, FN_SEL_SIM_2
,
479 FN_SEL_SSI8_0
, FN_SEL_SSI8_1
, FN_SEL_SSI8_2
,
481 FN_SEL_IICDVFS_0
, FN_SEL_IICDVFS_1
,
482 FN_SEL_IIC0_0
, FN_SEL_IIC0_1
,
483 FN_SEL_IEB_0
, FN_SEL_IEB_1
, FN_SEL_IEB_2
,
484 FN_SEL_IIC2_0
, FN_SEL_IIC2_1
, FN_SEL_IIC2_2
, FN_SEL_IIC2_3
,
486 FN_SEL_IIC1_0
, FN_SEL_IIC1_1
, FN_SEL_IIC1_2
,
487 FN_SEL_I2C2_0
, FN_SEL_I2C2_1
, FN_SEL_I2C2_2
, FN_SEL_I2C2_3
,
489 FN_SEL_I2C1_0
, FN_SEL_I2C1_1
, FN_SEL_I2C1_2
,
494 VI1_DATA7_VI1_B7_MARK
,
496 USB0_PWEN_MARK
, USB0_OVC_VBUS_MARK
,
497 USB2_PWEN_MARK
, USB2_OVC_MARK
, AVS1_MARK
, AVS2_MARK
,
498 DU_DOTCLKIN0_MARK
, DU_DOTCLKIN2_MARK
,
500 D0_MARK
, MSIOF3_SCK_B_MARK
, VI3_DATA0_MARK
, VI0_G4_MARK
, VI0_G4_B_MARK
,
501 D1_MARK
, MSIOF3_SYNC_B_MARK
, VI3_DATA1_MARK
, VI0_G5_MARK
,
502 VI0_G5_B_MARK
, D2_MARK
, MSIOF3_RXD_B_MARK
, VI3_DATA2_MARK
,
503 VI0_G6_MARK
, VI0_G6_B_MARK
, D3_MARK
, MSIOF3_TXD_B_MARK
,
504 VI3_DATA3_MARK
, VI0_G7_MARK
, VI0_G7_B_MARK
, D4_MARK
,
505 SCIFB1_RXD_F_MARK
, SCIFB0_RXD_C_MARK
, VI3_DATA4_MARK
,
506 VI0_R0_MARK
, VI0_R0_B_MARK
, RX0_B_MARK
, D5_MARK
,
507 SCIFB1_TXD_F_MARK
, SCIFB0_TXD_C_MARK
, VI3_DATA5_MARK
,
508 VI0_R1_MARK
, VI0_R1_B_MARK
, TX0_B_MARK
, D6_MARK
,
509 IIC2_SCL_C_MARK
, VI3_DATA6_MARK
, VI0_R2_MARK
, VI0_R2_B_MARK
,
510 I2C2_SCL_C_MARK
, D7_MARK
, AD_DI_B_MARK
, IIC2_SDA_C_MARK
,
511 VI3_DATA7_MARK
, VI0_R3_MARK
, VI0_R3_B_MARK
, I2C2_SDA_C_MARK
, TCLK1_MARK
,
512 D8_MARK
, SCIFA1_SCK_C_MARK
, AVB_TXD0_MARK
,
513 VI0_G0_MARK
, VI0_G0_B_MARK
, VI2_DATA0_VI2_B0_MARK
,
515 D9_MARK
, SCIFA1_RXD_C_MARK
, AVB_TXD1_MARK
,
516 VI0_G1_MARK
, VI0_G1_B_MARK
, VI2_DATA1_VI2_B1_MARK
, D10_MARK
,
517 SCIFA1_TXD_C_MARK
, AVB_TXD2_MARK
,
518 VI0_G2_MARK
, VI0_G2_B_MARK
, VI2_DATA2_VI2_B2_MARK
, D11_MARK
,
519 SCIFA1_CTS_N_C_MARK
, AVB_TXD3_MARK
,
520 VI0_G3_MARK
, VI0_G3_B_MARK
, VI2_DATA3_VI2_B3_MARK
,
521 D12_MARK
, SCIFA1_RTS_N_C_MARK
, AVB_TXD4_MARK
,
522 VI0_HSYNC_N_MARK
, VI0_HSYNC_N_B_MARK
, VI2_DATA4_VI2_B4_MARK
,
523 D13_MARK
, AVB_TXD5_MARK
, VI0_VSYNC_N_MARK
,
524 VI0_VSYNC_N_B_MARK
, VI2_DATA5_VI2_B5_MARK
, D14_MARK
,
525 SCIFB1_RXD_C_MARK
, AVB_TXD6_MARK
, RX1_B_MARK
,
526 VI0_CLKENB_MARK
, VI0_CLKENB_B_MARK
, VI2_DATA6_VI2_B6_MARK
,
527 D15_MARK
, SCIFB1_TXD_C_MARK
, AVB_TXD7_MARK
, TX1_B_MARK
,
528 VI0_FIELD_MARK
, VI0_FIELD_B_MARK
, VI2_DATA7_VI2_B7_MARK
,
529 A0_MARK
, PWM3_MARK
, A1_MARK
, PWM4_MARK
,
531 A2_MARK
, PWM5_MARK
, MSIOF1_SS1_B_MARK
, A3_MARK
,
532 PWM6_MARK
, MSIOF1_SS2_B_MARK
, A4_MARK
, MSIOF1_TXD_B_MARK
,
533 TPU0TO0_MARK
, A5_MARK
, SCIFA1_TXD_B_MARK
, TPU0TO1_MARK
,
534 A6_MARK
, SCIFA1_RTS_N_B_MARK
, TPU0TO2_MARK
, A7_MARK
,
535 SCIFA1_SCK_B_MARK
, AUDIO_CLKOUT_B_MARK
, TPU0TO3_MARK
,
536 A8_MARK
, SCIFA1_RXD_B_MARK
, SSI_SCK5_B_MARK
, VI0_R4_MARK
,
537 VI0_R4_B_MARK
, SCIFB2_RXD_C_MARK
, RX2_B_MARK
, VI2_DATA0_VI2_B0_B_MARK
,
538 A9_MARK
, SCIFA1_CTS_N_B_MARK
, SSI_WS5_B_MARK
, VI0_R5_MARK
,
539 VI0_R5_B_MARK
, SCIFB2_TXD_C_MARK
, TX2_B_MARK
, VI2_DATA1_VI2_B1_B_MARK
,
540 A10_MARK
, SSI_SDATA5_B_MARK
, MSIOF2_SYNC_MARK
, VI0_R6_MARK
,
541 VI0_R6_B_MARK
, VI2_DATA2_VI2_B2_B_MARK
,
543 A11_MARK
, SCIFB2_CTS_N_B_MARK
, MSIOF2_SCK_MARK
, VI1_R0_MARK
,
544 VI1_R0_B_MARK
, VI2_G0_MARK
, VI2_DATA3_VI2_B3_B_MARK
,
545 A12_MARK
, SCIFB2_RXD_B_MARK
, MSIOF2_TXD_MARK
, VI1_R1_MARK
,
546 VI1_R1_B_MARK
, VI2_G1_MARK
, VI2_DATA4_VI2_B4_B_MARK
,
547 A13_MARK
, SCIFB2_RTS_N_B_MARK
, EX_WAIT2_MARK
,
548 MSIOF2_RXD_MARK
, VI1_R2_MARK
, VI1_R2_B_MARK
, VI2_G2_MARK
,
549 VI2_DATA5_VI2_B5_B_MARK
, A14_MARK
, SCIFB2_TXD_B_MARK
,
550 ATACS11_N_MARK
, MSIOF2_SS1_MARK
, A15_MARK
, SCIFB2_SCK_B_MARK
,
551 ATARD1_N_MARK
, MSIOF2_SS2_MARK
, A16_MARK
, ATAWR1_N_MARK
,
552 A17_MARK
, AD_DO_B_MARK
, ATADIR1_N_MARK
, A18_MARK
,
553 AD_CLK_B_MARK
, ATAG1_N_MARK
, A19_MARK
, AD_NCS_N_B_MARK
,
554 ATACS01_N_MARK
, EX_WAIT0_B_MARK
, A20_MARK
, SPCLK_MARK
,
555 VI1_R3_MARK
, VI1_R3_B_MARK
, VI2_G4_MARK
,
557 A21_MARK
, MOSI_IO0_MARK
, VI1_R4_MARK
, VI1_R4_B_MARK
, VI2_G5_MARK
,
558 A22_MARK
, MISO_IO1_MARK
, VI1_R5_MARK
, VI1_R5_B_MARK
,
559 VI2_G6_MARK
, A23_MARK
, IO2_MARK
, VI1_G7_MARK
,
560 VI1_G7_B_MARK
, VI2_G7_MARK
, A24_MARK
, IO3_MARK
,
561 VI1_R7_MARK
, VI1_R7_B_MARK
, VI2_CLKENB_MARK
,
562 VI2_CLKENB_B_MARK
, A25_MARK
, SSL_MARK
, VI1_G6_MARK
,
563 VI1_G6_B_MARK
, VI2_FIELD_MARK
, VI2_FIELD_B_MARK
, CS0_N_MARK
,
564 VI1_R6_MARK
, VI1_R6_B_MARK
, VI2_G3_MARK
, MSIOF0_SS2_B_MARK
,
565 CS1_N_A26_MARK
, SPEEDIN_MARK
, VI0_R7_MARK
, VI0_R7_B_MARK
,
566 VI2_CLK_MARK
, VI2_CLK_B_MARK
, EX_CS0_N_MARK
, HRX1_B_MARK
,
567 VI1_G5_MARK
, VI1_G5_B_MARK
, VI2_R0_MARK
, HTX0_B_MARK
,
568 MSIOF0_SS1_B_MARK
, EX_CS1_N_MARK
, GPS_CLK_MARK
,
569 HCTS1_N_B_MARK
, VI1_FIELD_MARK
, VI1_FIELD_B_MARK
,
570 VI2_R1_MARK
, EX_CS2_N_MARK
, GPS_SIGN_MARK
, HRTS1_N_B_MARK
,
571 VI3_CLKENB_MARK
, VI1_G0_MARK
, VI1_G0_B_MARK
, VI2_R2_MARK
,
573 EX_CS3_N_MARK
, GPS_MAG_MARK
, VI3_FIELD_MARK
,
574 VI1_G1_MARK
, VI1_G1_B_MARK
, VI2_R3_MARK
,
575 EX_CS4_N_MARK
, MSIOF1_SCK_B_MARK
, VI3_HSYNC_N_MARK
,
576 VI2_HSYNC_N_MARK
, IIC1_SCL_MARK
, VI2_HSYNC_N_B_MARK
,
577 INTC_EN0_N_MARK
, I2C1_SCL_MARK
, EX_CS5_N_MARK
, CAN0_RX_MARK
,
578 MSIOF1_RXD_B_MARK
, VI3_VSYNC_N_MARK
, VI1_G2_MARK
,
579 VI1_G2_B_MARK
, VI2_R4_MARK
, IIC1_SDA_MARK
, INTC_EN1_N_MARK
,
580 I2C1_SDA_MARK
, BS_N_MARK
, IETX_MARK
, HTX1_B_MARK
,
581 CAN1_TX_MARK
, DRACK0_MARK
, IETX_C_MARK
, RD_N_MARK
,
582 CAN0_TX_MARK
, SCIFA0_SCK_B_MARK
, RD_WR_N_MARK
, VI1_G3_MARK
,
583 VI1_G3_B_MARK
, VI2_R5_MARK
, SCIFA0_RXD_B_MARK
,
584 INTC_IRQ4_N_MARK
, WE0_N_MARK
, IECLK_MARK
, CAN_CLK_MARK
,
585 VI2_VSYNC_N_MARK
, SCIFA0_TXD_B_MARK
, VI2_VSYNC_N_B_MARK
,
586 WE1_N_MARK
, IERX_MARK
, CAN1_RX_MARK
, VI1_G4_MARK
,
587 VI1_G4_B_MARK
, VI2_R6_MARK
, SCIFA0_CTS_N_B_MARK
,
588 IERX_C_MARK
, EX_WAIT0_MARK
, IRQ3_MARK
, INTC_IRQ3_N_MARK
,
589 VI3_CLK_MARK
, SCIFA0_RTS_N_B_MARK
, HRX0_B_MARK
,
590 MSIOF0_SCK_B_MARK
, DREQ0_N_MARK
, VI1_HSYNC_N_MARK
,
591 VI1_HSYNC_N_B_MARK
, VI2_R7_MARK
, SSI_SCK78_C_MARK
,
594 DACK0_MARK
, IRQ0_MARK
, INTC_IRQ0_N_MARK
, SSI_SCK6_B_MARK
,
595 VI1_VSYNC_N_MARK
, VI1_VSYNC_N_B_MARK
, SSI_WS78_C_MARK
,
596 DREQ1_N_MARK
, VI1_CLKENB_MARK
, VI1_CLKENB_B_MARK
,
597 SSI_SDATA7_C_MARK
, SSI_SCK78_B_MARK
, DACK1_MARK
, IRQ1_MARK
,
598 INTC_IRQ1_N_MARK
, SSI_WS6_B_MARK
, SSI_SDATA8_C_MARK
,
599 DREQ2_N_MARK
, HSCK1_B_MARK
, HCTS0_N_B_MARK
,
600 MSIOF0_TXD_B_MARK
, DACK2_MARK
, IRQ2_MARK
, INTC_IRQ2_N_MARK
,
601 SSI_SDATA6_B_MARK
, HRTS0_N_B_MARK
, MSIOF0_RXD_B_MARK
,
602 ETH_CRS_DV_MARK
, STP_ISCLK_0_B_MARK
,
603 TS_SDEN0_D_MARK
, GLO_Q0_C_MARK
, IIC2_SCL_E_MARK
,
604 I2C2_SCL_E_MARK
, ETH_RX_ER_MARK
,
605 STP_ISD_0_B_MARK
, TS_SPSYNC0_D_MARK
, GLO_Q1_C_MARK
,
606 IIC2_SDA_E_MARK
, I2C2_SDA_E_MARK
, ETH_RXD0_MARK
,
607 STP_ISEN_0_B_MARK
, TS_SDAT0_D_MARK
, GLO_I0_C_MARK
,
608 SCIFB1_SCK_G_MARK
, SCK1_E_MARK
, ETH_RXD1_MARK
,
609 HRX0_E_MARK
, STP_ISSYNC_0_B_MARK
,
610 TS_SCK0_D_MARK
, GLO_I1_C_MARK
, SCIFB1_RXD_G_MARK
,
611 RX1_E_MARK
, ETH_LINK_MARK
, HTX0_E_MARK
,
612 STP_IVCXO27_0_B_MARK
, SCIFB1_TXD_G_MARK
, TX1_E_MARK
,
613 ETH_REF_CLK_MARK
, HCTS0_N_E_MARK
,
614 STP_IVCXO27_1_B_MARK
, HRX0_F_MARK
,
616 ETH_MDIO_MARK
, HRTS0_N_E_MARK
,
617 SIM0_D_C_MARK
, HCTS0_N_F_MARK
, ETH_TXD1_MARK
,
618 HTX0_F_MARK
, BPFCLK_G_MARK
,
619 ETH_TX_EN_MARK
, SIM0_CLK_C_MARK
,
620 HRTS0_N_F_MARK
, ETH_MAGIC_MARK
,
621 SIM0_RST_C_MARK
, ETH_TXD0_MARK
,
622 STP_ISCLK_1_B_MARK
, TS_SDEN1_C_MARK
, GLO_SCLK_C_MARK
,
623 ETH_MDC_MARK
, STP_ISD_1_B_MARK
,
624 TS_SPSYNC1_C_MARK
, GLO_SDATA_C_MARK
, PWM0_MARK
,
625 SCIFA2_SCK_C_MARK
, STP_ISEN_1_B_MARK
, TS_SDAT1_C_MARK
,
626 GLO_SS_C_MARK
, PWM1_MARK
, SCIFA2_TXD_C_MARK
,
627 STP_ISSYNC_1_B_MARK
, TS_SCK1_C_MARK
, GLO_RFON_C_MARK
,
628 PCMOE_N_MARK
, PWM2_MARK
, PWMFSW0_MARK
, SCIFA2_RXD_C_MARK
,
629 PCMWE_N_MARK
, IECLK_C_MARK
, DU_DOTCLKIN1_MARK
,
630 AUDIO_CLKC_MARK
, AUDIO_CLKOUT_C_MARK
, VI0_CLK_MARK
,
631 ATACS00_N_MARK
, AVB_RXD1_MARK
,
632 VI0_DATA0_VI0_B0_MARK
, ATACS10_N_MARK
, AVB_RXD2_MARK
,
634 VI0_DATA1_VI0_B1_MARK
, ATARD0_N_MARK
, AVB_RXD3_MARK
,
635 VI0_DATA2_VI0_B2_MARK
, ATAWR0_N_MARK
,
636 AVB_RXD4_MARK
, VI0_DATA3_VI0_B3_MARK
, ATADIR0_N_MARK
,
637 AVB_RXD5_MARK
, VI0_DATA4_VI0_B4_MARK
, ATAG0_N_MARK
,
638 AVB_RXD6_MARK
, VI0_DATA5_VI0_B5_MARK
, EX_WAIT1_MARK
,
639 AVB_RXD7_MARK
, VI0_DATA6_VI0_B6_MARK
, AVB_RX_ER_MARK
,
640 VI0_DATA7_VI0_B7_MARK
, AVB_RX_CLK_MARK
,
641 VI1_CLK_MARK
, AVB_RX_DV_MARK
,
642 VI1_DATA0_VI1_B0_MARK
, SCIFA1_SCK_D_MARK
,
643 AVB_CRS_MARK
, VI1_DATA1_VI1_B1_MARK
,
644 SCIFA1_RXD_D_MARK
, AVB_MDC_MARK
,
645 VI1_DATA2_VI1_B2_MARK
, SCIFA1_TXD_D_MARK
, AVB_MDIO_MARK
,
646 VI1_DATA3_VI1_B3_MARK
, SCIFA1_CTS_N_D_MARK
,
647 AVB_GTX_CLK_MARK
, VI1_DATA4_VI1_B4_MARK
, SCIFA1_RTS_N_D_MARK
,
648 AVB_MAGIC_MARK
, VI1_DATA5_VI1_B5_MARK
,
649 AVB_PHY_INT_MARK
, VI1_DATA6_VI1_B6_MARK
, AVB_GTXREFCLK_MARK
,
650 SD0_CLK_MARK
, VI1_DATA0_VI1_B0_B_MARK
, SD0_CMD_MARK
,
651 SCIFB1_SCK_B_MARK
, VI1_DATA1_VI1_B1_B_MARK
,
653 SD0_DAT0_MARK
, SCIFB1_RXD_B_MARK
, VI1_DATA2_VI1_B2_B_MARK
,
654 SD0_DAT1_MARK
, SCIFB1_TXD_B_MARK
, VI1_DATA3_VI1_B3_B_MARK
,
655 SD0_DAT2_MARK
, SCIFB1_CTS_N_B_MARK
, VI1_DATA4_VI1_B4_B_MARK
,
656 SD0_DAT3_MARK
, SCIFB1_RTS_N_B_MARK
, VI1_DATA5_VI1_B5_B_MARK
,
657 SD0_CD_MARK
, MMC0_D6_MARK
, TS_SDEN0_B_MARK
, USB0_EXTP_MARK
,
658 GLO_SCLK_MARK
, VI1_DATA6_VI1_B6_B_MARK
, IIC1_SCL_B_MARK
,
659 I2C1_SCL_B_MARK
, VI2_DATA6_VI2_B6_B_MARK
, SD0_WP_MARK
,
660 MMC0_D7_MARK
, TS_SPSYNC0_B_MARK
, USB0_IDIN_MARK
,
661 GLO_SDATA_MARK
, VI1_DATA7_VI1_B7_B_MARK
, IIC1_SDA_B_MARK
,
662 I2C1_SDA_B_MARK
, VI2_DATA7_VI2_B7_B_MARK
, SD1_CLK_MARK
,
663 AVB_TX_EN_MARK
, SD1_CMD_MARK
,
664 AVB_TX_ER_MARK
, SCIFB0_SCK_B_MARK
,
665 SD1_DAT0_MARK
, AVB_TX_CLK_MARK
,
666 SCIFB0_RXD_B_MARK
, SD1_DAT1_MARK
, AVB_LINK_MARK
,
667 SCIFB0_TXD_B_MARK
, SD1_DAT2_MARK
,
668 AVB_COL_MARK
, SCIFB0_CTS_N_B_MARK
,
669 SD1_DAT3_MARK
, AVB_RXD0_MARK
,
670 SCIFB0_RTS_N_B_MARK
, SD1_CD_MARK
, MMC1_D6_MARK
,
671 TS_SDEN1_MARK
, USB1_EXTP_MARK
, GLO_SS_MARK
, VI0_CLK_B_MARK
,
672 IIC2_SCL_D_MARK
, I2C2_SCL_D_MARK
, SIM0_CLK_B_MARK
,
675 SD1_WP_MARK
, MMC1_D7_MARK
, TS_SPSYNC1_MARK
, USB1_IDIN_MARK
,
676 GLO_RFON_MARK
, VI1_CLK_B_MARK
, IIC2_SDA_D_MARK
, I2C2_SDA_D_MARK
,
677 SIM0_D_B_MARK
, SD2_CLK_MARK
, MMC0_CLK_MARK
, SIM0_CLK_MARK
,
678 VI0_DATA0_VI0_B0_B_MARK
, TS_SDEN0_C_MARK
, GLO_SCLK_B_MARK
,
679 VI3_DATA0_B_MARK
, SD2_CMD_MARK
, MMC0_CMD_MARK
, SIM0_D_MARK
,
680 VI0_DATA1_VI0_B1_B_MARK
, SCIFB1_SCK_E_MARK
, SCK1_D_MARK
,
681 TS_SPSYNC0_C_MARK
, GLO_SDATA_B_MARK
, VI3_DATA1_B_MARK
,
682 SD2_DAT0_MARK
, MMC0_D0_MARK
, FMCLK_B_MARK
,
683 VI0_DATA2_VI0_B2_B_MARK
, SCIFB1_RXD_E_MARK
, RX1_D_MARK
,
684 TS_SDAT0_C_MARK
, GLO_SS_B_MARK
, VI3_DATA2_B_MARK
,
685 SD2_DAT1_MARK
, MMC0_D1_MARK
, FMIN_B_MARK
,
686 VI0_DATA3_VI0_B3_B_MARK
, SCIFB1_TXD_E_MARK
, TX1_D_MARK
,
687 TS_SCK0_C_MARK
, GLO_RFON_B_MARK
, VI3_DATA3_B_MARK
,
688 SD2_DAT2_MARK
, MMC0_D2_MARK
, BPFCLK_B_MARK
,
689 VI0_DATA4_VI0_B4_B_MARK
, HRX0_D_MARK
, TS_SDEN1_B_MARK
,
690 GLO_Q0_B_MARK
, VI3_DATA4_B_MARK
, SD2_DAT3_MARK
,
691 MMC0_D3_MARK
, SIM0_RST_MARK
, VI0_DATA5_VI0_B5_B_MARK
,
692 HTX0_D_MARK
, TS_SPSYNC1_B_MARK
, GLO_Q1_B_MARK
,
693 VI3_DATA5_B_MARK
, SD2_CD_MARK
, MMC0_D4_MARK
,
694 TS_SDAT0_B_MARK
, USB2_EXTP_MARK
, GLO_I0_MARK
,
695 VI0_DATA6_VI0_B6_B_MARK
, HCTS0_N_D_MARK
, TS_SDAT1_B_MARK
,
696 GLO_I0_B_MARK
, VI3_DATA6_B_MARK
,
698 SD2_WP_MARK
, MMC0_D5_MARK
, TS_SCK0_B_MARK
, USB2_IDIN_MARK
,
699 GLO_I1_MARK
, VI0_DATA7_VI0_B7_B_MARK
, HRTS0_N_D_MARK
,
700 TS_SCK1_B_MARK
, GLO_I1_B_MARK
, VI3_DATA7_B_MARK
,
701 SD3_CLK_MARK
, MMC1_CLK_MARK
, SD3_CMD_MARK
, MMC1_CMD_MARK
,
702 MTS_N_MARK
, SD3_DAT0_MARK
, MMC1_D0_MARK
, STM_N_MARK
,
703 SD3_DAT1_MARK
, MMC1_D1_MARK
, MDATA_MARK
, SD3_DAT2_MARK
,
704 MMC1_D2_MARK
, SDATA_MARK
, SD3_DAT3_MARK
, MMC1_D3_MARK
,
705 SCKZ_MARK
, SD3_CD_MARK
, MMC1_D4_MARK
, TS_SDAT1_MARK
,
706 VSP_MARK
, GLO_Q0_MARK
, SIM0_RST_B_MARK
, SD3_WP_MARK
,
707 MMC1_D5_MARK
, TS_SCK1_MARK
, GLO_Q1_MARK
, FMIN_C_MARK
,
708 FMIN_E_MARK
, FMIN_F_MARK
,
709 MLB_CLK_MARK
, IIC2_SCL_B_MARK
, I2C2_SCL_B_MARK
,
710 MLB_SIG_MARK
, SCIFB1_RXD_D_MARK
, RX1_C_MARK
, IIC2_SDA_B_MARK
,
711 I2C2_SDA_B_MARK
, MLB_DAT_MARK
,
712 SCIFB1_TXD_D_MARK
, TX1_C_MARK
, BPFCLK_C_MARK
,
713 SSI_SCK0129_MARK
, CAN_CLK_B_MARK
,
716 SSI_WS0129_MARK
, CAN0_TX_B_MARK
, MOUT1_MARK
,
717 SSI_SDATA0_MARK
, CAN0_RX_B_MARK
, MOUT2_MARK
,
718 SSI_SDATA1_MARK
, CAN1_TX_B_MARK
, MOUT5_MARK
,
719 SSI_SDATA2_MARK
, CAN1_RX_B_MARK
, SSI_SCK1_MARK
, MOUT6_MARK
,
720 SSI_SCK34_MARK
, STP_OPWM_0_MARK
, SCIFB0_SCK_MARK
,
721 MSIOF1_SCK_MARK
, CAN_DEBUG_HW_TRIGGER_MARK
, SSI_WS34_MARK
,
722 STP_IVCXO27_0_MARK
, SCIFB0_RXD_MARK
, MSIOF1_SYNC_MARK
,
723 CAN_STEP0_MARK
, SSI_SDATA3_MARK
, STP_ISCLK_0_MARK
,
724 SCIFB0_TXD_MARK
, MSIOF1_SS1_MARK
, CAN_TXCLK_MARK
,
725 SSI_SCK4_MARK
, STP_ISD_0_MARK
, SCIFB0_CTS_N_MARK
,
726 MSIOF1_SS2_MARK
, SSI_SCK5_C_MARK
, CAN_DEBUGOUT0_MARK
,
727 SSI_WS4_MARK
, STP_ISEN_0_MARK
, SCIFB0_RTS_N_MARK
,
728 MSIOF1_TXD_MARK
, SSI_WS5_C_MARK
, CAN_DEBUGOUT1_MARK
,
729 SSI_SDATA4_MARK
, STP_ISSYNC_0_MARK
, MSIOF1_RXD_MARK
,
730 CAN_DEBUGOUT2_MARK
, SSI_SCK5_MARK
, SCIFB1_SCK_MARK
,
731 IERX_B_MARK
, DU2_EXHSYNC_DU2_HSYNC_MARK
, QSTH_QHS_MARK
,
732 CAN_DEBUGOUT3_MARK
, SSI_WS5_MARK
, SCIFB1_RXD_MARK
,
733 IECLK_B_MARK
, DU2_EXVSYNC_DU2_VSYNC_MARK
, QSTB_QHE_MARK
,
736 SSI_SDATA5_MARK
, SCIFB1_TXD_MARK
, IETX_B_MARK
, DU2_DR2_MARK
,
737 LCDOUT2_MARK
, CAN_DEBUGOUT5_MARK
, SSI_SCK6_MARK
,
738 SCIFB1_CTS_N_MARK
, BPFCLK_D_MARK
,
739 DU2_DR3_MARK
, LCDOUT3_MARK
, CAN_DEBUGOUT6_MARK
,
740 BPFCLK_F_MARK
, SSI_WS6_MARK
,
741 SCIFB1_RTS_N_MARK
, CAN0_TX_D_MARK
, DU2_DR4_MARK
,
742 LCDOUT4_MARK
, CAN_DEBUGOUT7_MARK
, SSI_SDATA6_MARK
,
743 FMIN_D_MARK
, DU2_DR5_MARK
, LCDOUT5_MARK
,
744 CAN_DEBUGOUT8_MARK
, SSI_SCK78_MARK
, STP_IVCXO27_1_MARK
,
745 SCK1_MARK
, SCIFA1_SCK_MARK
, DU2_DR6_MARK
, LCDOUT6_MARK
,
746 CAN_DEBUGOUT9_MARK
, SSI_WS78_MARK
, STP_ISCLK_1_MARK
,
747 SCIFB2_SCK_MARK
, SCIFA2_CTS_N_MARK
, DU2_DR7_MARK
,
748 LCDOUT7_MARK
, CAN_DEBUGOUT10_MARK
, SSI_SDATA7_MARK
,
749 STP_ISD_1_MARK
, SCIFB2_RXD_MARK
, SCIFA2_RTS_N_MARK
,
750 TCLK2_MARK
, QSTVA_QVS_MARK
, CAN_DEBUGOUT11_MARK
,
751 BPFCLK_E_MARK
, SSI_SDATA7_B_MARK
,
752 FMIN_G_MARK
, SSI_SDATA8_MARK
,
753 STP_ISEN_1_MARK
, SCIFB2_TXD_MARK
, CAN0_TX_C_MARK
,
754 CAN_DEBUGOUT12_MARK
, SSI_SDATA8_B_MARK
, SSI_SDATA9_MARK
,
755 STP_ISSYNC_1_MARK
, SCIFB2_CTS_N_MARK
, SSI_WS1_MARK
,
756 SSI_SDATA5_C_MARK
, CAN_DEBUGOUT13_MARK
, AUDIO_CLKA_MARK
,
757 SCIFB2_RTS_N_MARK
, CAN_DEBUGOUT14_MARK
,
759 AUDIO_CLKB_MARK
, SCIF_CLK_MARK
, CAN0_RX_D_MARK
,
760 DVC_MUTE_MARK
, CAN0_RX_C_MARK
, CAN_DEBUGOUT15_MARK
,
761 REMOCON_MARK
, SCIFA0_SCK_MARK
, HSCK1_MARK
, SCK0_MARK
,
762 MSIOF3_SS2_MARK
, DU2_DG2_MARK
, LCDOUT10_MARK
, IIC1_SDA_C_MARK
,
763 I2C1_SDA_C_MARK
, SCIFA0_RXD_MARK
, HRX1_MARK
, RX0_MARK
,
764 DU2_DR0_MARK
, LCDOUT0_MARK
, SCIFA0_TXD_MARK
, HTX1_MARK
,
765 TX0_MARK
, DU2_DR1_MARK
, LCDOUT1_MARK
, SCIFA0_CTS_N_MARK
,
766 HCTS1_N_MARK
, CTS0_N_MARK
, MSIOF3_SYNC_MARK
, DU2_DG3_MARK
,
767 LCDOUT11_MARK
, PWM0_B_MARK
, IIC1_SCL_C_MARK
, I2C1_SCL_C_MARK
,
768 SCIFA0_RTS_N_MARK
, HRTS1_N_MARK
, RTS0_N_MARK
,
769 MSIOF3_SS1_MARK
, DU2_DG0_MARK
, LCDOUT8_MARK
, PWM1_B_MARK
,
770 SCIFA1_RXD_MARK
, AD_DI_MARK
, RX1_MARK
,
771 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK
, QCPV_QDE_MARK
,
772 SCIFA1_TXD_MARK
, AD_DO_MARK
, TX1_MARK
, DU2_DG1_MARK
,
773 LCDOUT9_MARK
, SCIFA1_CTS_N_MARK
, AD_CLK_MARK
,
774 CTS1_N_MARK
, MSIOF3_RXD_MARK
, DU0_DOTCLKOUT_MARK
, QCLK_MARK
,
775 SCIFA1_RTS_N_MARK
, AD_NCS_N_MARK
, RTS1_N_MARK
,
776 MSIOF3_TXD_MARK
, DU1_DOTCLKOUT_MARK
, QSTVB_QVE_MARK
,
779 SCIFA2_SCK_MARK
, FMCLK_MARK
, SCK2_MARK
, MSIOF3_SCK_MARK
, DU2_DG7_MARK
,
780 LCDOUT15_MARK
, SCIF_CLK_B_MARK
, SCIFA2_RXD_MARK
, FMIN_MARK
,
781 TX2_MARK
, DU2_DB0_MARK
, LCDOUT16_MARK
, IIC2_SCL_MARK
, I2C2_SCL_MARK
,
782 SCIFA2_TXD_MARK
, BPFCLK_MARK
, RX2_MARK
, DU2_DB1_MARK
, LCDOUT17_MARK
,
783 IIC2_SDA_MARK
, I2C2_SDA_MARK
, HSCK0_MARK
, TS_SDEN0_MARK
,
784 DU2_DG4_MARK
, LCDOUT12_MARK
, HCTS0_N_C_MARK
, HRX0_MARK
,
785 DU2_DB2_MARK
, LCDOUT18_MARK
, HTX0_MARK
, DU2_DB3_MARK
,
786 LCDOUT19_MARK
, HCTS0_N_MARK
, SSI_SCK9_MARK
, DU2_DB4_MARK
,
787 LCDOUT20_MARK
, HRTS0_N_MARK
, SSI_WS9_MARK
, DU2_DB5_MARK
,
788 LCDOUT21_MARK
, MSIOF0_SCK_MARK
, TS_SDAT0_MARK
, ADICLK_MARK
,
789 DU2_DB6_MARK
, LCDOUT22_MARK
, MSIOF0_SYNC_MARK
, TS_SCK0_MARK
,
790 SSI_SCK2_MARK
, ADIDATA_MARK
, DU2_DB7_MARK
, LCDOUT23_MARK
,
791 HRX0_C_MARK
, MSIOF0_SS1_MARK
, ADICHS0_MARK
,
792 DU2_DG5_MARK
, LCDOUT13_MARK
, MSIOF0_TXD_MARK
, ADICHS1_MARK
,
793 DU2_DG6_MARK
, LCDOUT14_MARK
,
795 MSIOF0_SS2_MARK
, AUDIO_CLKOUT_MARK
, ADICHS2_MARK
,
796 DU2_DISP_MARK
, QPOLA_MARK
, HTX0_C_MARK
, SCIFA2_TXD_B_MARK
,
797 MSIOF0_RXD_MARK
, TS_SPSYNC0_MARK
, SSI_WS2_MARK
,
798 ADICS_SAMP_MARK
, DU2_CDE_MARK
, QPOLB_MARK
, SCIFA2_RXD_B_MARK
,
799 USB1_PWEN_MARK
, AUDIO_CLKOUT_D_MARK
, USB1_OVC_MARK
,
802 IIC0_SCL_MARK
, IIC0_SDA_MARK
, I2C0_SCL_MARK
, I2C0_SDA_MARK
,
803 IIC3_SCL_MARK
, IIC3_SDA_MARK
, I2C3_SCL_MARK
, I2C3_SDA_MARK
,
807 static const u16 pinmux_data
[] = {
808 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
810 PINMUX_DATA(VI1_DATA7_VI1_B7_MARK
, FN_VI1_DATA7_VI1_B7
),
811 PINMUX_DATA(USB0_PWEN_MARK
, FN_USB0_PWEN
),
812 PINMUX_DATA(USB0_OVC_VBUS_MARK
, FN_USB0_OVC_VBUS
),
813 PINMUX_DATA(USB2_PWEN_MARK
, FN_USB2_PWEN
),
814 PINMUX_DATA(USB2_OVC_MARK
, FN_USB2_OVC
),
815 PINMUX_DATA(AVS1_MARK
, FN_AVS1
),
816 PINMUX_DATA(AVS2_MARK
, FN_AVS2
),
817 PINMUX_DATA(DU_DOTCLKIN0_MARK
, FN_DU_DOTCLKIN0
),
818 PINMUX_DATA(DU_DOTCLKIN2_MARK
, FN_DU_DOTCLKIN2
),
820 PINMUX_IPSR_DATA(IP0_2_0
, D0
),
821 PINMUX_IPSR_MSEL(IP0_2_0
, MSIOF3_SCK_B
, SEL_SOF3_1
),
822 PINMUX_IPSR_MSEL(IP0_2_0
, VI3_DATA0
, SEL_VI3_0
),
823 PINMUX_IPSR_MSEL(IP0_2_0
, VI0_G4
, SEL_VI0_0
),
824 PINMUX_IPSR_MSEL(IP0_2_0
, VI0_G4_B
, SEL_VI0_1
),
825 PINMUX_IPSR_DATA(IP0_5_3
, D1
),
826 PINMUX_IPSR_MSEL(IP0_5_3
, MSIOF3_SYNC_B
, SEL_SOF3_1
),
827 PINMUX_IPSR_MSEL(IP0_5_3
, VI3_DATA1
, SEL_VI3_0
),
828 PINMUX_IPSR_MSEL(IP0_5_3
, VI0_G5
, SEL_VI0_0
),
829 PINMUX_IPSR_MSEL(IP0_5_3
, VI0_G5_B
, SEL_VI0_1
),
830 PINMUX_IPSR_DATA(IP0_8_6
, D2
),
831 PINMUX_IPSR_MSEL(IP0_8_6
, MSIOF3_RXD_B
, SEL_SOF3_1
),
832 PINMUX_IPSR_MSEL(IP0_8_6
, VI3_DATA2
, SEL_VI3_0
),
833 PINMUX_IPSR_MSEL(IP0_8_6
, VI0_G6
, SEL_VI0_0
),
834 PINMUX_IPSR_MSEL(IP0_8_6
, VI0_G6_B
, SEL_VI0_1
),
835 PINMUX_IPSR_DATA(IP0_11_9
, D3
),
836 PINMUX_IPSR_MSEL(IP0_11_9
, MSIOF3_TXD_B
, SEL_SOF3_1
),
837 PINMUX_IPSR_MSEL(IP0_11_9
, VI3_DATA3
, SEL_VI3_0
),
838 PINMUX_IPSR_MSEL(IP0_11_9
, VI0_G7
, SEL_VI0_0
),
839 PINMUX_IPSR_MSEL(IP0_11_9
, VI0_G7_B
, SEL_VI0_1
),
840 PINMUX_IPSR_DATA(IP0_15_12
, D4
),
841 PINMUX_IPSR_MSEL(IP0_15_12
, SCIFB1_RXD_F
, SEL_SCIFB1_5
),
842 PINMUX_IPSR_MSEL(IP0_15_12
, SCIFB0_RXD_C
, SEL_SCIFB_2
),
843 PINMUX_IPSR_MSEL(IP0_15_12
, VI3_DATA4
, SEL_VI3_0
),
844 PINMUX_IPSR_MSEL(IP0_15_12
, VI0_R0
, SEL_VI0_0
),
845 PINMUX_IPSR_MSEL(IP0_15_12
, VI0_R0_B
, SEL_VI0_1
),
846 PINMUX_IPSR_MSEL(IP0_15_12
, RX0_B
, SEL_SCIF0_1
),
847 PINMUX_IPSR_DATA(IP0_19_16
, D5
),
848 PINMUX_IPSR_MSEL(IP0_19_16
, SCIFB1_TXD_F
, SEL_SCIFB1_5
),
849 PINMUX_IPSR_MSEL(IP0_19_16
, SCIFB0_TXD_C
, SEL_SCIFB_2
),
850 PINMUX_IPSR_MSEL(IP0_19_16
, VI3_DATA5
, SEL_VI3_0
),
851 PINMUX_IPSR_MSEL(IP0_19_16
, VI0_R1
, SEL_VI0_0
),
852 PINMUX_IPSR_MSEL(IP0_19_16
, VI0_R1_B
, SEL_VI0_1
),
853 PINMUX_IPSR_MSEL(IP0_19_16
, TX0_B
, SEL_SCIF0_1
),
854 PINMUX_IPSR_DATA(IP0_22_20
, D6
),
855 PINMUX_IPSR_MSEL(IP0_22_20
, IIC2_SCL_C
, SEL_IIC2_2
),
856 PINMUX_IPSR_MSEL(IP0_22_20
, VI3_DATA6
, SEL_VI3_0
),
857 PINMUX_IPSR_MSEL(IP0_22_20
, VI0_R2
, SEL_VI0_0
),
858 PINMUX_IPSR_MSEL(IP0_22_20
, VI0_R2_B
, SEL_VI0_1
),
859 PINMUX_IPSR_MSEL(IP0_22_20
, I2C2_SCL_C
, SEL_I2C2_2
),
860 PINMUX_IPSR_DATA(IP0_26_23
, D7
),
861 PINMUX_IPSR_MSEL(IP0_26_23
, AD_DI_B
, SEL_ADI_1
),
862 PINMUX_IPSR_MSEL(IP0_26_23
, IIC2_SDA_C
, SEL_IIC2_2
),
863 PINMUX_IPSR_MSEL(IP0_26_23
, VI3_DATA7
, SEL_VI3_0
),
864 PINMUX_IPSR_MSEL(IP0_26_23
, VI0_R3
, SEL_VI0_0
),
865 PINMUX_IPSR_MSEL(IP0_26_23
, VI0_R3_B
, SEL_VI0_1
),
866 PINMUX_IPSR_MSEL(IP0_26_23
, I2C2_SDA_C
, SEL_I2C2_2
),
867 PINMUX_IPSR_MSEL(IP0_26_23
, TCLK1
, SEL_TMU1_0
),
868 PINMUX_IPSR_DATA(IP0_30_27
, D8
),
869 PINMUX_IPSR_MSEL(IP0_30_27
, SCIFA1_SCK_C
, SEL_SCIFA1_2
),
870 PINMUX_IPSR_DATA(IP0_30_27
, AVB_TXD0
),
871 PINMUX_IPSR_MSEL(IP0_30_27
, VI0_G0
, SEL_VI0_0
),
872 PINMUX_IPSR_MSEL(IP0_30_27
, VI0_G0_B
, SEL_VI0_1
),
873 PINMUX_IPSR_MSEL(IP0_30_27
, VI2_DATA0_VI2_B0
, SEL_VI2_0
),
875 PINMUX_IPSR_DATA(IP1_3_0
, D9
),
876 PINMUX_IPSR_MSEL(IP1_3_0
, SCIFA1_RXD_C
, SEL_SCIFA1_2
),
877 PINMUX_IPSR_DATA(IP1_3_0
, AVB_TXD1
),
878 PINMUX_IPSR_MSEL(IP1_3_0
, VI0_G1
, SEL_VI0_0
),
879 PINMUX_IPSR_MSEL(IP1_3_0
, VI0_G1_B
, SEL_VI0_1
),
880 PINMUX_IPSR_MSEL(IP1_3_0
, VI2_DATA1_VI2_B1
, SEL_VI2_0
),
881 PINMUX_IPSR_DATA(IP1_7_4
, D10
),
882 PINMUX_IPSR_MSEL(IP1_7_4
, SCIFA1_TXD_C
, SEL_SCIFA1_2
),
883 PINMUX_IPSR_DATA(IP1_7_4
, AVB_TXD2
),
884 PINMUX_IPSR_MSEL(IP1_7_4
, VI0_G2
, SEL_VI0_0
),
885 PINMUX_IPSR_MSEL(IP1_7_4
, VI0_G2_B
, SEL_VI0_1
),
886 PINMUX_IPSR_MSEL(IP1_7_4
, VI2_DATA2_VI2_B2
, SEL_VI2_0
),
887 PINMUX_IPSR_DATA(IP1_11_8
, D11
),
888 PINMUX_IPSR_MSEL(IP1_11_8
, SCIFA1_CTS_N_C
, SEL_SCIFA1_2
),
889 PINMUX_IPSR_DATA(IP1_11_8
, AVB_TXD3
),
890 PINMUX_IPSR_MSEL(IP1_11_8
, VI0_G3
, SEL_VI0_0
),
891 PINMUX_IPSR_MSEL(IP1_11_8
, VI0_G3_B
, SEL_VI0_1
),
892 PINMUX_IPSR_MSEL(IP1_11_8
, VI2_DATA3_VI2_B3
, SEL_VI2_0
),
893 PINMUX_IPSR_DATA(IP1_14_12
, D12
),
894 PINMUX_IPSR_MSEL(IP1_14_12
, SCIFA1_RTS_N_C
, SEL_SCIFA1_2
),
895 PINMUX_IPSR_DATA(IP1_14_12
, AVB_TXD4
),
896 PINMUX_IPSR_MSEL(IP1_14_12
, VI0_HSYNC_N
, SEL_VI0_0
),
897 PINMUX_IPSR_MSEL(IP1_14_12
, VI0_HSYNC_N_B
, SEL_VI0_1
),
898 PINMUX_IPSR_MSEL(IP1_14_12
, VI2_DATA4_VI2_B4
, SEL_VI2_0
),
899 PINMUX_IPSR_DATA(IP1_17_15
, D13
),
900 PINMUX_IPSR_DATA(IP1_17_15
, AVB_TXD5
),
901 PINMUX_IPSR_MSEL(IP1_17_15
, VI0_VSYNC_N
, SEL_VI0_0
),
902 PINMUX_IPSR_MSEL(IP1_17_15
, VI0_VSYNC_N_B
, SEL_VI0_1
),
903 PINMUX_IPSR_MSEL(IP1_17_15
, VI2_DATA5_VI2_B5
, SEL_VI2_0
),
904 PINMUX_IPSR_DATA(IP1_21_18
, D14
),
905 PINMUX_IPSR_MSEL(IP1_21_18
, SCIFB1_RXD_C
, SEL_SCIFB1_2
),
906 PINMUX_IPSR_DATA(IP1_21_18
, AVB_TXD6
),
907 PINMUX_IPSR_MSEL(IP1_21_18
, RX1_B
, SEL_SCIF1_1
),
908 PINMUX_IPSR_MSEL(IP1_21_18
, VI0_CLKENB
, SEL_VI0_0
),
909 PINMUX_IPSR_MSEL(IP1_21_18
, VI0_CLKENB_B
, SEL_VI0_1
),
910 PINMUX_IPSR_MSEL(IP1_21_18
, VI2_DATA6_VI2_B6
, SEL_VI2_0
),
911 PINMUX_IPSR_DATA(IP1_25_22
, D15
),
912 PINMUX_IPSR_MSEL(IP1_25_22
, SCIFB1_TXD_C
, SEL_SCIFB1_2
),
913 PINMUX_IPSR_DATA(IP1_25_22
, AVB_TXD7
),
914 PINMUX_IPSR_MSEL(IP1_25_22
, TX1_B
, SEL_SCIF1_1
),
915 PINMUX_IPSR_MSEL(IP1_25_22
, VI0_FIELD
, SEL_VI0_0
),
916 PINMUX_IPSR_MSEL(IP1_25_22
, VI0_FIELD_B
, SEL_VI0_1
),
917 PINMUX_IPSR_MSEL(IP1_25_22
, VI2_DATA7_VI2_B7
, SEL_VI2_0
),
918 PINMUX_IPSR_DATA(IP1_27_26
, A0
),
919 PINMUX_IPSR_DATA(IP1_27_26
, PWM3
),
920 PINMUX_IPSR_DATA(IP1_29_28
, A1
),
921 PINMUX_IPSR_DATA(IP1_29_28
, PWM4
),
923 PINMUX_IPSR_DATA(IP2_2_0
, A2
),
924 PINMUX_IPSR_DATA(IP2_2_0
, PWM5
),
925 PINMUX_IPSR_MSEL(IP2_2_0
, MSIOF1_SS1_B
, SEL_SOF1_1
),
926 PINMUX_IPSR_DATA(IP2_5_3
, A3
),
927 PINMUX_IPSR_DATA(IP2_5_3
, PWM6
),
928 PINMUX_IPSR_MSEL(IP2_5_3
, MSIOF1_SS2_B
, SEL_SOF1_1
),
929 PINMUX_IPSR_DATA(IP2_8_6
, A4
),
930 PINMUX_IPSR_MSEL(IP2_8_6
, MSIOF1_TXD_B
, SEL_SOF1_1
),
931 PINMUX_IPSR_DATA(IP2_8_6
, TPU0TO0
),
932 PINMUX_IPSR_DATA(IP2_11_9
, A5
),
933 PINMUX_IPSR_MSEL(IP2_11_9
, SCIFA1_TXD_B
, SEL_SCIFA1_1
),
934 PINMUX_IPSR_DATA(IP2_11_9
, TPU0TO1
),
935 PINMUX_IPSR_DATA(IP2_14_12
, A6
),
936 PINMUX_IPSR_MSEL(IP2_14_12
, SCIFA1_RTS_N_B
, SEL_SCIFA1_1
),
937 PINMUX_IPSR_DATA(IP2_14_12
, TPU0TO2
),
938 PINMUX_IPSR_DATA(IP2_17_15
, A7
),
939 PINMUX_IPSR_MSEL(IP2_17_15
, SCIFA1_SCK_B
, SEL_SCIFA1_1
),
940 PINMUX_IPSR_DATA(IP2_17_15
, AUDIO_CLKOUT_B
),
941 PINMUX_IPSR_DATA(IP2_17_15
, TPU0TO3
),
942 PINMUX_IPSR_DATA(IP2_21_18
, A8
),
943 PINMUX_IPSR_MSEL(IP2_21_18
, SCIFA1_RXD_B
, SEL_SCIFA1_1
),
944 PINMUX_IPSR_MSEL(IP2_21_18
, SSI_SCK5_B
, SEL_SSI5_1
),
945 PINMUX_IPSR_MSEL(IP2_21_18
, VI0_R4
, SEL_VI0_0
),
946 PINMUX_IPSR_MSEL(IP2_21_18
, VI0_R4_B
, SEL_VI0_1
),
947 PINMUX_IPSR_MSEL(IP2_21_18
, SCIFB2_RXD_C
, SEL_SCIFB2_2
),
948 PINMUX_IPSR_MSEL(IP2_21_18
, RX2_B
, SEL_SCIF2_1
),
949 PINMUX_IPSR_MSEL(IP2_21_18
, VI2_DATA0_VI2_B0_B
, SEL_VI2_1
),
950 PINMUX_IPSR_DATA(IP2_25_22
, A9
),
951 PINMUX_IPSR_MSEL(IP2_25_22
, SCIFA1_CTS_N_B
, SEL_SCIFA1_1
),
952 PINMUX_IPSR_MSEL(IP2_25_22
, SSI_WS5_B
, SEL_SSI5_1
),
953 PINMUX_IPSR_MSEL(IP2_25_22
, VI0_R5
, SEL_VI0_0
),
954 PINMUX_IPSR_MSEL(IP2_25_22
, VI0_R5_B
, SEL_VI0_1
),
955 PINMUX_IPSR_MSEL(IP2_25_22
, SCIFB2_TXD_C
, SEL_SCIFB2_2
),
956 PINMUX_IPSR_MSEL(IP2_25_22
, TX2_B
, SEL_SCIF2_1
),
957 PINMUX_IPSR_MSEL(IP2_25_22
, VI2_DATA1_VI2_B1_B
, SEL_VI2_1
),
958 PINMUX_IPSR_DATA(IP2_28_26
, A10
),
959 PINMUX_IPSR_MSEL(IP2_28_26
, SSI_SDATA5_B
, SEL_SSI5_1
),
960 PINMUX_IPSR_DATA(IP2_28_26
, MSIOF2_SYNC
),
961 PINMUX_IPSR_MSEL(IP2_28_26
, VI0_R6
, SEL_VI0_0
),
962 PINMUX_IPSR_MSEL(IP2_28_26
, VI0_R6_B
, SEL_VI0_1
),
963 PINMUX_IPSR_MSEL(IP2_28_26
, VI2_DATA2_VI2_B2_B
, SEL_VI2_1
),
965 PINMUX_IPSR_DATA(IP3_3_0
, A11
),
966 PINMUX_IPSR_MSEL(IP3_3_0
, SCIFB2_CTS_N_B
, SEL_SCIFB2_1
),
967 PINMUX_IPSR_DATA(IP3_3_0
, MSIOF2_SCK
),
968 PINMUX_IPSR_MSEL(IP3_3_0
, VI1_R0
, SEL_VI1_0
),
969 PINMUX_IPSR_MSEL(IP3_3_0
, VI1_R0_B
, SEL_VI1_1
),
970 PINMUX_IPSR_DATA(IP3_3_0
, VI2_G0
),
971 PINMUX_IPSR_MSEL(IP3_3_0
, VI2_DATA3_VI2_B3_B
, SEL_VI2_1
),
972 PINMUX_IPSR_DATA(IP3_7_4
, A12
),
973 PINMUX_IPSR_MSEL(IP3_7_4
, SCIFB2_RXD_B
, SEL_SCIFB2_1
),
974 PINMUX_IPSR_DATA(IP3_7_4
, MSIOF2_TXD
),
975 PINMUX_IPSR_MSEL(IP3_7_4
, VI1_R1
, SEL_VI1_0
),
976 PINMUX_IPSR_MSEL(IP3_7_4
, VI1_R1_B
, SEL_VI1_1
),
977 PINMUX_IPSR_DATA(IP3_7_4
, VI2_G1
),
978 PINMUX_IPSR_MSEL(IP3_7_4
, VI2_DATA4_VI2_B4_B
, SEL_VI2_1
),
979 PINMUX_IPSR_DATA(IP3_11_8
, A13
),
980 PINMUX_IPSR_MSEL(IP3_11_8
, SCIFB2_RTS_N_B
, SEL_SCIFB2_1
),
981 PINMUX_IPSR_DATA(IP3_11_8
, EX_WAIT2
),
982 PINMUX_IPSR_DATA(IP3_11_8
, MSIOF2_RXD
),
983 PINMUX_IPSR_MSEL(IP3_11_8
, VI1_R2
, SEL_VI1_0
),
984 PINMUX_IPSR_MSEL(IP3_11_8
, VI1_R2_B
, SEL_VI1_1
),
985 PINMUX_IPSR_DATA(IP3_11_8
, VI2_G2
),
986 PINMUX_IPSR_MSEL(IP3_11_8
, VI2_DATA5_VI2_B5_B
, SEL_VI2_1
),
987 PINMUX_IPSR_DATA(IP3_14_12
, A14
),
988 PINMUX_IPSR_MSEL(IP3_14_12
, SCIFB2_TXD_B
, SEL_SCIFB2_1
),
989 PINMUX_IPSR_DATA(IP3_14_12
, ATACS11_N
),
990 PINMUX_IPSR_DATA(IP3_14_12
, MSIOF2_SS1
),
991 PINMUX_IPSR_DATA(IP3_17_15
, A15
),
992 PINMUX_IPSR_MSEL(IP3_17_15
, SCIFB2_SCK_B
, SEL_SCIFB2_1
),
993 PINMUX_IPSR_DATA(IP3_17_15
, ATARD1_N
),
994 PINMUX_IPSR_DATA(IP3_17_15
, MSIOF2_SS2
),
995 PINMUX_IPSR_DATA(IP3_19_18
, A16
),
996 PINMUX_IPSR_DATA(IP3_19_18
, ATAWR1_N
),
997 PINMUX_IPSR_DATA(IP3_22_20
, A17
),
998 PINMUX_IPSR_MSEL(IP3_22_20
, AD_DO_B
, SEL_ADI_1
),
999 PINMUX_IPSR_DATA(IP3_22_20
, ATADIR1_N
),
1000 PINMUX_IPSR_DATA(IP3_25_23
, A18
),
1001 PINMUX_IPSR_MSEL(IP3_25_23
, AD_CLK_B
, SEL_ADI_1
),
1002 PINMUX_IPSR_DATA(IP3_25_23
, ATAG1_N
),
1003 PINMUX_IPSR_DATA(IP3_28_26
, A19
),
1004 PINMUX_IPSR_MSEL(IP3_28_26
, AD_NCS_N_B
, SEL_ADI_1
),
1005 PINMUX_IPSR_DATA(IP3_28_26
, ATACS01_N
),
1006 PINMUX_IPSR_MSEL(IP3_28_26
, EX_WAIT0_B
, SEL_LBS_1
),
1007 PINMUX_IPSR_DATA(IP3_31_29
, A20
),
1008 PINMUX_IPSR_DATA(IP3_31_29
, SPCLK
),
1009 PINMUX_IPSR_MSEL(IP3_31_29
, VI1_R3
, SEL_VI1_0
),
1010 PINMUX_IPSR_MSEL(IP3_31_29
, VI1_R3_B
, SEL_VI1_1
),
1011 PINMUX_IPSR_DATA(IP3_31_29
, VI2_G4
),
1013 PINMUX_IPSR_DATA(IP4_2_0
, A21
),
1014 PINMUX_IPSR_DATA(IP4_2_0
, MOSI_IO0
),
1015 PINMUX_IPSR_MSEL(IP4_2_0
, VI1_R4
, SEL_VI1_0
),
1016 PINMUX_IPSR_MSEL(IP4_2_0
, VI1_R4_B
, SEL_VI1_1
),
1017 PINMUX_IPSR_DATA(IP4_2_0
, VI2_G5
),
1018 PINMUX_IPSR_DATA(IP4_5_3
, A22
),
1019 PINMUX_IPSR_DATA(IP4_5_3
, MISO_IO1
),
1020 PINMUX_IPSR_MSEL(IP4_5_3
, VI1_R5
, SEL_VI1_0
),
1021 PINMUX_IPSR_MSEL(IP4_5_3
, VI1_R5_B
, SEL_VI1_1
),
1022 PINMUX_IPSR_DATA(IP4_5_3
, VI2_G6
),
1023 PINMUX_IPSR_DATA(IP4_8_6
, A23
),
1024 PINMUX_IPSR_DATA(IP4_8_6
, IO2
),
1025 PINMUX_IPSR_MSEL(IP4_8_6
, VI1_G7
, SEL_VI1_0
),
1026 PINMUX_IPSR_MSEL(IP4_8_6
, VI1_G7_B
, SEL_VI1_1
),
1027 PINMUX_IPSR_DATA(IP4_8_6
, VI2_G7
),
1028 PINMUX_IPSR_DATA(IP4_11_9
, A24
),
1029 PINMUX_IPSR_DATA(IP4_11_9
, IO3
),
1030 PINMUX_IPSR_MSEL(IP4_11_9
, VI1_R7
, SEL_VI1_0
),
1031 PINMUX_IPSR_MSEL(IP4_11_9
, VI1_R7_B
, SEL_VI1_1
),
1032 PINMUX_IPSR_MSEL(IP4_11_9
, VI2_CLKENB
, SEL_VI2_0
),
1033 PINMUX_IPSR_MSEL(IP4_11_9
, VI2_CLKENB_B
, SEL_VI2_1
),
1034 PINMUX_IPSR_DATA(IP4_14_12
, A25
),
1035 PINMUX_IPSR_DATA(IP4_14_12
, SSL
),
1036 PINMUX_IPSR_MSEL(IP4_14_12
, VI1_G6
, SEL_VI1_0
),
1037 PINMUX_IPSR_MSEL(IP4_14_12
, VI1_G6_B
, SEL_VI1_1
),
1038 PINMUX_IPSR_MSEL(IP4_14_12
, VI2_FIELD
, SEL_VI2_0
),
1039 PINMUX_IPSR_MSEL(IP4_14_12
, VI2_FIELD_B
, SEL_VI2_1
),
1040 PINMUX_IPSR_DATA(IP4_17_15
, CS0_N
),
1041 PINMUX_IPSR_MSEL(IP4_17_15
, VI1_R6
, SEL_VI1_0
),
1042 PINMUX_IPSR_MSEL(IP4_17_15
, VI1_R6_B
, SEL_VI1_1
),
1043 PINMUX_IPSR_DATA(IP4_17_15
, VI2_G3
),
1044 PINMUX_IPSR_MSEL(IP4_17_15
, MSIOF0_SS2_B
, SEL_SOF0_1
),
1045 PINMUX_IPSR_DATA(IP4_20_18
, CS1_N_A26
),
1046 PINMUX_IPSR_DATA(IP4_20_18
, SPEEDIN
),
1047 PINMUX_IPSR_MSEL(IP4_20_18
, VI0_R7
, SEL_VI0_0
),
1048 PINMUX_IPSR_MSEL(IP4_20_18
, VI0_R7_B
, SEL_VI0_1
),
1049 PINMUX_IPSR_MSEL(IP4_20_18
, VI2_CLK
, SEL_VI2_0
),
1050 PINMUX_IPSR_MSEL(IP4_20_18
, VI2_CLK_B
, SEL_VI2_1
),
1051 PINMUX_IPSR_DATA(IP4_23_21
, EX_CS0_N
),
1052 PINMUX_IPSR_MSEL(IP4_23_21
, HRX1_B
, SEL_HSCIF1_1
),
1053 PINMUX_IPSR_MSEL(IP4_23_21
, VI1_G5
, SEL_VI1_0
),
1054 PINMUX_IPSR_MSEL(IP4_23_21
, VI1_G5_B
, SEL_VI1_1
),
1055 PINMUX_IPSR_DATA(IP4_23_21
, VI2_R0
),
1056 PINMUX_IPSR_MSEL(IP4_23_21
, HTX0_B
, SEL_HSCIF0_1
),
1057 PINMUX_IPSR_MSEL(IP4_23_21
, MSIOF0_SS1_B
, SEL_SOF0_1
),
1058 PINMUX_IPSR_DATA(IP4_26_24
, EX_CS1_N
),
1059 PINMUX_IPSR_DATA(IP4_26_24
, GPS_CLK
),
1060 PINMUX_IPSR_MSEL(IP4_26_24
, HCTS1_N_B
, SEL_HSCIF1_1
),
1061 PINMUX_IPSR_MSEL(IP4_26_24
, VI1_FIELD
, SEL_VI1_0
),
1062 PINMUX_IPSR_MSEL(IP4_26_24
, VI1_FIELD_B
, SEL_VI1_1
),
1063 PINMUX_IPSR_DATA(IP4_26_24
, VI2_R1
),
1064 PINMUX_IPSR_DATA(IP4_29_27
, EX_CS2_N
),
1065 PINMUX_IPSR_DATA(IP4_29_27
, GPS_SIGN
),
1066 PINMUX_IPSR_MSEL(IP4_29_27
, HRTS1_N_B
, SEL_HSCIF1_1
),
1067 PINMUX_IPSR_DATA(IP4_29_27
, VI3_CLKENB
),
1068 PINMUX_IPSR_MSEL(IP4_29_27
, VI1_G0
, SEL_VI1_0
),
1069 PINMUX_IPSR_MSEL(IP4_29_27
, VI1_G0_B
, SEL_VI1_1
),
1070 PINMUX_IPSR_DATA(IP4_29_27
, VI2_R2
),
1072 PINMUX_IPSR_DATA(IP5_2_0
, EX_CS3_N
),
1073 PINMUX_IPSR_DATA(IP5_2_0
, GPS_MAG
),
1074 PINMUX_IPSR_DATA(IP5_2_0
, VI3_FIELD
),
1075 PINMUX_IPSR_MSEL(IP5_2_0
, VI1_G1
, SEL_VI1_0
),
1076 PINMUX_IPSR_MSEL(IP5_2_0
, VI1_G1_B
, SEL_VI1_1
),
1077 PINMUX_IPSR_DATA(IP5_2_0
, VI2_R3
),
1078 PINMUX_IPSR_DATA(IP5_5_3
, EX_CS4_N
),
1079 PINMUX_IPSR_MSEL(IP5_5_3
, MSIOF1_SCK_B
, SEL_SOF1_1
),
1080 PINMUX_IPSR_DATA(IP5_5_3
, VI3_HSYNC_N
),
1081 PINMUX_IPSR_MSEL(IP5_5_3
, VI2_HSYNC_N
, SEL_VI2_0
),
1082 PINMUX_IPSR_MSEL(IP5_5_3
, IIC1_SCL
, SEL_IIC1_0
),
1083 PINMUX_IPSR_MSEL(IP5_5_3
, VI2_HSYNC_N_B
, SEL_VI2_1
),
1084 PINMUX_IPSR_DATA(IP5_5_3
, INTC_EN0_N
),
1085 PINMUX_IPSR_MSEL(IP5_5_3
, I2C1_SCL
, SEL_I2C1_0
),
1086 PINMUX_IPSR_DATA(IP5_9_6
, EX_CS5_N
),
1087 PINMUX_IPSR_MSEL(IP5_9_6
, CAN0_RX
, SEL_CAN0_0
),
1088 PINMUX_IPSR_MSEL(IP5_9_6
, MSIOF1_RXD_B
, SEL_SOF1_1
),
1089 PINMUX_IPSR_DATA(IP5_9_6
, VI3_VSYNC_N
),
1090 PINMUX_IPSR_MSEL(IP5_9_6
, VI1_G2
, SEL_VI1_0
),
1091 PINMUX_IPSR_MSEL(IP5_9_6
, VI1_G2_B
, SEL_VI1_1
),
1092 PINMUX_IPSR_DATA(IP5_9_6
, VI2_R4
),
1093 PINMUX_IPSR_MSEL(IP5_9_6
, IIC1_SDA
, SEL_IIC1_0
),
1094 PINMUX_IPSR_DATA(IP5_9_6
, INTC_EN1_N
),
1095 PINMUX_IPSR_MSEL(IP5_9_6
, I2C1_SDA
, SEL_I2C1_0
),
1096 PINMUX_IPSR_DATA(IP5_12_10
, BS_N
),
1097 PINMUX_IPSR_MSEL(IP5_12_10
, IETX
, SEL_IEB_0
),
1098 PINMUX_IPSR_MSEL(IP5_12_10
, HTX1_B
, SEL_HSCIF1_1
),
1099 PINMUX_IPSR_MSEL(IP5_12_10
, CAN1_TX
, SEL_CAN1_0
),
1100 PINMUX_IPSR_DATA(IP5_12_10
, DRACK0
),
1101 PINMUX_IPSR_MSEL(IP5_12_10
, IETX_C
, SEL_IEB_2
),
1102 PINMUX_IPSR_DATA(IP5_14_13
, RD_N
),
1103 PINMUX_IPSR_MSEL(IP5_14_13
, CAN0_TX
, SEL_CAN0_0
),
1104 PINMUX_IPSR_MSEL(IP5_14_13
, SCIFA0_SCK_B
, SEL_SCFA_1
),
1105 PINMUX_IPSR_DATA(IP5_17_15
, RD_WR_N
),
1106 PINMUX_IPSR_MSEL(IP5_17_15
, VI1_G3
, SEL_VI1_0
),
1107 PINMUX_IPSR_MSEL(IP5_17_15
, VI1_G3_B
, SEL_VI1_1
),
1108 PINMUX_IPSR_DATA(IP5_17_15
, VI2_R5
),
1109 PINMUX_IPSR_MSEL(IP5_17_15
, SCIFA0_RXD_B
, SEL_SCFA_1
),
1110 PINMUX_IPSR_DATA(IP5_17_15
, INTC_IRQ4_N
),
1111 PINMUX_IPSR_DATA(IP5_20_18
, WE0_N
),
1112 PINMUX_IPSR_MSEL(IP5_20_18
, IECLK
, SEL_IEB_0
),
1113 PINMUX_IPSR_MSEL(IP5_20_18
, CAN_CLK
, SEL_CANCLK_0
),
1114 PINMUX_IPSR_MSEL(IP5_20_18
, VI2_VSYNC_N
, SEL_VI2_0
),
1115 PINMUX_IPSR_MSEL(IP5_20_18
, SCIFA0_TXD_B
, SEL_SCFA_1
),
1116 PINMUX_IPSR_MSEL(IP5_20_18
, VI2_VSYNC_N_B
, SEL_VI2_1
),
1117 PINMUX_IPSR_DATA(IP5_23_21
, WE1_N
),
1118 PINMUX_IPSR_MSEL(IP5_23_21
, IERX
, SEL_IEB_0
),
1119 PINMUX_IPSR_MSEL(IP5_23_21
, CAN1_RX
, SEL_CAN1_0
),
1120 PINMUX_IPSR_MSEL(IP5_23_21
, VI1_G4
, SEL_VI1_0
),
1121 PINMUX_IPSR_MSEL(IP5_23_21
, VI1_G4_B
, SEL_VI1_1
),
1122 PINMUX_IPSR_DATA(IP5_23_21
, VI2_R6
),
1123 PINMUX_IPSR_MSEL(IP5_23_21
, SCIFA0_CTS_N_B
, SEL_SCFA_1
),
1124 PINMUX_IPSR_MSEL(IP5_23_21
, IERX_C
, SEL_IEB_2
),
1125 PINMUX_IPSR_MSEL(IP5_26_24
, EX_WAIT0
, SEL_LBS_0
),
1126 PINMUX_IPSR_DATA(IP5_26_24
, IRQ3
),
1127 PINMUX_IPSR_DATA(IP5_26_24
, INTC_IRQ3_N
),
1128 PINMUX_IPSR_MSEL(IP5_26_24
, VI3_CLK
, SEL_VI3_0
),
1129 PINMUX_IPSR_MSEL(IP5_26_24
, SCIFA0_RTS_N_B
, SEL_SCFA_1
),
1130 PINMUX_IPSR_MSEL(IP5_26_24
, HRX0_B
, SEL_HSCIF0_1
),
1131 PINMUX_IPSR_MSEL(IP5_26_24
, MSIOF0_SCK_B
, SEL_SOF0_1
),
1132 PINMUX_IPSR_DATA(IP5_29_27
, DREQ0_N
),
1133 PINMUX_IPSR_MSEL(IP5_29_27
, VI1_HSYNC_N
, SEL_VI1_0
),
1134 PINMUX_IPSR_MSEL(IP5_29_27
, VI1_HSYNC_N_B
, SEL_VI1_1
),
1135 PINMUX_IPSR_DATA(IP5_29_27
, VI2_R7
),
1136 PINMUX_IPSR_MSEL(IP5_29_27
, SSI_SCK78_C
, SEL_SSI7_2
),
1137 PINMUX_IPSR_MSEL(IP5_29_27
, SSI_WS78_B
, SEL_SSI7_1
),
1139 PINMUX_IPSR_DATA(IP6_2_0
, DACK0
),
1140 PINMUX_IPSR_DATA(IP6_2_0
, IRQ0
),
1141 PINMUX_IPSR_DATA(IP6_2_0
, INTC_IRQ0_N
),
1142 PINMUX_IPSR_MSEL(IP6_2_0
, SSI_SCK6_B
, SEL_SSI6_1
),
1143 PINMUX_IPSR_MSEL(IP6_2_0
, VI1_VSYNC_N
, SEL_VI1_0
),
1144 PINMUX_IPSR_MSEL(IP6_2_0
, VI1_VSYNC_N_B
, SEL_VI1_1
),
1145 PINMUX_IPSR_MSEL(IP6_2_0
, SSI_WS78_C
, SEL_SSI7_2
),
1146 PINMUX_IPSR_DATA(IP6_5_3
, DREQ1_N
),
1147 PINMUX_IPSR_MSEL(IP6_5_3
, VI1_CLKENB
, SEL_VI1_0
),
1148 PINMUX_IPSR_MSEL(IP6_5_3
, VI1_CLKENB_B
, SEL_VI1_1
),
1149 PINMUX_IPSR_MSEL(IP6_5_3
, SSI_SDATA7_C
, SEL_SSI7_2
),
1150 PINMUX_IPSR_MSEL(IP6_5_3
, SSI_SCK78_B
, SEL_SSI7_1
),
1151 PINMUX_IPSR_DATA(IP6_8_6
, DACK1
),
1152 PINMUX_IPSR_DATA(IP6_8_6
, IRQ1
),
1153 PINMUX_IPSR_DATA(IP6_8_6
, INTC_IRQ1_N
),
1154 PINMUX_IPSR_MSEL(IP6_8_6
, SSI_WS6_B
, SEL_SSI6_1
),
1155 PINMUX_IPSR_MSEL(IP6_8_6
, SSI_SDATA8_C
, SEL_SSI8_2
),
1156 PINMUX_IPSR_DATA(IP6_10_9
, DREQ2_N
),
1157 PINMUX_IPSR_MSEL(IP6_10_9
, HSCK1_B
, SEL_HSCIF1_1
),
1158 PINMUX_IPSR_MSEL(IP6_10_9
, HCTS0_N_B
, SEL_HSCIF0_1
),
1159 PINMUX_IPSR_MSEL(IP6_10_9
, MSIOF0_TXD_B
, SEL_SOF0_1
),
1160 PINMUX_IPSR_DATA(IP6_13_11
, DACK2
),
1161 PINMUX_IPSR_DATA(IP6_13_11
, IRQ2
),
1162 PINMUX_IPSR_DATA(IP6_13_11
, INTC_IRQ2_N
),
1163 PINMUX_IPSR_MSEL(IP6_13_11
, SSI_SDATA6_B
, SEL_SSI6_1
),
1164 PINMUX_IPSR_MSEL(IP6_13_11
, HRTS0_N_B
, SEL_HSCIF0_1
),
1165 PINMUX_IPSR_MSEL(IP6_13_11
, MSIOF0_RXD_B
, SEL_SOF0_1
),
1166 PINMUX_IPSR_DATA(IP6_16_14
, ETH_CRS_DV
),
1167 PINMUX_IPSR_MSEL(IP6_16_14
, STP_ISCLK_0_B
, SEL_SSP_1
),
1168 PINMUX_IPSR_MSEL(IP6_16_14
, TS_SDEN0_D
, SEL_TSIF0_3
),
1169 PINMUX_IPSR_MSEL(IP6_16_14
, GLO_Q0_C
, SEL_GPS_2
),
1170 PINMUX_IPSR_MSEL(IP6_16_14
, IIC2_SCL_E
, SEL_IIC2_4
),
1171 PINMUX_IPSR_MSEL(IP6_16_14
, I2C2_SCL_E
, SEL_I2C2_4
),
1172 PINMUX_IPSR_DATA(IP6_19_17
, ETH_RX_ER
),
1173 PINMUX_IPSR_MSEL(IP6_19_17
, STP_ISD_0_B
, SEL_SSP_1
),
1174 PINMUX_IPSR_MSEL(IP6_19_17
, TS_SPSYNC0_D
, SEL_TSIF0_3
),
1175 PINMUX_IPSR_MSEL(IP6_19_17
, GLO_Q1_C
, SEL_GPS_2
),
1176 PINMUX_IPSR_MSEL(IP6_19_17
, IIC2_SDA_E
, SEL_IIC2_4
),
1177 PINMUX_IPSR_MSEL(IP6_19_17
, I2C2_SDA_E
, SEL_I2C2_4
),
1178 PINMUX_IPSR_DATA(IP6_22_20
, ETH_RXD0
),
1179 PINMUX_IPSR_MSEL(IP6_22_20
, STP_ISEN_0_B
, SEL_SSP_1
),
1180 PINMUX_IPSR_MSEL(IP6_22_20
, TS_SDAT0_D
, SEL_TSIF0_3
),
1181 PINMUX_IPSR_MSEL(IP6_22_20
, GLO_I0_C
, SEL_GPS_2
),
1182 PINMUX_IPSR_MSEL(IP6_22_20
, SCIFB1_SCK_G
, SEL_SCIFB1_6
),
1183 PINMUX_IPSR_MSEL(IP6_22_20
, SCK1_E
, SEL_SCIF1_4
),
1184 PINMUX_IPSR_DATA(IP6_25_23
, ETH_RXD1
),
1185 PINMUX_IPSR_MSEL(IP6_25_23
, HRX0_E
, SEL_HSCIF0_4
),
1186 PINMUX_IPSR_MSEL(IP6_25_23
, STP_ISSYNC_0_B
, SEL_SSP_1
),
1187 PINMUX_IPSR_MSEL(IP6_25_23
, TS_SCK0_D
, SEL_TSIF0_3
),
1188 PINMUX_IPSR_MSEL(IP6_25_23
, GLO_I1_C
, SEL_GPS_2
),
1189 PINMUX_IPSR_MSEL(IP6_25_23
, SCIFB1_RXD_G
, SEL_SCIFB1_6
),
1190 PINMUX_IPSR_MSEL(IP6_25_23
, RX1_E
, SEL_SCIF1_4
),
1191 PINMUX_IPSR_DATA(IP6_28_26
, ETH_LINK
),
1192 PINMUX_IPSR_MSEL(IP6_28_26
, HTX0_E
, SEL_HSCIF0_4
),
1193 PINMUX_IPSR_MSEL(IP6_28_26
, STP_IVCXO27_0_B
, SEL_SSP_1
),
1194 PINMUX_IPSR_MSEL(IP6_28_26
, SCIFB1_TXD_G
, SEL_SCIFB1_6
),
1195 PINMUX_IPSR_MSEL(IP6_28_26
, TX1_E
, SEL_SCIF1_4
),
1196 PINMUX_IPSR_DATA(IP6_31_29
, ETH_REF_CLK
),
1197 PINMUX_IPSR_MSEL(IP6_31_29
, HCTS0_N_E
, SEL_HSCIF0_4
),
1198 PINMUX_IPSR_MSEL(IP6_31_29
, STP_IVCXO27_1_B
, SEL_SSP_1
),
1199 PINMUX_IPSR_MSEL(IP6_31_29
, HRX0_F
, SEL_HSCIF0_5
),
1201 PINMUX_IPSR_DATA(IP7_2_0
, ETH_MDIO
),
1202 PINMUX_IPSR_MSEL(IP7_2_0
, HRTS0_N_E
, SEL_HSCIF0_4
),
1203 PINMUX_IPSR_MSEL(IP7_2_0
, SIM0_D_C
, SEL_SIM_2
),
1204 PINMUX_IPSR_MSEL(IP7_2_0
, HCTS0_N_F
, SEL_HSCIF0_5
),
1205 PINMUX_IPSR_DATA(IP7_5_3
, ETH_TXD1
),
1206 PINMUX_IPSR_MSEL(IP7_5_3
, HTX0_F
, SEL_HSCIF0_5
),
1207 PINMUX_IPSR_MSEL(IP7_5_3
, BPFCLK_G
, SEL_FM_6
),
1208 PINMUX_IPSR_DATA(IP7_7_6
, ETH_TX_EN
),
1209 PINMUX_IPSR_MSEL(IP7_7_6
, SIM0_CLK_C
, SEL_SIM_2
),
1210 PINMUX_IPSR_MSEL(IP7_7_6
, HRTS0_N_F
, SEL_HSCIF0_5
),
1211 PINMUX_IPSR_DATA(IP7_9_8
, ETH_MAGIC
),
1212 PINMUX_IPSR_MSEL(IP7_9_8
, SIM0_RST_C
, SEL_SIM_2
),
1213 PINMUX_IPSR_DATA(IP7_12_10
, ETH_TXD0
),
1214 PINMUX_IPSR_MSEL(IP7_12_10
, STP_ISCLK_1_B
, SEL_SSP_1
),
1215 PINMUX_IPSR_MSEL(IP7_12_10
, TS_SDEN1_C
, SEL_TSIF1_2
),
1216 PINMUX_IPSR_MSEL(IP7_12_10
, GLO_SCLK_C
, SEL_GPS_2
),
1217 PINMUX_IPSR_DATA(IP7_15_13
, ETH_MDC
),
1218 PINMUX_IPSR_MSEL(IP7_15_13
, STP_ISD_1_B
, SEL_SSP_1
),
1219 PINMUX_IPSR_MSEL(IP7_15_13
, TS_SPSYNC1_C
, SEL_TSIF1_2
),
1220 PINMUX_IPSR_MSEL(IP7_15_13
, GLO_SDATA_C
, SEL_GPS_2
),
1221 PINMUX_IPSR_DATA(IP7_18_16
, PWM0
),
1222 PINMUX_IPSR_MSEL(IP7_18_16
, SCIFA2_SCK_C
, SEL_SCIFA2_2
),
1223 PINMUX_IPSR_MSEL(IP7_18_16
, STP_ISEN_1_B
, SEL_SSP_1
),
1224 PINMUX_IPSR_MSEL(IP7_18_16
, TS_SDAT1_C
, SEL_TSIF1_2
),
1225 PINMUX_IPSR_MSEL(IP7_18_16
, GLO_SS_C
, SEL_GPS_2
),
1226 PINMUX_IPSR_DATA(IP7_21_19
, PWM1
),
1227 PINMUX_IPSR_MSEL(IP7_21_19
, SCIFA2_TXD_C
, SEL_SCIFA2_2
),
1228 PINMUX_IPSR_MSEL(IP7_21_19
, STP_ISSYNC_1_B
, SEL_SSP_1
),
1229 PINMUX_IPSR_MSEL(IP7_21_19
, TS_SCK1_C
, SEL_TSIF1_2
),
1230 PINMUX_IPSR_MSEL(IP7_21_19
, GLO_RFON_C
, SEL_GPS_2
),
1231 PINMUX_IPSR_DATA(IP7_21_19
, PCMOE_N
),
1232 PINMUX_IPSR_DATA(IP7_24_22
, PWM2
),
1233 PINMUX_IPSR_DATA(IP7_24_22
, PWMFSW0
),
1234 PINMUX_IPSR_MSEL(IP7_24_22
, SCIFA2_RXD_C
, SEL_SCIFA2_2
),
1235 PINMUX_IPSR_DATA(IP7_24_22
, PCMWE_N
),
1236 PINMUX_IPSR_MSEL(IP7_24_22
, IECLK_C
, SEL_IEB_2
),
1237 PINMUX_IPSR_DATA(IP7_26_25
, DU_DOTCLKIN1
),
1238 PINMUX_IPSR_DATA(IP7_26_25
, AUDIO_CLKC
),
1239 PINMUX_IPSR_DATA(IP7_26_25
, AUDIO_CLKOUT_C
),
1240 PINMUX_IPSR_MSEL(IP7_28_27
, VI0_CLK
, SEL_VI0_0
),
1241 PINMUX_IPSR_DATA(IP7_28_27
, ATACS00_N
),
1242 PINMUX_IPSR_DATA(IP7_28_27
, AVB_RXD1
),
1243 PINMUX_IPSR_MSEL(IP7_30_29
, VI0_DATA0_VI0_B0
, SEL_VI0_0
),
1244 PINMUX_IPSR_DATA(IP7_30_29
, ATACS10_N
),
1245 PINMUX_IPSR_DATA(IP7_30_29
, AVB_RXD2
),
1247 PINMUX_IPSR_MSEL(IP8_1_0
, VI0_DATA1_VI0_B1
, SEL_VI0_0
),
1248 PINMUX_IPSR_DATA(IP8_1_0
, ATARD0_N
),
1249 PINMUX_IPSR_DATA(IP8_1_0
, AVB_RXD3
),
1250 PINMUX_IPSR_MSEL(IP8_3_2
, VI0_DATA2_VI0_B2
, SEL_VI0_0
),
1251 PINMUX_IPSR_DATA(IP8_3_2
, ATAWR0_N
),
1252 PINMUX_IPSR_DATA(IP8_3_2
, AVB_RXD4
),
1253 PINMUX_IPSR_MSEL(IP8_5_4
, VI0_DATA3_VI0_B3
, SEL_VI0_0
),
1254 PINMUX_IPSR_DATA(IP8_5_4
, ATADIR0_N
),
1255 PINMUX_IPSR_DATA(IP8_5_4
, AVB_RXD5
),
1256 PINMUX_IPSR_MSEL(IP8_7_6
, VI0_DATA4_VI0_B4
, SEL_VI0_0
),
1257 PINMUX_IPSR_DATA(IP8_7_6
, ATAG0_N
),
1258 PINMUX_IPSR_DATA(IP8_7_6
, AVB_RXD6
),
1259 PINMUX_IPSR_MSEL(IP8_9_8
, VI0_DATA5_VI0_B5
, SEL_VI0_0
),
1260 PINMUX_IPSR_DATA(IP8_9_8
, EX_WAIT1
),
1261 PINMUX_IPSR_DATA(IP8_9_8
, AVB_RXD7
),
1262 PINMUX_IPSR_MSEL(IP8_11_10
, VI0_DATA6_VI0_B6
, SEL_VI0_0
),
1263 PINMUX_IPSR_DATA(IP8_11_10
, AVB_RX_ER
),
1264 PINMUX_IPSR_MSEL(IP8_13_12
, VI0_DATA7_VI0_B7
, SEL_VI0_0
),
1265 PINMUX_IPSR_DATA(IP8_13_12
, AVB_RX_CLK
),
1266 PINMUX_IPSR_MSEL(IP8_15_14
, VI1_CLK
, SEL_VI1_0
),
1267 PINMUX_IPSR_DATA(IP8_15_14
, AVB_RX_DV
),
1268 PINMUX_IPSR_MSEL(IP8_17_16
, VI1_DATA0_VI1_B0
, SEL_VI1_0
),
1269 PINMUX_IPSR_MSEL(IP8_17_16
, SCIFA1_SCK_D
, SEL_SCIFA1_3
),
1270 PINMUX_IPSR_DATA(IP8_17_16
, AVB_CRS
),
1271 PINMUX_IPSR_MSEL(IP8_19_18
, VI1_DATA1_VI1_B1
, SEL_VI1_0
),
1272 PINMUX_IPSR_MSEL(IP8_19_18
, SCIFA1_RXD_D
, SEL_SCIFA1_3
),
1273 PINMUX_IPSR_DATA(IP8_19_18
, AVB_MDC
),
1274 PINMUX_IPSR_MSEL(IP8_21_20
, VI1_DATA2_VI1_B2
, SEL_VI1_0
),
1275 PINMUX_IPSR_MSEL(IP8_21_20
, SCIFA1_TXD_D
, SEL_SCIFA1_3
),
1276 PINMUX_IPSR_DATA(IP8_21_20
, AVB_MDIO
),
1277 PINMUX_IPSR_MSEL(IP8_23_22
, VI1_DATA3_VI1_B3
, SEL_VI1_0
),
1278 PINMUX_IPSR_MSEL(IP8_23_22
, SCIFA1_CTS_N_D
, SEL_SCIFA1_3
),
1279 PINMUX_IPSR_DATA(IP8_23_22
, AVB_GTX_CLK
),
1280 PINMUX_IPSR_MSEL(IP8_25_24
, VI1_DATA4_VI1_B4
, SEL_VI1_0
),
1281 PINMUX_IPSR_MSEL(IP8_25_24
, SCIFA1_RTS_N_D
, SEL_SCIFA1_3
),
1282 PINMUX_IPSR_DATA(IP8_25_24
, AVB_MAGIC
),
1283 PINMUX_IPSR_MSEL(IP8_26
, VI1_DATA5_VI1_B5
, SEL_VI1_0
),
1284 PINMUX_IPSR_DATA(IP8_26
, AVB_PHY_INT
),
1285 PINMUX_IPSR_MSEL(IP8_27
, VI1_DATA6_VI1_B6
, SEL_VI1_0
),
1286 PINMUX_IPSR_DATA(IP8_27
, AVB_GTXREFCLK
),
1287 PINMUX_IPSR_DATA(IP8_28
, SD0_CLK
),
1288 PINMUX_IPSR_MSEL(IP8_28
, VI1_DATA0_VI1_B0_B
, SEL_VI1_1
),
1289 PINMUX_IPSR_DATA(IP8_30_29
, SD0_CMD
),
1290 PINMUX_IPSR_MSEL(IP8_30_29
, SCIFB1_SCK_B
, SEL_SCIFB1_1
),
1291 PINMUX_IPSR_MSEL(IP8_30_29
, VI1_DATA1_VI1_B1_B
, SEL_VI1_1
),
1293 PINMUX_IPSR_DATA(IP9_1_0
, SD0_DAT0
),
1294 PINMUX_IPSR_MSEL(IP9_1_0
, SCIFB1_RXD_B
, SEL_SCIFB1_1
),
1295 PINMUX_IPSR_MSEL(IP9_1_0
, VI1_DATA2_VI1_B2_B
, SEL_VI1_1
),
1296 PINMUX_IPSR_DATA(IP9_3_2
, SD0_DAT1
),
1297 PINMUX_IPSR_MSEL(IP9_3_2
, SCIFB1_TXD_B
, SEL_SCIFB1_1
),
1298 PINMUX_IPSR_MSEL(IP9_3_2
, VI1_DATA3_VI1_B3_B
, SEL_VI1_1
),
1299 PINMUX_IPSR_DATA(IP9_5_4
, SD0_DAT2
),
1300 PINMUX_IPSR_MSEL(IP9_5_4
, SCIFB1_CTS_N_B
, SEL_SCIFB1_1
),
1301 PINMUX_IPSR_MSEL(IP9_5_4
, VI1_DATA4_VI1_B4_B
, SEL_VI1_1
),
1302 PINMUX_IPSR_DATA(IP9_7_6
, SD0_DAT3
),
1303 PINMUX_IPSR_MSEL(IP9_7_6
, SCIFB1_RTS_N_B
, SEL_SCIFB1_1
),
1304 PINMUX_IPSR_MSEL(IP9_7_6
, VI1_DATA5_VI1_B5_B
, SEL_VI1_1
),
1305 PINMUX_IPSR_DATA(IP9_11_8
, SD0_CD
),
1306 PINMUX_IPSR_DATA(IP9_11_8
, MMC0_D6
),
1307 PINMUX_IPSR_MSEL(IP9_11_8
, TS_SDEN0_B
, SEL_TSIF0_1
),
1308 PINMUX_IPSR_DATA(IP9_11_8
, USB0_EXTP
),
1309 PINMUX_IPSR_MSEL(IP9_11_8
, GLO_SCLK
, SEL_GPS_0
),
1310 PINMUX_IPSR_MSEL(IP9_11_8
, VI1_DATA6_VI1_B6_B
, SEL_VI1_1
),
1311 PINMUX_IPSR_MSEL(IP9_11_8
, IIC1_SCL_B
, SEL_IIC1_1
),
1312 PINMUX_IPSR_MSEL(IP9_11_8
, I2C1_SCL_B
, SEL_I2C1_1
),
1313 PINMUX_IPSR_MSEL(IP9_11_8
, VI2_DATA6_VI2_B6_B
, SEL_VI2_1
),
1314 PINMUX_IPSR_DATA(IP9_15_12
, SD0_WP
),
1315 PINMUX_IPSR_DATA(IP9_15_12
, MMC0_D7
),
1316 PINMUX_IPSR_MSEL(IP9_15_12
, TS_SPSYNC0_B
, SEL_TSIF0_1
),
1317 PINMUX_IPSR_DATA(IP9_15_12
, USB0_IDIN
),
1318 PINMUX_IPSR_MSEL(IP9_15_12
, GLO_SDATA
, SEL_GPS_0
),
1319 PINMUX_IPSR_MSEL(IP9_15_12
, VI1_DATA7_VI1_B7_B
, SEL_VI1_1
),
1320 PINMUX_IPSR_MSEL(IP9_15_12
, IIC1_SDA_B
, SEL_IIC1_1
),
1321 PINMUX_IPSR_MSEL(IP9_15_12
, I2C1_SDA_B
, SEL_I2C1_1
),
1322 PINMUX_IPSR_MSEL(IP9_15_12
, VI2_DATA7_VI2_B7_B
, SEL_VI2_1
),
1323 PINMUX_IPSR_DATA(IP9_17_16
, SD1_CLK
),
1324 PINMUX_IPSR_DATA(IP9_17_16
, AVB_TX_EN
),
1325 PINMUX_IPSR_DATA(IP9_19_18
, SD1_CMD
),
1326 PINMUX_IPSR_DATA(IP9_19_18
, AVB_TX_ER
),
1327 PINMUX_IPSR_MSEL(IP9_19_18
, SCIFB0_SCK_B
, SEL_SCIFB_1
),
1328 PINMUX_IPSR_DATA(IP9_21_20
, SD1_DAT0
),
1329 PINMUX_IPSR_DATA(IP9_21_20
, AVB_TX_CLK
),
1330 PINMUX_IPSR_MSEL(IP9_21_20
, SCIFB0_RXD_B
, SEL_SCIFB_1
),
1331 PINMUX_IPSR_DATA(IP9_23_22
, SD1_DAT1
),
1332 PINMUX_IPSR_DATA(IP9_23_22
, AVB_LINK
),
1333 PINMUX_IPSR_MSEL(IP9_23_22
, SCIFB0_TXD_B
, SEL_SCIFB_1
),
1334 PINMUX_IPSR_DATA(IP9_25_24
, SD1_DAT2
),
1335 PINMUX_IPSR_DATA(IP9_25_24
, AVB_COL
),
1336 PINMUX_IPSR_MSEL(IP9_25_24
, SCIFB0_CTS_N_B
, SEL_SCIFB_1
),
1337 PINMUX_IPSR_DATA(IP9_27_26
, SD1_DAT3
),
1338 PINMUX_IPSR_DATA(IP9_27_26
, AVB_RXD0
),
1339 PINMUX_IPSR_MSEL(IP9_27_26
, SCIFB0_RTS_N_B
, SEL_SCIFB_1
),
1340 PINMUX_IPSR_DATA(IP9_31_28
, SD1_CD
),
1341 PINMUX_IPSR_DATA(IP9_31_28
, MMC1_D6
),
1342 PINMUX_IPSR_MSEL(IP9_31_28
, TS_SDEN1
, SEL_TSIF1_0
),
1343 PINMUX_IPSR_DATA(IP9_31_28
, USB1_EXTP
),
1344 PINMUX_IPSR_MSEL(IP9_31_28
, GLO_SS
, SEL_GPS_0
),
1345 PINMUX_IPSR_MSEL(IP9_31_28
, VI0_CLK_B
, SEL_VI0_1
),
1346 PINMUX_IPSR_MSEL(IP9_31_28
, IIC2_SCL_D
, SEL_IIC2_3
),
1347 PINMUX_IPSR_MSEL(IP9_31_28
, I2C2_SCL_D
, SEL_I2C2_3
),
1348 PINMUX_IPSR_MSEL(IP9_31_28
, SIM0_CLK_B
, SEL_SIM_1
),
1349 PINMUX_IPSR_MSEL(IP9_31_28
, VI3_CLK_B
, SEL_VI3_1
),
1351 PINMUX_IPSR_DATA(IP10_3_0
, SD1_WP
),
1352 PINMUX_IPSR_DATA(IP10_3_0
, MMC1_D7
),
1353 PINMUX_IPSR_MSEL(IP10_3_0
, TS_SPSYNC1
, SEL_TSIF1_0
),
1354 PINMUX_IPSR_DATA(IP10_3_0
, USB1_IDIN
),
1355 PINMUX_IPSR_MSEL(IP10_3_0
, GLO_RFON
, SEL_GPS_0
),
1356 PINMUX_IPSR_MSEL(IP10_3_0
, VI1_CLK_B
, SEL_VI1_1
),
1357 PINMUX_IPSR_MSEL(IP10_3_0
, IIC2_SDA_D
, SEL_IIC2_3
),
1358 PINMUX_IPSR_MSEL(IP10_3_0
, I2C2_SDA_D
, SEL_I2C2_3
),
1359 PINMUX_IPSR_MSEL(IP10_3_0
, SIM0_D_B
, SEL_SIM_1
),
1360 PINMUX_IPSR_DATA(IP10_6_4
, SD2_CLK
),
1361 PINMUX_IPSR_DATA(IP10_6_4
, MMC0_CLK
),
1362 PINMUX_IPSR_MSEL(IP10_6_4
, SIM0_CLK
, SEL_SIM_0
),
1363 PINMUX_IPSR_MSEL(IP10_6_4
, VI0_DATA0_VI0_B0_B
, SEL_VI0_1
),
1364 PINMUX_IPSR_MSEL(IP10_6_4
, TS_SDEN0_C
, SEL_TSIF0_2
),
1365 PINMUX_IPSR_MSEL(IP10_6_4
, GLO_SCLK_B
, SEL_GPS_1
),
1366 PINMUX_IPSR_MSEL(IP10_6_4
, VI3_DATA0_B
, SEL_VI3_1
),
1367 PINMUX_IPSR_DATA(IP10_10_7
, SD2_CMD
),
1368 PINMUX_IPSR_DATA(IP10_10_7
, MMC0_CMD
),
1369 PINMUX_IPSR_MSEL(IP10_10_7
, SIM0_D
, SEL_SIM_0
),
1370 PINMUX_IPSR_MSEL(IP10_10_7
, VI0_DATA1_VI0_B1_B
, SEL_VI0_1
),
1371 PINMUX_IPSR_MSEL(IP10_10_7
, SCIFB1_SCK_E
, SEL_SCIFB1_4
),
1372 PINMUX_IPSR_MSEL(IP10_10_7
, SCK1_D
, SEL_SCIF1_3
),
1373 PINMUX_IPSR_MSEL(IP10_10_7
, TS_SPSYNC0_C
, SEL_TSIF0_2
),
1374 PINMUX_IPSR_MSEL(IP10_10_7
, GLO_SDATA_B
, SEL_GPS_1
),
1375 PINMUX_IPSR_MSEL(IP10_10_7
, VI3_DATA1_B
, SEL_VI3_1
),
1376 PINMUX_IPSR_DATA(IP10_14_11
, SD2_DAT0
),
1377 PINMUX_IPSR_DATA(IP10_14_11
, MMC0_D0
),
1378 PINMUX_IPSR_MSEL(IP10_14_11
, FMCLK_B
, SEL_FM_1
),
1379 PINMUX_IPSR_MSEL(IP10_14_11
, VI0_DATA2_VI0_B2_B
, SEL_VI0_1
),
1380 PINMUX_IPSR_MSEL(IP10_14_11
, SCIFB1_RXD_E
, SEL_SCIFB1_4
),
1381 PINMUX_IPSR_MSEL(IP10_14_11
, RX1_D
, SEL_SCIF1_3
),
1382 PINMUX_IPSR_MSEL(IP10_14_11
, TS_SDAT0_C
, SEL_TSIF0_2
),
1383 PINMUX_IPSR_MSEL(IP10_14_11
, GLO_SS_B
, SEL_GPS_1
),
1384 PINMUX_IPSR_MSEL(IP10_14_11
, VI3_DATA2_B
, SEL_VI3_1
),
1385 PINMUX_IPSR_DATA(IP10_18_15
, SD2_DAT1
),
1386 PINMUX_IPSR_DATA(IP10_18_15
, MMC0_D1
),
1387 PINMUX_IPSR_MSEL(IP10_18_15
, FMIN_B
, SEL_FM_1
),
1388 PINMUX_IPSR_MSEL(IP10_18_15
, VI0_DATA3_VI0_B3_B
, SEL_VI0_1
),
1389 PINMUX_IPSR_MSEL(IP10_18_15
, SCIFB1_TXD_E
, SEL_SCIFB1_4
),
1390 PINMUX_IPSR_MSEL(IP10_18_15
, TX1_D
, SEL_SCIF1_3
),
1391 PINMUX_IPSR_MSEL(IP10_18_15
, TS_SCK0_C
, SEL_TSIF0_2
),
1392 PINMUX_IPSR_MSEL(IP10_18_15
, GLO_RFON_B
, SEL_GPS_1
),
1393 PINMUX_IPSR_MSEL(IP10_18_15
, VI3_DATA3_B
, SEL_VI3_1
),
1394 PINMUX_IPSR_DATA(IP10_22_19
, SD2_DAT2
),
1395 PINMUX_IPSR_DATA(IP10_22_19
, MMC0_D2
),
1396 PINMUX_IPSR_MSEL(IP10_22_19
, BPFCLK_B
, SEL_FM_1
),
1397 PINMUX_IPSR_MSEL(IP10_22_19
, VI0_DATA4_VI0_B4_B
, SEL_VI0_1
),
1398 PINMUX_IPSR_MSEL(IP10_22_19
, HRX0_D
, SEL_HSCIF0_3
),
1399 PINMUX_IPSR_MSEL(IP10_22_19
, TS_SDEN1_B
, SEL_TSIF1_1
),
1400 PINMUX_IPSR_MSEL(IP10_22_19
, GLO_Q0_B
, SEL_GPS_1
),
1401 PINMUX_IPSR_MSEL(IP10_22_19
, VI3_DATA4_B
, SEL_VI3_1
),
1402 PINMUX_IPSR_DATA(IP10_25_23
, SD2_DAT3
),
1403 PINMUX_IPSR_DATA(IP10_25_23
, MMC0_D3
),
1404 PINMUX_IPSR_MSEL(IP10_25_23
, SIM0_RST
, SEL_SIM_0
),
1405 PINMUX_IPSR_MSEL(IP10_25_23
, VI0_DATA5_VI0_B5_B
, SEL_VI0_1
),
1406 PINMUX_IPSR_MSEL(IP10_25_23
, HTX0_D
, SEL_HSCIF0_3
),
1407 PINMUX_IPSR_MSEL(IP10_25_23
, TS_SPSYNC1_B
, SEL_TSIF1_1
),
1408 PINMUX_IPSR_MSEL(IP10_25_23
, GLO_Q1_B
, SEL_GPS_1
),
1409 PINMUX_IPSR_MSEL(IP10_25_23
, VI3_DATA5_B
, SEL_VI3_1
),
1410 PINMUX_IPSR_DATA(IP10_29_26
, SD2_CD
),
1411 PINMUX_IPSR_DATA(IP10_29_26
, MMC0_D4
),
1412 PINMUX_IPSR_MSEL(IP10_29_26
, TS_SDAT0_B
, SEL_TSIF0_1
),
1413 PINMUX_IPSR_DATA(IP10_29_26
, USB2_EXTP
),
1414 PINMUX_IPSR_MSEL(IP10_29_26
, GLO_I0
, SEL_GPS_0
),
1415 PINMUX_IPSR_MSEL(IP10_29_26
, VI0_DATA6_VI0_B6_B
, SEL_VI0_1
),
1416 PINMUX_IPSR_MSEL(IP10_29_26
, HCTS0_N_D
, SEL_HSCIF0_3
),
1417 PINMUX_IPSR_MSEL(IP10_29_26
, TS_SDAT1_B
, SEL_TSIF1_1
),
1418 PINMUX_IPSR_MSEL(IP10_29_26
, GLO_I0_B
, SEL_GPS_1
),
1419 PINMUX_IPSR_MSEL(IP10_29_26
, VI3_DATA6_B
, SEL_VI3_1
),
1421 PINMUX_IPSR_DATA(IP11_3_0
, SD2_WP
),
1422 PINMUX_IPSR_DATA(IP11_3_0
, MMC0_D5
),
1423 PINMUX_IPSR_MSEL(IP11_3_0
, TS_SCK0_B
, SEL_TSIF0_1
),
1424 PINMUX_IPSR_DATA(IP11_3_0
, USB2_IDIN
),
1425 PINMUX_IPSR_MSEL(IP11_3_0
, GLO_I1
, SEL_GPS_0
),
1426 PINMUX_IPSR_MSEL(IP11_3_0
, VI0_DATA7_VI0_B7_B
, SEL_VI0_1
),
1427 PINMUX_IPSR_MSEL(IP11_3_0
, HRTS0_N_D
, SEL_HSCIF0_3
),
1428 PINMUX_IPSR_MSEL(IP11_3_0
, TS_SCK1_B
, SEL_TSIF1_1
),
1429 PINMUX_IPSR_MSEL(IP11_3_0
, GLO_I1_B
, SEL_GPS_1
),
1430 PINMUX_IPSR_MSEL(IP11_3_0
, VI3_DATA7_B
, SEL_VI3_1
),
1431 PINMUX_IPSR_DATA(IP11_4
, SD3_CLK
),
1432 PINMUX_IPSR_DATA(IP11_4
, MMC1_CLK
),
1433 PINMUX_IPSR_DATA(IP11_6_5
, SD3_CMD
),
1434 PINMUX_IPSR_DATA(IP11_6_5
, MMC1_CMD
),
1435 PINMUX_IPSR_DATA(IP11_6_5
, MTS_N
),
1436 PINMUX_IPSR_DATA(IP11_8_7
, SD3_DAT0
),
1437 PINMUX_IPSR_DATA(IP11_8_7
, MMC1_D0
),
1438 PINMUX_IPSR_DATA(IP11_8_7
, STM_N
),
1439 PINMUX_IPSR_DATA(IP11_10_9
, SD3_DAT1
),
1440 PINMUX_IPSR_DATA(IP11_10_9
, MMC1_D1
),
1441 PINMUX_IPSR_DATA(IP11_10_9
, MDATA
),
1442 PINMUX_IPSR_DATA(IP11_12_11
, SD3_DAT2
),
1443 PINMUX_IPSR_DATA(IP11_12_11
, MMC1_D2
),
1444 PINMUX_IPSR_DATA(IP11_12_11
, SDATA
),
1445 PINMUX_IPSR_DATA(IP11_14_13
, SD3_DAT3
),
1446 PINMUX_IPSR_DATA(IP11_14_13
, MMC1_D3
),
1447 PINMUX_IPSR_DATA(IP11_14_13
, SCKZ
),
1448 PINMUX_IPSR_DATA(IP11_17_15
, SD3_CD
),
1449 PINMUX_IPSR_DATA(IP11_17_15
, MMC1_D4
),
1450 PINMUX_IPSR_MSEL(IP11_17_15
, TS_SDAT1
, SEL_TSIF1_0
),
1451 PINMUX_IPSR_DATA(IP11_17_15
, VSP
),
1452 PINMUX_IPSR_MSEL(IP11_17_15
, GLO_Q0
, SEL_GPS_0
),
1453 PINMUX_IPSR_MSEL(IP11_17_15
, SIM0_RST_B
, SEL_SIM_1
),
1454 PINMUX_IPSR_DATA(IP11_21_18
, SD3_WP
),
1455 PINMUX_IPSR_DATA(IP11_21_18
, MMC1_D5
),
1456 PINMUX_IPSR_MSEL(IP11_21_18
, TS_SCK1
, SEL_TSIF1_0
),
1457 PINMUX_IPSR_MSEL(IP11_21_18
, GLO_Q1
, SEL_GPS_0
),
1458 PINMUX_IPSR_MSEL(IP11_21_18
, FMIN_C
, SEL_FM_2
),
1459 PINMUX_IPSR_MSEL(IP11_21_18
, FMIN_E
, SEL_FM_4
),
1460 PINMUX_IPSR_MSEL(IP11_21_18
, FMIN_F
, SEL_FM_5
),
1461 PINMUX_IPSR_DATA(IP11_23_22
, MLB_CLK
),
1462 PINMUX_IPSR_MSEL(IP11_23_22
, IIC2_SCL_B
, SEL_IIC2_1
),
1463 PINMUX_IPSR_MSEL(IP11_23_22
, I2C2_SCL_B
, SEL_I2C2_1
),
1464 PINMUX_IPSR_DATA(IP11_26_24
, MLB_SIG
),
1465 PINMUX_IPSR_MSEL(IP11_26_24
, SCIFB1_RXD_D
, SEL_SCIFB1_3
),
1466 PINMUX_IPSR_MSEL(IP11_26_24
, RX1_C
, SEL_SCIF1_2
),
1467 PINMUX_IPSR_MSEL(IP11_26_24
, IIC2_SDA_B
, SEL_IIC2_1
),
1468 PINMUX_IPSR_MSEL(IP11_26_24
, I2C2_SDA_B
, SEL_I2C2_1
),
1469 PINMUX_IPSR_DATA(IP11_29_27
, MLB_DAT
),
1470 PINMUX_IPSR_MSEL(IP11_29_27
, SCIFB1_TXD_D
, SEL_SCIFB1_3
),
1471 PINMUX_IPSR_MSEL(IP11_29_27
, TX1_C
, SEL_SCIF1_2
),
1472 PINMUX_IPSR_MSEL(IP11_29_27
, BPFCLK_C
, SEL_FM_2
),
1473 PINMUX_IPSR_DATA(IP11_31_30
, SSI_SCK0129
),
1474 PINMUX_IPSR_MSEL(IP11_31_30
, CAN_CLK_B
, SEL_CANCLK_1
),
1475 PINMUX_IPSR_DATA(IP11_31_30
, MOUT0
),
1477 PINMUX_IPSR_DATA(IP12_1_0
, SSI_WS0129
),
1478 PINMUX_IPSR_MSEL(IP12_1_0
, CAN0_TX_B
, SEL_CAN0_1
),
1479 PINMUX_IPSR_DATA(IP12_1_0
, MOUT1
),
1480 PINMUX_IPSR_DATA(IP12_3_2
, SSI_SDATA0
),
1481 PINMUX_IPSR_MSEL(IP12_3_2
, CAN0_RX_B
, SEL_CAN0_1
),
1482 PINMUX_IPSR_DATA(IP12_3_2
, MOUT2
),
1483 PINMUX_IPSR_DATA(IP12_5_4
, SSI_SDATA1
),
1484 PINMUX_IPSR_MSEL(IP12_5_4
, CAN1_TX_B
, SEL_CAN1_1
),
1485 PINMUX_IPSR_DATA(IP12_5_4
, MOUT5
),
1486 PINMUX_IPSR_DATA(IP12_7_6
, SSI_SDATA2
),
1487 PINMUX_IPSR_MSEL(IP12_7_6
, CAN1_RX_B
, SEL_CAN1_1
),
1488 PINMUX_IPSR_DATA(IP12_7_6
, SSI_SCK1
),
1489 PINMUX_IPSR_DATA(IP12_7_6
, MOUT6
),
1490 PINMUX_IPSR_DATA(IP12_10_8
, SSI_SCK34
),
1491 PINMUX_IPSR_DATA(IP12_10_8
, STP_OPWM_0
),
1492 PINMUX_IPSR_MSEL(IP12_10_8
, SCIFB0_SCK
, SEL_SCIFB_0
),
1493 PINMUX_IPSR_MSEL(IP12_10_8
, MSIOF1_SCK
, SEL_SOF1_0
),
1494 PINMUX_IPSR_DATA(IP12_10_8
, CAN_DEBUG_HW_TRIGGER
),
1495 PINMUX_IPSR_DATA(IP12_13_11
, SSI_WS34
),
1496 PINMUX_IPSR_MSEL(IP12_13_11
, STP_IVCXO27_0
, SEL_SSP_0
),
1497 PINMUX_IPSR_MSEL(IP12_13_11
, SCIFB0_RXD
, SEL_SCIFB_0
),
1498 PINMUX_IPSR_DATA(IP12_13_11
, MSIOF1_SYNC
),
1499 PINMUX_IPSR_DATA(IP12_13_11
, CAN_STEP0
),
1500 PINMUX_IPSR_DATA(IP12_16_14
, SSI_SDATA3
),
1501 PINMUX_IPSR_MSEL(IP12_16_14
, STP_ISCLK_0
, SEL_SSP_0
),
1502 PINMUX_IPSR_MSEL(IP12_16_14
, SCIFB0_TXD
, SEL_SCIFB_0
),
1503 PINMUX_IPSR_MSEL(IP12_16_14
, MSIOF1_SS1
, SEL_SOF1_0
),
1504 PINMUX_IPSR_DATA(IP12_16_14
, CAN_TXCLK
),
1505 PINMUX_IPSR_DATA(IP12_19_17
, SSI_SCK4
),
1506 PINMUX_IPSR_MSEL(IP12_19_17
, STP_ISD_0
, SEL_SSP_0
),
1507 PINMUX_IPSR_MSEL(IP12_19_17
, SCIFB0_CTS_N
, SEL_SCIFB_0
),
1508 PINMUX_IPSR_MSEL(IP12_19_17
, MSIOF1_SS2
, SEL_SOF1_0
),
1509 PINMUX_IPSR_MSEL(IP12_19_17
, SSI_SCK5_C
, SEL_SSI5_2
),
1510 PINMUX_IPSR_DATA(IP12_19_17
, CAN_DEBUGOUT0
),
1511 PINMUX_IPSR_DATA(IP12_22_20
, SSI_WS4
),
1512 PINMUX_IPSR_MSEL(IP12_22_20
, STP_ISEN_0
, SEL_SSP_0
),
1513 PINMUX_IPSR_MSEL(IP12_22_20
, SCIFB0_RTS_N
, SEL_SCIFB_0
),
1514 PINMUX_IPSR_MSEL(IP12_22_20
, MSIOF1_TXD
, SEL_SOF1_0
),
1515 PINMUX_IPSR_MSEL(IP12_22_20
, SSI_WS5_C
, SEL_SSI5_2
),
1516 PINMUX_IPSR_DATA(IP12_22_20
, CAN_DEBUGOUT1
),
1517 PINMUX_IPSR_DATA(IP12_24_23
, SSI_SDATA4
),
1518 PINMUX_IPSR_MSEL(IP12_24_23
, STP_ISSYNC_0
, SEL_SSP_0
),
1519 PINMUX_IPSR_MSEL(IP12_24_23
, MSIOF1_RXD
, SEL_SOF1_0
),
1520 PINMUX_IPSR_DATA(IP12_24_23
, CAN_DEBUGOUT2
),
1521 PINMUX_IPSR_MSEL(IP12_27_25
, SSI_SCK5
, SEL_SSI5_0
),
1522 PINMUX_IPSR_MSEL(IP12_27_25
, SCIFB1_SCK
, SEL_SCIFB1_0
),
1523 PINMUX_IPSR_MSEL(IP12_27_25
, IERX_B
, SEL_IEB_1
),
1524 PINMUX_IPSR_DATA(IP12_27_25
, DU2_EXHSYNC_DU2_HSYNC
),
1525 PINMUX_IPSR_DATA(IP12_27_25
, QSTH_QHS
),
1526 PINMUX_IPSR_DATA(IP12_27_25
, CAN_DEBUGOUT3
),
1527 PINMUX_IPSR_MSEL(IP12_30_28
, SSI_WS5
, SEL_SSI5_0
),
1528 PINMUX_IPSR_MSEL(IP12_30_28
, SCIFB1_RXD
, SEL_SCIFB1_0
),
1529 PINMUX_IPSR_MSEL(IP12_30_28
, IECLK_B
, SEL_IEB_1
),
1530 PINMUX_IPSR_DATA(IP12_30_28
, DU2_EXVSYNC_DU2_VSYNC
),
1531 PINMUX_IPSR_DATA(IP12_30_28
, QSTB_QHE
),
1532 PINMUX_IPSR_DATA(IP12_30_28
, CAN_DEBUGOUT4
),
1534 PINMUX_IPSR_MSEL(IP13_2_0
, SSI_SDATA5
, SEL_SSI5_0
),
1535 PINMUX_IPSR_MSEL(IP13_2_0
, SCIFB1_TXD
, SEL_SCIFB1_0
),
1536 PINMUX_IPSR_MSEL(IP13_2_0
, IETX_B
, SEL_IEB_1
),
1537 PINMUX_IPSR_DATA(IP13_2_0
, DU2_DR2
),
1538 PINMUX_IPSR_DATA(IP13_2_0
, LCDOUT2
),
1539 PINMUX_IPSR_DATA(IP13_2_0
, CAN_DEBUGOUT5
),
1540 PINMUX_IPSR_MSEL(IP13_6_3
, SSI_SCK6
, SEL_SSI6_0
),
1541 PINMUX_IPSR_MSEL(IP13_6_3
, SCIFB1_CTS_N
, SEL_SCIFB1_0
),
1542 PINMUX_IPSR_MSEL(IP13_6_3
, BPFCLK_D
, SEL_FM_3
),
1543 PINMUX_IPSR_DATA(IP13_6_3
, DU2_DR3
),
1544 PINMUX_IPSR_DATA(IP13_6_3
, LCDOUT3
),
1545 PINMUX_IPSR_DATA(IP13_6_3
, CAN_DEBUGOUT6
),
1546 PINMUX_IPSR_MSEL(IP13_6_3
, BPFCLK_F
, SEL_FM_5
),
1547 PINMUX_IPSR_MSEL(IP13_9_7
, SSI_WS6
, SEL_SSI6_0
),
1548 PINMUX_IPSR_MSEL(IP13_9_7
, SCIFB1_RTS_N
, SEL_SCIFB1_0
),
1549 PINMUX_IPSR_MSEL(IP13_9_7
, CAN0_TX_D
, SEL_CAN0_3
),
1550 PINMUX_IPSR_DATA(IP13_9_7
, DU2_DR4
),
1551 PINMUX_IPSR_DATA(IP13_9_7
, LCDOUT4
),
1552 PINMUX_IPSR_DATA(IP13_9_7
, CAN_DEBUGOUT7
),
1553 PINMUX_IPSR_MSEL(IP13_12_10
, SSI_SDATA6
, SEL_SSI6_0
),
1554 PINMUX_IPSR_MSEL(IP13_12_10
, FMIN_D
, SEL_FM_3
),
1555 PINMUX_IPSR_DATA(IP13_12_10
, DU2_DR5
),
1556 PINMUX_IPSR_DATA(IP13_12_10
, LCDOUT5
),
1557 PINMUX_IPSR_DATA(IP13_12_10
, CAN_DEBUGOUT8
),
1558 PINMUX_IPSR_MSEL(IP13_15_13
, SSI_SCK78
, SEL_SSI7_0
),
1559 PINMUX_IPSR_MSEL(IP13_15_13
, STP_IVCXO27_1
, SEL_SSP_0
),
1560 PINMUX_IPSR_MSEL(IP13_15_13
, SCK1
, SEL_SCIF1_0
),
1561 PINMUX_IPSR_MSEL(IP13_15_13
, SCIFA1_SCK
, SEL_SCIFA1_0
),
1562 PINMUX_IPSR_DATA(IP13_15_13
, DU2_DR6
),
1563 PINMUX_IPSR_DATA(IP13_15_13
, LCDOUT6
),
1564 PINMUX_IPSR_DATA(IP13_15_13
, CAN_DEBUGOUT9
),
1565 PINMUX_IPSR_MSEL(IP13_18_16
, SSI_WS78
, SEL_SSI7_0
),
1566 PINMUX_IPSR_MSEL(IP13_18_16
, STP_ISCLK_1
, SEL_SSP_0
),
1567 PINMUX_IPSR_MSEL(IP13_18_16
, SCIFB2_SCK
, SEL_SCIFB2_0
),
1568 PINMUX_IPSR_DATA(IP13_18_16
, SCIFA2_CTS_N
),
1569 PINMUX_IPSR_DATA(IP13_18_16
, DU2_DR7
),
1570 PINMUX_IPSR_DATA(IP13_18_16
, LCDOUT7
),
1571 PINMUX_IPSR_DATA(IP13_18_16
, CAN_DEBUGOUT10
),
1572 PINMUX_IPSR_MSEL(IP13_22_19
, SSI_SDATA7
, SEL_SSI7_0
),
1573 PINMUX_IPSR_MSEL(IP13_22_19
, STP_ISD_1
, SEL_SSP_0
),
1574 PINMUX_IPSR_MSEL(IP13_22_19
, SCIFB2_RXD
, SEL_SCIFB2_0
),
1575 PINMUX_IPSR_DATA(IP13_22_19
, SCIFA2_RTS_N
),
1576 PINMUX_IPSR_DATA(IP13_22_19
, TCLK2
),
1577 PINMUX_IPSR_DATA(IP13_22_19
, QSTVA_QVS
),
1578 PINMUX_IPSR_DATA(IP13_22_19
, CAN_DEBUGOUT11
),
1579 PINMUX_IPSR_MSEL(IP13_22_19
, BPFCLK_E
, SEL_FM_4
),
1580 PINMUX_IPSR_MSEL(IP13_22_19
, SSI_SDATA7_B
, SEL_SSI7_1
),
1581 PINMUX_IPSR_MSEL(IP13_22_19
, FMIN_G
, SEL_FM_6
),
1582 PINMUX_IPSR_MSEL(IP13_25_23
, SSI_SDATA8
, SEL_SSI8_0
),
1583 PINMUX_IPSR_MSEL(IP13_25_23
, STP_ISEN_1
, SEL_SSP_0
),
1584 PINMUX_IPSR_MSEL(IP13_25_23
, SCIFB2_TXD
, SEL_SCIFB2_0
),
1585 PINMUX_IPSR_MSEL(IP13_25_23
, CAN0_TX_C
, SEL_CAN0_2
),
1586 PINMUX_IPSR_DATA(IP13_25_23
, CAN_DEBUGOUT12
),
1587 PINMUX_IPSR_MSEL(IP13_25_23
, SSI_SDATA8_B
, SEL_SSI8_1
),
1588 PINMUX_IPSR_DATA(IP13_28_26
, SSI_SDATA9
),
1589 PINMUX_IPSR_MSEL(IP13_28_26
, STP_ISSYNC_1
, SEL_SSP_0
),
1590 PINMUX_IPSR_MSEL(IP13_28_26
, SCIFB2_CTS_N
, SEL_SCIFB2_0
),
1591 PINMUX_IPSR_DATA(IP13_28_26
, SSI_WS1
),
1592 PINMUX_IPSR_MSEL(IP13_28_26
, SSI_SDATA5_C
, SEL_SSI5_2
),
1593 PINMUX_IPSR_DATA(IP13_28_26
, CAN_DEBUGOUT13
),
1594 PINMUX_IPSR_DATA(IP13_30_29
, AUDIO_CLKA
),
1595 PINMUX_IPSR_MSEL(IP13_30_29
, SCIFB2_RTS_N
, SEL_SCIFB2_0
),
1596 PINMUX_IPSR_DATA(IP13_30_29
, CAN_DEBUGOUT14
),
1598 PINMUX_IPSR_DATA(IP14_2_0
, AUDIO_CLKB
),
1599 PINMUX_IPSR_MSEL(IP14_2_0
, SCIF_CLK
, SEL_SCIFCLK_0
),
1600 PINMUX_IPSR_MSEL(IP14_2_0
, CAN0_RX_D
, SEL_CAN0_3
),
1601 PINMUX_IPSR_DATA(IP14_2_0
, DVC_MUTE
),
1602 PINMUX_IPSR_MSEL(IP14_2_0
, CAN0_RX_C
, SEL_CAN0_2
),
1603 PINMUX_IPSR_DATA(IP14_2_0
, CAN_DEBUGOUT15
),
1604 PINMUX_IPSR_DATA(IP14_2_0
, REMOCON
),
1605 PINMUX_IPSR_MSEL(IP14_5_3
, SCIFA0_SCK
, SEL_SCFA_0
),
1606 PINMUX_IPSR_MSEL(IP14_5_3
, HSCK1
, SEL_HSCIF1_0
),
1607 PINMUX_IPSR_DATA(IP14_5_3
, SCK0
),
1608 PINMUX_IPSR_DATA(IP14_5_3
, MSIOF3_SS2
),
1609 PINMUX_IPSR_DATA(IP14_5_3
, DU2_DG2
),
1610 PINMUX_IPSR_DATA(IP14_5_3
, LCDOUT10
),
1611 PINMUX_IPSR_MSEL(IP14_5_3
, IIC1_SDA_C
, SEL_IIC1_2
),
1612 PINMUX_IPSR_MSEL(IP14_5_3
, I2C1_SDA_C
, SEL_I2C1_2
),
1613 PINMUX_IPSR_MSEL(IP14_8_6
, SCIFA0_RXD
, SEL_SCFA_0
),
1614 PINMUX_IPSR_MSEL(IP14_8_6
, HRX1
, SEL_HSCIF1_0
),
1615 PINMUX_IPSR_MSEL(IP14_8_6
, RX0
, SEL_SCIF0_0
),
1616 PINMUX_IPSR_DATA(IP14_8_6
, DU2_DR0
),
1617 PINMUX_IPSR_DATA(IP14_8_6
, LCDOUT0
),
1618 PINMUX_IPSR_MSEL(IP14_11_9
, SCIFA0_TXD
, SEL_SCFA_0
),
1619 PINMUX_IPSR_MSEL(IP14_11_9
, HTX1
, SEL_HSCIF1_0
),
1620 PINMUX_IPSR_MSEL(IP14_11_9
, TX0
, SEL_SCIF0_0
),
1621 PINMUX_IPSR_DATA(IP14_11_9
, DU2_DR1
),
1622 PINMUX_IPSR_DATA(IP14_11_9
, LCDOUT1
),
1623 PINMUX_IPSR_MSEL(IP14_15_12
, SCIFA0_CTS_N
, SEL_SCFA_0
),
1624 PINMUX_IPSR_MSEL(IP14_15_12
, HCTS1_N
, SEL_HSCIF1_0
),
1625 PINMUX_IPSR_DATA(IP14_15_12
, CTS0_N
),
1626 PINMUX_IPSR_MSEL(IP14_15_12
, MSIOF3_SYNC
, SEL_SOF3_0
),
1627 PINMUX_IPSR_DATA(IP14_15_12
, DU2_DG3
),
1628 PINMUX_IPSR_DATA(IP14_15_12
, LCDOUT11
),
1629 PINMUX_IPSR_DATA(IP14_15_12
, PWM0_B
),
1630 PINMUX_IPSR_MSEL(IP14_15_12
, IIC1_SCL_C
, SEL_IIC1_2
),
1631 PINMUX_IPSR_MSEL(IP14_15_12
, I2C1_SCL_C
, SEL_I2C1_2
),
1632 PINMUX_IPSR_MSEL(IP14_18_16
, SCIFA0_RTS_N
, SEL_SCFA_0
),
1633 PINMUX_IPSR_MSEL(IP14_18_16
, HRTS1_N
, SEL_HSCIF1_0
),
1634 PINMUX_IPSR_DATA(IP14_18_16
, RTS0_N
),
1635 PINMUX_IPSR_DATA(IP14_18_16
, MSIOF3_SS1
),
1636 PINMUX_IPSR_DATA(IP14_18_16
, DU2_DG0
),
1637 PINMUX_IPSR_DATA(IP14_18_16
, LCDOUT8
),
1638 PINMUX_IPSR_DATA(IP14_18_16
, PWM1_B
),
1639 PINMUX_IPSR_MSEL(IP14_21_19
, SCIFA1_RXD
, SEL_SCIFA1_0
),
1640 PINMUX_IPSR_MSEL(IP14_21_19
, AD_DI
, SEL_ADI_0
),
1641 PINMUX_IPSR_MSEL(IP14_21_19
, RX1
, SEL_SCIF1_0
),
1642 PINMUX_IPSR_DATA(IP14_21_19
, DU2_EXODDF_DU2_ODDF_DISP_CDE
),
1643 PINMUX_IPSR_DATA(IP14_21_19
, QCPV_QDE
),
1644 PINMUX_IPSR_MSEL(IP14_24_22
, SCIFA1_TXD
, SEL_SCIFA1_0
),
1645 PINMUX_IPSR_MSEL(IP14_24_22
, AD_DO
, SEL_ADI_0
),
1646 PINMUX_IPSR_MSEL(IP14_24_22
, TX1
, SEL_SCIF1_0
),
1647 PINMUX_IPSR_DATA(IP14_24_22
, DU2_DG1
),
1648 PINMUX_IPSR_DATA(IP14_24_22
, LCDOUT9
),
1649 PINMUX_IPSR_MSEL(IP14_27_25
, SCIFA1_CTS_N
, SEL_SCIFA1_0
),
1650 PINMUX_IPSR_MSEL(IP14_27_25
, AD_CLK
, SEL_ADI_0
),
1651 PINMUX_IPSR_DATA(IP14_27_25
, CTS1_N
),
1652 PINMUX_IPSR_MSEL(IP14_27_25
, MSIOF3_RXD
, SEL_SOF3_0
),
1653 PINMUX_IPSR_DATA(IP14_27_25
, DU0_DOTCLKOUT
),
1654 PINMUX_IPSR_DATA(IP14_27_25
, QCLK
),
1655 PINMUX_IPSR_MSEL(IP14_30_28
, SCIFA1_RTS_N
, SEL_SCIFA1_0
),
1656 PINMUX_IPSR_MSEL(IP14_30_28
, AD_NCS_N
, SEL_ADI_0
),
1657 PINMUX_IPSR_DATA(IP14_30_28
, RTS1_N
),
1658 PINMUX_IPSR_MSEL(IP14_30_28
, MSIOF3_TXD
, SEL_SOF3_0
),
1659 PINMUX_IPSR_DATA(IP14_30_28
, DU1_DOTCLKOUT
),
1660 PINMUX_IPSR_DATA(IP14_30_28
, QSTVB_QVE
),
1661 PINMUX_IPSR_MSEL(IP14_30_28
, HRTS0_N_C
, SEL_HSCIF0_2
),
1663 PINMUX_IPSR_MSEL(IP15_2_0
, SCIFA2_SCK
, SEL_SCIFA2_0
),
1664 PINMUX_IPSR_MSEL(IP15_2_0
, FMCLK
, SEL_FM_0
),
1665 PINMUX_IPSR_DATA(IP15_2_0
, SCK2
),
1666 PINMUX_IPSR_MSEL(IP15_2_0
, MSIOF3_SCK
, SEL_SOF3_0
),
1667 PINMUX_IPSR_DATA(IP15_2_0
, DU2_DG7
),
1668 PINMUX_IPSR_DATA(IP15_2_0
, LCDOUT15
),
1669 PINMUX_IPSR_MSEL(IP15_2_0
, SCIF_CLK_B
, SEL_SCIFCLK_1
),
1670 PINMUX_IPSR_MSEL(IP15_5_3
, SCIFA2_RXD
, SEL_SCIFA2_0
),
1671 PINMUX_IPSR_MSEL(IP15_5_3
, FMIN
, SEL_FM_0
),
1672 PINMUX_IPSR_MSEL(IP15_5_3
, TX2
, SEL_SCIF2_0
),
1673 PINMUX_IPSR_DATA(IP15_5_3
, DU2_DB0
),
1674 PINMUX_IPSR_DATA(IP15_5_3
, LCDOUT16
),
1675 PINMUX_IPSR_MSEL(IP15_5_3
, IIC2_SCL
, SEL_IIC2_0
),
1676 PINMUX_IPSR_MSEL(IP15_5_3
, I2C2_SCL
, SEL_I2C2_0
),
1677 PINMUX_IPSR_MSEL(IP15_8_6
, SCIFA2_TXD
, SEL_SCIFA2_0
),
1678 PINMUX_IPSR_MSEL(IP15_8_6
, BPFCLK
, SEL_FM_0
),
1679 PINMUX_IPSR_MSEL(IP15_8_6
, RX2
, SEL_SCIF2_0
),
1680 PINMUX_IPSR_DATA(IP15_8_6
, DU2_DB1
),
1681 PINMUX_IPSR_DATA(IP15_8_6
, LCDOUT17
),
1682 PINMUX_IPSR_MSEL(IP15_8_6
, IIC2_SDA
, SEL_IIC2_0
),
1683 PINMUX_IPSR_MSEL(IP15_8_6
, I2C2_SDA
, SEL_I2C2_0
),
1684 PINMUX_IPSR_DATA(IP15_11_9
, HSCK0
),
1685 PINMUX_IPSR_MSEL(IP15_11_9
, TS_SDEN0
, SEL_TSIF0_0
),
1686 PINMUX_IPSR_DATA(IP15_11_9
, DU2_DG4
),
1687 PINMUX_IPSR_DATA(IP15_11_9
, LCDOUT12
),
1688 PINMUX_IPSR_MSEL(IP15_11_9
, HCTS0_N_C
, SEL_HSCIF0_2
),
1689 PINMUX_IPSR_MSEL(IP15_13_12
, HRX0
, SEL_HSCIF0_0
),
1690 PINMUX_IPSR_DATA(IP15_13_12
, DU2_DB2
),
1691 PINMUX_IPSR_DATA(IP15_13_12
, LCDOUT18
),
1692 PINMUX_IPSR_MSEL(IP15_15_14
, HTX0
, SEL_HSCIF0_0
),
1693 PINMUX_IPSR_DATA(IP15_15_14
, DU2_DB3
),
1694 PINMUX_IPSR_DATA(IP15_15_14
, LCDOUT19
),
1695 PINMUX_IPSR_MSEL(IP15_17_16
, HCTS0_N
, SEL_HSCIF0_0
),
1696 PINMUX_IPSR_DATA(IP15_17_16
, SSI_SCK9
),
1697 PINMUX_IPSR_DATA(IP15_17_16
, DU2_DB4
),
1698 PINMUX_IPSR_DATA(IP15_17_16
, LCDOUT20
),
1699 PINMUX_IPSR_MSEL(IP15_19_18
, HRTS0_N
, SEL_HSCIF0_0
),
1700 PINMUX_IPSR_DATA(IP15_19_18
, SSI_WS9
),
1701 PINMUX_IPSR_DATA(IP15_19_18
, DU2_DB5
),
1702 PINMUX_IPSR_DATA(IP15_19_18
, LCDOUT21
),
1703 PINMUX_IPSR_MSEL(IP15_22_20
, MSIOF0_SCK
, SEL_SOF0_0
),
1704 PINMUX_IPSR_MSEL(IP15_22_20
, TS_SDAT0
, SEL_TSIF0_0
),
1705 PINMUX_IPSR_DATA(IP15_22_20
, ADICLK
),
1706 PINMUX_IPSR_DATA(IP15_22_20
, DU2_DB6
),
1707 PINMUX_IPSR_DATA(IP15_22_20
, LCDOUT22
),
1708 PINMUX_IPSR_DATA(IP15_25_23
, MSIOF0_SYNC
),
1709 PINMUX_IPSR_MSEL(IP15_25_23
, TS_SCK0
, SEL_TSIF0_0
),
1710 PINMUX_IPSR_DATA(IP15_25_23
, SSI_SCK2
),
1711 PINMUX_IPSR_DATA(IP15_25_23
, ADIDATA
),
1712 PINMUX_IPSR_DATA(IP15_25_23
, DU2_DB7
),
1713 PINMUX_IPSR_DATA(IP15_25_23
, LCDOUT23
),
1714 PINMUX_IPSR_MSEL(IP15_25_23
, HRX0_C
, SEL_SCIFA2_1
),
1715 PINMUX_IPSR_MSEL(IP15_27_26
, MSIOF0_SS1
, SEL_SOF0_0
),
1716 PINMUX_IPSR_DATA(IP15_27_26
, ADICHS0
),
1717 PINMUX_IPSR_DATA(IP15_27_26
, DU2_DG5
),
1718 PINMUX_IPSR_DATA(IP15_27_26
, LCDOUT13
),
1719 PINMUX_IPSR_MSEL(IP15_29_28
, MSIOF0_TXD
, SEL_SOF0_0
),
1720 PINMUX_IPSR_DATA(IP15_29_28
, ADICHS1
),
1721 PINMUX_IPSR_DATA(IP15_29_28
, DU2_DG6
),
1722 PINMUX_IPSR_DATA(IP15_29_28
, LCDOUT14
),
1724 PINMUX_IPSR_MSEL(IP16_2_0
, MSIOF0_SS2
, SEL_SOF0_0
),
1725 PINMUX_IPSR_DATA(IP16_2_0
, AUDIO_CLKOUT
),
1726 PINMUX_IPSR_DATA(IP16_2_0
, ADICHS2
),
1727 PINMUX_IPSR_DATA(IP16_2_0
, DU2_DISP
),
1728 PINMUX_IPSR_DATA(IP16_2_0
, QPOLA
),
1729 PINMUX_IPSR_MSEL(IP16_2_0
, HTX0_C
, SEL_HSCIF0_2
),
1730 PINMUX_IPSR_MSEL(IP16_2_0
, SCIFA2_TXD_B
, SEL_SCIFA2_1
),
1731 PINMUX_IPSR_MSEL(IP16_5_3
, MSIOF0_RXD
, SEL_SOF0_0
),
1732 PINMUX_IPSR_MSEL(IP16_5_3
, TS_SPSYNC0
, SEL_TSIF0_0
),
1733 PINMUX_IPSR_DATA(IP16_5_3
, SSI_WS2
),
1734 PINMUX_IPSR_DATA(IP16_5_3
, ADICS_SAMP
),
1735 PINMUX_IPSR_DATA(IP16_5_3
, DU2_CDE
),
1736 PINMUX_IPSR_DATA(IP16_5_3
, QPOLB
),
1737 PINMUX_IPSR_MSEL(IP16_5_3
, SCIFA2_RXD_B
, SEL_HSCIF0_2
),
1738 PINMUX_IPSR_DATA(IP16_6
, USB1_PWEN
),
1739 PINMUX_IPSR_DATA(IP16_6
, AUDIO_CLKOUT_D
),
1740 PINMUX_IPSR_DATA(IP16_7
, USB1_OVC
),
1741 PINMUX_IPSR_MSEL(IP16_7
, TCLK1_B
, SEL_TMU1_1
),
1743 PINMUX_DATA(IIC0_SCL_MARK
, FN_SEL_IIC0_0
),
1744 PINMUX_DATA(IIC0_SDA_MARK
, FN_SEL_IIC0_0
),
1745 PINMUX_DATA(I2C0_SCL_MARK
, FN_SEL_IIC0_1
),
1746 PINMUX_DATA(I2C0_SDA_MARK
, FN_SEL_IIC0_1
),
1748 PINMUX_DATA(IIC3_SCL_MARK
, FN_SEL_IICDVFS_0
),
1749 PINMUX_DATA(IIC3_SDA_MARK
, FN_SEL_IICDVFS_0
),
1750 PINMUX_DATA(I2C3_SCL_MARK
, FN_SEL_IICDVFS_1
),
1751 PINMUX_DATA(I2C3_SDA_MARK
, FN_SEL_IICDVFS_1
),
1754 /* R8A7790 has 6 banks with 32 GPIOs in each = 192 GPIOs */
1755 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1756 #define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200)
1757 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1759 static const struct sh_pfc_pin pinmux_pins
[] = {
1760 PINMUX_GPIO_GP_ALL(),
1762 /* Pins not associated with a GPIO port */
1763 SH_PFC_PIN_NAMED(ROW_GROUP_A('F'), 15, AF15
),
1764 SH_PFC_PIN_NAMED(ROW_GROUP_A('G'), 15, AG15
),
1765 SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15
),
1766 SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15
),
1769 /* - AUDIO CLOCK ------------------------------------------------------------ */
1770 static const unsigned int audio_clk_a_pins
[] = {
1774 static const unsigned int audio_clk_a_mux
[] = {
1777 static const unsigned int audio_clk_b_pins
[] = {
1781 static const unsigned int audio_clk_b_mux
[] = {
1784 static const unsigned int audio_clk_c_pins
[] = {
1788 static const unsigned int audio_clk_c_mux
[] = {
1791 static const unsigned int audio_clkout_pins
[] = {
1795 static const unsigned int audio_clkout_mux
[] = {
1798 static const unsigned int audio_clkout_b_pins
[] = {
1802 static const unsigned int audio_clkout_b_mux
[] = {
1803 AUDIO_CLKOUT_B_MARK
,
1805 static const unsigned int audio_clkout_c_pins
[] = {
1809 static const unsigned int audio_clkout_c_mux
[] = {
1810 AUDIO_CLKOUT_C_MARK
,
1812 static const unsigned int audio_clkout_d_pins
[] = {
1816 static const unsigned int audio_clkout_d_mux
[] = {
1817 AUDIO_CLKOUT_D_MARK
,
1819 /* - AVB -------------------------------------------------------------------- */
1820 static const unsigned int avb_link_pins
[] = {
1823 static const unsigned int avb_link_mux
[] = {
1826 static const unsigned int avb_magic_pins
[] = {
1829 static const unsigned int avb_magic_mux
[] = {
1832 static const unsigned int avb_phy_int_pins
[] = {
1835 static const unsigned int avb_phy_int_mux
[] = {
1838 static const unsigned int avb_mdio_pins
[] = {
1839 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1841 static const unsigned int avb_mdio_mux
[] = {
1842 AVB_MDC_MARK
, AVB_MDIO_MARK
,
1844 static const unsigned int avb_mii_pins
[] = {
1845 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1848 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1851 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1852 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 10),
1855 static const unsigned int avb_mii_mux
[] = {
1856 AVB_TXD0_MARK
, AVB_TXD1_MARK
, AVB_TXD2_MARK
,
1859 AVB_RXD0_MARK
, AVB_RXD1_MARK
, AVB_RXD2_MARK
,
1862 AVB_RX_ER_MARK
, AVB_RX_CLK_MARK
, AVB_RX_DV_MARK
,
1863 AVB_CRS_MARK
, AVB_TX_EN_MARK
, AVB_TX_CLK_MARK
,
1866 static const unsigned int avb_gmii_pins
[] = {
1867 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1868 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1869 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
1871 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1872 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
1873 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
1875 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1876 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 16),
1877 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
1880 static const unsigned int avb_gmii_mux
[] = {
1881 AVB_TXD0_MARK
, AVB_TXD1_MARK
, AVB_TXD2_MARK
,
1882 AVB_TXD3_MARK
, AVB_TXD4_MARK
, AVB_TXD5_MARK
,
1883 AVB_TXD6_MARK
, AVB_TXD7_MARK
,
1885 AVB_RXD0_MARK
, AVB_RXD1_MARK
, AVB_RXD2_MARK
,
1886 AVB_RXD3_MARK
, AVB_RXD4_MARK
, AVB_RXD5_MARK
,
1887 AVB_RXD6_MARK
, AVB_RXD7_MARK
,
1889 AVB_RX_ER_MARK
, AVB_RX_CLK_MARK
, AVB_RX_DV_MARK
,
1890 AVB_CRS_MARK
, AVB_GTX_CLK_MARK
, AVB_GTXREFCLK_MARK
,
1891 AVB_TX_EN_MARK
, AVB_TX_ER_MARK
, AVB_TX_CLK_MARK
,
1894 /* - DU RGB ----------------------------------------------------------------- */
1895 static const unsigned int du_rgb666_pins
[] = {
1896 /* R[7:2], G[7:2], B[7:2] */
1897 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1898 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1899 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
1900 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
1901 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
1902 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
1904 static const unsigned int du_rgb666_mux
[] = {
1905 DU2_DR7_MARK
, DU2_DR6_MARK
, DU2_DR5_MARK
, DU2_DR4_MARK
,
1906 DU2_DR3_MARK
, DU2_DR2_MARK
,
1907 DU2_DG7_MARK
, DU2_DG6_MARK
, DU2_DG5_MARK
, DU2_DG4_MARK
,
1908 DU2_DG3_MARK
, DU2_DG2_MARK
,
1909 DU2_DB7_MARK
, DU2_DB6_MARK
, DU2_DB5_MARK
, DU2_DB4_MARK
,
1910 DU2_DB3_MARK
, DU2_DB2_MARK
,
1912 static const unsigned int du_rgb888_pins
[] = {
1913 /* R[7:0], G[7:0], B[7:0] */
1914 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1915 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1916 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4),
1917 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7),
1918 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1),
1919 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12),
1920 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9),
1921 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
1923 static const unsigned int du_rgb888_mux
[] = {
1924 DU2_DR7_MARK
, DU2_DR6_MARK
, DU2_DR5_MARK
, DU2_DR4_MARK
,
1925 DU2_DR3_MARK
, DU2_DR2_MARK
, DU2_DR1_MARK
, DU2_DR0_MARK
,
1926 DU2_DG7_MARK
, DU2_DG6_MARK
, DU2_DG5_MARK
, DU2_DG4_MARK
,
1927 DU2_DG3_MARK
, DU2_DG2_MARK
, DU2_DG1_MARK
, DU2_DG0_MARK
,
1928 DU2_DB7_MARK
, DU2_DB6_MARK
, DU2_DB5_MARK
, DU2_DB4_MARK
,
1929 DU2_DB3_MARK
, DU2_DB2_MARK
, DU2_DB1_MARK
, DU2_DB0_MARK
,
1931 static const unsigned int du_clk_out_0_pins
[] = {
1935 static const unsigned int du_clk_out_0_mux
[] = {
1938 static const unsigned int du_clk_out_1_pins
[] = {
1942 static const unsigned int du_clk_out_1_mux
[] = {
1945 static const unsigned int du_sync_0_pins
[] = {
1946 /* VSYNC, HSYNC, DISP */
1947 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0),
1949 static const unsigned int du_sync_0_mux
[] = {
1950 DU2_EXVSYNC_DU2_VSYNC_MARK
, DU2_EXHSYNC_DU2_HSYNC_MARK
,
1951 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK
1953 static const unsigned int du_sync_1_pins
[] = {
1954 /* VSYNC, HSYNC, DISP */
1955 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16),
1957 static const unsigned int du_sync_1_mux
[] = {
1958 DU2_EXVSYNC_DU2_VSYNC_MARK
, DU2_EXHSYNC_DU2_HSYNC_MARK
,
1961 static const unsigned int du_cde_pins
[] = {
1965 static const unsigned int du_cde_mux
[] = {
1968 /* - DU0 -------------------------------------------------------------------- */
1969 static const unsigned int du0_clk_in_pins
[] = {
1973 static const unsigned int du0_clk_in_mux
[] = {
1976 /* - DU1 -------------------------------------------------------------------- */
1977 static const unsigned int du1_clk_in_pins
[] = {
1981 static const unsigned int du1_clk_in_mux
[] = {
1984 /* - DU2 -------------------------------------------------------------------- */
1985 static const unsigned int du2_clk_in_pins
[] = {
1989 static const unsigned int du2_clk_in_mux
[] = {
1992 /* - ETH -------------------------------------------------------------------- */
1993 static const unsigned int eth_link_pins
[] = {
1997 static const unsigned int eth_link_mux
[] = {
2000 static const unsigned int eth_magic_pins
[] = {
2004 static const unsigned int eth_magic_mux
[] = {
2007 static const unsigned int eth_mdio_pins
[] = {
2009 RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
2011 static const unsigned int eth_mdio_mux
[] = {
2012 ETH_MDC_MARK
, ETH_MDIO_MARK
,
2014 static const unsigned int eth_rmii_pins
[] = {
2015 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
2016 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
2017 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
2018 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
2020 static const unsigned int eth_rmii_mux
[] = {
2021 ETH_RXD0_MARK
, ETH_RXD1_MARK
, ETH_RX_ER_MARK
, ETH_CRS_DV_MARK
,
2022 ETH_TXD0_MARK
, ETH_TXD1_MARK
, ETH_TX_EN_MARK
, ETH_REF_CLK_MARK
,
2024 /* - HSCIF0 ----------------------------------------------------------------- */
2025 static const unsigned int hscif0_data_pins
[] = {
2027 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
2029 static const unsigned int hscif0_data_mux
[] = {
2030 HRX0_MARK
, HTX0_MARK
,
2032 static const unsigned int hscif0_clk_pins
[] = {
2036 static const unsigned int hscif0_clk_mux
[] = {
2039 static const unsigned int hscif0_ctrl_pins
[] = {
2041 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2043 static const unsigned int hscif0_ctrl_mux
[] = {
2044 HRTS0_N_MARK
, HCTS0_N_MARK
,
2046 static const unsigned int hscif0_data_b_pins
[] = {
2048 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12),
2050 static const unsigned int hscif0_data_b_mux
[] = {
2051 HRX0_B_MARK
, HTX0_B_MARK
,
2053 static const unsigned int hscif0_ctrl_b_pins
[] = {
2055 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28),
2057 static const unsigned int hscif0_ctrl_b_mux
[] = {
2058 HRTS0_N_B_MARK
, HCTS0_N_B_MARK
,
2060 static const unsigned int hscif0_data_c_pins
[] = {
2062 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
2064 static const unsigned int hscif0_data_c_mux
[] = {
2065 HRX0_C_MARK
, HTX0_C_MARK
,
2067 static const unsigned int hscif0_ctrl_c_pins
[] = {
2069 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7),
2071 static const unsigned int hscif0_ctrl_c_mux
[] = {
2072 HRTS0_N_C_MARK
, HCTS0_N_C_MARK
,
2074 static const unsigned int hscif0_data_d_pins
[] = {
2076 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2078 static const unsigned int hscif0_data_d_mux
[] = {
2079 HRX0_D_MARK
, HTX0_D_MARK
,
2081 static const unsigned int hscif0_ctrl_d_pins
[] = {
2083 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22),
2085 static const unsigned int hscif0_ctrl_d_mux
[] = {
2086 HRTS0_N_D_MARK
, HCTS0_N_D_MARK
,
2088 static const unsigned int hscif0_data_e_pins
[] = {
2090 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2092 static const unsigned int hscif0_data_e_mux
[] = {
2093 HRX0_E_MARK
, HTX0_E_MARK
,
2095 static const unsigned int hscif0_ctrl_e_pins
[] = {
2097 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
2099 static const unsigned int hscif0_ctrl_e_mux
[] = {
2100 HRTS0_N_E_MARK
, HCTS0_N_E_MARK
,
2102 static const unsigned int hscif0_data_f_pins
[] = {
2104 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25),
2106 static const unsigned int hscif0_data_f_mux
[] = {
2107 HRX0_F_MARK
, HTX0_F_MARK
,
2109 static const unsigned int hscif0_ctrl_f_pins
[] = {
2111 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24),
2113 static const unsigned int hscif0_ctrl_f_mux
[] = {
2114 HRTS0_N_F_MARK
, HCTS0_N_F_MARK
,
2116 /* - HSCIF1 ----------------------------------------------------------------- */
2117 static const unsigned int hscif1_data_pins
[] = {
2119 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2121 static const unsigned int hscif1_data_mux
[] = {
2122 HRX1_MARK
, HTX1_MARK
,
2124 static const unsigned int hscif1_clk_pins
[] = {
2128 static const unsigned int hscif1_clk_mux
[] = {
2131 static const unsigned int hscif1_ctrl_pins
[] = {
2133 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2135 static const unsigned int hscif1_ctrl_mux
[] = {
2136 HRTS1_N_MARK
, HCTS1_N_MARK
,
2138 static const unsigned int hscif1_data_b_pins
[] = {
2140 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18),
2142 static const unsigned int hscif1_data_b_mux
[] = {
2143 HRX1_B_MARK
, HTX1_B_MARK
,
2145 static const unsigned int hscif1_clk_b_pins
[] = {
2149 static const unsigned int hscif1_clk_b_mux
[] = {
2152 static const unsigned int hscif1_ctrl_b_pins
[] = {
2154 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2156 static const unsigned int hscif1_ctrl_b_mux
[] = {
2157 HRTS1_N_B_MARK
, HCTS1_N_B_MARK
,
2159 /* - I2C0 ------------------------------------------------------------------- */
2160 static const unsigned int i2c0_pins
[] = {
2162 PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
2164 static const unsigned int i2c0_mux
[] = {
2165 I2C0_SCL_MARK
, I2C0_SDA_MARK
,
2167 /* - I2C1 ------------------------------------------------------------------- */
2168 static const unsigned int i2c1_pins
[] = {
2170 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2172 static const unsigned int i2c1_mux
[] = {
2173 I2C1_SCL_MARK
, I2C1_SDA_MARK
,
2175 static const unsigned int i2c1_b_pins
[] = {
2177 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2179 static const unsigned int i2c1_b_mux
[] = {
2180 I2C1_SCL_B_MARK
, I2C1_SDA_B_MARK
,
2182 static const unsigned int i2c1_c_pins
[] = {
2184 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2186 static const unsigned int i2c1_c_mux
[] = {
2187 I2C1_SCL_C_MARK
, I2C1_SDA_C_MARK
,
2189 /* - I2C2 ------------------------------------------------------------------- */
2190 static const unsigned int i2c2_pins
[] = {
2192 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2194 static const unsigned int i2c2_mux
[] = {
2195 I2C2_SCL_MARK
, I2C2_SDA_MARK
,
2197 static const unsigned int i2c2_b_pins
[] = {
2199 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2201 static const unsigned int i2c2_b_mux
[] = {
2202 I2C2_SCL_B_MARK
, I2C2_SDA_B_MARK
,
2204 static const unsigned int i2c2_c_pins
[] = {
2206 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2208 static const unsigned int i2c2_c_mux
[] = {
2209 I2C2_SCL_C_MARK
, I2C2_SDA_C_MARK
,
2211 static const unsigned int i2c2_d_pins
[] = {
2213 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2215 static const unsigned int i2c2_d_mux
[] = {
2216 I2C2_SCL_D_MARK
, I2C2_SDA_D_MARK
,
2218 static const unsigned int i2c2_e_pins
[] = {
2220 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2222 static const unsigned int i2c2_e_mux
[] = {
2223 I2C2_SCL_E_MARK
, I2C2_SDA_E_MARK
,
2225 /* - I2C3 ------------------------------------------------------------------- */
2226 static const unsigned int i2c3_pins
[] = {
2228 PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
2230 static const unsigned int i2c3_mux
[] = {
2231 I2C3_SCL_MARK
, I2C3_SDA_MARK
,
2233 /* - IIC0 (I2C4) ------------------------------------------------------------ */
2234 static const unsigned int iic0_pins
[] = {
2236 PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
2238 static const unsigned int iic0_mux
[] = {
2239 IIC0_SCL_MARK
, IIC0_SDA_MARK
,
2241 /* - IIC1 (I2C5) ------------------------------------------------------------ */
2242 static const unsigned int iic1_pins
[] = {
2244 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2246 static const unsigned int iic1_mux
[] = {
2247 IIC1_SCL_MARK
, IIC1_SDA_MARK
,
2249 static const unsigned int iic1_b_pins
[] = {
2251 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2253 static const unsigned int iic1_b_mux
[] = {
2254 IIC1_SCL_B_MARK
, IIC1_SDA_B_MARK
,
2256 static const unsigned int iic1_c_pins
[] = {
2258 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2260 static const unsigned int iic1_c_mux
[] = {
2261 IIC1_SCL_C_MARK
, IIC1_SDA_C_MARK
,
2263 /* - IIC2 (I2C6) ------------------------------------------------------------ */
2264 static const unsigned int iic2_pins
[] = {
2266 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2268 static const unsigned int iic2_mux
[] = {
2269 IIC2_SCL_MARK
, IIC2_SDA_MARK
,
2271 static const unsigned int iic2_b_pins
[] = {
2273 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2275 static const unsigned int iic2_b_mux
[] = {
2276 IIC2_SCL_B_MARK
, IIC2_SDA_B_MARK
,
2278 static const unsigned int iic2_c_pins
[] = {
2280 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2282 static const unsigned int iic2_c_mux
[] = {
2283 IIC2_SCL_C_MARK
, IIC2_SDA_C_MARK
,
2285 static const unsigned int iic2_d_pins
[] = {
2287 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2289 static const unsigned int iic2_d_mux
[] = {
2290 IIC2_SCL_D_MARK
, IIC2_SDA_D_MARK
,
2292 static const unsigned int iic2_e_pins
[] = {
2294 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2296 static const unsigned int iic2_e_mux
[] = {
2297 IIC2_SCL_E_MARK
, IIC2_SDA_E_MARK
,
2299 /* - IIC3 (I2C7) ------------------------------------------------------------ */
2300 static const unsigned int iic3_pins
[] = {
2302 PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
2304 static const unsigned int iic3_mux
[] = {
2305 IIC3_SCL_MARK
, IIC3_SDA_MARK
,
2307 /* - INTC ------------------------------------------------------------------- */
2308 static const unsigned int intc_irq0_pins
[] = {
2312 static const unsigned int intc_irq0_mux
[] = {
2315 static const unsigned int intc_irq1_pins
[] = {
2319 static const unsigned int intc_irq1_mux
[] = {
2322 static const unsigned int intc_irq2_pins
[] = {
2326 static const unsigned int intc_irq2_mux
[] = {
2329 static const unsigned int intc_irq3_pins
[] = {
2333 static const unsigned int intc_irq3_mux
[] = {
2336 /* - MLB+ ------------------------------------------------------------------- */
2337 static const unsigned int mlb_3pin_pins
[] = {
2338 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2340 static const unsigned int mlb_3pin_mux
[] = {
2341 MLB_CLK_MARK
, MLB_SIG_MARK
, MLB_DAT_MARK
,
2343 /* - MMCIF0 ----------------------------------------------------------------- */
2344 static const unsigned int mmc0_data1_pins
[] = {
2348 static const unsigned int mmc0_data1_mux
[] = {
2351 static const unsigned int mmc0_data4_pins
[] = {
2353 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2354 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2356 static const unsigned int mmc0_data4_mux
[] = {
2357 MMC0_D0_MARK
, MMC0_D1_MARK
, MMC0_D2_MARK
, MMC0_D3_MARK
,
2359 static const unsigned int mmc0_data8_pins
[] = {
2361 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2362 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2363 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2364 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2366 static const unsigned int mmc0_data8_mux
[] = {
2367 MMC0_D0_MARK
, MMC0_D1_MARK
, MMC0_D2_MARK
, MMC0_D3_MARK
,
2368 MMC0_D4_MARK
, MMC0_D5_MARK
, MMC0_D6_MARK
, MMC0_D7_MARK
,
2370 static const unsigned int mmc0_ctrl_pins
[] = {
2372 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
2374 static const unsigned int mmc0_ctrl_mux
[] = {
2375 MMC0_CLK_MARK
, MMC0_CMD_MARK
,
2377 /* - MMCIF1 ----------------------------------------------------------------- */
2378 static const unsigned int mmc1_data1_pins
[] = {
2382 static const unsigned int mmc1_data1_mux
[] = {
2385 static const unsigned int mmc1_data4_pins
[] = {
2387 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2388 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2390 static const unsigned int mmc1_data4_mux
[] = {
2391 MMC1_D0_MARK
, MMC1_D1_MARK
, MMC1_D2_MARK
, MMC1_D3_MARK
,
2393 static const unsigned int mmc1_data8_pins
[] = {
2395 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2396 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2397 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2398 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2400 static const unsigned int mmc1_data8_mux
[] = {
2401 MMC1_D0_MARK
, MMC1_D1_MARK
, MMC1_D2_MARK
, MMC1_D3_MARK
,
2402 MMC1_D4_MARK
, MMC1_D5_MARK
, MMC1_D6_MARK
, MMC1_D7_MARK
,
2404 static const unsigned int mmc1_ctrl_pins
[] = {
2406 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
2408 static const unsigned int mmc1_ctrl_mux
[] = {
2409 MMC1_CLK_MARK
, MMC1_CMD_MARK
,
2411 /* - MSIOF0 ----------------------------------------------------------------- */
2412 static const unsigned int msiof0_clk_pins
[] = {
2416 static const unsigned int msiof0_clk_mux
[] = {
2419 static const unsigned int msiof0_sync_pins
[] = {
2423 static const unsigned int msiof0_sync_mux
[] = {
2426 static const unsigned int msiof0_ss1_pins
[] = {
2430 static const unsigned int msiof0_ss1_mux
[] = {
2433 static const unsigned int msiof0_ss2_pins
[] = {
2437 static const unsigned int msiof0_ss2_mux
[] = {
2440 static const unsigned int msiof0_rx_pins
[] = {
2444 static const unsigned int msiof0_rx_mux
[] = {
2447 static const unsigned int msiof0_tx_pins
[] = {
2451 static const unsigned int msiof0_tx_mux
[] = {
2455 static const unsigned int msiof0_clk_b_pins
[] = {
2459 static const unsigned int msiof0_clk_b_mux
[] = {
2462 static const unsigned int msiof0_ss1_b_pins
[] = {
2466 static const unsigned int msiof0_ss1_b_mux
[] = {
2469 static const unsigned int msiof0_ss2_b_pins
[] = {
2473 static const unsigned int msiof0_ss2_b_mux
[] = {
2476 static const unsigned int msiof0_rx_b_pins
[] = {
2480 static const unsigned int msiof0_rx_b_mux
[] = {
2483 static const unsigned int msiof0_tx_b_pins
[] = {
2487 static const unsigned int msiof0_tx_b_mux
[] = {
2490 /* - MSIOF1 ----------------------------------------------------------------- */
2491 static const unsigned int msiof1_clk_pins
[] = {
2495 static const unsigned int msiof1_clk_mux
[] = {
2498 static const unsigned int msiof1_sync_pins
[] = {
2502 static const unsigned int msiof1_sync_mux
[] = {
2505 static const unsigned int msiof1_ss1_pins
[] = {
2509 static const unsigned int msiof1_ss1_mux
[] = {
2512 static const unsigned int msiof1_ss2_pins
[] = {
2516 static const unsigned int msiof1_ss2_mux
[] = {
2519 static const unsigned int msiof1_rx_pins
[] = {
2523 static const unsigned int msiof1_rx_mux
[] = {
2526 static const unsigned int msiof1_tx_pins
[] = {
2530 static const unsigned int msiof1_tx_mux
[] = {
2534 static const unsigned int msiof1_clk_b_pins
[] = {
2538 static const unsigned int msiof1_clk_b_mux
[] = {
2541 static const unsigned int msiof1_ss1_b_pins
[] = {
2545 static const unsigned int msiof1_ss1_b_mux
[] = {
2548 static const unsigned int msiof1_ss2_b_pins
[] = {
2552 static const unsigned int msiof1_ss2_b_mux
[] = {
2555 static const unsigned int msiof1_rx_b_pins
[] = {
2559 static const unsigned int msiof1_rx_b_mux
[] = {
2562 static const unsigned int msiof1_tx_b_pins
[] = {
2566 static const unsigned int msiof1_tx_b_mux
[] = {
2569 /* - MSIOF2 ----------------------------------------------------------------- */
2570 static const unsigned int msiof2_clk_pins
[] = {
2574 static const unsigned int msiof2_clk_mux
[] = {
2577 static const unsigned int msiof2_sync_pins
[] = {
2581 static const unsigned int msiof2_sync_mux
[] = {
2584 static const unsigned int msiof2_ss1_pins
[] = {
2588 static const unsigned int msiof2_ss1_mux
[] = {
2591 static const unsigned int msiof2_ss2_pins
[] = {
2595 static const unsigned int msiof2_ss2_mux
[] = {
2598 static const unsigned int msiof2_rx_pins
[] = {
2602 static const unsigned int msiof2_rx_mux
[] = {
2605 static const unsigned int msiof2_tx_pins
[] = {
2609 static const unsigned int msiof2_tx_mux
[] = {
2612 /* - MSIOF3 ----------------------------------------------------------------- */
2613 static const unsigned int msiof3_clk_pins
[] = {
2617 static const unsigned int msiof3_clk_mux
[] = {
2620 static const unsigned int msiof3_sync_pins
[] = {
2624 static const unsigned int msiof3_sync_mux
[] = {
2627 static const unsigned int msiof3_ss1_pins
[] = {
2631 static const unsigned int msiof3_ss1_mux
[] = {
2634 static const unsigned int msiof3_ss2_pins
[] = {
2638 static const unsigned int msiof3_ss2_mux
[] = {
2641 static const unsigned int msiof3_rx_pins
[] = {
2645 static const unsigned int msiof3_rx_mux
[] = {
2648 static const unsigned int msiof3_tx_pins
[] = {
2652 static const unsigned int msiof3_tx_mux
[] = {
2656 static const unsigned int msiof3_clk_b_pins
[] = {
2660 static const unsigned int msiof3_clk_b_mux
[] = {
2663 static const unsigned int msiof3_sync_b_pins
[] = {
2667 static const unsigned int msiof3_sync_b_mux
[] = {
2670 static const unsigned int msiof3_rx_b_pins
[] = {
2674 static const unsigned int msiof3_rx_b_mux
[] = {
2677 static const unsigned int msiof3_tx_b_pins
[] = {
2681 static const unsigned int msiof3_tx_b_mux
[] = {
2684 /* - PWM -------------------------------------------------------------------- */
2685 static const unsigned int pwm0_pins
[] = {
2688 static const unsigned int pwm0_mux
[] = {
2691 static const unsigned int pwm0_b_pins
[] = {
2694 static const unsigned int pwm0_b_mux
[] = {
2697 static const unsigned int pwm1_pins
[] = {
2700 static const unsigned int pwm1_mux
[] = {
2703 static const unsigned int pwm1_b_pins
[] = {
2706 static const unsigned int pwm1_b_mux
[] = {
2709 static const unsigned int pwm2_pins
[] = {
2712 static const unsigned int pwm2_mux
[] = {
2715 static const unsigned int pwm3_pins
[] = {
2718 static const unsigned int pwm3_mux
[] = {
2721 static const unsigned int pwm4_pins
[] = {
2724 static const unsigned int pwm4_mux
[] = {
2727 static const unsigned int pwm5_pins
[] = {
2730 static const unsigned int pwm5_mux
[] = {
2733 static const unsigned int pwm6_pins
[] = {
2736 static const unsigned int pwm6_mux
[] = {
2739 /* - QSPI ------------------------------------------------------------------- */
2740 static const unsigned int qspi_ctrl_pins
[] = {
2742 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2744 static const unsigned int qspi_ctrl_mux
[] = {
2745 SPCLK_MARK
, SSL_MARK
,
2747 static const unsigned int qspi_data2_pins
[] = {
2748 /* MOSI_IO0, MISO_IO1 */
2749 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2751 static const unsigned int qspi_data2_mux
[] = {
2752 MOSI_IO0_MARK
, MISO_IO1_MARK
,
2754 static const unsigned int qspi_data4_pins
[] = {
2755 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2756 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2759 static const unsigned int qspi_data4_mux
[] = {
2760 MOSI_IO0_MARK
, MISO_IO1_MARK
, IO2_MARK
, IO3_MARK
,
2762 /* - SCIF0 ------------------------------------------------------------------ */
2763 static const unsigned int scif0_data_pins
[] = {
2765 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2767 static const unsigned int scif0_data_mux
[] = {
2770 static const unsigned int scif0_clk_pins
[] = {
2774 static const unsigned int scif0_clk_mux
[] = {
2777 static const unsigned int scif0_ctrl_pins
[] = {
2779 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2781 static const unsigned int scif0_ctrl_mux
[] = {
2782 RTS0_N_MARK
, CTS0_N_MARK
,
2784 static const unsigned int scif0_data_b_pins
[] = {
2786 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2788 static const unsigned int scif0_data_b_mux
[] = {
2789 RX0_B_MARK
, TX0_B_MARK
,
2791 /* - SCIF1 ------------------------------------------------------------------ */
2792 static const unsigned int scif1_data_pins
[] = {
2794 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2796 static const unsigned int scif1_data_mux
[] = {
2799 static const unsigned int scif1_clk_pins
[] = {
2803 static const unsigned int scif1_clk_mux
[] = {
2806 static const unsigned int scif1_ctrl_pins
[] = {
2808 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2810 static const unsigned int scif1_ctrl_mux
[] = {
2811 RTS1_N_MARK
, CTS1_N_MARK
,
2813 static const unsigned int scif1_data_b_pins
[] = {
2815 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2817 static const unsigned int scif1_data_b_mux
[] = {
2818 RX1_B_MARK
, TX1_B_MARK
,
2820 static const unsigned int scif1_data_c_pins
[] = {
2822 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2824 static const unsigned int scif1_data_c_mux
[] = {
2825 RX1_C_MARK
, TX1_C_MARK
,
2827 static const unsigned int scif1_data_d_pins
[] = {
2829 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2831 static const unsigned int scif1_data_d_mux
[] = {
2832 RX1_D_MARK
, TX1_D_MARK
,
2834 static const unsigned int scif1_clk_d_pins
[] = {
2838 static const unsigned int scif1_clk_d_mux
[] = {
2841 static const unsigned int scif1_data_e_pins
[] = {
2843 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2845 static const unsigned int scif1_data_e_mux
[] = {
2846 RX1_E_MARK
, TX1_E_MARK
,
2848 static const unsigned int scif1_clk_e_pins
[] = {
2852 static const unsigned int scif1_clk_e_mux
[] = {
2855 /* - SCIF2 ------------------------------------------------------------------ */
2856 static const unsigned int scif2_data_pins
[] = {
2858 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
2860 static const unsigned int scif2_data_mux
[] = {
2863 static const unsigned int scif2_clk_pins
[] = {
2867 static const unsigned int scif2_clk_mux
[] = {
2870 static const unsigned int scif2_data_b_pins
[] = {
2872 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2874 static const unsigned int scif2_data_b_mux
[] = {
2875 RX2_B_MARK
, TX2_B_MARK
,
2877 /* - SCIFA0 ----------------------------------------------------------------- */
2878 static const unsigned int scifa0_data_pins
[] = {
2880 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2882 static const unsigned int scifa0_data_mux
[] = {
2883 SCIFA0_RXD_MARK
, SCIFA0_TXD_MARK
,
2885 static const unsigned int scifa0_clk_pins
[] = {
2889 static const unsigned int scifa0_clk_mux
[] = {
2892 static const unsigned int scifa0_ctrl_pins
[] = {
2894 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2896 static const unsigned int scifa0_ctrl_mux
[] = {
2897 SCIFA0_RTS_N_MARK
, SCIFA0_CTS_N_MARK
,
2899 static const unsigned int scifa0_data_b_pins
[] = {
2901 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
2903 static const unsigned int scifa0_data_b_mux
[] = {
2904 SCIFA0_RXD_B_MARK
, SCIFA0_TXD_B_MARK
2906 static const unsigned int scifa0_clk_b_pins
[] = {
2910 static const unsigned int scifa0_clk_b_mux
[] = {
2913 static const unsigned int scifa0_ctrl_b_pins
[] = {
2915 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
2917 static const unsigned int scifa0_ctrl_b_mux
[] = {
2918 SCIFA0_RTS_N_B_MARK
, SCIFA0_CTS_N_B_MARK
,
2920 /* - SCIFA1 ----------------------------------------------------------------- */
2921 static const unsigned int scifa1_data_pins
[] = {
2923 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2925 static const unsigned int scifa1_data_mux
[] = {
2926 SCIFA1_RXD_MARK
, SCIFA1_TXD_MARK
,
2928 static const unsigned int scifa1_clk_pins
[] = {
2932 static const unsigned int scifa1_clk_mux
[] = {
2935 static const unsigned int scifa1_ctrl_pins
[] = {
2937 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2939 static const unsigned int scifa1_ctrl_mux
[] = {
2940 SCIFA1_RTS_N_MARK
, SCIFA1_CTS_N_MARK
,
2942 static const unsigned int scifa1_data_b_pins
[] = {
2944 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
2946 static const unsigned int scifa1_data_b_mux
[] = {
2947 SCIFA1_RXD_B_MARK
, SCIFA1_TXD_B_MARK
,
2949 static const unsigned int scifa1_clk_b_pins
[] = {
2953 static const unsigned int scifa1_clk_b_mux
[] = {
2956 static const unsigned int scifa1_ctrl_b_pins
[] = {
2958 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
2960 static const unsigned int scifa1_ctrl_b_mux
[] = {
2961 SCIFA1_RTS_N_B_MARK
, SCIFA1_CTS_N_B_MARK
,
2963 static const unsigned int scifa1_data_c_pins
[] = {
2965 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2967 static const unsigned int scifa1_data_c_mux
[] = {
2968 SCIFA1_RXD_C_MARK
, SCIFA1_TXD_C_MARK
,
2970 static const unsigned int scifa1_clk_c_pins
[] = {
2974 static const unsigned int scifa1_clk_c_mux
[] = {
2977 static const unsigned int scifa1_ctrl_c_pins
[] = {
2979 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
2981 static const unsigned int scifa1_ctrl_c_mux
[] = {
2982 SCIFA1_RTS_N_C_MARK
, SCIFA1_CTS_N_C_MARK
,
2984 static const unsigned int scifa1_data_d_pins
[] = {
2986 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2988 static const unsigned int scifa1_data_d_mux
[] = {
2989 SCIFA1_RXD_D_MARK
, SCIFA1_TXD_D_MARK
,
2991 static const unsigned int scifa1_clk_d_pins
[] = {
2995 static const unsigned int scifa1_clk_d_mux
[] = {
2998 static const unsigned int scifa1_ctrl_d_pins
[] = {
3000 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3002 static const unsigned int scifa1_ctrl_d_mux
[] = {
3003 SCIFA1_RTS_N_D_MARK
, SCIFA1_CTS_N_D_MARK
,
3005 /* - SCIFA2 ----------------------------------------------------------------- */
3006 static const unsigned int scifa2_data_pins
[] = {
3008 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3010 static const unsigned int scifa2_data_mux
[] = {
3011 SCIFA2_RXD_MARK
, SCIFA2_TXD_MARK
,
3013 static const unsigned int scifa2_clk_pins
[] = {
3017 static const unsigned int scifa2_clk_mux
[] = {
3020 static const unsigned int scifa2_ctrl_pins
[] = {
3022 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
3024 static const unsigned int scifa2_ctrl_mux
[] = {
3025 SCIFA2_RTS_N_MARK
, SCIFA2_CTS_N_MARK
,
3027 static const unsigned int scifa2_data_b_pins
[] = {
3029 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
3031 static const unsigned int scifa2_data_b_mux
[] = {
3032 SCIFA2_RXD_B_MARK
, SCIFA2_TXD_B_MARK
,
3034 static const unsigned int scifa2_data_c_pins
[] = {
3036 RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
3038 static const unsigned int scifa2_data_c_mux
[] = {
3039 SCIFA2_RXD_C_MARK
, SCIFA2_TXD_C_MARK
,
3041 static const unsigned int scifa2_clk_c_pins
[] = {
3045 static const unsigned int scifa2_clk_c_mux
[] = {
3048 /* - SCIFB0 ----------------------------------------------------------------- */
3049 static const unsigned int scifb0_data_pins
[] = {
3051 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3053 static const unsigned int scifb0_data_mux
[] = {
3054 SCIFB0_RXD_MARK
, SCIFB0_TXD_MARK
,
3056 static const unsigned int scifb0_clk_pins
[] = {
3060 static const unsigned int scifb0_clk_mux
[] = {
3063 static const unsigned int scifb0_ctrl_pins
[] = {
3065 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
3067 static const unsigned int scifb0_ctrl_mux
[] = {
3068 SCIFB0_RTS_N_MARK
, SCIFB0_CTS_N_MARK
,
3070 static const unsigned int scifb0_data_b_pins
[] = {
3072 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3074 static const unsigned int scifb0_data_b_mux
[] = {
3075 SCIFB0_RXD_B_MARK
, SCIFB0_TXD_B_MARK
,
3077 static const unsigned int scifb0_clk_b_pins
[] = {
3081 static const unsigned int scifb0_clk_b_mux
[] = {
3084 static const unsigned int scifb0_ctrl_b_pins
[] = {
3086 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
3088 static const unsigned int scifb0_ctrl_b_mux
[] = {
3089 SCIFB0_RTS_N_B_MARK
, SCIFB0_CTS_N_B_MARK
,
3091 static const unsigned int scifb0_data_c_pins
[] = {
3093 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3095 static const unsigned int scifb0_data_c_mux
[] = {
3096 SCIFB0_RXD_C_MARK
, SCIFB0_TXD_C_MARK
,
3098 /* - SCIFB1 ----------------------------------------------------------------- */
3099 static const unsigned int scifb1_data_pins
[] = {
3101 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3103 static const unsigned int scifb1_data_mux
[] = {
3104 SCIFB1_RXD_MARK
, SCIFB1_TXD_MARK
,
3106 static const unsigned int scifb1_clk_pins
[] = {
3110 static const unsigned int scifb1_clk_mux
[] = {
3113 static const unsigned int scifb1_ctrl_pins
[] = {
3115 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
3117 static const unsigned int scifb1_ctrl_mux
[] = {
3118 SCIFB1_RTS_N_MARK
, SCIFB1_CTS_N_MARK
,
3120 static const unsigned int scifb1_data_b_pins
[] = {
3122 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3124 static const unsigned int scifb1_data_b_mux
[] = {
3125 SCIFB1_RXD_B_MARK
, SCIFB1_TXD_B_MARK
,
3127 static const unsigned int scifb1_clk_b_pins
[] = {
3131 static const unsigned int scifb1_clk_b_mux
[] = {
3134 static const unsigned int scifb1_ctrl_b_pins
[] = {
3136 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
3138 static const unsigned int scifb1_ctrl_b_mux
[] = {
3139 SCIFB1_RTS_N_B_MARK
, SCIFB1_CTS_N_B_MARK
,
3141 static const unsigned int scifb1_data_c_pins
[] = {
3143 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3145 static const unsigned int scifb1_data_c_mux
[] = {
3146 SCIFB1_RXD_C_MARK
, SCIFB1_TXD_C_MARK
,
3148 static const unsigned int scifb1_data_d_pins
[] = {
3150 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
3152 static const unsigned int scifb1_data_d_mux
[] = {
3153 SCIFB1_RXD_D_MARK
, SCIFB1_TXD_D_MARK
,
3155 static const unsigned int scifb1_data_e_pins
[] = {
3157 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
3159 static const unsigned int scifb1_data_e_mux
[] = {
3160 SCIFB1_RXD_E_MARK
, SCIFB1_TXD_E_MARK
,
3162 static const unsigned int scifb1_clk_e_pins
[] = {
3166 static const unsigned int scifb1_clk_e_mux
[] = {
3169 static const unsigned int scifb1_data_f_pins
[] = {
3171 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3173 static const unsigned int scifb1_data_f_mux
[] = {
3174 SCIFB1_RXD_F_MARK
, SCIFB1_TXD_F_MARK
,
3176 static const unsigned int scifb1_data_g_pins
[] = {
3178 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
3180 static const unsigned int scifb1_data_g_mux
[] = {
3181 SCIFB1_RXD_G_MARK
, SCIFB1_TXD_G_MARK
,
3183 static const unsigned int scifb1_clk_g_pins
[] = {
3187 static const unsigned int scifb1_clk_g_mux
[] = {
3190 /* - SCIFB2 ----------------------------------------------------------------- */
3191 static const unsigned int scifb2_data_pins
[] = {
3193 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
3195 static const unsigned int scifb2_data_mux
[] = {
3196 SCIFB2_RXD_MARK
, SCIFB2_TXD_MARK
,
3198 static const unsigned int scifb2_clk_pins
[] = {
3202 static const unsigned int scifb2_clk_mux
[] = {
3205 static const unsigned int scifb2_ctrl_pins
[] = {
3207 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
3209 static const unsigned int scifb2_ctrl_mux
[] = {
3210 SCIFB2_RTS_N_MARK
, SCIFB2_CTS_N_MARK
,
3212 static const unsigned int scifb2_data_b_pins
[] = {
3214 RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
3216 static const unsigned int scifb2_data_b_mux
[] = {
3217 SCIFB2_RXD_B_MARK
, SCIFB2_TXD_B_MARK
,
3219 static const unsigned int scifb2_clk_b_pins
[] = {
3223 static const unsigned int scifb2_clk_b_mux
[] = {
3226 static const unsigned int scifb2_ctrl_b_pins
[] = {
3228 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
3230 static const unsigned int scifb2_ctrl_b_mux
[] = {
3231 SCIFB2_RTS_N_B_MARK
, SCIFB2_CTS_N_B_MARK
,
3233 static const unsigned int scifb2_data_c_pins
[] = {
3235 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3237 static const unsigned int scifb2_data_c_mux
[] = {
3238 SCIFB2_RXD_C_MARK
, SCIFB2_TXD_C_MARK
,
3240 /* - SDHI0 ------------------------------------------------------------------ */
3241 static const unsigned int sdhi0_data1_pins
[] = {
3245 static const unsigned int sdhi0_data1_mux
[] = {
3248 static const unsigned int sdhi0_data4_pins
[] = {
3250 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3252 static const unsigned int sdhi0_data4_mux
[] = {
3253 SD0_DAT0_MARK
, SD0_DAT1_MARK
, SD0_DAT2_MARK
, SD0_DAT3_MARK
,
3255 static const unsigned int sdhi0_ctrl_pins
[] = {
3257 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3259 static const unsigned int sdhi0_ctrl_mux
[] = {
3260 SD0_CLK_MARK
, SD0_CMD_MARK
,
3262 static const unsigned int sdhi0_cd_pins
[] = {
3266 static const unsigned int sdhi0_cd_mux
[] = {
3269 static const unsigned int sdhi0_wp_pins
[] = {
3273 static const unsigned int sdhi0_wp_mux
[] = {
3276 /* - SDHI1 ------------------------------------------------------------------ */
3277 static const unsigned int sdhi1_data1_pins
[] = {
3281 static const unsigned int sdhi1_data1_mux
[] = {
3284 static const unsigned int sdhi1_data4_pins
[] = {
3286 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3288 static const unsigned int sdhi1_data4_mux
[] = {
3289 SD1_DAT0_MARK
, SD1_DAT1_MARK
, SD1_DAT2_MARK
, SD1_DAT3_MARK
,
3291 static const unsigned int sdhi1_ctrl_pins
[] = {
3293 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3295 static const unsigned int sdhi1_ctrl_mux
[] = {
3296 SD1_CLK_MARK
, SD1_CMD_MARK
,
3298 static const unsigned int sdhi1_cd_pins
[] = {
3302 static const unsigned int sdhi1_cd_mux
[] = {
3305 static const unsigned int sdhi1_wp_pins
[] = {
3309 static const unsigned int sdhi1_wp_mux
[] = {
3312 /* - SDHI2 ------------------------------------------------------------------ */
3313 static const unsigned int sdhi2_data1_pins
[] = {
3317 static const unsigned int sdhi2_data1_mux
[] = {
3320 static const unsigned int sdhi2_data4_pins
[] = {
3322 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
3324 static const unsigned int sdhi2_data4_mux
[] = {
3325 SD2_DAT0_MARK
, SD2_DAT1_MARK
, SD2_DAT2_MARK
, SD2_DAT3_MARK
,
3327 static const unsigned int sdhi2_ctrl_pins
[] = {
3329 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
3331 static const unsigned int sdhi2_ctrl_mux
[] = {
3332 SD2_CLK_MARK
, SD2_CMD_MARK
,
3334 static const unsigned int sdhi2_cd_pins
[] = {
3338 static const unsigned int sdhi2_cd_mux
[] = {
3341 static const unsigned int sdhi2_wp_pins
[] = {
3345 static const unsigned int sdhi2_wp_mux
[] = {
3348 /* - SDHI3 ------------------------------------------------------------------ */
3349 static const unsigned int sdhi3_data1_pins
[] = {
3353 static const unsigned int sdhi3_data1_mux
[] = {
3356 static const unsigned int sdhi3_data4_pins
[] = {
3358 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
3360 static const unsigned int sdhi3_data4_mux
[] = {
3361 SD3_DAT0_MARK
, SD3_DAT1_MARK
, SD3_DAT2_MARK
, SD3_DAT3_MARK
,
3363 static const unsigned int sdhi3_ctrl_pins
[] = {
3365 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
3367 static const unsigned int sdhi3_ctrl_mux
[] = {
3368 SD3_CLK_MARK
, SD3_CMD_MARK
,
3370 static const unsigned int sdhi3_cd_pins
[] = {
3374 static const unsigned int sdhi3_cd_mux
[] = {
3377 static const unsigned int sdhi3_wp_pins
[] = {
3381 static const unsigned int sdhi3_wp_mux
[] = {
3384 /* - SSI -------------------------------------------------------------------- */
3385 static const unsigned int ssi0_data_pins
[] = {
3389 static const unsigned int ssi0_data_mux
[] = {
3392 static const unsigned int ssi0129_ctrl_pins
[] = {
3394 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4),
3396 static const unsigned int ssi0129_ctrl_mux
[] = {
3397 SSI_SCK0129_MARK
, SSI_WS0129_MARK
,
3399 static const unsigned int ssi1_data_pins
[] = {
3403 static const unsigned int ssi1_data_mux
[] = {
3406 static const unsigned int ssi1_ctrl_pins
[] = {
3408 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24),
3410 static const unsigned int ssi1_ctrl_mux
[] = {
3411 SSI_SCK1_MARK
, SSI_WS1_MARK
,
3413 static const unsigned int ssi2_data_pins
[] = {
3417 static const unsigned int ssi2_data_mux
[] = {
3420 static const unsigned int ssi2_ctrl_pins
[] = {
3422 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17),
3424 static const unsigned int ssi2_ctrl_mux
[] = {
3425 SSI_SCK2_MARK
, SSI_WS2_MARK
,
3427 static const unsigned int ssi3_data_pins
[] = {
3431 static const unsigned int ssi3_data_mux
[] = {
3434 static const unsigned int ssi34_ctrl_pins
[] = {
3436 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
3438 static const unsigned int ssi34_ctrl_mux
[] = {
3439 SSI_SCK34_MARK
, SSI_WS34_MARK
,
3441 static const unsigned int ssi4_data_pins
[] = {
3445 static const unsigned int ssi4_data_mux
[] = {
3448 static const unsigned int ssi4_ctrl_pins
[] = {
3450 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3452 static const unsigned int ssi4_ctrl_mux
[] = {
3453 SSI_SCK4_MARK
, SSI_WS4_MARK
,
3455 static const unsigned int ssi5_pins
[] = {
3456 /* SDATA5, SCK, WS */
3457 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
3459 static const unsigned int ssi5_mux
[] = {
3460 SSI_SDATA5_MARK
, SSI_SCK5_MARK
, SSI_WS5_MARK
,
3462 static const unsigned int ssi5_b_pins
[] = {
3463 /* SDATA5, SCK, WS */
3464 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3466 static const unsigned int ssi5_b_mux
[] = {
3467 SSI_SDATA5_B_MARK
, SSI_SCK5_B_MARK
, SSI_WS5_B_MARK
3469 static const unsigned int ssi5_c_pins
[] = {
3470 /* SDATA5, SCK, WS */
3471 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3473 static const unsigned int ssi5_c_mux
[] = {
3474 SSI_SDATA5_C_MARK
, SSI_SCK5_C_MARK
, SSI_WS5_C_MARK
,
3476 static const unsigned int ssi6_pins
[] = {
3477 /* SDATA6, SCK, WS */
3478 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3480 static const unsigned int ssi6_mux
[] = {
3481 SSI_SDATA6_MARK
, SSI_SCK6_MARK
, SSI_WS6_MARK
,
3483 static const unsigned int ssi6_b_pins
[] = {
3484 /* SDATA6, SCK, WS */
3485 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27),
3487 static const unsigned int ssi6_b_mux
[] = {
3488 SSI_SDATA6_B_MARK
, SSI_SCK6_B_MARK
, SSI_WS6_B_MARK
,
3490 static const unsigned int ssi7_data_pins
[] = {
3494 static const unsigned int ssi7_data_mux
[] = {
3497 static const unsigned int ssi7_b_data_pins
[] = {
3501 static const unsigned int ssi7_b_data_mux
[] = {
3504 static const unsigned int ssi7_c_data_pins
[] = {
3508 static const unsigned int ssi7_c_data_mux
[] = {
3511 static const unsigned int ssi78_ctrl_pins
[] = {
3513 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3515 static const unsigned int ssi78_ctrl_mux
[] = {
3516 SSI_SCK78_MARK
, SSI_WS78_MARK
,
3518 static const unsigned int ssi78_b_ctrl_pins
[] = {
3520 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24),
3522 static const unsigned int ssi78_b_ctrl_mux
[] = {
3523 SSI_SCK78_B_MARK
, SSI_WS78_B_MARK
,
3525 static const unsigned int ssi78_c_ctrl_pins
[] = {
3527 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
3529 static const unsigned int ssi78_c_ctrl_mux
[] = {
3530 SSI_SCK78_C_MARK
, SSI_WS78_C_MARK
,
3532 static const unsigned int ssi8_data_pins
[] = {
3536 static const unsigned int ssi8_data_mux
[] = {
3539 static const unsigned int ssi8_b_data_pins
[] = {
3543 static const unsigned int ssi8_b_data_mux
[] = {
3546 static const unsigned int ssi8_c_data_pins
[] = {
3550 static const unsigned int ssi8_c_data_mux
[] = {
3553 static const unsigned int ssi9_data_pins
[] = {
3557 static const unsigned int ssi9_data_mux
[] = {
3560 static const unsigned int ssi9_ctrl_pins
[] = {
3562 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
3564 static const unsigned int ssi9_ctrl_mux
[] = {
3565 SSI_SCK9_MARK
, SSI_WS9_MARK
,
3567 /* - TPU0 ------------------------------------------------------------------- */
3568 static const unsigned int tpu0_to0_pins
[] = {
3572 static const unsigned int tpu0_to0_mux
[] = {
3575 static const unsigned int tpu0_to1_pins
[] = {
3579 static const unsigned int tpu0_to1_mux
[] = {
3582 static const unsigned int tpu0_to2_pins
[] = {
3586 static const unsigned int tpu0_to2_mux
[] = {
3589 static const unsigned int tpu0_to3_pins
[] = {
3593 static const unsigned int tpu0_to3_mux
[] = {
3596 /* - USB0 ------------------------------------------------------------------- */
3597 static const unsigned int usb0_pins
[] = {
3598 /* PWEN, OVC/VBUS */
3599 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
3601 static const unsigned int usb0_mux
[] = {
3602 USB0_PWEN_MARK
, USB0_OVC_VBUS_MARK
,
3604 static const unsigned int usb0_ovc_vbus_pins
[] = {
3608 static const unsigned int usb0_ovc_vbus_mux
[] = {
3611 /* - USB1 ------------------------------------------------------------------- */
3612 static const unsigned int usb1_pins
[] = {
3614 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
3616 static const unsigned int usb1_mux
[] = {
3617 USB1_PWEN_MARK
, USB1_OVC_MARK
,
3619 /* - USB2 ------------------------------------------------------------------- */
3620 static const unsigned int usb2_pins
[] = {
3622 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
3624 static const unsigned int usb2_mux
[] = {
3625 USB2_PWEN_MARK
, USB2_OVC_MARK
,
3627 /* - VIN0 ------------------------------------------------------------------- */
3628 static const union vin_data vin0_data_pins
= {
3631 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
3632 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3633 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3634 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3636 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3637 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3638 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3639 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3641 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3642 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3643 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3644 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3647 static const union vin_data vin0_data_mux
= {
3650 VI0_DATA0_VI0_B0_MARK
, VI0_DATA1_VI0_B1_MARK
,
3651 VI0_DATA2_VI0_B2_MARK
, VI0_DATA3_VI0_B3_MARK
,
3652 VI0_DATA4_VI0_B4_MARK
, VI0_DATA5_VI0_B5_MARK
,
3653 VI0_DATA6_VI0_B6_MARK
, VI0_DATA7_VI0_B7_MARK
,
3655 VI0_G0_MARK
, VI0_G1_MARK
,
3656 VI0_G2_MARK
, VI0_G3_MARK
,
3657 VI0_G4_MARK
, VI0_G5_MARK
,
3658 VI0_G6_MARK
, VI0_G7_MARK
,
3660 VI0_R0_MARK
, VI0_R1_MARK
,
3661 VI0_R2_MARK
, VI0_R3_MARK
,
3662 VI0_R4_MARK
, VI0_R5_MARK
,
3663 VI0_R6_MARK
, VI0_R7_MARK
,
3666 static const unsigned int vin0_data18_pins
[] = {
3668 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3669 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3670 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3672 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3673 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3674 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3676 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3677 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3678 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3680 static const unsigned int vin0_data18_mux
[] = {
3682 VI0_DATA2_VI0_B2_MARK
, VI0_DATA3_VI0_B3_MARK
,
3683 VI0_DATA4_VI0_B4_MARK
, VI0_DATA5_VI0_B5_MARK
,
3684 VI0_DATA6_VI0_B6_MARK
, VI0_DATA7_VI0_B7_MARK
,
3686 VI0_G2_MARK
, VI0_G3_MARK
,
3687 VI0_G4_MARK
, VI0_G5_MARK
,
3688 VI0_G6_MARK
, VI0_G7_MARK
,
3690 VI0_R2_MARK
, VI0_R3_MARK
,
3691 VI0_R4_MARK
, VI0_R5_MARK
,
3692 VI0_R6_MARK
, VI0_R7_MARK
,
3694 static const unsigned int vin0_sync_pins
[] = {
3695 RCAR_GP_PIN(0, 12), /* HSYNC */
3696 RCAR_GP_PIN(0, 13), /* VSYNC */
3698 static const unsigned int vin0_sync_mux
[] = {
3702 static const unsigned int vin0_field_pins
[] = {
3705 static const unsigned int vin0_field_mux
[] = {
3708 static const unsigned int vin0_clkenb_pins
[] = {
3711 static const unsigned int vin0_clkenb_mux
[] = {
3714 static const unsigned int vin0_clk_pins
[] = {
3717 static const unsigned int vin0_clk_mux
[] = {
3720 /* - VIN1 ------------------------------------------------------------------- */
3721 static const union vin_data vin1_data_pins
= {
3724 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3725 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3726 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3727 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3729 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3730 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3731 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3732 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3734 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3735 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3736 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3737 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3740 static const union vin_data vin1_data_mux
= {
3743 VI1_DATA0_VI1_B0_MARK
, VI1_DATA1_VI1_B1_MARK
,
3744 VI1_DATA2_VI1_B2_MARK
, VI1_DATA3_VI1_B3_MARK
,
3745 VI1_DATA4_VI1_B4_MARK
, VI1_DATA5_VI1_B5_MARK
,
3746 VI1_DATA6_VI1_B6_MARK
, VI1_DATA7_VI1_B7_MARK
,
3748 VI1_G0_MARK
, VI1_G1_MARK
,
3749 VI1_G2_MARK
, VI1_G3_MARK
,
3750 VI1_G4_MARK
, VI1_G5_MARK
,
3751 VI1_G6_MARK
, VI1_G7_MARK
,
3753 VI1_R0_MARK
, VI1_R1_MARK
,
3754 VI1_R2_MARK
, VI1_R3_MARK
,
3755 VI1_R4_MARK
, VI1_R5_MARK
,
3756 VI1_R6_MARK
, VI1_R7_MARK
,
3759 static const unsigned int vin1_data18_pins
[] = {
3761 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3762 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3763 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3765 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3766 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3767 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3769 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3770 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3771 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3773 static const unsigned int vin1_data18_mux
[] = {
3775 VI1_DATA2_VI1_B2_MARK
, VI1_DATA3_VI1_B3_MARK
,
3776 VI1_DATA4_VI1_B4_MARK
, VI1_DATA5_VI1_B5_MARK
,
3777 VI1_DATA6_VI1_B6_MARK
, VI1_DATA7_VI1_B7_MARK
,
3779 VI1_G2_MARK
, VI1_G3_MARK
,
3780 VI1_G4_MARK
, VI1_G5_MARK
,
3781 VI1_G6_MARK
, VI1_G7_MARK
,
3783 VI1_R2_MARK
, VI1_R3_MARK
,
3784 VI1_R4_MARK
, VI1_R5_MARK
,
3785 VI1_R6_MARK
, VI1_R7_MARK
,
3787 static const unsigned int vin1_sync_pins
[] = {
3788 RCAR_GP_PIN(1, 24), /* HSYNC */
3789 RCAR_GP_PIN(1, 25), /* VSYNC */
3791 static const unsigned int vin1_sync_mux
[] = {
3795 static const unsigned int vin1_field_pins
[] = {
3798 static const unsigned int vin1_field_mux
[] = {
3801 static const unsigned int vin1_clkenb_pins
[] = {
3804 static const unsigned int vin1_clkenb_mux
[] = {
3807 static const unsigned int vin1_clk_pins
[] = {
3810 static const unsigned int vin1_clk_mux
[] = {
3813 /* - VIN2 ----------------------------------------------------------------- */
3814 static const union vin_data vin2_data_pins
= {
3817 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3818 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3819 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3820 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3822 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3823 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3824 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3825 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3827 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3828 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3829 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3830 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3833 static const union vin_data vin2_data_mux
= {
3836 VI2_DATA0_VI2_B0_MARK
, VI2_DATA1_VI2_B1_MARK
,
3837 VI2_DATA2_VI2_B2_MARK
, VI2_DATA3_VI2_B3_MARK
,
3838 VI2_DATA4_VI2_B4_MARK
, VI2_DATA5_VI2_B5_MARK
,
3839 VI2_DATA6_VI2_B6_MARK
, VI2_DATA7_VI2_B7_MARK
,
3841 VI2_G0_MARK
, VI2_G1_MARK
,
3842 VI2_G2_MARK
, VI2_G3_MARK
,
3843 VI2_G4_MARK
, VI2_G5_MARK
,
3844 VI2_G6_MARK
, VI2_G7_MARK
,
3846 VI2_R0_MARK
, VI2_R1_MARK
,
3847 VI2_R2_MARK
, VI2_R3_MARK
,
3848 VI2_R4_MARK
, VI2_R5_MARK
,
3849 VI2_R6_MARK
, VI2_R7_MARK
,
3852 static const unsigned int vin2_data18_pins
[] = {
3854 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3855 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3856 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3858 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3859 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3860 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3862 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3863 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3864 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3866 static const unsigned int vin2_data18_mux
[] = {
3868 VI2_DATA2_VI2_B2_MARK
, VI2_DATA3_VI2_B3_MARK
,
3869 VI2_DATA4_VI2_B4_MARK
, VI2_DATA5_VI2_B5_MARK
,
3870 VI2_DATA6_VI2_B6_MARK
, VI2_DATA7_VI2_B7_MARK
,
3872 VI2_G2_MARK
, VI2_G3_MARK
,
3873 VI2_G4_MARK
, VI2_G5_MARK
,
3874 VI2_G6_MARK
, VI2_G7_MARK
,
3876 VI2_R2_MARK
, VI2_R3_MARK
,
3877 VI2_R4_MARK
, VI2_R5_MARK
,
3878 VI2_R6_MARK
, VI2_R7_MARK
,
3880 static const unsigned int vin2_sync_pins
[] = {
3881 RCAR_GP_PIN(1, 16), /* HSYNC */
3882 RCAR_GP_PIN(1, 21), /* VSYNC */
3884 static const unsigned int vin2_sync_mux
[] = {
3888 static const unsigned int vin2_field_pins
[] = {
3891 static const unsigned int vin2_field_mux
[] = {
3894 static const unsigned int vin2_clkenb_pins
[] = {
3897 static const unsigned int vin2_clkenb_mux
[] = {
3900 static const unsigned int vin2_clk_pins
[] = {
3903 static const unsigned int vin2_clk_mux
[] = {
3906 /* - VIN3 ----------------------------------------------------------------- */
3907 static const unsigned int vin3_data8_pins
[] = {
3908 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3909 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3910 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3911 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3913 static const unsigned int vin3_data8_mux
[] = {
3914 VI3_DATA0_MARK
, VI3_DATA1_MARK
,
3915 VI3_DATA2_MARK
, VI3_DATA3_MARK
,
3916 VI3_DATA4_MARK
, VI3_DATA5_MARK
,
3917 VI3_DATA6_MARK
, VI3_DATA7_MARK
,
3919 static const unsigned int vin3_sync_pins
[] = {
3920 RCAR_GP_PIN(1, 16), /* HSYNC */
3921 RCAR_GP_PIN(1, 17), /* VSYNC */
3923 static const unsigned int vin3_sync_mux
[] = {
3927 static const unsigned int vin3_field_pins
[] = {
3930 static const unsigned int vin3_field_mux
[] = {
3933 static const unsigned int vin3_clkenb_pins
[] = {
3936 static const unsigned int vin3_clkenb_mux
[] = {
3939 static const unsigned int vin3_clk_pins
[] = {
3942 static const unsigned int vin3_clk_mux
[] = {
3946 static const struct sh_pfc_pin_group pinmux_groups
[] = {
3947 SH_PFC_PIN_GROUP(audio_clk_a
),
3948 SH_PFC_PIN_GROUP(audio_clk_b
),
3949 SH_PFC_PIN_GROUP(audio_clk_c
),
3950 SH_PFC_PIN_GROUP(audio_clkout
),
3951 SH_PFC_PIN_GROUP(audio_clkout_b
),
3952 SH_PFC_PIN_GROUP(audio_clkout_c
),
3953 SH_PFC_PIN_GROUP(audio_clkout_d
),
3954 SH_PFC_PIN_GROUP(avb_link
),
3955 SH_PFC_PIN_GROUP(avb_magic
),
3956 SH_PFC_PIN_GROUP(avb_phy_int
),
3957 SH_PFC_PIN_GROUP(avb_mdio
),
3958 SH_PFC_PIN_GROUP(avb_mii
),
3959 SH_PFC_PIN_GROUP(avb_gmii
),
3960 SH_PFC_PIN_GROUP(du_rgb666
),
3961 SH_PFC_PIN_GROUP(du_rgb888
),
3962 SH_PFC_PIN_GROUP(du_clk_out_0
),
3963 SH_PFC_PIN_GROUP(du_clk_out_1
),
3964 SH_PFC_PIN_GROUP(du_sync_0
),
3965 SH_PFC_PIN_GROUP(du_sync_1
),
3966 SH_PFC_PIN_GROUP(du_cde
),
3967 SH_PFC_PIN_GROUP(du0_clk_in
),
3968 SH_PFC_PIN_GROUP(du1_clk_in
),
3969 SH_PFC_PIN_GROUP(du2_clk_in
),
3970 SH_PFC_PIN_GROUP(eth_link
),
3971 SH_PFC_PIN_GROUP(eth_magic
),
3972 SH_PFC_PIN_GROUP(eth_mdio
),
3973 SH_PFC_PIN_GROUP(eth_rmii
),
3974 SH_PFC_PIN_GROUP(hscif0_data
),
3975 SH_PFC_PIN_GROUP(hscif0_clk
),
3976 SH_PFC_PIN_GROUP(hscif0_ctrl
),
3977 SH_PFC_PIN_GROUP(hscif0_data_b
),
3978 SH_PFC_PIN_GROUP(hscif0_ctrl_b
),
3979 SH_PFC_PIN_GROUP(hscif0_data_c
),
3980 SH_PFC_PIN_GROUP(hscif0_ctrl_c
),
3981 SH_PFC_PIN_GROUP(hscif0_data_d
),
3982 SH_PFC_PIN_GROUP(hscif0_ctrl_d
),
3983 SH_PFC_PIN_GROUP(hscif0_data_e
),
3984 SH_PFC_PIN_GROUP(hscif0_ctrl_e
),
3985 SH_PFC_PIN_GROUP(hscif0_data_f
),
3986 SH_PFC_PIN_GROUP(hscif0_ctrl_f
),
3987 SH_PFC_PIN_GROUP(hscif1_data
),
3988 SH_PFC_PIN_GROUP(hscif1_clk
),
3989 SH_PFC_PIN_GROUP(hscif1_ctrl
),
3990 SH_PFC_PIN_GROUP(hscif1_data_b
),
3991 SH_PFC_PIN_GROUP(hscif1_clk_b
),
3992 SH_PFC_PIN_GROUP(hscif1_ctrl_b
),
3993 SH_PFC_PIN_GROUP(i2c0
),
3994 SH_PFC_PIN_GROUP(i2c1
),
3995 SH_PFC_PIN_GROUP(i2c1_b
),
3996 SH_PFC_PIN_GROUP(i2c1_c
),
3997 SH_PFC_PIN_GROUP(i2c2
),
3998 SH_PFC_PIN_GROUP(i2c2_b
),
3999 SH_PFC_PIN_GROUP(i2c2_c
),
4000 SH_PFC_PIN_GROUP(i2c2_d
),
4001 SH_PFC_PIN_GROUP(i2c2_e
),
4002 SH_PFC_PIN_GROUP(i2c3
),
4003 SH_PFC_PIN_GROUP(iic0
),
4004 SH_PFC_PIN_GROUP(iic1
),
4005 SH_PFC_PIN_GROUP(iic1_b
),
4006 SH_PFC_PIN_GROUP(iic1_c
),
4007 SH_PFC_PIN_GROUP(iic2
),
4008 SH_PFC_PIN_GROUP(iic2_b
),
4009 SH_PFC_PIN_GROUP(iic2_c
),
4010 SH_PFC_PIN_GROUP(iic2_d
),
4011 SH_PFC_PIN_GROUP(iic2_e
),
4012 SH_PFC_PIN_GROUP(iic3
),
4013 SH_PFC_PIN_GROUP(intc_irq0
),
4014 SH_PFC_PIN_GROUP(intc_irq1
),
4015 SH_PFC_PIN_GROUP(intc_irq2
),
4016 SH_PFC_PIN_GROUP(intc_irq3
),
4017 SH_PFC_PIN_GROUP(mlb_3pin
),
4018 SH_PFC_PIN_GROUP(mmc0_data1
),
4019 SH_PFC_PIN_GROUP(mmc0_data4
),
4020 SH_PFC_PIN_GROUP(mmc0_data8
),
4021 SH_PFC_PIN_GROUP(mmc0_ctrl
),
4022 SH_PFC_PIN_GROUP(mmc1_data1
),
4023 SH_PFC_PIN_GROUP(mmc1_data4
),
4024 SH_PFC_PIN_GROUP(mmc1_data8
),
4025 SH_PFC_PIN_GROUP(mmc1_ctrl
),
4026 SH_PFC_PIN_GROUP(msiof0_clk
),
4027 SH_PFC_PIN_GROUP(msiof0_sync
),
4028 SH_PFC_PIN_GROUP(msiof0_ss1
),
4029 SH_PFC_PIN_GROUP(msiof0_ss2
),
4030 SH_PFC_PIN_GROUP(msiof0_rx
),
4031 SH_PFC_PIN_GROUP(msiof0_tx
),
4032 SH_PFC_PIN_GROUP(msiof0_clk_b
),
4033 SH_PFC_PIN_GROUP(msiof0_ss1_b
),
4034 SH_PFC_PIN_GROUP(msiof0_ss2_b
),
4035 SH_PFC_PIN_GROUP(msiof0_rx_b
),
4036 SH_PFC_PIN_GROUP(msiof0_tx_b
),
4037 SH_PFC_PIN_GROUP(msiof1_clk
),
4038 SH_PFC_PIN_GROUP(msiof1_sync
),
4039 SH_PFC_PIN_GROUP(msiof1_ss1
),
4040 SH_PFC_PIN_GROUP(msiof1_ss2
),
4041 SH_PFC_PIN_GROUP(msiof1_rx
),
4042 SH_PFC_PIN_GROUP(msiof1_tx
),
4043 SH_PFC_PIN_GROUP(msiof1_clk_b
),
4044 SH_PFC_PIN_GROUP(msiof1_ss1_b
),
4045 SH_PFC_PIN_GROUP(msiof1_ss2_b
),
4046 SH_PFC_PIN_GROUP(msiof1_rx_b
),
4047 SH_PFC_PIN_GROUP(msiof1_tx_b
),
4048 SH_PFC_PIN_GROUP(msiof2_clk
),
4049 SH_PFC_PIN_GROUP(msiof2_sync
),
4050 SH_PFC_PIN_GROUP(msiof2_ss1
),
4051 SH_PFC_PIN_GROUP(msiof2_ss2
),
4052 SH_PFC_PIN_GROUP(msiof2_rx
),
4053 SH_PFC_PIN_GROUP(msiof2_tx
),
4054 SH_PFC_PIN_GROUP(msiof3_clk
),
4055 SH_PFC_PIN_GROUP(msiof3_sync
),
4056 SH_PFC_PIN_GROUP(msiof3_ss1
),
4057 SH_PFC_PIN_GROUP(msiof3_ss2
),
4058 SH_PFC_PIN_GROUP(msiof3_rx
),
4059 SH_PFC_PIN_GROUP(msiof3_tx
),
4060 SH_PFC_PIN_GROUP(msiof3_clk_b
),
4061 SH_PFC_PIN_GROUP(msiof3_sync_b
),
4062 SH_PFC_PIN_GROUP(msiof3_rx_b
),
4063 SH_PFC_PIN_GROUP(msiof3_tx_b
),
4064 SH_PFC_PIN_GROUP(pwm0
),
4065 SH_PFC_PIN_GROUP(pwm0_b
),
4066 SH_PFC_PIN_GROUP(pwm1
),
4067 SH_PFC_PIN_GROUP(pwm1_b
),
4068 SH_PFC_PIN_GROUP(pwm2
),
4069 SH_PFC_PIN_GROUP(pwm3
),
4070 SH_PFC_PIN_GROUP(pwm4
),
4071 SH_PFC_PIN_GROUP(pwm5
),
4072 SH_PFC_PIN_GROUP(pwm6
),
4073 SH_PFC_PIN_GROUP(qspi_ctrl
),
4074 SH_PFC_PIN_GROUP(qspi_data2
),
4075 SH_PFC_PIN_GROUP(qspi_data4
),
4076 SH_PFC_PIN_GROUP(scif0_data
),
4077 SH_PFC_PIN_GROUP(scif0_clk
),
4078 SH_PFC_PIN_GROUP(scif0_ctrl
),
4079 SH_PFC_PIN_GROUP(scif0_data_b
),
4080 SH_PFC_PIN_GROUP(scif1_data
),
4081 SH_PFC_PIN_GROUP(scif1_clk
),
4082 SH_PFC_PIN_GROUP(scif1_ctrl
),
4083 SH_PFC_PIN_GROUP(scif1_data_b
),
4084 SH_PFC_PIN_GROUP(scif1_data_c
),
4085 SH_PFC_PIN_GROUP(scif1_data_d
),
4086 SH_PFC_PIN_GROUP(scif1_clk_d
),
4087 SH_PFC_PIN_GROUP(scif1_data_e
),
4088 SH_PFC_PIN_GROUP(scif1_clk_e
),
4089 SH_PFC_PIN_GROUP(scif2_data
),
4090 SH_PFC_PIN_GROUP(scif2_clk
),
4091 SH_PFC_PIN_GROUP(scif2_data_b
),
4092 SH_PFC_PIN_GROUP(scifa0_data
),
4093 SH_PFC_PIN_GROUP(scifa0_clk
),
4094 SH_PFC_PIN_GROUP(scifa0_ctrl
),
4095 SH_PFC_PIN_GROUP(scifa0_data_b
),
4096 SH_PFC_PIN_GROUP(scifa0_clk_b
),
4097 SH_PFC_PIN_GROUP(scifa0_ctrl_b
),
4098 SH_PFC_PIN_GROUP(scifa1_data
),
4099 SH_PFC_PIN_GROUP(scifa1_clk
),
4100 SH_PFC_PIN_GROUP(scifa1_ctrl
),
4101 SH_PFC_PIN_GROUP(scifa1_data_b
),
4102 SH_PFC_PIN_GROUP(scifa1_clk_b
),
4103 SH_PFC_PIN_GROUP(scifa1_ctrl_b
),
4104 SH_PFC_PIN_GROUP(scifa1_data_c
),
4105 SH_PFC_PIN_GROUP(scifa1_clk_c
),
4106 SH_PFC_PIN_GROUP(scifa1_ctrl_c
),
4107 SH_PFC_PIN_GROUP(scifa1_data_d
),
4108 SH_PFC_PIN_GROUP(scifa1_clk_d
),
4109 SH_PFC_PIN_GROUP(scifa1_ctrl_d
),
4110 SH_PFC_PIN_GROUP(scifa2_data
),
4111 SH_PFC_PIN_GROUP(scifa2_clk
),
4112 SH_PFC_PIN_GROUP(scifa2_ctrl
),
4113 SH_PFC_PIN_GROUP(scifa2_data_b
),
4114 SH_PFC_PIN_GROUP(scifa2_data_c
),
4115 SH_PFC_PIN_GROUP(scifa2_clk_c
),
4116 SH_PFC_PIN_GROUP(scifb0_data
),
4117 SH_PFC_PIN_GROUP(scifb0_clk
),
4118 SH_PFC_PIN_GROUP(scifb0_ctrl
),
4119 SH_PFC_PIN_GROUP(scifb0_data_b
),
4120 SH_PFC_PIN_GROUP(scifb0_clk_b
),
4121 SH_PFC_PIN_GROUP(scifb0_ctrl_b
),
4122 SH_PFC_PIN_GROUP(scifb0_data_c
),
4123 SH_PFC_PIN_GROUP(scifb1_data
),
4124 SH_PFC_PIN_GROUP(scifb1_clk
),
4125 SH_PFC_PIN_GROUP(scifb1_ctrl
),
4126 SH_PFC_PIN_GROUP(scifb1_data_b
),
4127 SH_PFC_PIN_GROUP(scifb1_clk_b
),
4128 SH_PFC_PIN_GROUP(scifb1_ctrl_b
),
4129 SH_PFC_PIN_GROUP(scifb1_data_c
),
4130 SH_PFC_PIN_GROUP(scifb1_data_d
),
4131 SH_PFC_PIN_GROUP(scifb1_data_e
),
4132 SH_PFC_PIN_GROUP(scifb1_clk_e
),
4133 SH_PFC_PIN_GROUP(scifb1_data_f
),
4134 SH_PFC_PIN_GROUP(scifb1_data_g
),
4135 SH_PFC_PIN_GROUP(scifb1_clk_g
),
4136 SH_PFC_PIN_GROUP(scifb2_data
),
4137 SH_PFC_PIN_GROUP(scifb2_clk
),
4138 SH_PFC_PIN_GROUP(scifb2_ctrl
),
4139 SH_PFC_PIN_GROUP(scifb2_data_b
),
4140 SH_PFC_PIN_GROUP(scifb2_clk_b
),
4141 SH_PFC_PIN_GROUP(scifb2_ctrl_b
),
4142 SH_PFC_PIN_GROUP(scifb2_data_c
),
4143 SH_PFC_PIN_GROUP(sdhi0_data1
),
4144 SH_PFC_PIN_GROUP(sdhi0_data4
),
4145 SH_PFC_PIN_GROUP(sdhi0_ctrl
),
4146 SH_PFC_PIN_GROUP(sdhi0_cd
),
4147 SH_PFC_PIN_GROUP(sdhi0_wp
),
4148 SH_PFC_PIN_GROUP(sdhi1_data1
),
4149 SH_PFC_PIN_GROUP(sdhi1_data4
),
4150 SH_PFC_PIN_GROUP(sdhi1_ctrl
),
4151 SH_PFC_PIN_GROUP(sdhi1_cd
),
4152 SH_PFC_PIN_GROUP(sdhi1_wp
),
4153 SH_PFC_PIN_GROUP(sdhi2_data1
),
4154 SH_PFC_PIN_GROUP(sdhi2_data4
),
4155 SH_PFC_PIN_GROUP(sdhi2_ctrl
),
4156 SH_PFC_PIN_GROUP(sdhi2_cd
),
4157 SH_PFC_PIN_GROUP(sdhi2_wp
),
4158 SH_PFC_PIN_GROUP(sdhi3_data1
),
4159 SH_PFC_PIN_GROUP(sdhi3_data4
),
4160 SH_PFC_PIN_GROUP(sdhi3_ctrl
),
4161 SH_PFC_PIN_GROUP(sdhi3_cd
),
4162 SH_PFC_PIN_GROUP(sdhi3_wp
),
4163 SH_PFC_PIN_GROUP(ssi0_data
),
4164 SH_PFC_PIN_GROUP(ssi0129_ctrl
),
4165 SH_PFC_PIN_GROUP(ssi1_data
),
4166 SH_PFC_PIN_GROUP(ssi1_ctrl
),
4167 SH_PFC_PIN_GROUP(ssi2_data
),
4168 SH_PFC_PIN_GROUP(ssi2_ctrl
),
4169 SH_PFC_PIN_GROUP(ssi3_data
),
4170 SH_PFC_PIN_GROUP(ssi34_ctrl
),
4171 SH_PFC_PIN_GROUP(ssi4_data
),
4172 SH_PFC_PIN_GROUP(ssi4_ctrl
),
4173 SH_PFC_PIN_GROUP(ssi5
),
4174 SH_PFC_PIN_GROUP(ssi5_b
),
4175 SH_PFC_PIN_GROUP(ssi5_c
),
4176 SH_PFC_PIN_GROUP(ssi6
),
4177 SH_PFC_PIN_GROUP(ssi6_b
),
4178 SH_PFC_PIN_GROUP(ssi7_data
),
4179 SH_PFC_PIN_GROUP(ssi7_b_data
),
4180 SH_PFC_PIN_GROUP(ssi7_c_data
),
4181 SH_PFC_PIN_GROUP(ssi78_ctrl
),
4182 SH_PFC_PIN_GROUP(ssi78_b_ctrl
),
4183 SH_PFC_PIN_GROUP(ssi78_c_ctrl
),
4184 SH_PFC_PIN_GROUP(ssi8_data
),
4185 SH_PFC_PIN_GROUP(ssi8_b_data
),
4186 SH_PFC_PIN_GROUP(ssi8_c_data
),
4187 SH_PFC_PIN_GROUP(ssi9_data
),
4188 SH_PFC_PIN_GROUP(ssi9_ctrl
),
4189 SH_PFC_PIN_GROUP(tpu0_to0
),
4190 SH_PFC_PIN_GROUP(tpu0_to1
),
4191 SH_PFC_PIN_GROUP(tpu0_to2
),
4192 SH_PFC_PIN_GROUP(tpu0_to3
),
4193 SH_PFC_PIN_GROUP(usb0
),
4194 SH_PFC_PIN_GROUP(usb0_ovc_vbus
),
4195 SH_PFC_PIN_GROUP(usb1
),
4196 SH_PFC_PIN_GROUP(usb2
),
4197 VIN_DATA_PIN_GROUP(vin0_data
, 24),
4198 VIN_DATA_PIN_GROUP(vin0_data
, 20),
4199 SH_PFC_PIN_GROUP(vin0_data18
),
4200 VIN_DATA_PIN_GROUP(vin0_data
, 16),
4201 VIN_DATA_PIN_GROUP(vin0_data
, 12),
4202 VIN_DATA_PIN_GROUP(vin0_data
, 10),
4203 VIN_DATA_PIN_GROUP(vin0_data
, 8),
4204 VIN_DATA_PIN_GROUP(vin0_data
, 4),
4205 SH_PFC_PIN_GROUP(vin0_sync
),
4206 SH_PFC_PIN_GROUP(vin0_field
),
4207 SH_PFC_PIN_GROUP(vin0_clkenb
),
4208 SH_PFC_PIN_GROUP(vin0_clk
),
4209 VIN_DATA_PIN_GROUP(vin1_data
, 24),
4210 VIN_DATA_PIN_GROUP(vin1_data
, 20),
4211 SH_PFC_PIN_GROUP(vin1_data18
),
4212 VIN_DATA_PIN_GROUP(vin1_data
, 16),
4213 VIN_DATA_PIN_GROUP(vin1_data
, 12),
4214 VIN_DATA_PIN_GROUP(vin1_data
, 10),
4215 VIN_DATA_PIN_GROUP(vin1_data
, 8),
4216 VIN_DATA_PIN_GROUP(vin1_data
, 4),
4217 SH_PFC_PIN_GROUP(vin1_sync
),
4218 SH_PFC_PIN_GROUP(vin1_field
),
4219 SH_PFC_PIN_GROUP(vin1_clkenb
),
4220 SH_PFC_PIN_GROUP(vin1_clk
),
4221 VIN_DATA_PIN_GROUP(vin2_data
, 24),
4222 SH_PFC_PIN_GROUP(vin2_data18
),
4223 VIN_DATA_PIN_GROUP(vin2_data
, 16),
4224 VIN_DATA_PIN_GROUP(vin2_data
, 8),
4225 VIN_DATA_PIN_GROUP(vin2_data
, 4),
4226 SH_PFC_PIN_GROUP(vin2_sync
),
4227 SH_PFC_PIN_GROUP(vin2_field
),
4228 SH_PFC_PIN_GROUP(vin2_clkenb
),
4229 SH_PFC_PIN_GROUP(vin2_clk
),
4230 SH_PFC_PIN_GROUP(vin3_data8
),
4231 SH_PFC_PIN_GROUP(vin3_sync
),
4232 SH_PFC_PIN_GROUP(vin3_field
),
4233 SH_PFC_PIN_GROUP(vin3_clkenb
),
4234 SH_PFC_PIN_GROUP(vin3_clk
),
4237 static const char * const audio_clk_groups
[] = {
4247 static const char * const avb_groups
[] = {
4256 static const char * const du_groups
[] = {
4266 static const char * const du0_groups
[] = {
4270 static const char * const du1_groups
[] = {
4274 static const char * const du2_groups
[] = {
4278 static const char * const eth_groups
[] = {
4285 static const char * const hscif0_groups
[] = {
4301 static const char * const hscif1_groups
[] = {
4310 static const char * const i2c0_groups
[] = {
4314 static const char * const i2c1_groups
[] = {
4320 static const char * const i2c2_groups
[] = {
4328 static const char * const i2c3_groups
[] = {
4332 static const char * const iic0_groups
[] = {
4336 static const char * const iic1_groups
[] = {
4342 static const char * const iic2_groups
[] = {
4350 static const char * const iic3_groups
[] = {
4354 static const char * const intc_groups
[] = {
4361 static const char * const mlb_groups
[] = {
4365 static const char * const mmc0_groups
[] = {
4372 static const char * const mmc1_groups
[] = {
4379 static const char * const msiof0_groups
[] = {
4393 static const char * const msiof1_groups
[] = {
4407 static const char * const msiof2_groups
[] = {
4416 static const char * const msiof3_groups
[] = {
4429 static const char * const pwm0_groups
[] = {
4434 static const char * const pwm1_groups
[] = {
4439 static const char * const pwm2_groups
[] = {
4443 static const char * const pwm3_groups
[] = {
4447 static const char * const pwm4_groups
[] = {
4451 static const char * const pwm5_groups
[] = {
4455 static const char * const pwm6_groups
[] = {
4459 static const char * const qspi_groups
[] = {
4465 static const char * const scif0_groups
[] = {
4472 static const char * const scif1_groups
[] = {
4484 static const char * const scif2_groups
[] = {
4490 static const char * const scifa0_groups
[] = {
4499 static const char * const scifa1_groups
[] = {
4514 static const char * const scifa2_groups
[] = {
4523 static const char * const scifb0_groups
[] = {
4533 static const char * const scifb1_groups
[] = {
4549 static const char * const scifb2_groups
[] = {
4559 static const char * const sdhi0_groups
[] = {
4567 static const char * const sdhi1_groups
[] = {
4575 static const char * const sdhi2_groups
[] = {
4583 static const char * const sdhi3_groups
[] = {
4591 static const char * const ssi_groups
[] = {
4620 static const char * const tpu0_groups
[] = {
4627 static const char * const usb0_groups
[] = {
4632 static const char * const usb1_groups
[] = {
4636 static const char * const usb2_groups
[] = {
4640 static const char * const vin0_groups
[] = {
4655 static const char * const vin1_groups
[] = {
4670 static const char * const vin2_groups
[] = {
4682 static const char * const vin3_groups
[] = {
4690 static const struct sh_pfc_function pinmux_functions
[] = {
4691 SH_PFC_FUNCTION(audio_clk
),
4692 SH_PFC_FUNCTION(avb
),
4693 SH_PFC_FUNCTION(du
),
4694 SH_PFC_FUNCTION(du0
),
4695 SH_PFC_FUNCTION(du1
),
4696 SH_PFC_FUNCTION(du2
),
4697 SH_PFC_FUNCTION(eth
),
4698 SH_PFC_FUNCTION(hscif0
),
4699 SH_PFC_FUNCTION(hscif1
),
4700 SH_PFC_FUNCTION(i2c0
),
4701 SH_PFC_FUNCTION(i2c1
),
4702 SH_PFC_FUNCTION(i2c2
),
4703 SH_PFC_FUNCTION(i2c3
),
4704 SH_PFC_FUNCTION(iic0
),
4705 SH_PFC_FUNCTION(iic1
),
4706 SH_PFC_FUNCTION(iic2
),
4707 SH_PFC_FUNCTION(iic3
),
4708 SH_PFC_FUNCTION(intc
),
4709 SH_PFC_FUNCTION(mlb
),
4710 SH_PFC_FUNCTION(mmc0
),
4711 SH_PFC_FUNCTION(mmc1
),
4712 SH_PFC_FUNCTION(msiof0
),
4713 SH_PFC_FUNCTION(msiof1
),
4714 SH_PFC_FUNCTION(msiof2
),
4715 SH_PFC_FUNCTION(msiof3
),
4716 SH_PFC_FUNCTION(pwm0
),
4717 SH_PFC_FUNCTION(pwm1
),
4718 SH_PFC_FUNCTION(pwm2
),
4719 SH_PFC_FUNCTION(pwm3
),
4720 SH_PFC_FUNCTION(pwm4
),
4721 SH_PFC_FUNCTION(pwm5
),
4722 SH_PFC_FUNCTION(pwm6
),
4723 SH_PFC_FUNCTION(qspi
),
4724 SH_PFC_FUNCTION(scif0
),
4725 SH_PFC_FUNCTION(scif1
),
4726 SH_PFC_FUNCTION(scif2
),
4727 SH_PFC_FUNCTION(scifa0
),
4728 SH_PFC_FUNCTION(scifa1
),
4729 SH_PFC_FUNCTION(scifa2
),
4730 SH_PFC_FUNCTION(scifb0
),
4731 SH_PFC_FUNCTION(scifb1
),
4732 SH_PFC_FUNCTION(scifb2
),
4733 SH_PFC_FUNCTION(sdhi0
),
4734 SH_PFC_FUNCTION(sdhi1
),
4735 SH_PFC_FUNCTION(sdhi2
),
4736 SH_PFC_FUNCTION(sdhi3
),
4737 SH_PFC_FUNCTION(ssi
),
4738 SH_PFC_FUNCTION(tpu0
),
4739 SH_PFC_FUNCTION(usb0
),
4740 SH_PFC_FUNCTION(usb1
),
4741 SH_PFC_FUNCTION(usb2
),
4742 SH_PFC_FUNCTION(vin0
),
4743 SH_PFC_FUNCTION(vin1
),
4744 SH_PFC_FUNCTION(vin2
),
4745 SH_PFC_FUNCTION(vin3
),
4748 static const struct pinmux_cfg_reg pinmux_config_regs
[] = {
4749 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
4750 GP_0_31_FN
, FN_IP3_17_15
,
4751 GP_0_30_FN
, FN_IP3_14_12
,
4752 GP_0_29_FN
, FN_IP3_11_8
,
4753 GP_0_28_FN
, FN_IP3_7_4
,
4754 GP_0_27_FN
, FN_IP3_3_0
,
4755 GP_0_26_FN
, FN_IP2_28_26
,
4756 GP_0_25_FN
, FN_IP2_25_22
,
4757 GP_0_24_FN
, FN_IP2_21_18
,
4758 GP_0_23_FN
, FN_IP2_17_15
,
4759 GP_0_22_FN
, FN_IP2_14_12
,
4760 GP_0_21_FN
, FN_IP2_11_9
,
4761 GP_0_20_FN
, FN_IP2_8_6
,
4762 GP_0_19_FN
, FN_IP2_5_3
,
4763 GP_0_18_FN
, FN_IP2_2_0
,
4764 GP_0_17_FN
, FN_IP1_29_28
,
4765 GP_0_16_FN
, FN_IP1_27_26
,
4766 GP_0_15_FN
, FN_IP1_25_22
,
4767 GP_0_14_FN
, FN_IP1_21_18
,
4768 GP_0_13_FN
, FN_IP1_17_15
,
4769 GP_0_12_FN
, FN_IP1_14_12
,
4770 GP_0_11_FN
, FN_IP1_11_8
,
4771 GP_0_10_FN
, FN_IP1_7_4
,
4772 GP_0_9_FN
, FN_IP1_3_0
,
4773 GP_0_8_FN
, FN_IP0_30_27
,
4774 GP_0_7_FN
, FN_IP0_26_23
,
4775 GP_0_6_FN
, FN_IP0_22_20
,
4776 GP_0_5_FN
, FN_IP0_19_16
,
4777 GP_0_4_FN
, FN_IP0_15_12
,
4778 GP_0_3_FN
, FN_IP0_11_9
,
4779 GP_0_2_FN
, FN_IP0_8_6
,
4780 GP_0_1_FN
, FN_IP0_5_3
,
4781 GP_0_0_FN
, FN_IP0_2_0
}
4783 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
4786 GP_1_29_FN
, FN_IP6_13_11
,
4787 GP_1_28_FN
, FN_IP6_10_9
,
4788 GP_1_27_FN
, FN_IP6_8_6
,
4789 GP_1_26_FN
, FN_IP6_5_3
,
4790 GP_1_25_FN
, FN_IP6_2_0
,
4791 GP_1_24_FN
, FN_IP5_29_27
,
4792 GP_1_23_FN
, FN_IP5_26_24
,
4793 GP_1_22_FN
, FN_IP5_23_21
,
4794 GP_1_21_FN
, FN_IP5_20_18
,
4795 GP_1_20_FN
, FN_IP5_17_15
,
4796 GP_1_19_FN
, FN_IP5_14_13
,
4797 GP_1_18_FN
, FN_IP5_12_10
,
4798 GP_1_17_FN
, FN_IP5_9_6
,
4799 GP_1_16_FN
, FN_IP5_5_3
,
4800 GP_1_15_FN
, FN_IP5_2_0
,
4801 GP_1_14_FN
, FN_IP4_29_27
,
4802 GP_1_13_FN
, FN_IP4_26_24
,
4803 GP_1_12_FN
, FN_IP4_23_21
,
4804 GP_1_11_FN
, FN_IP4_20_18
,
4805 GP_1_10_FN
, FN_IP4_17_15
,
4806 GP_1_9_FN
, FN_IP4_14_12
,
4807 GP_1_8_FN
, FN_IP4_11_9
,
4808 GP_1_7_FN
, FN_IP4_8_6
,
4809 GP_1_6_FN
, FN_IP4_5_3
,
4810 GP_1_5_FN
, FN_IP4_2_0
,
4811 GP_1_4_FN
, FN_IP3_31_29
,
4812 GP_1_3_FN
, FN_IP3_28_26
,
4813 GP_1_2_FN
, FN_IP3_25_23
,
4814 GP_1_1_FN
, FN_IP3_22_20
,
4815 GP_1_0_FN
, FN_IP3_19_18
, }
4817 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
4820 GP_2_29_FN
, FN_IP7_15_13
,
4821 GP_2_28_FN
, FN_IP7_12_10
,
4822 GP_2_27_FN
, FN_IP7_9_8
,
4823 GP_2_26_FN
, FN_IP7_7_6
,
4824 GP_2_25_FN
, FN_IP7_5_3
,
4825 GP_2_24_FN
, FN_IP7_2_0
,
4826 GP_2_23_FN
, FN_IP6_31_29
,
4827 GP_2_22_FN
, FN_IP6_28_26
,
4828 GP_2_21_FN
, FN_IP6_25_23
,
4829 GP_2_20_FN
, FN_IP6_22_20
,
4830 GP_2_19_FN
, FN_IP6_19_17
,
4831 GP_2_18_FN
, FN_IP6_16_14
,
4832 GP_2_17_FN
, FN_VI1_DATA7_VI1_B7
,
4833 GP_2_16_FN
, FN_IP8_27
,
4834 GP_2_15_FN
, FN_IP8_26
,
4835 GP_2_14_FN
, FN_IP8_25_24
,
4836 GP_2_13_FN
, FN_IP8_23_22
,
4837 GP_2_12_FN
, FN_IP8_21_20
,
4838 GP_2_11_FN
, FN_IP8_19_18
,
4839 GP_2_10_FN
, FN_IP8_17_16
,
4840 GP_2_9_FN
, FN_IP8_15_14
,
4841 GP_2_8_FN
, FN_IP8_13_12
,
4842 GP_2_7_FN
, FN_IP8_11_10
,
4843 GP_2_6_FN
, FN_IP8_9_8
,
4844 GP_2_5_FN
, FN_IP8_7_6
,
4845 GP_2_4_FN
, FN_IP8_5_4
,
4846 GP_2_3_FN
, FN_IP8_3_2
,
4847 GP_2_2_FN
, FN_IP8_1_0
,
4848 GP_2_1_FN
, FN_IP7_30_29
,
4849 GP_2_0_FN
, FN_IP7_28_27
}
4851 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
4852 GP_3_31_FN
, FN_IP11_21_18
,
4853 GP_3_30_FN
, FN_IP11_17_15
,
4854 GP_3_29_FN
, FN_IP11_14_13
,
4855 GP_3_28_FN
, FN_IP11_12_11
,
4856 GP_3_27_FN
, FN_IP11_10_9
,
4857 GP_3_26_FN
, FN_IP11_8_7
,
4858 GP_3_25_FN
, FN_IP11_6_5
,
4859 GP_3_24_FN
, FN_IP11_4
,
4860 GP_3_23_FN
, FN_IP11_3_0
,
4861 GP_3_22_FN
, FN_IP10_29_26
,
4862 GP_3_21_FN
, FN_IP10_25_23
,
4863 GP_3_20_FN
, FN_IP10_22_19
,
4864 GP_3_19_FN
, FN_IP10_18_15
,
4865 GP_3_18_FN
, FN_IP10_14_11
,
4866 GP_3_17_FN
, FN_IP10_10_7
,
4867 GP_3_16_FN
, FN_IP10_6_4
,
4868 GP_3_15_FN
, FN_IP10_3_0
,
4869 GP_3_14_FN
, FN_IP9_31_28
,
4870 GP_3_13_FN
, FN_IP9_27_26
,
4871 GP_3_12_FN
, FN_IP9_25_24
,
4872 GP_3_11_FN
, FN_IP9_23_22
,
4873 GP_3_10_FN
, FN_IP9_21_20
,
4874 GP_3_9_FN
, FN_IP9_19_18
,
4875 GP_3_8_FN
, FN_IP9_17_16
,
4876 GP_3_7_FN
, FN_IP9_15_12
,
4877 GP_3_6_FN
, FN_IP9_11_8
,
4878 GP_3_5_FN
, FN_IP9_7_6
,
4879 GP_3_4_FN
, FN_IP9_5_4
,
4880 GP_3_3_FN
, FN_IP9_3_2
,
4881 GP_3_2_FN
, FN_IP9_1_0
,
4882 GP_3_1_FN
, FN_IP8_30_29
,
4883 GP_3_0_FN
, FN_IP8_28
}
4885 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
4886 GP_4_31_FN
, FN_IP14_18_16
,
4887 GP_4_30_FN
, FN_IP14_15_12
,
4888 GP_4_29_FN
, FN_IP14_11_9
,
4889 GP_4_28_FN
, FN_IP14_8_6
,
4890 GP_4_27_FN
, FN_IP14_5_3
,
4891 GP_4_26_FN
, FN_IP14_2_0
,
4892 GP_4_25_FN
, FN_IP13_30_29
,
4893 GP_4_24_FN
, FN_IP13_28_26
,
4894 GP_4_23_FN
, FN_IP13_25_23
,
4895 GP_4_22_FN
, FN_IP13_22_19
,
4896 GP_4_21_FN
, FN_IP13_18_16
,
4897 GP_4_20_FN
, FN_IP13_15_13
,
4898 GP_4_19_FN
, FN_IP13_12_10
,
4899 GP_4_18_FN
, FN_IP13_9_7
,
4900 GP_4_17_FN
, FN_IP13_6_3
,
4901 GP_4_16_FN
, FN_IP13_2_0
,
4902 GP_4_15_FN
, FN_IP12_30_28
,
4903 GP_4_14_FN
, FN_IP12_27_25
,
4904 GP_4_13_FN
, FN_IP12_24_23
,
4905 GP_4_12_FN
, FN_IP12_22_20
,
4906 GP_4_11_FN
, FN_IP12_19_17
,
4907 GP_4_10_FN
, FN_IP12_16_14
,
4908 GP_4_9_FN
, FN_IP12_13_11
,
4909 GP_4_8_FN
, FN_IP12_10_8
,
4910 GP_4_7_FN
, FN_IP12_7_6
,
4911 GP_4_6_FN
, FN_IP12_5_4
,
4912 GP_4_5_FN
, FN_IP12_3_2
,
4913 GP_4_4_FN
, FN_IP12_1_0
,
4914 GP_4_3_FN
, FN_IP11_31_30
,
4915 GP_4_2_FN
, FN_IP11_29_27
,
4916 GP_4_1_FN
, FN_IP11_26_24
,
4917 GP_4_0_FN
, FN_IP11_23_22
}
4919 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
4920 GP_5_31_FN
, FN_IP7_24_22
,
4921 GP_5_30_FN
, FN_IP7_21_19
,
4922 GP_5_29_FN
, FN_IP7_18_16
,
4923 GP_5_28_FN
, FN_DU_DOTCLKIN2
,
4924 GP_5_27_FN
, FN_IP7_26_25
,
4925 GP_5_26_FN
, FN_DU_DOTCLKIN0
,
4926 GP_5_25_FN
, FN_AVS2
,
4927 GP_5_24_FN
, FN_AVS1
,
4928 GP_5_23_FN
, FN_USB2_OVC
,
4929 GP_5_22_FN
, FN_USB2_PWEN
,
4930 GP_5_21_FN
, FN_IP16_7
,
4931 GP_5_20_FN
, FN_IP16_6
,
4932 GP_5_19_FN
, FN_USB0_OVC_VBUS
,
4933 GP_5_18_FN
, FN_USB0_PWEN
,
4934 GP_5_17_FN
, FN_IP16_5_3
,
4935 GP_5_16_FN
, FN_IP16_2_0
,
4936 GP_5_15_FN
, FN_IP15_29_28
,
4937 GP_5_14_FN
, FN_IP15_27_26
,
4938 GP_5_13_FN
, FN_IP15_25_23
,
4939 GP_5_12_FN
, FN_IP15_22_20
,
4940 GP_5_11_FN
, FN_IP15_19_18
,
4941 GP_5_10_FN
, FN_IP15_17_16
,
4942 GP_5_9_FN
, FN_IP15_15_14
,
4943 GP_5_8_FN
, FN_IP15_13_12
,
4944 GP_5_7_FN
, FN_IP15_11_9
,
4945 GP_5_6_FN
, FN_IP15_8_6
,
4946 GP_5_5_FN
, FN_IP15_5_3
,
4947 GP_5_4_FN
, FN_IP15_2_0
,
4948 GP_5_3_FN
, FN_IP14_30_28
,
4949 GP_5_2_FN
, FN_IP14_27_25
,
4950 GP_5_1_FN
, FN_IP14_24_22
,
4951 GP_5_0_FN
, FN_IP14_21_19
}
4953 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4954 1, 4, 4, 3, 4, 4, 3, 3, 3, 3) {
4958 FN_D8
, FN_SCIFA1_SCK_C
, FN_AVB_TXD0
, 0,
4959 FN_VI0_G0
, FN_VI0_G0_B
, FN_VI2_DATA0_VI2_B0
,
4960 0, 0, 0, 0, 0, 0, 0, 0, 0,
4962 FN_D7
, FN_AD_DI_B
, FN_IIC2_SDA_C
,
4963 FN_VI3_DATA7
, FN_VI0_R3
, FN_VI0_R3_B
, FN_I2C2_SDA_C
,
4964 FN_TCLK1
, 0, 0, 0, 0, 0, 0, 0, 0,
4966 FN_D6
, FN_IIC2_SCL_C
, FN_VI3_DATA6
, FN_VI0_R2
, FN_VI0_R2_B
,
4967 FN_I2C2_SCL_C
, 0, 0,
4969 FN_D5
, FN_SCIFB1_TXD_F
, FN_SCIFB0_TXD_C
, FN_VI3_DATA5
,
4970 FN_VI0_R1
, FN_VI0_R1_B
, FN_TX0_B
,
4971 0, 0, 0, 0, 0, 0, 0, 0, 0,
4973 FN_D4
, FN_SCIFB1_RXD_F
, FN_SCIFB0_RXD_C
, FN_VI3_DATA4
,
4974 FN_VI0_R0
, FN_VI0_R0_B
, FN_RX0_B
,
4975 0, 0, 0, 0, 0, 0, 0, 0, 0,
4977 FN_D3
, FN_MSIOF3_TXD_B
, FN_VI3_DATA3
, FN_VI0_G7
, FN_VI0_G7_B
,
4980 FN_D2
, FN_MSIOF3_RXD_B
, FN_VI3_DATA2
, FN_VI0_G6
, FN_VI0_G6_B
,
4983 FN_D1
, FN_MSIOF3_SYNC_B
, FN_VI3_DATA1
, FN_VI0_G5
, FN_VI0_G5_B
,
4986 FN_D0
, FN_MSIOF3_SCK_B
, FN_VI3_DATA0
, FN_VI0_G4
, FN_VI0_G4_B
,
4989 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4990 2, 2, 2, 4, 4, 3, 3, 4, 4, 4) {
4994 FN_A1
, FN_PWM4
, 0, 0,
4996 FN_A0
, FN_PWM3
, 0, 0,
4998 FN_D15
, FN_SCIFB1_TXD_C
, FN_AVB_TXD7
, FN_TX1_B
,
4999 FN_VI0_FIELD
, FN_VI0_FIELD_B
, FN_VI2_DATA7_VI2_B7
,
5000 0, 0, 0, 0, 0, 0, 0, 0, 0,
5002 FN_D14
, FN_SCIFB1_RXD_C
, FN_AVB_TXD6
, FN_RX1_B
,
5003 FN_VI0_CLKENB
, FN_VI0_CLKENB_B
, FN_VI2_DATA6_VI2_B6
,
5004 0, 0, 0, 0, 0, 0, 0, 0, 0,
5006 FN_D13
, FN_AVB_TXD5
, FN_VI0_VSYNC_N
,
5007 FN_VI0_VSYNC_N_B
, FN_VI2_DATA5_VI2_B5
,
5010 FN_D12
, FN_SCIFA1_RTS_N_C
, FN_AVB_TXD4
,
5011 FN_VI0_HSYNC_N
, FN_VI0_HSYNC_N_B
, FN_VI2_DATA4_VI2_B4
,
5014 FN_D11
, FN_SCIFA1_CTS_N_C
, FN_AVB_TXD3
, 0,
5015 FN_VI0_G3
, FN_VI0_G3_B
, FN_VI2_DATA3_VI2_B3
,
5016 0, 0, 0, 0, 0, 0, 0, 0, 0,
5018 FN_D10
, FN_SCIFA1_TXD_C
, FN_AVB_TXD2
, 0,
5019 FN_VI0_G2
, FN_VI0_G2_B
, FN_VI2_DATA2_VI2_B2
,
5020 0, 0, 0, 0, 0, 0, 0, 0, 0,
5022 FN_D9
, FN_SCIFA1_RXD_C
, FN_AVB_TXD1
, 0,
5023 FN_VI0_G1
, FN_VI0_G1_B
, FN_VI2_DATA1_VI2_B1
,
5024 0, 0, 0, 0, 0, 0, 0, 0, 0, }
5026 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5027 3, 3, 4, 4, 3, 3, 3, 3, 3, 3) {
5029 0, 0, 0, 0, 0, 0, 0, 0,
5031 FN_A10
, FN_SSI_SDATA5_B
, FN_MSIOF2_SYNC
, FN_VI0_R6
,
5032 FN_VI0_R6_B
, FN_VI2_DATA2_VI2_B2_B
, 0, 0,
5034 FN_A9
, FN_SCIFA1_CTS_N_B
, FN_SSI_WS5_B
, FN_VI0_R5
,
5035 FN_VI0_R5_B
, FN_SCIFB2_TXD_C
, FN_TX2_B
, FN_VI2_DATA1_VI2_B1_B
,
5036 0, 0, 0, 0, 0, 0, 0, 0,
5038 FN_A8
, FN_SCIFA1_RXD_B
, FN_SSI_SCK5_B
, FN_VI0_R4
,
5039 FN_VI0_R4_B
, FN_SCIFB2_RXD_C
, FN_RX2_B
, FN_VI2_DATA0_VI2_B0_B
,
5040 0, 0, 0, 0, 0, 0, 0, 0,
5042 FN_A7
, FN_SCIFA1_SCK_B
, FN_AUDIO_CLKOUT_B
, FN_TPU0TO3
,
5045 FN_A6
, FN_SCIFA1_RTS_N_B
, FN_TPU0TO2
, 0, 0, 0, 0, 0,
5047 FN_A5
, FN_SCIFA1_TXD_B
, FN_TPU0TO1
, 0, 0, 0, 0, 0,
5049 FN_A4
, FN_MSIOF1_TXD_B
, FN_TPU0TO0
, 0, 0, 0, 0, 0,
5051 FN_A3
, FN_PWM6
, FN_MSIOF1_SS2_B
, 0, 0, 0, 0, 0,
5053 FN_A2
, FN_PWM5
, FN_MSIOF1_SS1_B
, 0, 0, 0, 0, 0, }
5055 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5056 3, 3, 3, 3, 2, 3, 3, 4, 4, 4) {
5058 FN_A20
, FN_SPCLK
, FN_VI1_R3
, FN_VI1_R3_B
, FN_VI2_G4
,
5061 FN_A19
, FN_AD_NCS_N_B
, FN_ATACS01_N
, FN_EX_WAIT0_B
,
5064 FN_A18
, FN_AD_CLK_B
, FN_ATAG1_N
, 0, 0, 0, 0, 0,
5066 FN_A17
, FN_AD_DO_B
, FN_ATADIR1_N
, 0, 0, 0, 0, 0,
5068 FN_A16
, FN_ATAWR1_N
, 0, 0,
5070 FN_A15
, FN_SCIFB2_SCK_B
, FN_ATARD1_N
, FN_MSIOF2_SS2
,
5073 FN_A14
, FN_SCIFB2_TXD_B
, FN_ATACS11_N
, FN_MSIOF2_SS1
,
5076 FN_A13
, FN_SCIFB2_RTS_N_B
, FN_EX_WAIT2
,
5077 FN_MSIOF2_RXD
, FN_VI1_R2
, FN_VI1_R2_B
, FN_VI2_G2
,
5078 FN_VI2_DATA5_VI2_B5_B
, 0, 0, 0, 0, 0, 0, 0, 0,
5080 FN_A12
, FN_SCIFB2_RXD_B
, FN_MSIOF2_TXD
, FN_VI1_R1
,
5081 FN_VI1_R1_B
, FN_VI2_G1
, FN_VI2_DATA4_VI2_B4_B
,
5082 0, 0, 0, 0, 0, 0, 0, 0, 0,
5084 FN_A11
, FN_SCIFB2_CTS_N_B
, FN_MSIOF2_SCK
, FN_VI1_R0
,
5085 FN_VI1_R0_B
, FN_VI2_G0
, FN_VI2_DATA3_VI2_B3_B
, 0,
5086 0, 0, 0, 0, 0, 0, 0, 0, }
5088 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5089 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
5093 FN_EX_CS2_N
, FN_GPS_SIGN
, FN_HRTS1_N_B
,
5094 FN_VI3_CLKENB
, FN_VI1_G0
, FN_VI1_G0_B
, FN_VI2_R2
, 0,
5096 FN_EX_CS1_N
, FN_GPS_CLK
, FN_HCTS1_N_B
, FN_VI1_FIELD
,
5097 FN_VI1_FIELD_B
, FN_VI2_R1
, 0, 0,
5099 FN_EX_CS0_N
, FN_HRX1_B
, FN_VI1_G5
, FN_VI1_G5_B
, FN_VI2_R0
,
5100 FN_HTX0_B
, FN_MSIOF0_SS1_B
, 0,
5102 FN_CS1_N_A26
, FN_SPEEDIN
, FN_VI0_R7
, FN_VI0_R7_B
,
5103 FN_VI2_CLK
, FN_VI2_CLK_B
, 0, 0,
5105 FN_CS0_N
, FN_VI1_R6
, FN_VI1_R6_B
, FN_VI2_G3
, FN_MSIOF0_SS2_B
,
5108 FN_A25
, FN_SSL
, FN_VI1_G6
, FN_VI1_G6_B
, FN_VI2_FIELD
,
5109 FN_VI2_FIELD_B
, 0, 0,
5111 FN_A24
, FN_IO3
, FN_VI1_R7
, FN_VI1_R7_B
, FN_VI2_CLKENB
,
5112 FN_VI2_CLKENB_B
, 0, 0,
5114 FN_A23
, FN_IO2
, FN_VI1_G7
, FN_VI1_G7_B
, FN_VI2_G7
, 0, 0, 0,
5116 FN_A22
, FN_MISO_IO1
, FN_VI1_R5
, FN_VI1_R5_B
, FN_VI2_G6
, 0, 0, 0,
5118 FN_A21
, FN_MOSI_IO0
, FN_VI1_R4
, FN_VI1_R4_B
, FN_VI2_G5
, 0, 0, 0,
5121 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5122 2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) {
5126 FN_DREQ0_N
, FN_VI1_HSYNC_N
, FN_VI1_HSYNC_N_B
, FN_VI2_R7
,
5127 FN_SSI_SCK78_C
, FN_SSI_WS78_B
, 0, 0,
5129 FN_EX_WAIT0
, FN_IRQ3
, FN_INTC_IRQ3_N
,
5130 FN_VI3_CLK
, FN_SCIFA0_RTS_N_B
, FN_HRX0_B
,
5133 FN_WE1_N
, FN_IERX
, FN_CAN1_RX
, FN_VI1_G4
,
5134 FN_VI1_G4_B
, FN_VI2_R6
, FN_SCIFA0_CTS_N_B
, FN_IERX_C
,
5136 FN_WE0_N
, FN_IECLK
, FN_CAN_CLK
,
5137 FN_VI2_VSYNC_N
, FN_SCIFA0_TXD_B
, FN_VI2_VSYNC_N_B
, 0, 0,
5139 FN_RD_WR_N
, FN_VI1_G3
, FN_VI1_G3_B
, FN_VI2_R5
, FN_SCIFA0_RXD_B
,
5140 FN_INTC_IRQ4_N
, 0, 0,
5142 FN_RD_N
, FN_CAN0_TX
, FN_SCIFA0_SCK_B
, 0,
5144 FN_BS_N
, FN_IETX
, FN_HTX1_B
, FN_CAN1_TX
, FN_DRACK0
, FN_IETX_C
,
5147 FN_EX_CS5_N
, FN_CAN0_RX
, FN_MSIOF1_RXD_B
, FN_VI3_VSYNC_N
,
5148 FN_VI1_G2
, FN_VI1_G2_B
, FN_VI2_R4
, FN_IIC1_SDA
, FN_INTC_EN1_N
,
5149 FN_I2C1_SDA
, 0, 0, 0, 0, 0, 0,
5151 FN_EX_CS4_N
, FN_MSIOF1_SCK_B
, FN_VI3_HSYNC_N
,
5152 FN_VI2_HSYNC_N
, FN_IIC1_SCL
, FN_VI2_HSYNC_N_B
,
5153 FN_INTC_EN0_N
, FN_I2C1_SCL
,
5155 FN_EX_CS3_N
, FN_GPS_MAG
, FN_VI3_FIELD
, FN_VI1_G1
, FN_VI1_G1_B
,
5158 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5159 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
5161 FN_ETH_REF_CLK
, 0, FN_HCTS0_N_E
,
5162 FN_STP_IVCXO27_1_B
, FN_HRX0_F
, 0, 0, 0,
5164 FN_ETH_LINK
, 0, FN_HTX0_E
,
5165 FN_STP_IVCXO27_0_B
, FN_SCIFB1_TXD_G
, FN_TX1_E
, 0, 0,
5167 FN_ETH_RXD1
, 0, FN_HRX0_E
, FN_STP_ISSYNC_0_B
,
5168 FN_TS_SCK0_D
, FN_GLO_I1_C
, FN_SCIFB1_RXD_G
, FN_RX1_E
,
5170 FN_ETH_RXD0
, 0, FN_STP_ISEN_0_B
, FN_TS_SDAT0_D
,
5171 FN_GLO_I0_C
, FN_SCIFB1_SCK_G
, FN_SCK1_E
, 0,
5173 FN_ETH_RX_ER
, 0, FN_STP_ISD_0_B
,
5174 FN_TS_SPSYNC0_D
, FN_GLO_Q1_C
, FN_IIC2_SDA_E
, FN_I2C2_SDA_E
, 0,
5176 FN_ETH_CRS_DV
, 0, FN_STP_ISCLK_0_B
,
5177 FN_TS_SDEN0_D
, FN_GLO_Q0_C
, FN_IIC2_SCL_E
,
5180 FN_DACK2
, FN_IRQ2
, FN_INTC_IRQ2_N
,
5181 FN_SSI_SDATA6_B
, FN_HRTS0_N_B
, FN_MSIOF0_RXD_B
, 0, 0,
5183 FN_DREQ2_N
, FN_HSCK1_B
, FN_HCTS0_N_B
, FN_MSIOF0_TXD_B
,
5185 FN_DACK1
, FN_IRQ1
, FN_INTC_IRQ1_N
, FN_SSI_WS6_B
,
5186 FN_SSI_SDATA8_C
, 0, 0, 0,
5188 FN_DREQ1_N
, FN_VI1_CLKENB
, FN_VI1_CLKENB_B
,
5189 FN_SSI_SDATA7_C
, FN_SSI_SCK78_B
, 0, 0, 0,
5191 FN_DACK0
, FN_IRQ0
, FN_INTC_IRQ0_N
, FN_SSI_SCK6_B
,
5192 FN_VI1_VSYNC_N
, FN_VI1_VSYNC_N_B
, FN_SSI_WS78_C
, 0, }
5194 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5195 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
5199 FN_VI0_DATA0_VI0_B0
, FN_ATACS10_N
, FN_AVB_RXD2
, 0,
5201 FN_VI0_CLK
, FN_ATACS00_N
, FN_AVB_RXD1
, 0,
5203 FN_DU_DOTCLKIN1
, FN_AUDIO_CLKC
, FN_AUDIO_CLKOUT_C
, 0,
5205 FN_PWM2
, FN_PWMFSW0
, FN_SCIFA2_RXD_C
, FN_PCMWE_N
, FN_IECLK_C
,
5208 FN_PWM1
, FN_SCIFA2_TXD_C
, FN_STP_ISSYNC_1_B
, FN_TS_SCK1_C
,
5209 FN_GLO_RFON_C
, FN_PCMOE_N
, 0, 0,
5211 FN_PWM0
, FN_SCIFA2_SCK_C
, FN_STP_ISEN_1_B
, FN_TS_SDAT1_C
,
5212 FN_GLO_SS_C
, 0, 0, 0,
5214 FN_ETH_MDC
, 0, FN_STP_ISD_1_B
,
5215 FN_TS_SPSYNC1_C
, FN_GLO_SDATA_C
, 0, 0, 0,
5217 FN_ETH_TXD0
, 0, FN_STP_ISCLK_1_B
, FN_TS_SDEN1_C
,
5218 FN_GLO_SCLK_C
, 0, 0, 0,
5220 FN_ETH_MAGIC
, 0, FN_SIM0_RST_C
, 0,
5222 FN_ETH_TX_EN
, 0, FN_SIM0_CLK_C
, FN_HRTS0_N_F
,
5224 FN_ETH_TXD1
, 0, FN_HTX0_F
, FN_BPFCLK_G
, 0, 0, 0, 0,
5226 FN_ETH_MDIO
, 0, FN_HRTS0_N_E
,
5227 FN_SIM0_D_C
, FN_HCTS0_N_F
, 0, 0, 0, }
5229 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5230 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2,
5231 2, 2, 2, 2, 2, 2, 2) {
5235 FN_SD0_CMD
, FN_SCIFB1_SCK_B
, FN_VI1_DATA1_VI1_B1_B
, 0,
5237 FN_SD0_CLK
, FN_VI1_DATA0_VI1_B0_B
,
5239 FN_VI1_DATA6_VI1_B6
, FN_AVB_GTXREFCLK
,
5241 FN_VI1_DATA5_VI1_B5
, FN_AVB_PHY_INT
,
5243 FN_VI1_DATA4_VI1_B4
, FN_SCIFA1_RTS_N_D
,
5246 FN_VI1_DATA3_VI1_B3
, FN_SCIFA1_CTS_N_D
, FN_AVB_GTX_CLK
, 0,
5248 FN_VI1_DATA2_VI1_B2
, FN_SCIFA1_TXD_D
, FN_AVB_MDIO
, 0,
5250 FN_VI1_DATA1_VI1_B1
, FN_SCIFA1_RXD_D
, FN_AVB_MDC
, 0,
5252 FN_VI1_DATA0_VI1_B0
, FN_SCIFA1_SCK_D
, FN_AVB_CRS
, 0,
5254 FN_VI1_CLK
, FN_AVB_RX_DV
, 0, 0,
5256 FN_VI0_DATA7_VI0_B7
, FN_AVB_RX_CLK
, 0, 0,
5258 FN_VI0_DATA6_VI0_B6
, FN_AVB_RX_ER
, 0, 0,
5260 FN_VI0_DATA5_VI0_B5
, FN_EX_WAIT1
, FN_AVB_RXD7
, 0,
5262 FN_VI0_DATA4_VI0_B4
, FN_ATAG0_N
, FN_AVB_RXD6
, 0,
5264 FN_VI0_DATA3_VI0_B3
, FN_ATADIR0_N
, FN_AVB_RXD5
, 0,
5266 FN_VI0_DATA2_VI0_B2
, FN_ATAWR0_N
, FN_AVB_RXD4
, 0,
5268 FN_VI0_DATA1_VI0_B1
, FN_ATARD0_N
, FN_AVB_RXD3
, 0, }
5270 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5271 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
5273 FN_SD1_CD
, FN_MMC1_D6
, FN_TS_SDEN1
, FN_USB1_EXTP
,
5274 FN_GLO_SS
, FN_VI0_CLK_B
, FN_IIC2_SCL_D
, FN_I2C2_SCL_D
,
5275 FN_SIM0_CLK_B
, FN_VI3_CLK_B
, 0, 0, 0, 0, 0, 0,
5277 FN_SD1_DAT3
, FN_AVB_RXD0
, 0, FN_SCIFB0_RTS_N_B
,
5279 FN_SD1_DAT2
, FN_AVB_COL
, 0, FN_SCIFB0_CTS_N_B
,
5281 FN_SD1_DAT1
, FN_AVB_LINK
, 0, FN_SCIFB0_TXD_B
,
5283 FN_SD1_DAT0
, FN_AVB_TX_CLK
, 0, FN_SCIFB0_RXD_B
,
5285 FN_SD1_CMD
, FN_AVB_TX_ER
, 0, FN_SCIFB0_SCK_B
,
5287 FN_SD1_CLK
, FN_AVB_TX_EN
, 0, 0,
5289 FN_SD0_WP
, FN_MMC0_D7
, FN_TS_SPSYNC0_B
, FN_USB0_IDIN
,
5290 FN_GLO_SDATA
, FN_VI1_DATA7_VI1_B7_B
, FN_IIC1_SDA_B
,
5291 FN_I2C1_SDA_B
, FN_VI2_DATA7_VI2_B7_B
, 0, 0, 0, 0, 0, 0, 0,
5293 FN_SD0_CD
, FN_MMC0_D6
, FN_TS_SDEN0_B
, FN_USB0_EXTP
,
5294 FN_GLO_SCLK
, FN_VI1_DATA6_VI1_B6_B
, FN_IIC1_SCL_B
,
5295 FN_I2C1_SCL_B
, FN_VI2_DATA6_VI2_B6_B
, 0, 0, 0, 0, 0, 0, 0,
5297 FN_SD0_DAT3
, FN_SCIFB1_RTS_N_B
, FN_VI1_DATA5_VI1_B5_B
, 0,
5299 FN_SD0_DAT2
, FN_SCIFB1_CTS_N_B
, FN_VI1_DATA4_VI1_B4_B
, 0,
5301 FN_SD0_DAT1
, FN_SCIFB1_TXD_B
, FN_VI1_DATA3_VI1_B3_B
, 0,
5303 FN_SD0_DAT0
, FN_SCIFB1_RXD_B
, FN_VI1_DATA2_VI1_B2_B
, 0, }
5305 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
5306 2, 4, 3, 4, 4, 4, 4, 3, 4) {
5307 /* IP10_31_30 [2] */
5309 /* IP10_29_26 [4] */
5310 FN_SD2_CD
, FN_MMC0_D4
, FN_TS_SDAT0_B
, FN_USB2_EXTP
, FN_GLO_I0
,
5311 FN_VI0_DATA6_VI0_B6_B
, FN_HCTS0_N_D
, FN_TS_SDAT1_B
,
5312 FN_GLO_I0_B
, FN_VI3_DATA6_B
, 0, 0, 0, 0, 0, 0,
5313 /* IP10_25_23 [3] */
5314 FN_SD2_DAT3
, FN_MMC0_D3
, FN_SIM0_RST
, FN_VI0_DATA5_VI0_B5_B
,
5315 FN_HTX0_D
, FN_TS_SPSYNC1_B
, FN_GLO_Q1_B
, FN_VI3_DATA5_B
,
5316 /* IP10_22_19 [4] */
5317 FN_SD2_DAT2
, FN_MMC0_D2
, FN_BPFCLK_B
, 0,
5318 FN_VI0_DATA4_VI0_B4_B
, FN_HRX0_D
, FN_TS_SDEN1_B
,
5319 FN_GLO_Q0_B
, FN_VI3_DATA4_B
, 0, 0, 0, 0, 0, 0, 0,
5320 /* IP10_18_15 [4] */
5321 FN_SD2_DAT1
, FN_MMC0_D1
, FN_FMIN_B
, 0,
5322 FN_VI0_DATA3_VI0_B3_B
, FN_SCIFB1_TXD_E
, FN_TX1_D
,
5323 FN_TS_SCK0_C
, FN_GLO_RFON_B
, FN_VI3_DATA3_B
,
5325 /* IP10_14_11 [4] */
5326 FN_SD2_DAT0
, FN_MMC0_D0
, FN_FMCLK_B
,
5327 FN_VI0_DATA2_VI0_B2_B
, FN_SCIFB1_RXD_E
, FN_RX1_D
,
5328 FN_TS_SDAT0_C
, FN_GLO_SS_B
, FN_VI3_DATA2_B
,
5329 0, 0, 0, 0, 0, 0, 0,
5331 FN_SD2_CMD
, FN_MMC0_CMD
, FN_SIM0_D
,
5332 FN_VI0_DATA1_VI0_B1_B
, FN_SCIFB1_SCK_E
, FN_SCK1_D
,
5333 FN_TS_SPSYNC0_C
, FN_GLO_SDATA_B
, FN_VI3_DATA1_B
,
5334 0, 0, 0, 0, 0, 0, 0,
5336 FN_SD2_CLK
, FN_MMC0_CLK
, FN_SIM0_CLK
,
5337 FN_VI0_DATA0_VI0_B0_B
, FN_TS_SDEN0_C
, FN_GLO_SCLK_B
,
5340 FN_SD1_WP
, FN_MMC1_D7
, FN_TS_SPSYNC1
, FN_USB1_IDIN
,
5341 FN_GLO_RFON
, FN_VI1_CLK_B
, FN_IIC2_SDA_D
, FN_I2C2_SDA_D
,
5342 FN_SIM0_D_B
, 0, 0, 0, 0, 0, 0, 0, }
5344 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
5345 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) {
5346 /* IP11_31_30 [2] */
5347 FN_SSI_SCK0129
, FN_CAN_CLK_B
, FN_MOUT0
, 0,
5348 /* IP11_29_27 [3] */
5349 FN_MLB_DAT
, 0, FN_SCIFB1_TXD_D
, FN_TX1_C
, FN_BPFCLK_C
,
5351 /* IP11_26_24 [3] */
5352 FN_MLB_SIG
, FN_SCIFB1_RXD_D
, FN_RX1_C
, FN_IIC2_SDA_B
, FN_I2C2_SDA_B
,
5354 /* IP11_23_22 [2] */
5355 FN_MLB_CLK
, FN_IIC2_SCL_B
, FN_I2C2_SCL_B
, 0,
5356 /* IP11_21_18 [4] */
5357 FN_SD3_WP
, FN_MMC1_D5
, FN_TS_SCK1
, FN_GLO_Q1
, FN_FMIN_C
,
5358 0, FN_FMIN_E
, 0, FN_FMIN_F
, 0, 0, 0, 0, 0, 0, 0,
5359 /* IP11_17_15 [3] */
5360 FN_SD3_CD
, FN_MMC1_D4
, FN_TS_SDAT1
,
5361 FN_VSP
, FN_GLO_Q0
, FN_SIM0_RST_B
, 0, 0,
5362 /* IP11_14_13 [2] */
5363 FN_SD3_DAT3
, FN_MMC1_D3
, FN_SCKZ
, 0,
5364 /* IP11_12_11 [2] */
5365 FN_SD3_DAT2
, FN_MMC1_D2
, FN_SDATA
, 0,
5367 FN_SD3_DAT1
, FN_MMC1_D1
, FN_MDATA
, 0,
5369 FN_SD3_DAT0
, FN_MMC1_D0
, FN_STM_N
, 0,
5371 FN_SD3_CMD
, FN_MMC1_CMD
, FN_MTS_N
, 0,
5373 FN_SD3_CLK
, FN_MMC1_CLK
,
5375 FN_SD2_WP
, FN_MMC0_D5
, FN_TS_SCK0_B
, FN_USB2_IDIN
,
5376 FN_GLO_I1
, FN_VI0_DATA7_VI0_B7_B
, FN_HRTS0_N_D
,
5377 FN_TS_SCK1_B
, FN_GLO_I1_B
, FN_VI3_DATA7_B
, 0, 0, 0, 0, 0, 0, }
5379 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
5380 1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
5383 /* IP12_30_28 [3] */
5384 FN_SSI_WS5
, FN_SCIFB1_RXD
, FN_IECLK_B
,
5385 FN_DU2_EXVSYNC_DU2_VSYNC
, FN_QSTB_QHE
,
5386 FN_CAN_DEBUGOUT4
, 0, 0,
5387 /* IP12_27_25 [3] */
5388 FN_SSI_SCK5
, FN_SCIFB1_SCK
,
5389 FN_IERX_B
, FN_DU2_EXHSYNC_DU2_HSYNC
, FN_QSTH_QHS
,
5390 FN_CAN_DEBUGOUT3
, 0, 0,
5391 /* IP12_24_23 [2] */
5392 FN_SSI_SDATA4
, FN_STP_ISSYNC_0
, FN_MSIOF1_RXD
,
5394 /* IP12_22_20 [3] */
5395 FN_SSI_WS4
, FN_STP_ISEN_0
, FN_SCIFB0_RTS_N
,
5396 FN_MSIOF1_TXD
, FN_SSI_WS5_C
, FN_CAN_DEBUGOUT1
, 0, 0,
5397 /* IP12_19_17 [3] */
5398 FN_SSI_SCK4
, FN_STP_ISD_0
, FN_SCIFB0_CTS_N
,
5399 FN_MSIOF1_SS2
, FN_SSI_SCK5_C
, FN_CAN_DEBUGOUT0
, 0, 0,
5400 /* IP12_16_14 [3] */
5401 FN_SSI_SDATA3
, FN_STP_ISCLK_0
,
5402 FN_SCIFB0_TXD
, FN_MSIOF1_SS1
, FN_CAN_TXCLK
, 0, 0, 0,
5403 /* IP12_13_11 [3] */
5404 FN_SSI_WS34
, FN_STP_IVCXO27_0
, FN_SCIFB0_RXD
, FN_MSIOF1_SYNC
,
5405 FN_CAN_STEP0
, 0, 0, 0,
5407 FN_SSI_SCK34
, FN_STP_OPWM_0
, FN_SCIFB0_SCK
,
5408 FN_MSIOF1_SCK
, FN_CAN_DEBUG_HW_TRIGGER
, 0, 0, 0,
5410 FN_SSI_SDATA2
, FN_CAN1_RX_B
, FN_SSI_SCK1
, FN_MOUT6
,
5412 FN_SSI_SDATA1
, FN_CAN1_TX_B
, FN_MOUT5
, 0,
5414 FN_SSI_SDATA0
, FN_CAN0_RX_B
, FN_MOUT2
, 0,
5416 FN_SSI_WS0129
, FN_CAN0_TX_B
, FN_MOUT1
, 0, }
5418 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5419 1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) {
5422 /* IP13_30_29 [2] */
5423 FN_AUDIO_CLKA
, FN_SCIFB2_RTS_N
, FN_CAN_DEBUGOUT14
, 0,
5424 /* IP13_28_26 [3] */
5425 FN_SSI_SDATA9
, FN_STP_ISSYNC_1
, FN_SCIFB2_CTS_N
, FN_SSI_WS1
,
5426 FN_SSI_SDATA5_C
, FN_CAN_DEBUGOUT13
, 0, 0,
5427 /* IP13_25_23 [3] */
5428 FN_SSI_SDATA8
, FN_STP_ISEN_1
, FN_SCIFB2_TXD
, FN_CAN0_TX_C
,
5429 FN_CAN_DEBUGOUT12
, FN_SSI_SDATA8_B
, 0, 0,
5430 /* IP13_22_19 [4] */
5431 FN_SSI_SDATA7
, FN_STP_ISD_1
, FN_SCIFB2_RXD
, FN_SCIFA2_RTS_N
,
5432 FN_TCLK2
, FN_QSTVA_QVS
, FN_CAN_DEBUGOUT11
, FN_BPFCLK_E
,
5433 0, FN_SSI_SDATA7_B
, FN_FMIN_G
, 0, 0, 0, 0, 0,
5434 /* IP13_18_16 [3] */
5435 FN_SSI_WS78
, FN_STP_ISCLK_1
, FN_SCIFB2_SCK
, FN_SCIFA2_CTS_N
,
5436 FN_DU2_DR7
, FN_LCDOUT7
, FN_CAN_DEBUGOUT10
, 0,
5437 /* IP13_15_13 [3] */
5438 FN_SSI_SCK78
, FN_STP_IVCXO27_1
, FN_SCK1
, FN_SCIFA1_SCK
,
5439 FN_DU2_DR6
, FN_LCDOUT6
, FN_CAN_DEBUGOUT9
, 0,
5440 /* IP13_12_10 [3] */
5441 FN_SSI_SDATA6
, FN_FMIN_D
, 0, FN_DU2_DR5
, FN_LCDOUT5
,
5442 FN_CAN_DEBUGOUT8
, 0, 0,
5444 FN_SSI_WS6
, FN_SCIFB1_RTS_N
, FN_CAN0_TX_D
, FN_DU2_DR4
,
5445 FN_LCDOUT4
, FN_CAN_DEBUGOUT7
, 0, 0,
5447 FN_SSI_SCK6
, FN_SCIFB1_CTS_N
, FN_BPFCLK_D
, 0,
5448 FN_DU2_DR3
, FN_LCDOUT3
, FN_CAN_DEBUGOUT6
,
5449 FN_BPFCLK_F
, 0, 0, 0, 0, 0, 0, 0, 0,
5451 FN_SSI_SDATA5
, FN_SCIFB1_TXD
, FN_IETX_B
, FN_DU2_DR2
,
5452 FN_LCDOUT2
, FN_CAN_DEBUGOUT5
, 0, 0, }
5454 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
5455 1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) {
5458 /* IP14_30_28 [3] */
5459 FN_SCIFA1_RTS_N
, FN_AD_NCS_N
, FN_RTS1_N
,
5460 FN_MSIOF3_TXD
, FN_DU1_DOTCLKOUT
, FN_QSTVB_QVE
,
5462 /* IP14_27_25 [3] */
5463 FN_SCIFA1_CTS_N
, FN_AD_CLK
, FN_CTS1_N
, FN_MSIOF3_RXD
,
5464 FN_DU0_DOTCLKOUT
, FN_QCLK
, 0, 0,
5465 /* IP14_24_22 [3] */
5466 FN_SCIFA1_TXD
, FN_AD_DO
, FN_TX1
, FN_DU2_DG1
,
5467 FN_LCDOUT9
, 0, 0, 0,
5468 /* IP14_21_19 [3] */
5469 FN_SCIFA1_RXD
, FN_AD_DI
, FN_RX1
,
5470 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE
, FN_QCPV_QDE
, 0, 0, 0,
5471 /* IP14_18_16 [3] */
5472 FN_SCIFA0_RTS_N
, FN_HRTS1_N
, FN_RTS0_N
,
5473 FN_MSIOF3_SS1
, FN_DU2_DG0
, FN_LCDOUT8
, FN_PWM1_B
, 0,
5474 /* IP14_15_12 [4] */
5475 FN_SCIFA0_CTS_N
, FN_HCTS1_N
, FN_CTS0_N
, FN_MSIOF3_SYNC
,
5476 FN_DU2_DG3
, FN_LCDOUT11
, FN_PWM0_B
, FN_IIC1_SCL_C
, FN_I2C1_SCL_C
,
5477 0, 0, 0, 0, 0, 0, 0,
5479 FN_SCIFA0_TXD
, FN_HTX1
, FN_TX0
, FN_DU2_DR1
, FN_LCDOUT1
,
5482 FN_SCIFA0_RXD
, FN_HRX1
, FN_RX0
, FN_DU2_DR0
, FN_LCDOUT0
,
5485 FN_SCIFA0_SCK
, FN_HSCK1
, FN_SCK0
, FN_MSIOF3_SS2
, FN_DU2_DG2
,
5486 FN_LCDOUT10
, FN_IIC1_SDA_C
, FN_I2C1_SDA_C
,
5488 FN_AUDIO_CLKB
, FN_SCIF_CLK
, FN_CAN0_RX_D
,
5489 FN_DVC_MUTE
, FN_CAN0_RX_C
, FN_CAN_DEBUGOUT15
,
5492 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
5493 2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) {
5494 /* IP15_31_30 [2] */
5496 /* IP15_29_28 [2] */
5497 FN_MSIOF0_TXD
, FN_ADICHS1
, FN_DU2_DG6
, FN_LCDOUT14
,
5498 /* IP15_27_26 [2] */
5499 FN_MSIOF0_SS1
, FN_ADICHS0
, FN_DU2_DG5
, FN_LCDOUT13
,
5500 /* IP15_25_23 [3] */
5501 FN_MSIOF0_SYNC
, FN_TS_SCK0
, FN_SSI_SCK2
, FN_ADIDATA
,
5502 FN_DU2_DB7
, FN_LCDOUT23
, FN_HRX0_C
, 0,
5503 /* IP15_22_20 [3] */
5504 FN_MSIOF0_SCK
, FN_TS_SDAT0
, FN_ADICLK
,
5505 FN_DU2_DB6
, FN_LCDOUT22
, 0, 0, 0,
5506 /* IP15_19_18 [2] */
5507 FN_HRTS0_N
, FN_SSI_WS9
, FN_DU2_DB5
, FN_LCDOUT21
,
5508 /* IP15_17_16 [2] */
5509 FN_HCTS0_N
, FN_SSI_SCK9
, FN_DU2_DB4
, FN_LCDOUT20
,
5510 /* IP15_15_14 [2] */
5511 FN_HTX0
, FN_DU2_DB3
, FN_LCDOUT19
, 0,
5512 /* IP15_13_12 [2] */
5513 FN_HRX0
, FN_DU2_DB2
, FN_LCDOUT18
, 0,
5515 FN_HSCK0
, FN_TS_SDEN0
, FN_DU2_DG4
, FN_LCDOUT12
, FN_HCTS0_N_C
,
5518 FN_SCIFA2_TXD
, FN_BPFCLK
, FN_RX2
, FN_DU2_DB1
, FN_LCDOUT17
,
5519 FN_IIC2_SDA
, FN_I2C2_SDA
, 0,
5521 FN_SCIFA2_RXD
, FN_FMIN
, FN_TX2
, FN_DU2_DB0
, FN_LCDOUT16
,
5522 FN_IIC2_SCL
, FN_I2C2_SCL
, 0,
5524 FN_SCIFA2_SCK
, FN_FMCLK
, FN_SCK2
, FN_MSIOF3_SCK
, FN_DU2_DG7
,
5525 FN_LCDOUT15
, FN_SCIF_CLK_B
, 0, }
5527 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
5528 4, 4, 4, 4, 4, 4, 1, 1, 3, 3) {
5529 /* IP16_31_28 [4] */
5530 0, 0, 0, 0, 0, 0, 0, 0,
5531 0, 0, 0, 0, 0, 0, 0, 0,
5532 /* IP16_27_24 [4] */
5533 0, 0, 0, 0, 0, 0, 0, 0,
5534 0, 0, 0, 0, 0, 0, 0, 0,
5535 /* IP16_23_20 [4] */
5536 0, 0, 0, 0, 0, 0, 0, 0,
5537 0, 0, 0, 0, 0, 0, 0, 0,
5538 /* IP16_19_16 [4] */
5539 0, 0, 0, 0, 0, 0, 0, 0,
5540 0, 0, 0, 0, 0, 0, 0, 0,
5541 /* IP16_15_12 [4] */
5542 0, 0, 0, 0, 0, 0, 0, 0,
5543 0, 0, 0, 0, 0, 0, 0, 0,
5545 0, 0, 0, 0, 0, 0, 0, 0,
5546 0, 0, 0, 0, 0, 0, 0, 0,
5548 FN_USB1_OVC
, FN_TCLK1_B
,
5550 FN_USB1_PWEN
, FN_AUDIO_CLKOUT_D
,
5552 FN_MSIOF0_RXD
, FN_TS_SPSYNC0
, FN_SSI_WS2
,
5553 FN_ADICS_SAMP
, FN_DU2_CDE
, FN_QPOLB
, FN_SCIFA2_RXD_B
, 0,
5555 FN_MSIOF0_SS2
, FN_AUDIO_CLKOUT
, FN_ADICHS2
,
5556 FN_DU2_DISP
, FN_QPOLA
, FN_HTX0_C
, FN_SCIFA2_TXD_B
, 0, }
5558 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5559 3, 2, 2, 3, 2, 1, 1, 1, 2, 1,
5560 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) {
5562 FN_SEL_SCIF1_0
, FN_SEL_SCIF1_1
, FN_SEL_SCIF1_2
, FN_SEL_SCIF1_3
,
5563 FN_SEL_SCIF1_4
, 0, 0, 0,
5565 FN_SEL_SCIFB_0
, FN_SEL_SCIFB_1
, FN_SEL_SCIFB_2
, 0,
5566 /* SEL_SCIFB2 [2] */
5567 FN_SEL_SCIFB2_0
, FN_SEL_SCIFB2_1
, FN_SEL_SCIFB2_2
, 0,
5568 /* SEL_SCIFB1 [3] */
5569 FN_SEL_SCIFB1_0
, FN_SEL_SCIFB1_1
, FN_SEL_SCIFB1_2
,
5570 FN_SEL_SCIFB1_3
, FN_SEL_SCIFB1_4
, FN_SEL_SCIFB1_5
,
5572 /* SEL_SCIFA1 [2] */
5573 FN_SEL_SCIFA1_0
, FN_SEL_SCIFA1_1
, FN_SEL_SCIFA1_2
,
5576 FN_SEL_SCIF0_0
, FN_SEL_SCIF0_1
,
5578 FN_SEL_SCFA_0
, FN_SEL_SCFA_1
,
5580 FN_SEL_SOF1_0
, FN_SEL_SOF1_1
,
5582 FN_SEL_SSI7_0
, FN_SEL_SSI7_1
, FN_SEL_SSI7_2
, 0,
5584 FN_SEL_SSI6_0
, FN_SEL_SSI6_1
,
5586 FN_SEL_SSI5_0
, FN_SEL_SSI5_1
, FN_SEL_SSI5_2
, 0,
5588 FN_SEL_VI3_0
, FN_SEL_VI3_1
,
5590 FN_SEL_VI2_0
, FN_SEL_VI2_1
,
5592 FN_SEL_VI1_0
, FN_SEL_VI1_1
,
5594 FN_SEL_VI0_0
, FN_SEL_VI0_1
,
5596 FN_SEL_TSIF1_0
, FN_SEL_TSIF1_1
, FN_SEL_TSIF1_2
, 0,
5600 FN_SEL_LBS_0
, FN_SEL_LBS_1
,
5602 FN_SEL_TSIF0_0
, FN_SEL_TSIF0_1
, FN_SEL_TSIF0_2
, FN_SEL_TSIF0_3
,
5604 FN_SEL_SOF3_0
, FN_SEL_SOF3_1
,
5606 FN_SEL_SOF0_0
, FN_SEL_SOF0_1
, }
5608 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
5609 3, 1, 1, 1, 2, 1, 2, 1, 2,
5610 1, 1, 1, 3, 3, 2, 3, 2, 2) {
5612 0, 0, 0, 0, 0, 0, 0, 0,
5614 FN_SEL_TMU1_0
, FN_SEL_TMU1_1
,
5615 /* SEL_HSCIF1 [1] */
5616 FN_SEL_HSCIF1_0
, FN_SEL_HSCIF1_1
,
5617 /* SEL_SCIFCLK [1] */
5618 FN_SEL_SCIFCLK_0
, FN_SEL_SCIFCLK_1
,
5620 FN_SEL_CAN0_0
, FN_SEL_CAN0_1
, FN_SEL_CAN0_2
, FN_SEL_CAN0_3
,
5621 /* SEL_CANCLK [1] */
5622 FN_SEL_CANCLK_0
, FN_SEL_CANCLK_1
,
5623 /* SEL_SCIFA2 [2] */
5624 FN_SEL_SCIFA2_0
, FN_SEL_SCIFA2_1
, FN_SEL_SCIFA2_2
, 0,
5626 FN_SEL_CAN1_0
, FN_SEL_CAN1_1
,
5630 FN_SEL_SCIF2_0
, FN_SEL_SCIF2_1
,
5632 FN_SEL_ADI_0
, FN_SEL_ADI_1
,
5634 FN_SEL_SSP_0
, FN_SEL_SSP_1
,
5636 FN_SEL_FM_0
, FN_SEL_FM_1
, FN_SEL_FM_2
, FN_SEL_FM_3
,
5637 FN_SEL_FM_4
, FN_SEL_FM_5
, FN_SEL_FM_6
, 0,
5638 /* SEL_HSCIF0 [3] */
5639 FN_SEL_HSCIF0_0
, FN_SEL_HSCIF0_1
, FN_SEL_HSCIF0_2
,
5640 FN_SEL_HSCIF0_3
, FN_SEL_HSCIF0_4
, FN_SEL_HSCIF0_5
, 0, 0,
5642 FN_SEL_GPS_0
, FN_SEL_GPS_1
, FN_SEL_GPS_2
, 0,
5644 0, 0, 0, 0, 0, 0, 0, 0,
5646 FN_SEL_SIM_0
, FN_SEL_SIM_1
, FN_SEL_SIM_2
, 0,
5648 FN_SEL_SSI8_0
, FN_SEL_SSI8_1
, FN_SEL_SSI8_2
, 0, }
5650 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5651 1, 1, 2, 4, 4, 2, 2,
5653 /* SEL_IICDVFS [1] */
5654 FN_SEL_IICDVFS_0
, FN_SEL_IICDVFS_1
,
5656 FN_SEL_IIC0_0
, FN_SEL_IIC0_1
,
5660 0, 0, 0, 0, 0, 0, 0, 0,
5661 0, 0, 0, 0, 0, 0, 0, 0,
5663 0, 0, 0, 0, 0, 0, 0, 0,
5664 0, 0, 0, 0, 0, 0, 0, 0,
5668 FN_SEL_IEB_0
, FN_SEL_IEB_1
, FN_SEL_IEB_2
, 0,
5670 0, 0, 0, 0, 0, 0, 0, 0,
5671 0, 0, 0, 0, 0, 0, 0, 0,
5675 FN_SEL_IIC2_0
, FN_SEL_IIC2_1
, FN_SEL_IIC2_2
, FN_SEL_IIC2_3
,
5676 FN_SEL_IIC2_4
, 0, 0, 0,
5678 FN_SEL_IIC1_0
, FN_SEL_IIC1_1
, FN_SEL_IIC1_2
, 0,
5680 FN_SEL_I2C2_0
, FN_SEL_I2C2_1
, FN_SEL_I2C2_2
, FN_SEL_I2C2_3
,
5681 FN_SEL_I2C2_4
, 0, 0, 0,
5683 FN_SEL_I2C1_0
, FN_SEL_I2C1_1
, FN_SEL_I2C1_2
, 0, }
5688 const struct sh_pfc_soc_info r8a7790_pinmux_info
= {
5689 .name
= "r8a77900_pfc",
5690 .unlock_reg
= 0xe6060000, /* PMMR */
5692 .function
= { PINMUX_FUNCTION_BEGIN
, PINMUX_FUNCTION_END
},
5694 .pins
= pinmux_pins
,
5695 .nr_pins
= ARRAY_SIZE(pinmux_pins
),
5696 .groups
= pinmux_groups
,
5697 .nr_groups
= ARRAY_SIZE(pinmux_groups
),
5698 .functions
= pinmux_functions
,
5699 .nr_functions
= ARRAY_SIZE(pinmux_functions
),
5701 .cfg_regs
= pinmux_config_regs
,
5703 .gpio_data
= pinmux_data
,
5704 .gpio_data_size
= ARRAY_SIZE(pinmux_data
),