2 * r8a7791 processor support - PFC hardware block.
4 * Copyright (C) 2013 Renesas Electronics Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/platform_data/gpio-rcar.h>
17 #define PORT_GP_26(bank, fn, sfx) \
18 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
19 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
20 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
21 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
22 PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
23 PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
24 PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
25 PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
26 PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
27 PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
28 PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
29 PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
30 PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx)
32 #define CPU_ALL_PORT(fn, sfx) \
33 PORT_GP_32(0, fn, sfx), \
34 PORT_GP_26(1, fn, sfx), \
35 PORT_GP_32(2, fn, sfx), \
36 PORT_GP_32(3, fn, sfx), \
37 PORT_GP_32(4, fn, sfx), \
38 PORT_GP_32(5, fn, sfx), \
39 PORT_GP_32(6, fn, sfx), \
40 PORT_GP_26(7, fn, sfx)
49 PINMUX_FUNCTION_BEGIN
,
53 FN_IP0_0
, FN_IP0_1
, FN_IP0_2
, FN_IP0_3
, FN_IP0_4
, FN_IP0_5
,
54 FN_IP0_6
, FN_IP0_7
, FN_IP0_8
, FN_IP0_9
, FN_IP0_10
, FN_IP0_11
,
55 FN_IP0_12
, FN_IP0_13
, FN_IP0_14
, FN_IP0_15
, FN_IP0_18_16
, FN_IP0_20_19
,
56 FN_IP0_22_21
, FN_IP0_24_23
, FN_IP0_26_25
, FN_IP0_28_27
, FN_IP0_30_29
,
57 FN_IP1_1_0
, FN_IP1_3_2
, FN_IP1_5_4
, FN_IP1_7_6
, FN_IP1_10_8
,
58 FN_IP1_13_11
, FN_IP1_16_14
, FN_IP1_19_17
, FN_IP1_22_20
,
61 FN_IP1_25_23
, FN_IP1_28_26
, FN_IP1_31_29
, FN_IP2_2_0
, FN_IP2_4_3
,
62 FN_IP2_6_5
, FN_IP2_9_7
, FN_IP2_12_10
, FN_IP2_15_13
, FN_IP2_18_16
,
63 FN_IP2_20_19
, FN_IP2_22_21
, FN_EX_CS0_N
, FN_IP2_24_23
, FN_IP2_26_25
,
64 FN_IP2_29_27
, FN_IP3_2_0
, FN_IP3_5_3
, FN_IP3_8_6
, FN_RD_N
,
65 FN_IP3_11_9
, FN_IP3_13_12
, FN_IP3_15_14
, FN_IP3_17_16
, FN_IP3_19_18
,
69 FN_IP3_27_25
, FN_IP3_30_28
, FN_IP4_1_0
, FN_IP4_4_2
, FN_IP4_7_5
,
70 FN_IP4_9_8
, FN_IP4_12_10
, FN_IP4_15_13
, FN_IP4_18_16
, FN_IP4_19
,
71 FN_IP4_20
, FN_IP4_21
, FN_IP4_23_22
, FN_IP4_25_24
, FN_IP4_27_26
,
72 FN_IP4_30_28
, FN_IP5_2_0
, FN_IP5_5_3
, FN_IP5_8_6
, FN_IP5_11_9
,
73 FN_IP5_14_12
, FN_IP5_16_15
, FN_IP5_19_17
, FN_IP5_21_20
, FN_IP5_23_22
,
74 FN_IP5_25_24
, FN_IP5_28_26
, FN_IP5_31_29
, FN_AUDIO_CLKA
, FN_IP6_2_0
,
75 FN_IP6_5_3
, FN_IP6_7_6
,
78 FN_IP7_5_3
, FN_IP7_8_6
, FN_IP7_10_9
, FN_IP7_12_11
, FN_IP7_14_13
,
79 FN_IP7_16_15
, FN_IP7_18_17
, FN_IP7_20_19
, FN_IP7_23_21
, FN_IP7_26_24
,
80 FN_IP7_29_27
, FN_IP8_2_0
, FN_IP8_5_3
, FN_IP8_8_6
, FN_IP8_11_9
,
81 FN_IP8_14_12
, FN_IP8_17_15
, FN_IP8_20_18
, FN_IP8_23_21
, FN_IP8_25_24
,
82 FN_IP8_27_26
, FN_IP8_30_28
, FN_IP9_2_0
, FN_IP9_5_3
, FN_IP9_6
, FN_IP9_7
,
83 FN_IP9_10_8
, FN_IP9_11
, FN_IP9_12
, FN_IP9_15_13
, FN_IP9_16
,
87 FN_VI0_CLK
, FN_IP9_20_19
, FN_IP9_22_21
, FN_IP9_24_23
, FN_IP9_26_25
,
88 FN_VI0_DATA0_VI0_B0
, FN_VI0_DATA1_VI0_B1
, FN_VI0_DATA2_VI0_B2
,
89 FN_IP9_28_27
, FN_VI0_DATA4_VI0_B4
, FN_VI0_DATA5_VI0_B5
,
90 FN_VI0_DATA6_VI0_B6
, FN_VI0_DATA7_VI0_B7
, FN_IP9_31_29
, FN_IP10_2_0
,
91 FN_IP10_5_3
, FN_IP10_8_6
, FN_IP10_11_9
, FN_IP10_14_12
, FN_IP10_16_15
,
92 FN_IP10_18_17
, FN_IP10_21_19
, FN_IP10_24_22
, FN_IP10_26_25
,
93 FN_IP10_28_27
, FN_IP10_31_29
, FN_IP11_2_0
, FN_IP11_5_3
, FN_IP11_8_6
,
94 FN_IP15_1_0
, FN_IP15_3_2
, FN_IP15_5_4
,
97 FN_IP11_11_9
, FN_IP11_14_12
, FN_IP11_16_15
, FN_IP11_18_17
, FN_IP11_19
,
98 FN_IP11_20
, FN_IP11_21
, FN_IP11_22
, FN_IP11_23
, FN_IP11_24
,
99 FN_IP11_25
, FN_IP11_26
, FN_IP11_27
, FN_IP11_29_28
, FN_IP11_31_30
,
100 FN_IP12_1_0
, FN_IP12_3_2
, FN_IP12_6_4
, FN_IP12_9_7
, FN_IP12_12_10
,
101 FN_IP12_15_13
, FN_IP12_17_16
, FN_IP12_19_18
, FN_IP12_21_20
,
102 FN_IP12_23_22
, FN_IP12_26_24
, FN_IP12_29_27
, FN_IP13_2_0
, FN_IP13_4_3
,
103 FN_IP13_6_5
, FN_IP13_9_7
, FN_IP3_24_22
,
106 FN_IP13_10
, FN_IP13_11
, FN_IP13_12
, FN_IP13_13
, FN_IP13_14
,
107 FN_IP13_15
, FN_IP13_18_16
, FN_IP13_21_19
,
108 FN_IP13_22
, FN_IP13_24_23
, FN_SD1_CLK
,
109 FN_IP13_25
, FN_IP13_26
, FN_IP13_27
, FN_IP13_30_28
, FN_IP14_1_0
,
110 FN_IP14_2
, FN_IP14_3
, FN_IP14_4
, FN_IP14_5
, FN_IP14_6
, FN_IP14_7
,
111 FN_IP14_10_8
, FN_IP14_13_11
, FN_IP14_16_14
, FN_IP14_19_17
,
112 FN_IP14_22_20
, FN_IP14_25_23
, FN_IP14_28_26
, FN_IP14_31_29
,
113 FN_USB1_OVC
, FN_DU0_DOTCLKIN
,
116 FN_IP15_17_15
, FN_IP15_20_18
, FN_IP15_23_21
, FN_IP15_26_24
,
117 FN_IP15_29_27
, FN_IP16_2_0
, FN_IP16_5_3
, FN_IP16_7_6
, FN_IP16_9_8
,
118 FN_IP16_11_10
, FN_IP6_9_8
, FN_IP6_11_10
, FN_IP6_13_12
, FN_IP6_15_14
,
119 FN_IP6_18_16
, FN_IP6_20_19
, FN_IP6_23_21
, FN_IP6_26_24
, FN_IP6_29_27
,
120 FN_IP7_2_0
, FN_IP15_8_6
, FN_IP15_11_9
, FN_IP15_14_12
,
121 FN_USB0_PWEN
, FN_USB0_OVC
, FN_USB1_PWEN
,
124 FN_D0
, FN_D1
, FN_D2
, FN_D3
, FN_D4
, FN_D5
, FN_D6
, FN_D7
, FN_D8
,
125 FN_D9
, FN_D10
, FN_D11
, FN_D12
, FN_D13
, FN_D14
, FN_D15
,
126 FN_A0
, FN_ATAWR0_N_C
, FN_MSIOF0_SCK_B
, FN_SCL0_C
, FN_PWM2_B
,
127 FN_A1
, FN_MSIOF0_SYNC_B
, FN_A2
, FN_MSIOF0_SS1_B
,
128 FN_A3
, FN_MSIOF0_SS2_B
, FN_A4
, FN_MSIOF0_TXD_B
,
129 FN_A5
, FN_MSIOF0_RXD_B
, FN_A6
, FN_MSIOF1_SCK
,
132 FN_A7
, FN_MSIOF1_SYNC
, FN_A8
, FN_MSIOF1_SS1
, FN_SCL0
,
133 FN_A9
, FN_MSIOF1_SS2
, FN_SDA0
,
134 FN_A10
, FN_MSIOF1_TXD
, FN_MSIOF1_TXD_D
,
135 FN_A11
, FN_MSIOF1_RXD
, FN_SCL3_D
, FN_MSIOF1_RXD_D
,
136 FN_A12
, FN_FMCLK
, FN_SDA3_D
, FN_MSIOF1_SCK_D
,
137 FN_A13
, FN_ATAG0_N_C
, FN_BPFCLK
, FN_MSIOF1_SS1_D
,
138 FN_A14
, FN_ATADIR0_N_C
, FN_FMIN
, FN_FMIN_C
, FN_MSIOF1_SYNC_D
,
140 FN_A16
, FN_DREQ2_B
, FN_FMCLK_C
, FN_SCIFA1_SCK_B
,
141 FN_A17
, FN_DACK2_B
, FN_SDA0_C
,
142 FN_A18
, FN_DREQ1
, FN_SCIFA1_RXD_C
, FN_SCIFB1_RXD_C
,
145 FN_A19
, FN_DACK1
, FN_SCIFA1_TXD_C
, FN_SCIFB1_TXD_C
, FN_SCIFB1_SCK_B
,
147 FN_A21
, FN_ATAWR0_N_B
, FN_MOSI_IO0
,
148 FN_A22
, FN_MISO_IO1
, FN_FMCLK_B
, FN_TX0
, FN_SCIFA0_TXD
,
149 FN_A23
, FN_IO2
, FN_BPFCLK_B
, FN_RX0
, FN_SCIFA0_RXD
,
150 FN_A24
, FN_DREQ2
, FN_IO3
, FN_TX1
, FN_SCIFA1_TXD
,
151 FN_A25
, FN_DACK2
, FN_SSL
, FN_DREQ1_C
, FN_RX1
, FN_SCIFA1_RXD
,
152 FN_CS0_N
, FN_ATAG0_N_B
, FN_SCL1
,
153 FN_CS1_N_A26
, FN_ATADIR0_N_B
, FN_SDA1
,
154 FN_EX_CS1_N
, FN_MSIOF2_SCK
,
155 FN_EX_CS2_N
, FN_ATAWR0_N
, FN_MSIOF2_SYNC
,
156 FN_EX_CS3_N
, FN_ATADIR0_N
, FN_MSIOF2_TXD
, FN_ATAG0_N
, FN_EX_WAIT1
,
159 FN_EX_CS4_N
, FN_ATARD0_N
, FN_MSIOF2_RXD
, FN_EX_WAIT2
,
160 FN_EX_CS5_N
, FN_ATACS00_N
, FN_MSIOF2_SS1
, FN_HRX1_B
,
161 FN_SCIFB1_RXD_B
, FN_PWM1
, FN_TPU_TO1
,
162 FN_BS_N
, FN_ATACS10_N
, FN_MSIOF2_SS2
, FN_HTX1_B
,
163 FN_SCIFB1_TXD_B
, FN_PWM2
, FN_TPU_TO2
,
164 FN_RD_WR_N
, FN_HRX2_B
, FN_FMIN_B
, FN_SCIFB0_RXD_B
, FN_DREQ1_D
,
165 FN_WE0_N
, FN_HCTS2_N_B
, FN_SCIFB0_TXD_B
,
166 FN_WE1_N
, FN_ATARD0_N_B
, FN_HTX2_B
, FN_SCIFB0_RTS_N_B
,
167 FN_EX_WAIT0
, FN_HRTS2_N_B
, FN_SCIFB0_CTS_N_B
,
168 FN_DREQ0
, FN_PWM3
, FN_TPU_TO3
,
169 FN_DACK0
, FN_DRACK0
, FN_REMOCON
,
170 FN_SPEEDIN
, FN_HSCK0_C
, FN_HSCK2_C
, FN_SCIFB0_SCK_B
,
171 FN_SCIFB2_SCK_B
, FN_DREQ2_C
, FN_HTX2_D
,
172 FN_SSI_SCK0129
, FN_HRX0_C
, FN_HRX2_C
, FN_SCIFB0_RXD_C
, FN_SCIFB2_RXD_C
,
173 FN_SSI_WS0129
, FN_HTX0_C
, FN_HTX2_C
, FN_SCIFB0_TXD_C
, FN_SCIFB2_TXD_C
,
176 FN_SSI_SDATA0
, FN_SCL0_B
, FN_SCL7_B
, FN_MSIOF2_SCK_C
,
177 FN_SSI_SCK1
, FN_SDA0_B
, FN_SDA7_B
, FN_MSIOF2_SYNC_C
, FN_GLO_I0_D
,
178 FN_SSI_WS1
, FN_SCL1_B
, FN_SCL8_B
, FN_MSIOF2_TXD_C
, FN_GLO_I1_D
,
179 FN_SSI_SDATA1
, FN_SDA1_B
, FN_SDA8_B
, FN_MSIOF2_RXD_C
,
180 FN_SSI_SCK2
, FN_SCL2
, FN_GPS_CLK_B
, FN_GLO_Q0_D
, FN_HSCK1_E
,
181 FN_SSI_WS2
, FN_SDA2
, FN_GPS_SIGN_B
, FN_RX2_E
,
182 FN_GLO_Q1_D
, FN_HCTS1_N_E
,
183 FN_SSI_SDATA2
, FN_GPS_MAG_B
, FN_TX2_E
, FN_HRTS1_N_E
,
184 FN_SSI_SCK34
, FN_SSI_WS34
, FN_SSI_SDATA3
,
185 FN_SSI_SCK4
, FN_GLO_SS_D
,
186 FN_SSI_WS4
, FN_GLO_RFON_D
,
187 FN_SSI_SDATA4
, FN_MSIOF2_SCK_D
,
188 FN_SSI_SCK5
, FN_MSIOF1_SCK_C
, FN_TS_SDATA0
, FN_GLO_I0
,
189 FN_MSIOF2_SYNC_D
, FN_VI1_R2_B
,
192 FN_SSI_WS5
, FN_MSIOF1_SYNC_C
, FN_TS_SCK0
, FN_GLO_I1
,
193 FN_MSIOF2_TXD_D
, FN_VI1_R3_B
,
194 FN_SSI_SDATA5
, FN_MSIOF1_TXD_C
, FN_TS_SDEN0
, FN_GLO_Q0
,
195 FN_MSIOF2_SS1_D
, FN_VI1_R4_B
,
196 FN_SSI_SCK6
, FN_MSIOF1_RXD_C
, FN_TS_SPSYNC0
, FN_GLO_Q1
,
197 FN_MSIOF2_RXD_D
, FN_VI1_R5_B
,
198 FN_SSI_WS6
, FN_GLO_SCLK
, FN_MSIOF2_SS2_D
, FN_VI1_R6_B
,
199 FN_SSI_SDATA6
, FN_STP_IVCXO27_0_B
, FN_GLO_SDATA
, FN_VI1_R7_B
,
200 FN_SSI_SCK78
, FN_STP_ISCLK_0_B
, FN_GLO_SS
,
201 FN_SSI_WS78
, FN_TX0_D
, FN_STP_ISD_0_B
, FN_GLO_RFON
,
202 FN_SSI_SDATA7
, FN_RX0_D
, FN_STP_ISEN_0_B
,
203 FN_SSI_SDATA8
, FN_TX1_D
, FN_STP_ISSYNC_0_B
,
204 FN_SSI_SCK9
, FN_RX1_D
, FN_GLO_SCLK_D
,
205 FN_SSI_WS9
, FN_TX3_D
, FN_CAN0_TX_D
, FN_GLO_SDATA_D
,
206 FN_SSI_SDATA9
, FN_RX3_D
, FN_CAN0_RX_D
,
209 FN_AUDIO_CLKB
, FN_STP_OPWM_0_B
, FN_MSIOF1_SCK_B
,
210 FN_SCIF_CLK
, FN_BPFCLK_E
,
211 FN_AUDIO_CLKC
, FN_SCIFB0_SCK_C
, FN_MSIOF1_SYNC_B
, FN_RX2
,
212 FN_SCIFA2_RXD
, FN_FMIN_E
,
213 FN_AUDIO_CLKOUT
, FN_MSIOF1_SS1_B
, FN_TX2
, FN_SCIFA2_TXD
,
214 FN_IRQ0
, FN_SCIFB1_RXD_D
, FN_INTC_IRQ0_N
,
215 FN_IRQ1
, FN_SCIFB1_SCK_C
, FN_INTC_IRQ1_N
,
216 FN_IRQ2
, FN_SCIFB1_TXD_D
, FN_INTC_IRQ2_N
,
217 FN_IRQ3
, FN_SCL4_C
, FN_MSIOF2_TXD_E
, FN_INTC_IRQ3_N
,
218 FN_IRQ4
, FN_HRX1_C
, FN_SDA4_C
, FN_MSIOF2_RXD_E
, FN_INTC_IRQ4_N
,
219 FN_IRQ5
, FN_HTX1_C
, FN_SCL1_E
, FN_MSIOF2_SCK_E
,
220 FN_IRQ6
, FN_HSCK1_C
, FN_MSIOF1_SS2_B
, FN_SDA1_E
, FN_MSIOF2_SYNC_E
,
221 FN_IRQ7
, FN_HCTS1_N_C
, FN_MSIOF1_TXD_B
, FN_GPS_CLK_C
, FN_GPS_CLK_D
,
222 FN_IRQ8
, FN_HRTS1_N_C
, FN_MSIOF1_RXD_B
, FN_GPS_SIGN_C
, FN_GPS_SIGN_D
,
225 FN_IRQ9
, FN_DU1_DOTCLKIN_B
, FN_CAN_CLK_D
, FN_GPS_MAG_C
,
226 FN_SCIF_CLK_B
, FN_GPS_MAG_D
,
227 FN_DU1_DR0
, FN_LCDOUT0
, FN_VI1_DATA0_B
, FN_TX0_B
,
228 FN_SCIFA0_TXD_B
, FN_MSIOF2_SCK_B
,
229 FN_DU1_DR1
, FN_LCDOUT1
, FN_VI1_DATA1_B
, FN_RX0_B
,
230 FN_SCIFA0_RXD_B
, FN_MSIOF2_SYNC_B
,
231 FN_DU1_DR2
, FN_LCDOUT2
, FN_SSI_SCK0129_B
,
232 FN_DU1_DR3
, FN_LCDOUT3
, FN_SSI_WS0129_B
,
233 FN_DU1_DR4
, FN_LCDOUT4
, FN_SSI_SDATA0_B
,
234 FN_DU1_DR5
, FN_LCDOUT5
, FN_SSI_SCK1_B
,
235 FN_DU1_DR6
, FN_LCDOUT6
, FN_SSI_WS1_B
,
236 FN_DU1_DR7
, FN_LCDOUT7
, FN_SSI_SDATA1_B
,
237 FN_DU1_DG0
, FN_LCDOUT8
, FN_VI1_DATA2_B
, FN_TX1_B
,
238 FN_SCIFA1_TXD_B
, FN_MSIOF2_SS1_B
,
239 FN_DU1_DG1
, FN_LCDOUT9
, FN_VI1_DATA3_B
, FN_RX1_B
,
240 FN_SCIFA1_RXD_B
, FN_MSIOF2_SS2_B
,
241 FN_DU1_DG2
, FN_LCDOUT10
, FN_VI1_DATA4_B
, FN_SCIF1_SCK_B
,
242 FN_SCIFA1_SCK
, FN_SSI_SCK78_B
,
245 FN_DU1_DG3
, FN_LCDOUT11
, FN_VI1_DATA5_B
, FN_SSI_WS78_B
,
246 FN_DU1_DG4
, FN_LCDOUT12
, FN_VI1_DATA6_B
, FN_HRX0_B
,
247 FN_SCIFB2_RXD_B
, FN_SSI_SDATA7_B
,
248 FN_DU1_DG5
, FN_LCDOUT13
, FN_VI1_DATA7_B
, FN_HCTS0_N_B
,
249 FN_SCIFB2_TXD_B
, FN_SSI_SDATA8_B
,
250 FN_DU1_DG6
, FN_LCDOUT14
, FN_HRTS0_N_B
,
251 FN_SCIFB2_CTS_N_B
, FN_SSI_SCK9_B
,
252 FN_DU1_DG7
, FN_LCDOUT15
, FN_HTX0_B
, FN_SCIFB2_RTS_N_B
, FN_SSI_WS9_B
,
253 FN_DU1_DB0
, FN_LCDOUT16
, FN_VI1_CLK_B
, FN_TX2_B
,
254 FN_SCIFA2_TXD_B
, FN_MSIOF2_TXD_B
,
255 FN_DU1_DB1
, FN_LCDOUT17
, FN_VI1_HSYNC_N_B
, FN_RX2_B
,
256 FN_SCIFA2_RXD_B
, FN_MSIOF2_RXD_B
,
257 FN_DU1_DB2
, FN_LCDOUT18
, FN_VI1_VSYNC_N_B
, FN_SCIF2_SCK_B
,
258 FN_SCIFA2_SCK
, FN_SSI_SDATA9_B
,
259 FN_DU1_DB3
, FN_LCDOUT19
, FN_VI1_CLKENB_B
,
260 FN_DU1_DB4
, FN_LCDOUT20
, FN_VI1_FIELD_B
, FN_CAN1_RX
,
261 FN_DU1_DB5
, FN_LCDOUT21
, FN_TX3
, FN_SCIFA3_TXD
, FN_CAN1_TX
,
264 FN_DU1_DB6
, FN_LCDOUT22
, FN_SCL3_C
, FN_RX3
, FN_SCIFA3_RXD
,
265 FN_DU1_DB7
, FN_LCDOUT23
, FN_SDA3_C
, FN_SCIF3_SCK
, FN_SCIFA3_SCK
,
266 FN_DU1_DOTCLKIN
, FN_QSTVA_QVS
,
267 FN_DU1_DOTCLKOUT0
, FN_QCLK
,
268 FN_DU1_DOTCLKOUT1
, FN_QSTVB_QVE
, FN_CAN0_TX
,
269 FN_TX3_B
, FN_SCL2_B
, FN_PWM4
,
270 FN_DU1_EXHSYNC_DU1_HSYNC
, FN_QSTH_QHS
,
271 FN_DU1_EXVSYNC_DU1_VSYNC
, FN_QSTB_QHE
,
272 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE
, FN_QCPV_QDE
,
273 FN_CAN0_RX
, FN_RX3_B
, FN_SDA2_B
,
274 FN_DU1_DISP
, FN_QPOLA
,
275 FN_DU1_CDE
, FN_QPOLB
, FN_PWM4_B
,
276 FN_VI0_CLKENB
, FN_TX4
, FN_SCIFA4_TXD
, FN_TS_SDATA0_D
,
277 FN_VI0_FIELD
, FN_RX4
, FN_SCIFA4_RXD
, FN_TS_SCK0_D
,
278 FN_VI0_HSYNC_N
, FN_TX5
, FN_SCIFA5_TXD
, FN_TS_SDEN0_D
,
279 FN_VI0_VSYNC_N
, FN_RX5
, FN_SCIFA5_RXD
, FN_TS_SPSYNC0_D
,
280 FN_VI0_DATA3_VI0_B3
, FN_SCIF3_SCK_B
, FN_SCIFA3_SCK_B
,
281 FN_VI0_G0
, FN_SCL8
, FN_STP_IVCXO27_0_C
, FN_SCL4
,
282 FN_HCTS2_N
, FN_SCIFB2_CTS_N
, FN_ATAWR1_N
,
285 FN_VI0_G1
, FN_SDA8
, FN_STP_ISCLK_0_C
, FN_SDA4
,
286 FN_HRTS2_N
, FN_SCIFB2_RTS_N
, FN_ATADIR1_N
,
287 FN_VI0_G2
, FN_VI2_HSYNC_N
, FN_STP_ISD_0_C
, FN_SCL3_B
,
288 FN_HSCK2
, FN_SCIFB2_SCK
, FN_ATARD1_N
,
289 FN_VI0_G3
, FN_VI2_VSYNC_N
, FN_STP_ISEN_0_C
, FN_SDA3_B
,
290 FN_HRX2
, FN_SCIFB2_RXD
, FN_ATACS01_N
,
291 FN_VI0_G4
, FN_VI2_CLKENB
, FN_STP_ISSYNC_0_C
,
292 FN_HTX2
, FN_SCIFB2_TXD
, FN_SCIFB0_SCK_D
,
293 FN_VI0_G5
, FN_VI2_FIELD
, FN_STP_OPWM_0_C
, FN_FMCLK_D
,
294 FN_CAN0_TX_E
, FN_HTX1_D
, FN_SCIFB0_TXD_D
,
295 FN_VI0_G6
, FN_VI2_CLK
, FN_BPFCLK_D
,
296 FN_VI0_G7
, FN_VI2_DATA0
, FN_FMIN_D
,
297 FN_VI0_R0
, FN_VI2_DATA1
, FN_GLO_I0_B
,
298 FN_TS_SDATA0_C
, FN_ATACS11_N
,
299 FN_VI0_R1
, FN_VI2_DATA2
, FN_GLO_I1_B
,
300 FN_TS_SCK0_C
, FN_ATAG1_N
,
301 FN_VI0_R2
, FN_VI2_DATA3
, FN_GLO_Q0_B
, FN_TS_SDEN0_C
,
302 FN_VI0_R3
, FN_VI2_DATA4
, FN_GLO_Q1_B
, FN_TS_SPSYNC0_C
,
303 FN_VI0_R4
, FN_VI2_DATA5
, FN_GLO_SCLK_B
, FN_TX0_C
, FN_SCL1_D
,
306 FN_VI0_R5
, FN_VI2_DATA6
, FN_GLO_SDATA_B
, FN_RX0_C
, FN_SDA1_D
,
307 FN_VI0_R6
, FN_VI2_DATA7
, FN_GLO_SS_B
, FN_TX1_C
, FN_SCL4_B
,
308 FN_VI0_R7
, FN_GLO_RFON_B
, FN_RX1_C
, FN_CAN0_RX_E
,
309 FN_SDA4_B
, FN_HRX1_D
, FN_SCIFB0_RXD_D
,
310 FN_VI1_HSYNC_N
, FN_AVB_RXD0
, FN_TS_SDATA0_B
, FN_TX4_B
, FN_SCIFA4_TXD_B
,
311 FN_VI1_VSYNC_N
, FN_AVB_RXD1
, FN_TS_SCK0_B
, FN_RX4_B
, FN_SCIFA4_RXD_B
,
312 FN_VI1_CLKENB
, FN_AVB_RXD2
, FN_TS_SDEN0_B
,
313 FN_VI1_FIELD
, FN_AVB_RXD3
, FN_TS_SPSYNC0_B
,
314 FN_VI1_CLK
, FN_AVB_RXD4
, FN_VI1_DATA0
, FN_AVB_RXD5
,
315 FN_VI1_DATA1
, FN_AVB_RXD6
, FN_VI1_DATA2
, FN_AVB_RXD7
,
316 FN_VI1_DATA3
, FN_AVB_RX_ER
, FN_VI1_DATA4
, FN_AVB_MDIO
,
317 FN_VI1_DATA5
, FN_AVB_RX_DV
, FN_VI1_DATA6
, FN_AVB_MAGIC
,
318 FN_VI1_DATA7
, FN_AVB_MDC
,
319 FN_ETH_MDIO
, FN_AVB_RX_CLK
, FN_SCL2_C
,
320 FN_ETH_CRS_DV
, FN_AVB_LINK
, FN_SDA2_C
,
323 FN_ETH_RX_ER
, FN_AVB_CRS
, FN_SCL3
, FN_SCL7
,
324 FN_ETH_RXD0
, FN_AVB_PHY_INT
, FN_SDA3
, FN_SDA7
,
325 FN_ETH_RXD1
, FN_AVB_GTXREFCLK
, FN_CAN0_TX_C
,
326 FN_SCL2_D
, FN_MSIOF1_RXD_E
,
327 FN_ETH_LINK
, FN_AVB_TXD0
, FN_CAN0_RX_C
, FN_SDA2_D
, FN_MSIOF1_SCK_E
,
328 FN_ETH_REFCLK
, FN_AVB_TXD1
, FN_SCIFA3_RXD_B
,
329 FN_CAN1_RX_C
, FN_MSIOF1_SYNC_E
,
330 FN_ETH_TXD1
, FN_AVB_TXD2
, FN_SCIFA3_TXD_B
,
331 FN_CAN1_TX_C
, FN_MSIOF1_TXD_E
,
332 FN_ETH_TX_EN
, FN_AVB_TXD3
, FN_TCLK1_B
, FN_CAN_CLK_B
,
333 FN_ETH_MAGIC
, FN_AVB_TXD4
, FN_IETX_C
,
334 FN_ETH_TXD0
, FN_AVB_TXD5
, FN_IECLK_C
,
335 FN_ETH_MDC
, FN_AVB_TXD6
, FN_IERX_C
,
336 FN_STP_IVCXO27_0
, FN_AVB_TXD7
, FN_SCIFB2_TXD_D
,
337 FN_ADIDATA_B
, FN_MSIOF0_SYNC_C
,
338 FN_STP_ISCLK_0
, FN_AVB_TX_EN
, FN_SCIFB2_RXD_D
,
339 FN_ADICS_SAMP_B
, FN_MSIOF0_SCK_C
,
342 FN_STP_ISD_0
, FN_AVB_TX_ER
, FN_SCIFB2_SCK_C
,
343 FN_ADICLK_B
, FN_MSIOF0_SS1_C
,
344 FN_STP_ISEN_0
, FN_AVB_TX_CLK
, FN_ADICHS0_B
, FN_MSIOF0_SS2_C
,
345 FN_STP_ISSYNC_0
, FN_AVB_COL
, FN_ADICHS1_B
, FN_MSIOF0_RXD_C
,
346 FN_STP_OPWM_0
, FN_AVB_GTX_CLK
, FN_PWM0_B
,
347 FN_ADICHS2_B
, FN_MSIOF0_TXD_C
,
348 FN_SD0_CLK
, FN_SPCLK_B
, FN_SD0_CMD
, FN_MOSI_IO0_B
,
349 FN_SD0_DATA0
, FN_MISO_IO1_B
, FN_SD0_DATA1
, FN_IO2_B
,
350 FN_SD0_DATA2
, FN_IO3_B
, FN_SD0_DATA3
, FN_SSL_B
,
351 FN_SD0_CD
, FN_MMC_D6_B
, FN_SIM0_RST_B
, FN_CAN0_RX_F
,
352 FN_SCIFA5_TXD_B
, FN_TX3_C
,
353 FN_SD0_WP
, FN_MMC_D7_B
, FN_SIM0_D_B
, FN_CAN0_TX_F
,
354 FN_SCIFA5_RXD_B
, FN_RX3_C
,
355 FN_SD1_CMD
, FN_REMOCON_B
, FN_SD1_DATA0
, FN_SPEEDIN_B
,
356 FN_SD1_DATA1
, FN_IETX_B
, FN_SD1_DATA2
, FN_IECLK_B
,
357 FN_SD1_DATA3
, FN_IERX_B
,
358 FN_SD1_CD
, FN_PWM0
, FN_TPU_TO0
, FN_SCL1_C
,
361 FN_SD1_WP
, FN_PWM1_B
, FN_SDA1_C
,
362 FN_SD2_CLK
, FN_MMC_CLK
, FN_SD2_CMD
, FN_MMC_CMD
,
363 FN_SD2_DATA0
, FN_MMC_D0
, FN_SD2_DATA1
, FN_MMC_D1
,
364 FN_SD2_DATA2
, FN_MMC_D2
, FN_SD2_DATA3
, FN_MMC_D3
,
365 FN_SD2_CD
, FN_MMC_D4
, FN_SCL8_C
, FN_TX5_B
, FN_SCIFA5_TXD_C
,
366 FN_SD2_WP
, FN_MMC_D5
, FN_SDA8_C
, FN_RX5_B
, FN_SCIFA5_RXD_C
,
367 FN_MSIOF0_SCK
, FN_RX2_C
, FN_ADIDATA
, FN_VI1_CLK_C
, FN_VI1_G0_B
,
368 FN_MSIOF0_SYNC
, FN_TX2_C
, FN_ADICS_SAMP
, FN_VI1_CLKENB_C
, FN_VI1_G1_B
,
369 FN_MSIOF0_TXD
, FN_ADICLK
, FN_VI1_FIELD_C
, FN_VI1_G2_B
,
370 FN_MSIOF0_RXD
, FN_ADICHS0
, FN_VI1_DATA0_C
, FN_VI1_G3_B
,
371 FN_MSIOF0_SS1
, FN_MMC_D6
, FN_ADICHS1
, FN_TX0_E
,
372 FN_VI1_HSYNC_N_C
, FN_SCL7_C
, FN_VI1_G4_B
,
373 FN_MSIOF0_SS2
, FN_MMC_D7
, FN_ADICHS2
, FN_RX0_E
,
374 FN_VI1_VSYNC_N_C
, FN_SDA7_C
, FN_VI1_G5_B
,
377 FN_SIM0_RST
, FN_IETX
, FN_CAN1_TX_D
,
378 FN_SIM0_CLK
, FN_IECLK
, FN_CAN_CLK_C
,
379 FN_SIM0_D
, FN_IERX
, FN_CAN1_RX_D
,
380 FN_GPS_CLK
, FN_DU1_DOTCLKIN_C
, FN_AUDIO_CLKB_B
,
381 FN_PWM5_B
, FN_SCIFA3_TXD_C
,
382 FN_GPS_SIGN
, FN_TX4_C
, FN_SCIFA4_TXD_C
, FN_PWM5
,
383 FN_VI1_G6_B
, FN_SCIFA3_RXD_C
,
384 FN_GPS_MAG
, FN_RX4_C
, FN_SCIFA4_RXD_C
, FN_PWM6
,
385 FN_VI1_G7_B
, FN_SCIFA3_SCK_C
,
386 FN_HCTS0_N
, FN_SCIFB0_CTS_N
, FN_GLO_I0_C
, FN_TCLK1
, FN_VI1_DATA1_C
,
387 FN_HRTS0_N
, FN_SCIFB0_RTS_N
, FN_GLO_I1_C
, FN_VI1_DATA2_C
,
388 FN_HSCK0
, FN_SCIFB0_SCK
, FN_GLO_Q0_C
, FN_CAN_CLK
,
389 FN_TCLK2
, FN_VI1_DATA3_C
,
390 FN_HRX0
, FN_SCIFB0_RXD
, FN_GLO_Q1_C
, FN_CAN0_RX_B
, FN_VI1_DATA4_C
,
391 FN_HTX0
, FN_SCIFB0_TXD
, FN_GLO_SCLK_C
, FN_CAN0_TX_B
, FN_VI1_DATA5_C
,
394 FN_HRX1
, FN_SCIFB1_RXD
, FN_VI1_R0_B
, FN_GLO_SDATA_C
, FN_VI1_DATA6_C
,
395 FN_HTX1
, FN_SCIFB1_TXD
, FN_VI1_R1_B
, FN_GLO_SS_C
, FN_VI1_DATA7_C
,
396 FN_HSCK1
, FN_SCIFB1_SCK
, FN_MLB_CLK
, FN_GLO_RFON_C
,
397 FN_HCTS1_N
, FN_SCIFB1_CTS_N
, FN_MLB_SIG
, FN_CAN1_TX_B
,
398 FN_HRTS1_N
, FN_SCIFB1_RTS_N
, FN_MLB_DAT
, FN_CAN1_RX_B
,
401 FN_SEL_SCIF1_0
, FN_SEL_SCIF1_1
, FN_SEL_SCIF1_2
, FN_SEL_SCIF1_3
,
402 FN_SEL_SCIFB_0
, FN_SEL_SCIFB_1
, FN_SEL_SCIFB_2
, FN_SEL_SCIFB_3
,
403 FN_SEL_SCIFB2_0
, FN_SEL_SCIFB2_1
, FN_SEL_SCIFB2_2
, FN_SEL_SCIFB2_3
,
404 FN_SEL_SCIFB1_0
, FN_SEL_SCIFB1_1
, FN_SEL_SCIFB1_2
, FN_SEL_SCIFB1_3
,
405 FN_SEL_SCIFA1_0
, FN_SEL_SCIFA1_1
, FN_SEL_SCIFA1_2
,
406 FN_SEL_SSI9_0
, FN_SEL_SSI9_1
,
407 FN_SEL_SCFA_0
, FN_SEL_SCFA_1
,
408 FN_SEL_QSP_0
, FN_SEL_QSP_1
,
409 FN_SEL_SSI7_0
, FN_SEL_SSI7_1
,
410 FN_SEL_HSCIF1_0
, FN_SEL_HSCIF1_1
, FN_SEL_HSCIF1_2
, FN_SEL_HSCIF1_3
,
412 FN_SEL_VI1_0
, FN_SEL_VI1_1
, FN_SEL_VI1_2
,
413 FN_SEL_TMU1_0
, FN_SEL_TMU1_1
,
414 FN_SEL_LBS_0
, FN_SEL_LBS_1
, FN_SEL_LBS_2
, FN_SEL_LBS_3
,
415 FN_SEL_TSIF0_0
, FN_SEL_TSIF0_1
, FN_SEL_TSIF0_2
, FN_SEL_TSIF0_3
,
416 FN_SEL_SOF0_0
, FN_SEL_SOF0_1
, FN_SEL_SOF0_2
,
419 FN_SEL_SCIF0_0
, FN_SEL_SCIF0_1
, FN_SEL_SCIF0_2
, FN_SEL_SCIF0_3
,
421 FN_SEL_SCIF_0
, FN_SEL_SCIF_1
,
422 FN_SEL_CAN0_0
, FN_SEL_CAN0_1
, FN_SEL_CAN0_2
, FN_SEL_CAN0_3
,
423 FN_SEL_CAN0_4
, FN_SEL_CAN0_5
,
424 FN_SEL_CAN1_0
, FN_SEL_CAN1_1
, FN_SEL_CAN1_2
, FN_SEL_CAN1_3
,
425 FN_SEL_SCIFA2_0
, FN_SEL_SCIFA2_1
,
426 FN_SEL_SCIF4_0
, FN_SEL_SCIF4_1
, FN_SEL_SCIF4_2
,
427 FN_SEL_ADG_0
, FN_SEL_ADG_1
,
428 FN_SEL_FM_0
, FN_SEL_FM_1
, FN_SEL_FM_2
, FN_SEL_FM_3
, FN_SEL_FM_4
,
429 FN_SEL_SCIFA5_0
, FN_SEL_SCIFA5_1
, FN_SEL_SCIFA5_2
,
430 FN_SEL_GPS_0
, FN_SEL_GPS_1
, FN_SEL_GPS_2
, FN_SEL_GPS_3
,
431 FN_SEL_SCIFA4_0
, FN_SEL_SCIFA4_1
, FN_SEL_SCIFA4_2
,
432 FN_SEL_SCIFA3_0
, FN_SEL_SCIFA3_1
, FN_SEL_SCIFA3_2
,
433 FN_SEL_SIM_0
, FN_SEL_SIM_1
,
434 FN_SEL_SSI8_0
, FN_SEL_SSI8_1
,
437 FN_SEL_HSCIF2_0
, FN_SEL_HSCIF2_1
, FN_SEL_HSCIF2_2
, FN_SEL_HSCIF2_3
,
438 FN_SEL_CANCLK_0
, FN_SEL_CANCLK_1
, FN_SEL_CANCLK_2
, FN_SEL_CANCLK_3
,
439 FN_SEL_IIC8_0
, FN_SEL_IIC8_1
, FN_SEL_IIC8_2
,
440 FN_SEL_IIC7_0
, FN_SEL_IIC7_1
, FN_SEL_IIC7_2
,
441 FN_SEL_IIC4_0
, FN_SEL_IIC4_1
, FN_SEL_IIC4_2
,
442 FN_SEL_IIC3_0
, FN_SEL_IIC3_1
, FN_SEL_IIC3_2
, FN_SEL_IIC3_3
,
443 FN_SEL_SCIF3_0
, FN_SEL_SCIF3_1
, FN_SEL_SCIF3_2
, FN_SEL_SCIF3_3
,
444 FN_SEL_IEB_0
, FN_SEL_IEB_1
, FN_SEL_IEB_2
,
445 FN_SEL_MMC_0
, FN_SEL_MMC_1
,
446 FN_SEL_SCIF5_0
, FN_SEL_SCIF5_1
,
447 FN_SEL_IIC2_0
, FN_SEL_IIC2_1
, FN_SEL_IIC2_2
, FN_SEL_IIC2_3
,
448 FN_SEL_IIC1_0
, FN_SEL_IIC1_1
, FN_SEL_IIC1_2
, FN_SEL_IIC1_3
,
450 FN_SEL_IIC0_0
, FN_SEL_IIC0_1
, FN_SEL_IIC0_2
,
453 FN_SEL_SOF1_0
, FN_SEL_SOF1_1
, FN_SEL_SOF1_2
, FN_SEL_SOF1_3
,
455 FN_SEL_HSCIF0_0
, FN_SEL_HSCIF0_1
, FN_SEL_HSCIF0_2
,
456 FN_SEL_DIS_0
, FN_SEL_DIS_1
, FN_SEL_DIS_2
,
457 FN_SEL_RAD_0
, FN_SEL_RAD_1
,
458 FN_SEL_RCN_0
, FN_SEL_RCN_1
,
459 FN_SEL_RSP_0
, FN_SEL_RSP_1
,
460 FN_SEL_SCIF2_0
, FN_SEL_SCIF2_1
, FN_SEL_SCIF2_2
, FN_SEL_SCIF2_3
,
462 FN_SEL_SOF2_0
, FN_SEL_SOF2_1
, FN_SEL_SOF2_2
, FN_SEL_SOF2_3
,
464 FN_SEL_SSI1_0
, FN_SEL_SSI1_1
,
465 FN_SEL_SSI0_0
, FN_SEL_SSI0_1
,
466 FN_SEL_SSP_0
, FN_SEL_SSP_1
, FN_SEL_SSP_2
,
471 EX_CS0_N_MARK
, RD_N_MARK
,
475 VI0_CLK_MARK
, VI0_DATA0_VI0_B0_MARK
, VI0_DATA1_VI0_B1_MARK
,
476 VI0_DATA2_VI0_B2_MARK
, VI0_DATA4_VI0_B4_MARK
, VI0_DATA5_VI0_B5_MARK
,
477 VI0_DATA6_VI0_B6_MARK
, VI0_DATA7_VI0_B7_MARK
,
481 USB0_PWEN_MARK
, USB0_OVC_MARK
, USB1_PWEN_MARK
, USB1_OVC_MARK
,
485 D0_MARK
, D1_MARK
, D2_MARK
, D3_MARK
, D4_MARK
, D5_MARK
,
486 D6_MARK
, D7_MARK
, D8_MARK
,
487 D9_MARK
, D10_MARK
, D11_MARK
, D12_MARK
, D13_MARK
, D14_MARK
, D15_MARK
,
488 A0_MARK
, ATAWR0_N_C_MARK
, MSIOF0_SCK_B_MARK
, SCL0_C_MARK
, PWM2_B_MARK
,
489 A1_MARK
, MSIOF0_SYNC_B_MARK
, A2_MARK
, MSIOF0_SS1_B_MARK
,
490 A3_MARK
, MSIOF0_SS2_B_MARK
, A4_MARK
, MSIOF0_TXD_B_MARK
,
491 A5_MARK
, MSIOF0_RXD_B_MARK
, A6_MARK
, MSIOF1_SCK_MARK
,
494 A7_MARK
, MSIOF1_SYNC_MARK
, A8_MARK
, MSIOF1_SS1_MARK
, SCL0_MARK
,
495 A9_MARK
, MSIOF1_SS2_MARK
, SDA0_MARK
,
496 A10_MARK
, MSIOF1_TXD_MARK
, MSIOF1_TXD_D_MARK
,
497 A11_MARK
, MSIOF1_RXD_MARK
, SCL3_D_MARK
, MSIOF1_RXD_D_MARK
,
498 A12_MARK
, FMCLK_MARK
, SDA3_D_MARK
, MSIOF1_SCK_D_MARK
,
499 A13_MARK
, ATAG0_N_C_MARK
, BPFCLK_MARK
, MSIOF1_SS1_D_MARK
,
500 A14_MARK
, ATADIR0_N_C_MARK
, FMIN_MARK
, FMIN_C_MARK
, MSIOF1_SYNC_D_MARK
,
501 A15_MARK
, BPFCLK_C_MARK
,
502 A16_MARK
, DREQ2_B_MARK
, FMCLK_C_MARK
, SCIFA1_SCK_B_MARK
,
503 A17_MARK
, DACK2_B_MARK
, SDA0_C_MARK
,
504 A18_MARK
, DREQ1_MARK
, SCIFA1_RXD_C_MARK
, SCIFB1_RXD_C_MARK
,
507 A19_MARK
, DACK1_MARK
, SCIFA1_TXD_C_MARK
,
508 SCIFB1_TXD_C_MARK
, SCIFB1_SCK_B_MARK
,
509 A20_MARK
, SPCLK_MARK
,
510 A21_MARK
, ATAWR0_N_B_MARK
, MOSI_IO0_MARK
,
511 A22_MARK
, MISO_IO1_MARK
, FMCLK_B_MARK
, TX0_MARK
, SCIFA0_TXD_MARK
,
512 A23_MARK
, IO2_MARK
, BPFCLK_B_MARK
, RX0_MARK
, SCIFA0_RXD_MARK
,
513 A24_MARK
, DREQ2_MARK
, IO3_MARK
, TX1_MARK
, SCIFA1_TXD_MARK
,
514 A25_MARK
, DACK2_MARK
, SSL_MARK
, DREQ1_C_MARK
,
515 RX1_MARK
, SCIFA1_RXD_MARK
,
516 CS0_N_MARK
, ATAG0_N_B_MARK
, SCL1_MARK
,
517 CS1_N_A26_MARK
, ATADIR0_N_B_MARK
, SDA1_MARK
,
518 EX_CS1_N_MARK
, MSIOF2_SCK_MARK
,
519 EX_CS2_N_MARK
, ATAWR0_N_MARK
, MSIOF2_SYNC_MARK
,
520 EX_CS3_N_MARK
, ATADIR0_N_MARK
, MSIOF2_TXD_MARK
,
521 ATAG0_N_MARK
, EX_WAIT1_MARK
,
524 EX_CS4_N_MARK
, ATARD0_N_MARK
, MSIOF2_RXD_MARK
, EX_WAIT2_MARK
,
525 EX_CS5_N_MARK
, ATACS00_N_MARK
, MSIOF2_SS1_MARK
, HRX1_B_MARK
,
526 SCIFB1_RXD_B_MARK
, PWM1_MARK
, TPU_TO1_MARK
,
527 BS_N_MARK
, ATACS10_N_MARK
, MSIOF2_SS2_MARK
, HTX1_B_MARK
,
528 SCIFB1_TXD_B_MARK
, PWM2_MARK
, TPU_TO2_MARK
,
529 RD_WR_N_MARK
, HRX2_B_MARK
, FMIN_B_MARK
,
530 SCIFB0_RXD_B_MARK
, DREQ1_D_MARK
,
531 WE0_N_MARK
, HCTS2_N_B_MARK
, SCIFB0_TXD_B_MARK
,
532 WE1_N_MARK
, ATARD0_N_B_MARK
, HTX2_B_MARK
, SCIFB0_RTS_N_B_MARK
,
533 EX_WAIT0_MARK
, HRTS2_N_B_MARK
, SCIFB0_CTS_N_B_MARK
,
534 DREQ0_MARK
, PWM3_MARK
, TPU_TO3_MARK
,
535 DACK0_MARK
, DRACK0_MARK
, REMOCON_MARK
,
536 SPEEDIN_MARK
, HSCK0_C_MARK
, HSCK2_C_MARK
, SCIFB0_SCK_B_MARK
,
537 SCIFB2_SCK_B_MARK
, DREQ2_C_MARK
, HTX2_D_MARK
,
538 SSI_SCK0129_MARK
, HRX0_C_MARK
, HRX2_C_MARK
,
539 SCIFB0_RXD_C_MARK
, SCIFB2_RXD_C_MARK
,
540 SSI_WS0129_MARK
, HTX0_C_MARK
, HTX2_C_MARK
,
541 SCIFB0_TXD_C_MARK
, SCIFB2_TXD_C_MARK
,
544 SSI_SDATA0_MARK
, SCL0_B_MARK
, SCL7_B_MARK
, MSIOF2_SCK_C_MARK
,
545 SSI_SCK1_MARK
, SDA0_B_MARK
, SDA7_B_MARK
,
546 MSIOF2_SYNC_C_MARK
, GLO_I0_D_MARK
,
547 SSI_WS1_MARK
, SCL1_B_MARK
, SCL8_B_MARK
,
548 MSIOF2_TXD_C_MARK
, GLO_I1_D_MARK
,
549 SSI_SDATA1_MARK
, SDA1_B_MARK
, SDA8_B_MARK
, MSIOF2_RXD_C_MARK
,
550 SSI_SCK2_MARK
, SCL2_MARK
, GPS_CLK_B_MARK
, GLO_Q0_D_MARK
, HSCK1_E_MARK
,
551 SSI_WS2_MARK
, SDA2_MARK
, GPS_SIGN_B_MARK
, RX2_E_MARK
,
552 GLO_Q1_D_MARK
, HCTS1_N_E_MARK
,
553 SSI_SDATA2_MARK
, GPS_MAG_B_MARK
, TX2_E_MARK
, HRTS1_N_E_MARK
,
554 SSI_SCK34_MARK
, SSI_WS34_MARK
, SSI_SDATA3_MARK
,
555 SSI_SCK4_MARK
, GLO_SS_D_MARK
,
556 SSI_WS4_MARK
, GLO_RFON_D_MARK
,
557 SSI_SDATA4_MARK
, MSIOF2_SCK_D_MARK
,
558 SSI_SCK5_MARK
, MSIOF1_SCK_C_MARK
, TS_SDATA0_MARK
, GLO_I0_MARK
,
559 MSIOF2_SYNC_D_MARK
, VI1_R2_B_MARK
,
562 SSI_WS5_MARK
, MSIOF1_SYNC_C_MARK
, TS_SCK0_MARK
, GLO_I1_MARK
,
563 MSIOF2_TXD_D_MARK
, VI1_R3_B_MARK
,
564 SSI_SDATA5_MARK
, MSIOF1_TXD_C_MARK
, TS_SDEN0_MARK
, GLO_Q0_MARK
,
565 MSIOF2_SS1_D_MARK
, VI1_R4_B_MARK
,
566 SSI_SCK6_MARK
, MSIOF1_RXD_C_MARK
, TS_SPSYNC0_MARK
, GLO_Q1_MARK
,
567 MSIOF2_RXD_D_MARK
, VI1_R5_B_MARK
,
568 SSI_WS6_MARK
, GLO_SCLK_MARK
, MSIOF2_SS2_D_MARK
, VI1_R6_B_MARK
,
569 SSI_SDATA6_MARK
, STP_IVCXO27_0_B_MARK
, GLO_SDATA_MARK
, VI1_R7_B_MARK
,
570 SSI_SCK78_MARK
, STP_ISCLK_0_B_MARK
, GLO_SS_MARK
,
571 SSI_WS78_MARK
, TX0_D_MARK
, STP_ISD_0_B_MARK
, GLO_RFON_MARK
,
572 SSI_SDATA7_MARK
, RX0_D_MARK
, STP_ISEN_0_B_MARK
,
573 SSI_SDATA8_MARK
, TX1_D_MARK
, STP_ISSYNC_0_B_MARK
,
574 SSI_SCK9_MARK
, RX1_D_MARK
, GLO_SCLK_D_MARK
,
575 SSI_WS9_MARK
, TX3_D_MARK
, CAN0_TX_D_MARK
, GLO_SDATA_D_MARK
,
576 SSI_SDATA9_MARK
, RX3_D_MARK
, CAN0_RX_D_MARK
,
579 AUDIO_CLKB_MARK
, STP_OPWM_0_B_MARK
, MSIOF1_SCK_B_MARK
,
580 SCIF_CLK_MARK
, BPFCLK_E_MARK
,
581 AUDIO_CLKC_MARK
, SCIFB0_SCK_C_MARK
, MSIOF1_SYNC_B_MARK
, RX2_MARK
,
582 SCIFA2_RXD_MARK
, FMIN_E_MARK
,
583 AUDIO_CLKOUT_MARK
, MSIOF1_SS1_B_MARK
, TX2_MARK
, SCIFA2_TXD_MARK
,
584 IRQ0_MARK
, SCIFB1_RXD_D_MARK
, INTC_IRQ0_N_MARK
,
585 IRQ1_MARK
, SCIFB1_SCK_C_MARK
, INTC_IRQ1_N_MARK
,
586 IRQ2_MARK
, SCIFB1_TXD_D_MARK
, INTC_IRQ2_N_MARK
,
587 IRQ3_MARK
, SCL4_C_MARK
, MSIOF2_TXD_E_MARK
, INTC_IRQ3_N_MARK
,
588 IRQ4_MARK
, HRX1_C_MARK
, SDA4_C_MARK
,
589 MSIOF2_RXD_E_MARK
, INTC_IRQ4_N_MARK
,
590 IRQ5_MARK
, HTX1_C_MARK
, SCL1_E_MARK
, MSIOF2_SCK_E_MARK
,
591 IRQ6_MARK
, HSCK1_C_MARK
, MSIOF1_SS2_B_MARK
,
592 SDA1_E_MARK
, MSIOF2_SYNC_E_MARK
,
593 IRQ7_MARK
, HCTS1_N_C_MARK
, MSIOF1_TXD_B_MARK
,
594 GPS_CLK_C_MARK
, GPS_CLK_D_MARK
,
595 IRQ8_MARK
, HRTS1_N_C_MARK
, MSIOF1_RXD_B_MARK
,
596 GPS_SIGN_C_MARK
, GPS_SIGN_D_MARK
,
599 IRQ9_MARK
, DU1_DOTCLKIN_B_MARK
, CAN_CLK_D_MARK
, GPS_MAG_C_MARK
,
600 SCIF_CLK_B_MARK
, GPS_MAG_D_MARK
,
601 DU1_DR0_MARK
, LCDOUT0_MARK
, VI1_DATA0_B_MARK
, TX0_B_MARK
,
602 SCIFA0_TXD_B_MARK
, MSIOF2_SCK_B_MARK
,
603 DU1_DR1_MARK
, LCDOUT1_MARK
, VI1_DATA1_B_MARK
, RX0_B_MARK
,
604 SCIFA0_RXD_B_MARK
, MSIOF2_SYNC_B_MARK
,
605 DU1_DR2_MARK
, LCDOUT2_MARK
, SSI_SCK0129_B_MARK
,
606 DU1_DR3_MARK
, LCDOUT3_MARK
, SSI_WS0129_B_MARK
,
607 DU1_DR4_MARK
, LCDOUT4_MARK
, SSI_SDATA0_B_MARK
,
608 DU1_DR5_MARK
, LCDOUT5_MARK
, SSI_SCK1_B_MARK
,
609 DU1_DR6_MARK
, LCDOUT6_MARK
, SSI_WS1_B_MARK
,
610 DU1_DR7_MARK
, LCDOUT7_MARK
, SSI_SDATA1_B_MARK
,
611 DU1_DG0_MARK
, LCDOUT8_MARK
, VI1_DATA2_B_MARK
, TX1_B_MARK
,
612 SCIFA1_TXD_B_MARK
, MSIOF2_SS1_B_MARK
,
613 DU1_DG1_MARK
, LCDOUT9_MARK
, VI1_DATA3_B_MARK
, RX1_B_MARK
,
614 SCIFA1_RXD_B_MARK
, MSIOF2_SS2_B_MARK
,
615 DU1_DG2_MARK
, LCDOUT10_MARK
, VI1_DATA4_B_MARK
, SCIF1_SCK_B_MARK
,
616 SCIFA1_SCK_MARK
, SSI_SCK78_B_MARK
,
619 DU1_DG3_MARK
, LCDOUT11_MARK
, VI1_DATA5_B_MARK
, SSI_WS78_B_MARK
,
620 DU1_DG4_MARK
, LCDOUT12_MARK
, VI1_DATA6_B_MARK
, HRX0_B_MARK
,
621 SCIFB2_RXD_B_MARK
, SSI_SDATA7_B_MARK
,
622 DU1_DG5_MARK
, LCDOUT13_MARK
, VI1_DATA7_B_MARK
, HCTS0_N_B_MARK
,
623 SCIFB2_TXD_B_MARK
, SSI_SDATA8_B_MARK
,
624 DU1_DG6_MARK
, LCDOUT14_MARK
, HRTS0_N_B_MARK
,
625 SCIFB2_CTS_N_B_MARK
, SSI_SCK9_B_MARK
,
626 DU1_DG7_MARK
, LCDOUT15_MARK
, HTX0_B_MARK
,
627 SCIFB2_RTS_N_B_MARK
, SSI_WS9_B_MARK
,
628 DU1_DB0_MARK
, LCDOUT16_MARK
, VI1_CLK_B_MARK
, TX2_B_MARK
,
629 SCIFA2_TXD_B_MARK
, MSIOF2_TXD_B_MARK
,
630 DU1_DB1_MARK
, LCDOUT17_MARK
, VI1_HSYNC_N_B_MARK
, RX2_B_MARK
,
631 SCIFA2_RXD_B_MARK
, MSIOF2_RXD_B_MARK
,
632 DU1_DB2_MARK
, LCDOUT18_MARK
, VI1_VSYNC_N_B_MARK
, SCIF2_SCK_B_MARK
,
633 SCIFA2_SCK_MARK
, SSI_SDATA9_B_MARK
,
634 DU1_DB3_MARK
, LCDOUT19_MARK
, VI1_CLKENB_B_MARK
,
635 DU1_DB4_MARK
, LCDOUT20_MARK
, VI1_FIELD_B_MARK
, CAN1_RX_MARK
,
636 DU1_DB5_MARK
, LCDOUT21_MARK
, TX3_MARK
, SCIFA3_TXD_MARK
, CAN1_TX_MARK
,
639 DU1_DB6_MARK
, LCDOUT22_MARK
, SCL3_C_MARK
, RX3_MARK
, SCIFA3_RXD_MARK
,
640 DU1_DB7_MARK
, LCDOUT23_MARK
, SDA3_C_MARK
,
641 SCIF3_SCK_MARK
, SCIFA3_SCK_MARK
,
642 DU1_DOTCLKIN_MARK
, QSTVA_QVS_MARK
,
643 DU1_DOTCLKOUT0_MARK
, QCLK_MARK
,
644 DU1_DOTCLKOUT1_MARK
, QSTVB_QVE_MARK
, CAN0_TX_MARK
,
645 TX3_B_MARK
, SCL2_B_MARK
, PWM4_MARK
,
646 DU1_EXHSYNC_DU1_HSYNC_MARK
, QSTH_QHS_MARK
,
647 DU1_EXVSYNC_DU1_VSYNC_MARK
, QSTB_QHE_MARK
,
648 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
, QCPV_QDE_MARK
,
649 CAN0_RX_MARK
, RX3_B_MARK
, SDA2_B_MARK
,
650 DU1_DISP_MARK
, QPOLA_MARK
,
651 DU1_CDE_MARK
, QPOLB_MARK
, PWM4_B_MARK
,
652 VI0_CLKENB_MARK
, TX4_MARK
, SCIFA4_TXD_MARK
, TS_SDATA0_D_MARK
,
653 VI0_FIELD_MARK
, RX4_MARK
, SCIFA4_RXD_MARK
, TS_SCK0_D_MARK
,
654 VI0_HSYNC_N_MARK
, TX5_MARK
, SCIFA5_TXD_MARK
, TS_SDEN0_D_MARK
,
655 VI0_VSYNC_N_MARK
, RX5_MARK
, SCIFA5_RXD_MARK
, TS_SPSYNC0_D_MARK
,
656 VI0_DATA3_VI0_B3_MARK
, SCIF3_SCK_B_MARK
, SCIFA3_SCK_B_MARK
,
657 VI0_G0_MARK
, SCL8_MARK
, STP_IVCXO27_0_C_MARK
, SCL4_MARK
,
658 HCTS2_N_MARK
, SCIFB2_CTS_N_MARK
, ATAWR1_N_MARK
,
661 VI0_G1_MARK
, SDA8_MARK
, STP_ISCLK_0_C_MARK
, SDA4_MARK
,
662 HRTS2_N_MARK
, SCIFB2_RTS_N_MARK
, ATADIR1_N_MARK
,
663 VI0_G2_MARK
, VI2_HSYNC_N_MARK
, STP_ISD_0_C_MARK
, SCL3_B_MARK
,
664 HSCK2_MARK
, SCIFB2_SCK_MARK
, ATARD1_N_MARK
,
665 VI0_G3_MARK
, VI2_VSYNC_N_MARK
, STP_ISEN_0_C_MARK
, SDA3_B_MARK
,
666 HRX2_MARK
, SCIFB2_RXD_MARK
, ATACS01_N_MARK
,
667 VI0_G4_MARK
, VI2_CLKENB_MARK
, STP_ISSYNC_0_C_MARK
,
668 HTX2_MARK
, SCIFB2_TXD_MARK
, SCIFB0_SCK_D_MARK
,
669 VI0_G5_MARK
, VI2_FIELD_MARK
, STP_OPWM_0_C_MARK
, FMCLK_D_MARK
,
670 CAN0_TX_E_MARK
, HTX1_D_MARK
, SCIFB0_TXD_D_MARK
,
671 VI0_G6_MARK
, VI2_CLK_MARK
, BPFCLK_D_MARK
,
672 VI0_G7_MARK
, VI2_DATA0_MARK
, FMIN_D_MARK
,
673 VI0_R0_MARK
, VI2_DATA1_MARK
, GLO_I0_B_MARK
,
674 TS_SDATA0_C_MARK
, ATACS11_N_MARK
,
675 VI0_R1_MARK
, VI2_DATA2_MARK
, GLO_I1_B_MARK
,
676 TS_SCK0_C_MARK
, ATAG1_N_MARK
,
677 VI0_R2_MARK
, VI2_DATA3_MARK
, GLO_Q0_B_MARK
, TS_SDEN0_C_MARK
,
678 VI0_R3_MARK
, VI2_DATA4_MARK
, GLO_Q1_B_MARK
, TS_SPSYNC0_C_MARK
,
679 VI0_R4_MARK
, VI2_DATA5_MARK
, GLO_SCLK_B_MARK
, TX0_C_MARK
, SCL1_D_MARK
,
682 VI0_R5_MARK
, VI2_DATA6_MARK
, GLO_SDATA_B_MARK
, RX0_C_MARK
, SDA1_D_MARK
,
683 VI0_R6_MARK
, VI2_DATA7_MARK
, GLO_SS_B_MARK
, TX1_C_MARK
, SCL4_B_MARK
,
684 VI0_R7_MARK
, GLO_RFON_B_MARK
, RX1_C_MARK
, CAN0_RX_E_MARK
,
685 SDA4_B_MARK
, HRX1_D_MARK
, SCIFB0_RXD_D_MARK
,
686 VI1_HSYNC_N_MARK
, AVB_RXD0_MARK
, TS_SDATA0_B_MARK
,
687 TX4_B_MARK
, SCIFA4_TXD_B_MARK
,
688 VI1_VSYNC_N_MARK
, AVB_RXD1_MARK
, TS_SCK0_B_MARK
,
689 RX4_B_MARK
, SCIFA4_RXD_B_MARK
,
690 VI1_CLKENB_MARK
, AVB_RXD2_MARK
, TS_SDEN0_B_MARK
,
691 VI1_FIELD_MARK
, AVB_RXD3_MARK
, TS_SPSYNC0_B_MARK
,
692 VI1_CLK_MARK
, AVB_RXD4_MARK
, VI1_DATA0_MARK
, AVB_RXD5_MARK
,
693 VI1_DATA1_MARK
, AVB_RXD6_MARK
, VI1_DATA2_MARK
, AVB_RXD7_MARK
,
694 VI1_DATA3_MARK
, AVB_RX_ER_MARK
, VI1_DATA4_MARK
, AVB_MDIO_MARK
,
695 VI1_DATA5_MARK
, AVB_RX_DV_MARK
, VI1_DATA6_MARK
, AVB_MAGIC_MARK
,
696 VI1_DATA7_MARK
, AVB_MDC_MARK
,
697 ETH_MDIO_MARK
, AVB_RX_CLK_MARK
, SCL2_C_MARK
,
698 ETH_CRS_DV_MARK
, AVB_LINK_MARK
, SDA2_C_MARK
,
701 ETH_RX_ER_MARK
, AVB_CRS_MARK
, SCL3_MARK
, SCL7_MARK
,
702 ETH_RXD0_MARK
, AVB_PHY_INT_MARK
, SDA3_MARK
, SDA7_MARK
,
703 ETH_RXD1_MARK
, AVB_GTXREFCLK_MARK
, CAN0_TX_C_MARK
,
704 SCL2_D_MARK
, MSIOF1_RXD_E_MARK
,
705 ETH_LINK_MARK
, AVB_TXD0_MARK
, CAN0_RX_C_MARK
,
706 SDA2_D_MARK
, MSIOF1_SCK_E_MARK
,
707 ETH_REFCLK_MARK
, AVB_TXD1_MARK
, SCIFA3_RXD_B_MARK
,
708 CAN1_RX_C_MARK
, MSIOF1_SYNC_E_MARK
,
709 ETH_TXD1_MARK
, AVB_TXD2_MARK
, SCIFA3_TXD_B_MARK
,
710 CAN1_TX_C_MARK
, MSIOF1_TXD_E_MARK
,
711 ETH_TX_EN_MARK
, AVB_TXD3_MARK
, TCLK1_B_MARK
, CAN_CLK_B_MARK
,
712 ETH_MAGIC_MARK
, AVB_TXD4_MARK
, IETX_C_MARK
,
713 ETH_TXD0_MARK
, AVB_TXD5_MARK
, IECLK_C_MARK
,
714 ETH_MDC_MARK
, AVB_TXD6_MARK
, IERX_C_MARK
,
715 STP_IVCXO27_0_MARK
, AVB_TXD7_MARK
, SCIFB2_TXD_D_MARK
,
716 ADIDATA_B_MARK
, MSIOF0_SYNC_C_MARK
,
717 STP_ISCLK_0_MARK
, AVB_TX_EN_MARK
, SCIFB2_RXD_D_MARK
,
718 ADICS_SAMP_B_MARK
, MSIOF0_SCK_C_MARK
,
721 STP_ISD_0_MARK
, AVB_TX_ER_MARK
, SCIFB2_SCK_C_MARK
,
722 ADICLK_B_MARK
, MSIOF0_SS1_C_MARK
,
723 STP_ISEN_0_MARK
, AVB_TX_CLK_MARK
, ADICHS0_B_MARK
, MSIOF0_SS2_C_MARK
,
724 STP_ISSYNC_0_MARK
, AVB_COL_MARK
, ADICHS1_B_MARK
, MSIOF0_RXD_C_MARK
,
725 STP_OPWM_0_MARK
, AVB_GTX_CLK_MARK
, PWM0_B_MARK
,
726 ADICHS2_B_MARK
, MSIOF0_TXD_C_MARK
,
727 SD0_CLK_MARK
, SPCLK_B_MARK
, SD0_CMD_MARK
, MOSI_IO0_B_MARK
,
728 SD0_DATA0_MARK
, MISO_IO1_B_MARK
, SD0_DATA1_MARK
, IO2_B_MARK
,
729 SD0_DATA2_MARK
, IO3_B_MARK
, SD0_DATA3_MARK
, SSL_B_MARK
,
730 SD0_CD_MARK
, MMC_D6_B_MARK
, SIM0_RST_B_MARK
, CAN0_RX_F_MARK
,
731 SCIFA5_TXD_B_MARK
, TX3_C_MARK
,
732 SD0_WP_MARK
, MMC_D7_B_MARK
, SIM0_D_B_MARK
, CAN0_TX_F_MARK
,
733 SCIFA5_RXD_B_MARK
, RX3_C_MARK
,
734 SD1_CMD_MARK
, REMOCON_B_MARK
, SD1_DATA0_MARK
, SPEEDIN_B_MARK
,
735 SD1_DATA1_MARK
, IETX_B_MARK
, SD1_DATA2_MARK
, IECLK_B_MARK
,
736 SD1_DATA3_MARK
, IERX_B_MARK
,
737 SD1_CD_MARK
, PWM0_MARK
, TPU_TO0_MARK
, SCL1_C_MARK
,
740 SD1_WP_MARK
, PWM1_B_MARK
, SDA1_C_MARK
,
741 SD2_CLK_MARK
, MMC_CLK_MARK
, SD2_CMD_MARK
, MMC_CMD_MARK
,
742 SD2_DATA0_MARK
, MMC_D0_MARK
, SD2_DATA1_MARK
, MMC_D1_MARK
,
743 SD2_DATA2_MARK
, MMC_D2_MARK
, SD2_DATA3_MARK
, MMC_D3_MARK
,
744 SD2_CD_MARK
, MMC_D4_MARK
, SCL8_C_MARK
, TX5_B_MARK
, SCIFA5_TXD_C_MARK
,
745 SD2_WP_MARK
, MMC_D5_MARK
, SDA8_C_MARK
, RX5_B_MARK
, SCIFA5_RXD_C_MARK
,
746 MSIOF0_SCK_MARK
, RX2_C_MARK
, ADIDATA_MARK
,
747 VI1_CLK_C_MARK
, VI1_G0_B_MARK
,
748 MSIOF0_SYNC_MARK
, TX2_C_MARK
, ADICS_SAMP_MARK
,
749 VI1_CLKENB_C_MARK
, VI1_G1_B_MARK
,
750 MSIOF0_TXD_MARK
, ADICLK_MARK
, VI1_FIELD_C_MARK
, VI1_G2_B_MARK
,
751 MSIOF0_RXD_MARK
, ADICHS0_MARK
, VI1_DATA0_C_MARK
, VI1_G3_B_MARK
,
752 MSIOF0_SS1_MARK
, MMC_D6_MARK
, ADICHS1_MARK
, TX0_E_MARK
,
753 VI1_HSYNC_N_C_MARK
, SCL7_C_MARK
, VI1_G4_B_MARK
,
754 MSIOF0_SS2_MARK
, MMC_D7_MARK
, ADICHS2_MARK
, RX0_E_MARK
,
755 VI1_VSYNC_N_C_MARK
, SDA7_C_MARK
, VI1_G5_B_MARK
,
758 SIM0_RST_MARK
, IETX_MARK
, CAN1_TX_D_MARK
,
759 SIM0_CLK_MARK
, IECLK_MARK
, CAN_CLK_C_MARK
,
760 SIM0_D_MARK
, IERX_MARK
, CAN1_RX_D_MARK
,
761 GPS_CLK_MARK
, DU1_DOTCLKIN_C_MARK
, AUDIO_CLKB_B_MARK
,
762 PWM5_B_MARK
, SCIFA3_TXD_C_MARK
,
763 GPS_SIGN_MARK
, TX4_C_MARK
, SCIFA4_TXD_C_MARK
, PWM5_MARK
,
764 VI1_G6_B_MARK
, SCIFA3_RXD_C_MARK
,
765 GPS_MAG_MARK
, RX4_C_MARK
, SCIFA4_RXD_C_MARK
, PWM6_MARK
,
766 VI1_G7_B_MARK
, SCIFA3_SCK_C_MARK
,
767 HCTS0_N_MARK
, SCIFB0_CTS_N_MARK
, GLO_I0_C_MARK
,
768 TCLK1_MARK
, VI1_DATA1_C_MARK
,
769 HRTS0_N_MARK
, SCIFB0_RTS_N_MARK
, GLO_I1_C_MARK
, VI1_DATA2_C_MARK
,
770 HSCK0_MARK
, SCIFB0_SCK_MARK
, GLO_Q0_C_MARK
, CAN_CLK_MARK
,
771 TCLK2_MARK
, VI1_DATA3_C_MARK
,
772 HRX0_MARK
, SCIFB0_RXD_MARK
, GLO_Q1_C_MARK
,
773 CAN0_RX_B_MARK
, VI1_DATA4_C_MARK
,
774 HTX0_MARK
, SCIFB0_TXD_MARK
, GLO_SCLK_C_MARK
,
775 CAN0_TX_B_MARK
, VI1_DATA5_C_MARK
,
778 HRX1_MARK
, SCIFB1_RXD_MARK
, VI1_R0_B_MARK
,
779 GLO_SDATA_C_MARK
, VI1_DATA6_C_MARK
,
780 HTX1_MARK
, SCIFB1_TXD_MARK
, VI1_R1_B_MARK
,
781 GLO_SS_C_MARK
, VI1_DATA7_C_MARK
,
782 HSCK1_MARK
, SCIFB1_SCK_MARK
, MLB_CLK_MARK
, GLO_RFON_C_MARK
,
783 HCTS1_N_MARK
, SCIFB1_CTS_N_MARK
, MLB_SIG_MARK
, CAN1_TX_B_MARK
,
784 HRTS1_N_MARK
, SCIFB1_RTS_N_MARK
, MLB_DAT_MARK
, CAN1_RX_B_MARK
,
788 static const u16 pinmux_data
[] = {
789 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
791 PINMUX_DATA(EX_CS0_N_MARK
, FN_EX_CS0_N
),
792 PINMUX_DATA(RD_N_MARK
, FN_RD_N
),
793 PINMUX_DATA(AUDIO_CLKA_MARK
, FN_AUDIO_CLKA
),
794 PINMUX_DATA(VI0_CLK_MARK
, FN_VI0_CLK
),
795 PINMUX_DATA(VI0_DATA0_VI0_B0_MARK
, FN_VI0_DATA0_VI0_B0
),
796 PINMUX_DATA(VI0_DATA1_VI0_B1_MARK
, FN_VI0_DATA1_VI0_B1
),
797 PINMUX_DATA(VI0_DATA2_VI0_B2_MARK
, FN_VI0_DATA2_VI0_B2
),
798 PINMUX_DATA(VI0_DATA4_VI0_B4_MARK
, FN_VI0_DATA4_VI0_B4
),
799 PINMUX_DATA(VI0_DATA5_VI0_B5_MARK
, FN_VI0_DATA5_VI0_B5
),
800 PINMUX_DATA(VI0_DATA6_VI0_B6_MARK
, FN_VI0_DATA6_VI0_B6
),
801 PINMUX_DATA(VI0_DATA7_VI0_B7_MARK
, FN_VI0_DATA7_VI0_B7
),
802 PINMUX_DATA(USB0_PWEN_MARK
, FN_USB0_PWEN
),
803 PINMUX_DATA(USB0_OVC_MARK
, FN_USB0_OVC
),
804 PINMUX_DATA(USB1_PWEN_MARK
, FN_USB1_PWEN
),
805 PINMUX_DATA(USB1_OVC_MARK
, FN_USB1_OVC
),
806 PINMUX_DATA(DU0_DOTCLKIN_MARK
, FN_DU0_DOTCLKIN
),
807 PINMUX_DATA(SD1_CLK_MARK
, FN_SD1_CLK
),
810 PINMUX_IPSR_DATA(IP0_0
, D0
),
811 PINMUX_IPSR_DATA(IP0_1
, D1
),
812 PINMUX_IPSR_DATA(IP0_2
, D2
),
813 PINMUX_IPSR_DATA(IP0_3
, D3
),
814 PINMUX_IPSR_DATA(IP0_4
, D4
),
815 PINMUX_IPSR_DATA(IP0_5
, D5
),
816 PINMUX_IPSR_DATA(IP0_6
, D6
),
817 PINMUX_IPSR_DATA(IP0_7
, D7
),
818 PINMUX_IPSR_DATA(IP0_8
, D8
),
819 PINMUX_IPSR_DATA(IP0_9
, D9
),
820 PINMUX_IPSR_DATA(IP0_10
, D10
),
821 PINMUX_IPSR_DATA(IP0_11
, D11
),
822 PINMUX_IPSR_DATA(IP0_12
, D12
),
823 PINMUX_IPSR_DATA(IP0_13
, D13
),
824 PINMUX_IPSR_DATA(IP0_14
, D14
),
825 PINMUX_IPSR_DATA(IP0_15
, D15
),
826 PINMUX_IPSR_DATA(IP0_18_16
, A0
),
827 PINMUX_IPSR_MODSEL_DATA(IP0_18_16
, ATAWR0_N_C
, SEL_LBS_2
),
828 PINMUX_IPSR_MODSEL_DATA(IP0_18_16
, MSIOF0_SCK_B
, SEL_SOF0_1
),
829 PINMUX_IPSR_MODSEL_DATA(IP0_18_16
, SCL0_C
, SEL_IIC0_2
),
830 PINMUX_IPSR_DATA(IP0_18_16
, PWM2_B
),
831 PINMUX_IPSR_DATA(IP0_20_19
, A1
),
832 PINMUX_IPSR_MODSEL_DATA(IP0_20_19
, MSIOF0_SYNC_B
, SEL_SOF0_1
),
833 PINMUX_IPSR_DATA(IP0_22_21
, A2
),
834 PINMUX_IPSR_MODSEL_DATA(IP0_22_21
, MSIOF0_SS1_B
, SEL_SOF0_1
),
835 PINMUX_IPSR_DATA(IP0_24_23
, A3
),
836 PINMUX_IPSR_MODSEL_DATA(IP0_24_23
, MSIOF0_SS2_B
, SEL_SOF0_1
),
837 PINMUX_IPSR_DATA(IP0_26_25
, A4
),
838 PINMUX_IPSR_MODSEL_DATA(IP0_26_25
, MSIOF0_TXD_B
, SEL_SOF0_1
),
839 PINMUX_IPSR_DATA(IP0_28_27
, A5
),
840 PINMUX_IPSR_MODSEL_DATA(IP0_28_27
, MSIOF0_RXD_B
, SEL_SOF0_1
),
841 PINMUX_IPSR_DATA(IP0_30_29
, A6
),
842 PINMUX_IPSR_MODSEL_DATA(IP0_30_29
, MSIOF1_SCK
, SEL_SOF1_0
),
845 PINMUX_IPSR_DATA(IP1_1_0
, A7
),
846 PINMUX_IPSR_MODSEL_DATA(IP1_1_0
, MSIOF1_SYNC
, SEL_SOF1_0
),
847 PINMUX_IPSR_DATA(IP1_3_2
, A8
),
848 PINMUX_IPSR_MODSEL_DATA(IP1_3_2
, MSIOF1_SS1
, SEL_SOF1_0
),
849 PINMUX_IPSR_MODSEL_DATA(IP1_3_2
, SCL0
, SEL_IIC0_0
),
850 PINMUX_IPSR_DATA(IP1_5_4
, A9
),
851 PINMUX_IPSR_MODSEL_DATA(IP1_5_4
, MSIOF1_SS2
, SEL_SOF1_0
),
852 PINMUX_IPSR_MODSEL_DATA(IP1_5_4
, SDA0
, SEL_IIC0_0
),
853 PINMUX_IPSR_DATA(IP1_7_6
, A10
),
854 PINMUX_IPSR_MODSEL_DATA(IP1_7_6
, MSIOF1_TXD
, SEL_SOF1_0
),
855 PINMUX_IPSR_MODSEL_DATA(IP1_7_6
, MSIOF1_TXD_D
, SEL_SOF1_3
),
856 PINMUX_IPSR_DATA(IP1_10_8
, A11
),
857 PINMUX_IPSR_MODSEL_DATA(IP1_10_8
, MSIOF1_RXD
, SEL_SOF1_0
),
858 PINMUX_IPSR_MODSEL_DATA(IP1_10_8
, SCL3_D
, SEL_IIC3_3
),
859 PINMUX_IPSR_MODSEL_DATA(IP1_10_8
, MSIOF1_RXD_D
, SEL_SOF1_3
),
860 PINMUX_IPSR_DATA(IP1_13_11
, A12
),
861 PINMUX_IPSR_MODSEL_DATA(IP1_13_11
, FMCLK
, SEL_FM_0
),
862 PINMUX_IPSR_MODSEL_DATA(IP1_13_11
, SDA3_D
, SEL_IIC3_3
),
863 PINMUX_IPSR_MODSEL_DATA(IP1_13_11
, MSIOF1_SCK_D
, SEL_SOF1_3
),
864 PINMUX_IPSR_DATA(IP1_16_14
, A13
),
865 PINMUX_IPSR_MODSEL_DATA(IP1_16_14
, ATAG0_N_C
, SEL_LBS_2
),
866 PINMUX_IPSR_MODSEL_DATA(IP1_16_14
, BPFCLK
, SEL_FM_0
),
867 PINMUX_IPSR_MODSEL_DATA(IP1_16_14
, MSIOF1_SS1_D
, SEL_SOF1_3
),
868 PINMUX_IPSR_DATA(IP1_19_17
, A14
),
869 PINMUX_IPSR_MODSEL_DATA(IP1_19_17
, ATADIR0_N_C
, SEL_LBS_2
),
870 PINMUX_IPSR_MODSEL_DATA(IP1_19_17
, FMIN
, SEL_FM_0
),
871 PINMUX_IPSR_MODSEL_DATA(IP1_19_17
, FMIN_C
, SEL_FM_2
),
872 PINMUX_IPSR_MODSEL_DATA(IP1_19_17
, MSIOF1_SYNC_D
, SEL_SOF1_3
),
873 PINMUX_IPSR_DATA(IP1_22_20
, A15
),
874 PINMUX_IPSR_MODSEL_DATA(IP1_22_20
, BPFCLK_C
, SEL_FM_2
),
875 PINMUX_IPSR_DATA(IP1_25_23
, A16
),
876 PINMUX_IPSR_MODSEL_DATA(IP1_25_23
, DREQ2_B
, SEL_LBS_1
),
877 PINMUX_IPSR_MODSEL_DATA(IP1_25_23
, FMCLK_C
, SEL_FM_2
),
878 PINMUX_IPSR_MODSEL_DATA(IP1_25_23
, SCIFA1_SCK_B
, SEL_SCIFA1_1
),
879 PINMUX_IPSR_DATA(IP1_28_26
, A17
),
880 PINMUX_IPSR_MODSEL_DATA(IP1_28_26
, DACK2_B
, SEL_LBS_1
),
881 PINMUX_IPSR_MODSEL_DATA(IP1_28_26
, SDA0_C
, SEL_IIC0_2
),
882 PINMUX_IPSR_DATA(IP1_31_29
, A18
),
883 PINMUX_IPSR_MODSEL_DATA(IP1_31_29
, DREQ1
, SEL_LBS_0
),
884 PINMUX_IPSR_MODSEL_DATA(IP1_31_29
, SCIFA1_RXD_C
, SEL_SCIFA1_2
),
885 PINMUX_IPSR_MODSEL_DATA(IP1_31_29
, SCIFB1_RXD_C
, SEL_SCIFB1_2
),
888 PINMUX_IPSR_DATA(IP2_2_0
, A19
),
889 PINMUX_IPSR_DATA(IP2_2_0
, DACK1
),
890 PINMUX_IPSR_MODSEL_DATA(IP2_2_0
, SCIFA1_TXD_C
, SEL_SCIFA1_2
),
891 PINMUX_IPSR_MODSEL_DATA(IP2_2_0
, SCIFB1_TXD_C
, SEL_SCIFB1_2
),
892 PINMUX_IPSR_MODSEL_DATA(IP2_2_0
, SCIFB1_SCK_B
, SEL_SCIFB1_1
),
893 PINMUX_IPSR_DATA(IP2_2_0
, A20
),
894 PINMUX_IPSR_MODSEL_DATA(IP2_4_3
, SPCLK
, SEL_QSP_0
),
895 PINMUX_IPSR_DATA(IP2_6_5
, A21
),
896 PINMUX_IPSR_MODSEL_DATA(IP2_6_5
, ATAWR0_N_B
, SEL_LBS_1
),
897 PINMUX_IPSR_MODSEL_DATA(IP2_6_5
, MOSI_IO0
, SEL_QSP_0
),
898 PINMUX_IPSR_DATA(IP2_9_7
, A22
),
899 PINMUX_IPSR_MODSEL_DATA(IP2_9_7
, MISO_IO1
, SEL_QSP_0
),
900 PINMUX_IPSR_MODSEL_DATA(IP2_9_7
, FMCLK_B
, SEL_FM_1
),
901 PINMUX_IPSR_MODSEL_DATA(IP2_9_7
, TX0
, SEL_SCIF0_0
),
902 PINMUX_IPSR_MODSEL_DATA(IP2_9_7
, SCIFA0_TXD
, SEL_SCFA_0
),
903 PINMUX_IPSR_DATA(IP2_12_10
, A23
),
904 PINMUX_IPSR_MODSEL_DATA(IP2_12_10
, IO2
, SEL_QSP_0
),
905 PINMUX_IPSR_MODSEL_DATA(IP2_12_10
, BPFCLK_B
, SEL_FM_1
),
906 PINMUX_IPSR_MODSEL_DATA(IP2_12_10
, RX0
, SEL_SCIF0_0
),
907 PINMUX_IPSR_MODSEL_DATA(IP2_12_10
, SCIFA0_RXD
, SEL_SCFA_0
),
908 PINMUX_IPSR_DATA(IP2_15_13
, A24
),
909 PINMUX_IPSR_MODSEL_DATA(IP2_15_13
, DREQ2
, SEL_LBS_0
),
910 PINMUX_IPSR_MODSEL_DATA(IP2_15_13
, IO3
, SEL_QSP_0
),
911 PINMUX_IPSR_MODSEL_DATA(IP2_15_13
, TX1
, SEL_SCIF1_0
),
912 PINMUX_IPSR_MODSEL_DATA(IP2_15_13
, SCIFA1_TXD
, SEL_SCIFA1_0
),
913 PINMUX_IPSR_DATA(IP2_18_16
, A25
),
914 PINMUX_IPSR_MODSEL_DATA(IP2_18_16
, DACK2
, SEL_LBS_0
),
915 PINMUX_IPSR_MODSEL_DATA(IP2_18_16
, SSL
, SEL_QSP_0
),
916 PINMUX_IPSR_MODSEL_DATA(IP2_18_16
, DREQ1_C
, SEL_LBS_2
),
917 PINMUX_IPSR_MODSEL_DATA(IP2_18_16
, RX1
, SEL_SCIF1_0
),
918 PINMUX_IPSR_MODSEL_DATA(IP2_18_16
, SCIFA1_RXD
, SEL_SCIFA1_0
),
919 PINMUX_IPSR_DATA(IP2_20_19
, CS0_N
),
920 PINMUX_IPSR_MODSEL_DATA(IP2_20_19
, ATAG0_N_B
, SEL_LBS_1
),
921 PINMUX_IPSR_MODSEL_DATA(IP2_20_19
, SCL1
, SEL_IIC1_0
),
922 PINMUX_IPSR_DATA(IP2_22_21
, CS1_N_A26
),
923 PINMUX_IPSR_MODSEL_DATA(IP2_22_21
, ATADIR0_N_B
, SEL_LBS_1
),
924 PINMUX_IPSR_MODSEL_DATA(IP2_22_21
, SDA1
, SEL_IIC1_0
),
925 PINMUX_IPSR_DATA(IP2_24_23
, EX_CS1_N
),
926 PINMUX_IPSR_MODSEL_DATA(IP2_24_23
, MSIOF2_SCK
, SEL_SOF2_0
),
927 PINMUX_IPSR_DATA(IP2_26_25
, EX_CS2_N
),
928 PINMUX_IPSR_MODSEL_DATA(IP2_26_25
, ATAWR0_N
, SEL_LBS_0
),
929 PINMUX_IPSR_MODSEL_DATA(IP2_26_25
, MSIOF2_SYNC
, SEL_SOF2_0
),
930 PINMUX_IPSR_DATA(IP2_29_27
, EX_CS3_N
),
931 PINMUX_IPSR_MODSEL_DATA(IP2_29_27
, ATADIR0_N
, SEL_LBS_0
),
932 PINMUX_IPSR_MODSEL_DATA(IP2_29_27
, MSIOF2_TXD
, SEL_SOF2_0
),
933 PINMUX_IPSR_MODSEL_DATA(IP2_29_27
, ATAG0_N
, SEL_LBS_0
),
934 PINMUX_IPSR_DATA(IP2_29_27
, EX_WAIT1
),
937 PINMUX_IPSR_DATA(IP3_2_0
, EX_CS4_N
),
938 PINMUX_IPSR_MODSEL_DATA(IP3_2_0
, ATARD0_N
, SEL_LBS_0
),
939 PINMUX_IPSR_MODSEL_DATA(IP3_2_0
, MSIOF2_RXD
, SEL_SOF2_0
),
940 PINMUX_IPSR_DATA(IP3_2_0
, EX_WAIT2
),
941 PINMUX_IPSR_DATA(IP3_5_3
, EX_CS5_N
),
942 PINMUX_IPSR_DATA(IP3_5_3
, ATACS00_N
),
943 PINMUX_IPSR_MODSEL_DATA(IP3_5_3
, MSIOF2_SS1
, SEL_SOF2_0
),
944 PINMUX_IPSR_MODSEL_DATA(IP3_5_3
, HRX1_B
, SEL_HSCIF1_1
),
945 PINMUX_IPSR_MODSEL_DATA(IP3_5_3
, SCIFB1_RXD_B
, SEL_SCIFB1_1
),
946 PINMUX_IPSR_DATA(IP3_5_3
, PWM1
),
947 PINMUX_IPSR_DATA(IP3_5_3
, TPU_TO1
),
948 PINMUX_IPSR_DATA(IP3_8_6
, BS_N
),
949 PINMUX_IPSR_DATA(IP3_8_6
, ATACS10_N
),
950 PINMUX_IPSR_MODSEL_DATA(IP3_8_6
, MSIOF2_SS2
, SEL_SOF2_0
),
951 PINMUX_IPSR_MODSEL_DATA(IP3_8_6
, HTX1_B
, SEL_HSCIF1_1
),
952 PINMUX_IPSR_MODSEL_DATA(IP3_8_6
, SCIFB1_TXD_B
, SEL_SCIFB1_1
),
953 PINMUX_IPSR_DATA(IP3_8_6
, PWM2
),
954 PINMUX_IPSR_DATA(IP3_8_6
, TPU_TO2
),
955 PINMUX_IPSR_DATA(IP3_11_9
, RD_WR_N
),
956 PINMUX_IPSR_MODSEL_DATA(IP3_11_9
, HRX2_B
, SEL_HSCIF2_1
),
957 PINMUX_IPSR_MODSEL_DATA(IP3_11_9
, FMIN_B
, SEL_FM_1
),
958 PINMUX_IPSR_MODSEL_DATA(IP3_11_9
, SCIFB0_RXD_B
, SEL_SCIFB_1
),
959 PINMUX_IPSR_MODSEL_DATA(IP3_11_9
, DREQ1_D
, SEL_LBS_1
),
960 PINMUX_IPSR_DATA(IP3_13_12
, WE0_N
),
961 PINMUX_IPSR_MODSEL_DATA(IP3_13_12
, HCTS2_N_B
, SEL_HSCIF2_1
),
962 PINMUX_IPSR_MODSEL_DATA(IP3_13_12
, SCIFB0_TXD_B
, SEL_SCIFB_1
),
963 PINMUX_IPSR_DATA(IP3_15_14
, WE1_N
),
964 PINMUX_IPSR_MODSEL_DATA(IP3_15_14
, ATARD0_N_B
, SEL_LBS_1
),
965 PINMUX_IPSR_MODSEL_DATA(IP3_15_14
, HTX2_B
, SEL_HSCIF2_1
),
966 PINMUX_IPSR_MODSEL_DATA(IP3_15_14
, SCIFB0_RTS_N_B
, SEL_SCIFB_1
),
967 PINMUX_IPSR_DATA(IP3_17_16
, EX_WAIT0
),
968 PINMUX_IPSR_MODSEL_DATA(IP3_17_16
, HRTS2_N_B
, SEL_HSCIF2_1
),
969 PINMUX_IPSR_MODSEL_DATA(IP3_17_16
, SCIFB0_CTS_N_B
, SEL_SCIFB_1
),
970 PINMUX_IPSR_DATA(IP3_19_18
, DREQ0
),
971 PINMUX_IPSR_DATA(IP3_19_18
, PWM3
),
972 PINMUX_IPSR_DATA(IP3_19_18
, TPU_TO3
),
973 PINMUX_IPSR_DATA(IP3_21_20
, DACK0
),
974 PINMUX_IPSR_DATA(IP3_21_20
, DRACK0
),
975 PINMUX_IPSR_MODSEL_DATA(IP3_21_20
, REMOCON
, SEL_RCN_0
),
976 PINMUX_IPSR_MODSEL_DATA(IP3_24_22
, SPEEDIN
, SEL_RSP_0
),
977 PINMUX_IPSR_MODSEL_DATA(IP3_24_22
, HSCK0_C
, SEL_HSCIF0_2
),
978 PINMUX_IPSR_MODSEL_DATA(IP3_24_22
, HSCK2_C
, SEL_HSCIF2_2
),
979 PINMUX_IPSR_MODSEL_DATA(IP3_24_22
, SCIFB0_SCK_B
, SEL_SCIFB_1
),
980 PINMUX_IPSR_MODSEL_DATA(IP3_24_22
, SCIFB2_SCK_B
, SEL_SCIFB2_1
),
981 PINMUX_IPSR_MODSEL_DATA(IP3_24_22
, DREQ2_C
, SEL_LBS_2
),
982 PINMUX_IPSR_MODSEL_DATA(IP3_30_28
, HTX2_C
, SEL_HSCIF2_2
),
983 PINMUX_IPSR_MODSEL_DATA(IP3_27_25
, SSI_SCK0129
, SEL_SSI0_0
),
984 PINMUX_IPSR_MODSEL_DATA(IP3_27_25
, HRX0_C
, SEL_HSCIF0_2
),
985 PINMUX_IPSR_MODSEL_DATA(IP3_27_25
, HRX2_C
, SEL_HSCIF2_2
),
986 PINMUX_IPSR_MODSEL_DATA(IP3_27_25
, SCIFB0_RXD_C
, SEL_SCIFB_2
),
987 PINMUX_IPSR_MODSEL_DATA(IP3_27_25
, SCIFB2_RXD_C
, SEL_SCIFB2_2
),
988 PINMUX_IPSR_MODSEL_DATA(IP3_30_28
, SSI_WS0129
, SEL_SSI0_0
),
989 PINMUX_IPSR_MODSEL_DATA(IP3_30_28
, HTX0_C
, SEL_HSCIF0_2
),
990 PINMUX_IPSR_MODSEL_DATA(IP3_30_28
, HTX2_C
, SEL_HSCIF2_2
),
991 PINMUX_IPSR_MODSEL_DATA(IP3_30_28
, SCIFB0_TXD_C
, SEL_SCIFB_2
),
992 PINMUX_IPSR_MODSEL_DATA(IP3_30_28
, SCIFB2_TXD_C
, SEL_SCIFB2_2
),
995 PINMUX_IPSR_MODSEL_DATA(IP4_1_0
, SSI_SDATA0
, SEL_SSI0_0
),
996 PINMUX_IPSR_MODSEL_DATA(IP4_1_0
, SCL0_B
, SEL_IIC0_1
),
997 PINMUX_IPSR_MODSEL_DATA(IP4_1_0
, SCL7_B
, SEL_IIC7_1
),
998 PINMUX_IPSR_MODSEL_DATA(IP4_1_0
, MSIOF2_SCK_C
, SEL_SOF2_2
),
999 PINMUX_IPSR_MODSEL_DATA(IP4_4_2
, SSI_SCK1
, SEL_SSI1_0
),
1000 PINMUX_IPSR_MODSEL_DATA(IP4_4_2
, SDA0_B
, SEL_IIC0_1
),
1001 PINMUX_IPSR_MODSEL_DATA(IP4_4_2
, SDA7_B
, SEL_IIC7_1
),
1002 PINMUX_IPSR_MODSEL_DATA(IP4_4_2
, MSIOF2_SYNC_C
, SEL_SOF2_2
),
1003 PINMUX_IPSR_MODSEL_DATA(IP4_4_2
, GLO_I0_D
, SEL_GPS_3
),
1004 PINMUX_IPSR_MODSEL_DATA(IP4_7_5
, SSI_WS1
, SEL_SSI1_0
),
1005 PINMUX_IPSR_MODSEL_DATA(IP4_7_5
, SCL1_B
, SEL_IIC1_1
),
1006 PINMUX_IPSR_MODSEL_DATA(IP4_7_5
, SCL8_B
, SEL_IIC8_1
),
1007 PINMUX_IPSR_MODSEL_DATA(IP4_7_5
, MSIOF2_TXD_C
, SEL_SOF2_2
),
1008 PINMUX_IPSR_MODSEL_DATA(IP4_7_5
, GLO_I1_D
, SEL_GPS_3
),
1009 PINMUX_IPSR_MODSEL_DATA(IP4_9_8
, SSI_SDATA1
, SEL_SSI1_0
),
1010 PINMUX_IPSR_MODSEL_DATA(IP4_9_8
, SDA1_B
, SEL_IIC1_1
),
1011 PINMUX_IPSR_MODSEL_DATA(IP4_9_8
, SDA8_B
, SEL_IIC8_1
),
1012 PINMUX_IPSR_MODSEL_DATA(IP4_9_8
, MSIOF2_RXD_C
, SEL_SOF2_2
),
1013 PINMUX_IPSR_DATA(IP4_12_10
, SSI_SCK2
),
1014 PINMUX_IPSR_MODSEL_DATA(IP4_12_10
, SCL2
, SEL_IIC2_0
),
1015 PINMUX_IPSR_MODSEL_DATA(IP4_12_10
, GPS_CLK_B
, SEL_GPS_1
),
1016 PINMUX_IPSR_MODSEL_DATA(IP4_12_10
, GLO_Q0_D
, SEL_GPS_3
),
1017 PINMUX_IPSR_DATA(IP4_15_13
, SSI_WS2
),
1018 PINMUX_IPSR_MODSEL_DATA(IP4_15_13
, SDA2
, SEL_IIC2_0
),
1019 PINMUX_IPSR_MODSEL_DATA(IP4_15_13
, GPS_SIGN_B
, SEL_GPS_1
),
1020 PINMUX_IPSR_MODSEL_DATA(IP4_15_13
, RX2_E
, SEL_SCIF2_4
),
1021 PINMUX_IPSR_MODSEL_DATA(IP4_15_13
, GLO_Q1_D
, SEL_GPS_3
),
1022 PINMUX_IPSR_DATA(IP4_18_16
, SSI_SDATA2
),
1023 PINMUX_IPSR_MODSEL_DATA(IP4_18_16
, GPS_MAG_B
, SEL_GPS_1
),
1024 PINMUX_IPSR_MODSEL_DATA(IP4_18_16
, TX2_E
, SEL_SCIF2_4
),
1025 PINMUX_IPSR_DATA(IP4_19
, SSI_SCK34
),
1026 PINMUX_IPSR_DATA(IP4_20
, SSI_WS34
),
1027 PINMUX_IPSR_DATA(IP4_21
, SSI_SDATA3
),
1028 PINMUX_IPSR_DATA(IP4_23_22
, SSI_SCK4
),
1029 PINMUX_IPSR_MODSEL_DATA(IP4_23_22
, GLO_SS_D
, SEL_GPS_3
),
1030 PINMUX_IPSR_DATA(IP4_25_24
, SSI_WS4
),
1031 PINMUX_IPSR_MODSEL_DATA(IP4_25_24
, GLO_RFON_D
, SEL_GPS_3
),
1032 PINMUX_IPSR_DATA(IP4_27_26
, SSI_SDATA4
),
1033 PINMUX_IPSR_MODSEL_DATA(IP4_27_26
, MSIOF2_SCK_D
, SEL_SOF2_3
),
1034 PINMUX_IPSR_DATA(IP4_30_28
, SSI_SCK5
),
1035 PINMUX_IPSR_MODSEL_DATA(IP4_30_28
, MSIOF1_SCK_C
, SEL_SOF1_2
),
1036 PINMUX_IPSR_MODSEL_DATA(IP4_30_28
, TS_SDATA0
, SEL_TSIF0_0
),
1037 PINMUX_IPSR_MODSEL_DATA(IP4_30_28
, GLO_I0
, SEL_GPS_0
),
1038 PINMUX_IPSR_MODSEL_DATA(IP4_30_28
, MSIOF2_SYNC_D
, SEL_SOF2_3
),
1039 PINMUX_IPSR_DATA(IP4_30_28
, VI1_R2_B
),
1042 PINMUX_IPSR_DATA(IP5_2_0
, SSI_WS5
),
1043 PINMUX_IPSR_MODSEL_DATA(IP5_2_0
, MSIOF1_SYNC_C
, SEL_SOF1_2
),
1044 PINMUX_IPSR_MODSEL_DATA(IP5_2_0
, TS_SCK0
, SEL_TSIF0_0
),
1045 PINMUX_IPSR_MODSEL_DATA(IP5_2_0
, GLO_I1
, SEL_GPS_0
),
1046 PINMUX_IPSR_MODSEL_DATA(IP5_2_0
, MSIOF2_TXD_D
, SEL_SOF2_3
),
1047 PINMUX_IPSR_DATA(IP5_2_0
, VI1_R3_B
),
1048 PINMUX_IPSR_DATA(IP5_5_3
, SSI_SDATA5
),
1049 PINMUX_IPSR_MODSEL_DATA(IP5_5_3
, MSIOF1_TXD_C
, SEL_SOF1_2
),
1050 PINMUX_IPSR_MODSEL_DATA(IP5_5_3
, TS_SDEN0
, SEL_TSIF0_0
),
1051 PINMUX_IPSR_MODSEL_DATA(IP5_5_3
, GLO_Q0
, SEL_GPS_0
),
1052 PINMUX_IPSR_MODSEL_DATA(IP5_5_3
, MSIOF2_SS1_D
, SEL_SOF2_3
),
1053 PINMUX_IPSR_DATA(IP5_5_3
, VI1_R4_B
),
1054 PINMUX_IPSR_DATA(IP5_8_6
, SSI_SCK6
),
1055 PINMUX_IPSR_MODSEL_DATA(IP5_8_6
, MSIOF1_RXD_C
, SEL_SOF1_2
),
1056 PINMUX_IPSR_MODSEL_DATA(IP5_8_6
, TS_SPSYNC0
, SEL_TSIF0_0
),
1057 PINMUX_IPSR_MODSEL_DATA(IP5_8_6
, GLO_Q1
, SEL_GPS_0
),
1058 PINMUX_IPSR_MODSEL_DATA(IP5_8_6
, MSIOF2_RXD_D
, SEL_SOF2_3
),
1059 PINMUX_IPSR_DATA(IP5_8_6
, VI1_R5_B
),
1060 PINMUX_IPSR_DATA(IP5_11_9
, SSI_WS6
),
1061 PINMUX_IPSR_MODSEL_DATA(IP5_11_9
, GLO_SCLK
, SEL_GPS_0
),
1062 PINMUX_IPSR_MODSEL_DATA(IP5_11_9
, MSIOF2_SS2_D
, SEL_SOF2_3
),
1063 PINMUX_IPSR_DATA(IP5_11_9
, VI1_R6_B
),
1064 PINMUX_IPSR_DATA(IP5_14_12
, SSI_SDATA6
),
1065 PINMUX_IPSR_MODSEL_DATA(IP5_14_12
, STP_IVCXO27_0_B
, SEL_SSP_1
),
1066 PINMUX_IPSR_MODSEL_DATA(IP5_14_12
, GLO_SDATA
, SEL_GPS_0
),
1067 PINMUX_IPSR_DATA(IP5_14_12
, VI1_R7_B
),
1068 PINMUX_IPSR_MODSEL_DATA(IP5_16_15
, SSI_SCK78
, SEL_SSI7_0
),
1069 PINMUX_IPSR_MODSEL_DATA(IP5_16_15
, STP_ISCLK_0_B
, SEL_SSP_1
),
1070 PINMUX_IPSR_MODSEL_DATA(IP5_16_15
, GLO_SS
, SEL_GPS_0
),
1071 PINMUX_IPSR_MODSEL_DATA(IP5_19_17
, SSI_WS78
, SEL_SSI7_0
),
1072 PINMUX_IPSR_MODSEL_DATA(IP5_19_17
, TX0_D
, SEL_SCIF0_3
),
1073 PINMUX_IPSR_MODSEL_DATA(IP5_19_17
, STP_ISD_0_B
, SEL_SSP_1
),
1074 PINMUX_IPSR_MODSEL_DATA(IP5_19_17
, GLO_RFON
, SEL_GPS_0
),
1075 PINMUX_IPSR_MODSEL_DATA(IP5_21_20
, SSI_SDATA7
, SEL_SSI7_0
),
1076 PINMUX_IPSR_MODSEL_DATA(IP5_21_20
, RX0_D
, SEL_SCIF0_3
),
1077 PINMUX_IPSR_MODSEL_DATA(IP5_21_20
, STP_ISEN_0_B
, SEL_SSP_1
),
1078 PINMUX_IPSR_MODSEL_DATA(IP5_23_22
, SSI_SDATA8
, SEL_SSI8_0
),
1079 PINMUX_IPSR_MODSEL_DATA(IP5_23_22
, TX1_D
, SEL_SCIF1_3
),
1080 PINMUX_IPSR_MODSEL_DATA(IP5_23_22
, STP_ISSYNC_0_B
, SEL_SSP_1
),
1081 PINMUX_IPSR_MODSEL_DATA(IP5_25_24
, SSI_SCK9
, SEL_SSI9_0
),
1082 PINMUX_IPSR_MODSEL_DATA(IP5_25_24
, RX1_D
, SEL_SCIF1_3
),
1083 PINMUX_IPSR_MODSEL_DATA(IP5_25_24
, GLO_SCLK_D
, SEL_GPS_3
),
1084 PINMUX_IPSR_MODSEL_DATA(IP5_28_26
, SSI_WS9
, SEL_SSI9_0
),
1085 PINMUX_IPSR_MODSEL_DATA(IP5_28_26
, TX3_D
, SEL_SCIF3_3
),
1086 PINMUX_IPSR_MODSEL_DATA(IP5_28_26
, CAN0_TX_D
, SEL_CAN0_3
),
1087 PINMUX_IPSR_MODSEL_DATA(IP5_28_26
, GLO_SDATA_D
, SEL_GPS_3
),
1088 PINMUX_IPSR_MODSEL_DATA(IP5_31_29
, SSI_SDATA9
, SEL_SSI9_0
),
1089 PINMUX_IPSR_MODSEL_DATA(IP5_31_29
, RX3_D
, SEL_SCIF3_3
),
1090 PINMUX_IPSR_MODSEL_DATA(IP5_31_29
, CAN0_RX_D
, SEL_CAN0_3
),
1093 PINMUX_IPSR_MODSEL_DATA(IP6_2_0
, AUDIO_CLKB
, SEL_ADG_0
),
1094 PINMUX_IPSR_MODSEL_DATA(IP6_2_0
, STP_OPWM_0_B
, SEL_SSP_1
),
1095 PINMUX_IPSR_MODSEL_DATA(IP6_2_0
, MSIOF1_SCK_B
, SEL_SOF1_1
),
1096 PINMUX_IPSR_MODSEL_DATA(IP6_2_0
, SCIF_CLK
, SEL_SCIF_0
),
1097 PINMUX_IPSR_MODSEL_DATA(IP6_2_0
, BPFCLK_E
, SEL_FM_4
),
1098 PINMUX_IPSR_DATA(IP6_5_3
, AUDIO_CLKC
),
1099 PINMUX_IPSR_MODSEL_DATA(IP6_5_3
, SCIFB0_SCK_C
, SEL_SCIFB_2
),
1100 PINMUX_IPSR_MODSEL_DATA(IP6_5_3
, MSIOF1_SYNC_B
, SEL_SOF1_1
),
1101 PINMUX_IPSR_MODSEL_DATA(IP6_5_3
, RX2
, SEL_SCIF2_0
),
1102 PINMUX_IPSR_MODSEL_DATA(IP6_5_3
, SCIFA2_RXD
, SEL_SCIFA2_0
),
1103 PINMUX_IPSR_MODSEL_DATA(IP6_5_3
, FMIN_E
, SEL_FM_4
),
1104 PINMUX_IPSR_DATA(IP6_7_6
, AUDIO_CLKOUT
),
1105 PINMUX_IPSR_MODSEL_DATA(IP6_7_6
, MSIOF1_SS1_B
, SEL_SOF1_1
),
1106 PINMUX_IPSR_MODSEL_DATA(IP6_5_3
, TX2
, SEL_SCIF2_0
),
1107 PINMUX_IPSR_MODSEL_DATA(IP6_7_6
, SCIFA2_TXD
, SEL_SCIFA2_0
),
1108 PINMUX_IPSR_DATA(IP6_9_8
, IRQ0
),
1109 PINMUX_IPSR_MODSEL_DATA(IP6_9_8
, SCIFB1_RXD_D
, SEL_SCIFB1_3
),
1110 PINMUX_IPSR_DATA(IP6_9_8
, INTC_IRQ0_N
),
1111 PINMUX_IPSR_DATA(IP6_11_10
, IRQ1
),
1112 PINMUX_IPSR_MODSEL_DATA(IP6_11_10
, SCIFB1_SCK_C
, SEL_SCIFB1_2
),
1113 PINMUX_IPSR_DATA(IP6_11_10
, INTC_IRQ1_N
),
1114 PINMUX_IPSR_DATA(IP6_13_12
, IRQ2
),
1115 PINMUX_IPSR_MODSEL_DATA(IP6_13_12
, SCIFB1_TXD_D
, SEL_SCIFB1_3
),
1116 PINMUX_IPSR_DATA(IP6_13_12
, INTC_IRQ2_N
),
1117 PINMUX_IPSR_DATA(IP6_15_14
, IRQ3
),
1118 PINMUX_IPSR_MODSEL_DATA(IP6_15_14
, SCL4_C
, SEL_IIC4_2
),
1119 PINMUX_IPSR_MODSEL_DATA(IP6_15_14
, MSIOF2_TXD_E
, SEL_SOF2_4
),
1120 PINMUX_IPSR_DATA(IP6_15_14
, INTC_IRQ4_N
),
1121 PINMUX_IPSR_DATA(IP6_18_16
, IRQ4
),
1122 PINMUX_IPSR_MODSEL_DATA(IP6_18_16
, HRX1_C
, SEL_HSCIF1_2
),
1123 PINMUX_IPSR_MODSEL_DATA(IP6_18_16
, SDA4_C
, SEL_IIC4_2
),
1124 PINMUX_IPSR_MODSEL_DATA(IP6_18_16
, MSIOF2_RXD_E
, SEL_SOF2_4
),
1125 PINMUX_IPSR_DATA(IP6_18_16
, INTC_IRQ4_N
),
1126 PINMUX_IPSR_DATA(IP6_20_19
, IRQ5
),
1127 PINMUX_IPSR_MODSEL_DATA(IP6_20_19
, HTX1_C
, SEL_HSCIF1_2
),
1128 PINMUX_IPSR_MODSEL_DATA(IP6_20_19
, SCL1_E
, SEL_IIC1_4
),
1129 PINMUX_IPSR_MODSEL_DATA(IP6_20_19
, MSIOF2_SCK_E
, SEL_SOF2_4
),
1130 PINMUX_IPSR_DATA(IP6_23_21
, IRQ6
),
1131 PINMUX_IPSR_MODSEL_DATA(IP6_23_21
, HSCK1_C
, SEL_HSCIF1_2
),
1132 PINMUX_IPSR_MODSEL_DATA(IP6_23_21
, MSIOF1_SS2_B
, SEL_SOF1_1
),
1133 PINMUX_IPSR_MODSEL_DATA(IP6_23_21
, SDA1_E
, SEL_IIC1_4
),
1134 PINMUX_IPSR_MODSEL_DATA(IP6_23_21
, MSIOF2_SYNC_E
, SEL_SOF2_4
),
1135 PINMUX_IPSR_DATA(IP6_26_24
, IRQ7
),
1136 PINMUX_IPSR_MODSEL_DATA(IP6_26_24
, HCTS1_N_C
, SEL_HSCIF1_2
),
1137 PINMUX_IPSR_MODSEL_DATA(IP6_26_24
, MSIOF1_TXD_B
, SEL_SOF1_1
),
1138 PINMUX_IPSR_MODSEL_DATA(IP6_26_24
, GPS_CLK_C
, SEL_GPS_2
),
1139 PINMUX_IPSR_MODSEL_DATA(IP6_26_24
, GPS_CLK_D
, SEL_GPS_3
),
1140 PINMUX_IPSR_DATA(IP6_29_27
, IRQ8
),
1141 PINMUX_IPSR_MODSEL_DATA(IP6_29_27
, HRTS1_N_C
, SEL_HSCIF1_2
),
1142 PINMUX_IPSR_MODSEL_DATA(IP6_29_27
, MSIOF1_RXD_B
, SEL_SOF1_1
),
1143 PINMUX_IPSR_MODSEL_DATA(IP6_29_27
, GPS_SIGN_C
, SEL_GPS_2
),
1144 PINMUX_IPSR_MODSEL_DATA(IP6_29_27
, GPS_SIGN_D
, SEL_GPS_3
),
1147 PINMUX_IPSR_DATA(IP7_2_0
, IRQ9
),
1148 PINMUX_IPSR_MODSEL_DATA(IP7_2_0
, DU1_DOTCLKIN_B
, SEL_DIS_1
),
1149 PINMUX_IPSR_MODSEL_DATA(IP7_2_0
, CAN_CLK_D
, SEL_CANCLK_3
),
1150 PINMUX_IPSR_MODSEL_DATA(IP7_2_0
, GPS_MAG_C
, SEL_GPS_2
),
1151 PINMUX_IPSR_MODSEL_DATA(IP7_2_0
, SCIF_CLK_B
, SEL_SCIF_1
),
1152 PINMUX_IPSR_MODSEL_DATA(IP7_2_0
, GPS_MAG_D
, SEL_GPS_3
),
1153 PINMUX_IPSR_DATA(IP7_5_3
, DU1_DR0
),
1154 PINMUX_IPSR_DATA(IP7_5_3
, LCDOUT0
),
1155 PINMUX_IPSR_MODSEL_DATA(IP7_5_3
, VI1_DATA0_B
, SEL_VI1_1
),
1156 PINMUX_IPSR_MODSEL_DATA(IP7_5_3
, TX0_B
, SEL_SCIF0_1
),
1157 PINMUX_IPSR_MODSEL_DATA(IP7_5_3
, SCIFA0_TXD_B
, SEL_SCFA_1
),
1158 PINMUX_IPSR_MODSEL_DATA(IP7_5_3
, MSIOF2_SCK_B
, SEL_SOF2_1
),
1159 PINMUX_IPSR_DATA(IP7_8_6
, DU1_DR1
),
1160 PINMUX_IPSR_DATA(IP7_8_6
, LCDOUT1
),
1161 PINMUX_IPSR_MODSEL_DATA(IP7_8_6
, VI1_DATA1_B
, SEL_VI1_1
),
1162 PINMUX_IPSR_MODSEL_DATA(IP7_8_6
, RX0_B
, SEL_SCIF0_1
),
1163 PINMUX_IPSR_MODSEL_DATA(IP7_8_6
, SCIFA0_RXD_B
, SEL_SCFA_1
),
1164 PINMUX_IPSR_MODSEL_DATA(IP7_8_6
, MSIOF2_SYNC_B
, SEL_SOF2_1
),
1165 PINMUX_IPSR_DATA(IP7_10_9
, DU1_DR2
),
1166 PINMUX_IPSR_DATA(IP7_10_9
, LCDOUT2
),
1167 PINMUX_IPSR_MODSEL_DATA(IP7_10_9
, SSI_SCK0129_B
, SEL_SSI0_1
),
1168 PINMUX_IPSR_DATA(IP7_12_11
, DU1_DR3
),
1169 PINMUX_IPSR_DATA(IP7_12_11
, LCDOUT3
),
1170 PINMUX_IPSR_MODSEL_DATA(IP7_12_11
, SSI_WS0129_B
, SEL_SSI0_1
),
1171 PINMUX_IPSR_DATA(IP7_14_13
, DU1_DR4
),
1172 PINMUX_IPSR_DATA(IP7_14_13
, LCDOUT4
),
1173 PINMUX_IPSR_MODSEL_DATA(IP7_14_13
, SSI_SDATA0_B
, SEL_SSI0_1
),
1174 PINMUX_IPSR_DATA(IP7_16_15
, DU1_DR5
),
1175 PINMUX_IPSR_DATA(IP7_16_15
, LCDOUT5
),
1176 PINMUX_IPSR_MODSEL_DATA(IP7_16_15
, SSI_SCK1_B
, SEL_SSI1_1
),
1177 PINMUX_IPSR_DATA(IP7_18_17
, DU1_DR6
),
1178 PINMUX_IPSR_DATA(IP7_18_17
, LCDOUT6
),
1179 PINMUX_IPSR_MODSEL_DATA(IP7_18_17
, SSI_WS1_B
, SEL_SSI1_1
),
1180 PINMUX_IPSR_DATA(IP7_20_19
, DU1_DR7
),
1181 PINMUX_IPSR_DATA(IP7_20_19
, LCDOUT7
),
1182 PINMUX_IPSR_MODSEL_DATA(IP7_20_19
, SSI_SDATA1_B
, SEL_SSI1_1
),
1183 PINMUX_IPSR_DATA(IP7_23_21
, DU1_DG0
),
1184 PINMUX_IPSR_DATA(IP7_23_21
, LCDOUT8
),
1185 PINMUX_IPSR_MODSEL_DATA(IP7_23_21
, VI1_DATA2_B
, SEL_VI1_1
),
1186 PINMUX_IPSR_MODSEL_DATA(IP7_23_21
, TX1_B
, SEL_SCIF1_1
),
1187 PINMUX_IPSR_MODSEL_DATA(IP7_23_21
, SCIFA1_TXD_B
, SEL_SCIFA1_1
),
1188 PINMUX_IPSR_MODSEL_DATA(IP7_23_21
, MSIOF2_SS1_B
, SEL_SOF2_1
),
1189 PINMUX_IPSR_DATA(IP7_26_24
, DU1_DG1
),
1190 PINMUX_IPSR_DATA(IP7_26_24
, LCDOUT9
),
1191 PINMUX_IPSR_MODSEL_DATA(IP7_26_24
, VI1_DATA3_B
, SEL_VI1_1
),
1192 PINMUX_IPSR_MODSEL_DATA(IP7_26_24
, RX1_B
, SEL_SCIF1_1
),
1193 PINMUX_IPSR_MODSEL_DATA(IP7_26_24
, SCIFA1_RXD_B
, SEL_SCIFA1_1
),
1194 PINMUX_IPSR_MODSEL_DATA(IP7_26_24
, MSIOF2_SS2_B
, SEL_SOF2_1
),
1195 PINMUX_IPSR_DATA(IP7_29_27
, DU1_DG2
),
1196 PINMUX_IPSR_DATA(IP7_29_27
, LCDOUT10
),
1197 PINMUX_IPSR_MODSEL_DATA(IP7_29_27
, VI1_DATA4_B
, SEL_VI1_1
),
1198 PINMUX_IPSR_DATA(IP7_29_27
, SCIF1_SCK_B
),
1199 PINMUX_IPSR_MODSEL_DATA(IP7_29_27
, SCIFA1_SCK
, SEL_SCIFA1_0
),
1200 PINMUX_IPSR_MODSEL_DATA(IP7_29_27
, SSI_SCK78_B
, SEL_SSI7_1
),
1203 PINMUX_IPSR_DATA(IP8_2_0
, DU1_DG3
),
1204 PINMUX_IPSR_DATA(IP8_2_0
, LCDOUT11
),
1205 PINMUX_IPSR_MODSEL_DATA(IP8_2_0
, VI1_DATA5_B
, SEL_VI1_1
),
1206 PINMUX_IPSR_MODSEL_DATA(IP8_2_0
, SSI_WS78_B
, SEL_SSI7_1
),
1207 PINMUX_IPSR_DATA(IP8_5_3
, DU1_DG4
),
1208 PINMUX_IPSR_DATA(IP8_5_3
, LCDOUT12
),
1209 PINMUX_IPSR_MODSEL_DATA(IP8_5_3
, VI1_DATA6_B
, SEL_VI1_1
),
1210 PINMUX_IPSR_MODSEL_DATA(IP8_5_3
, HRX0_B
, SEL_HSCIF0_1
),
1211 PINMUX_IPSR_MODSEL_DATA(IP8_5_3
, SCIFB2_RXD_B
, SEL_SCIFB2_1
),
1212 PINMUX_IPSR_MODSEL_DATA(IP8_5_3
, SSI_SDATA7_B
, SEL_SSI7_1
),
1213 PINMUX_IPSR_DATA(IP8_8_6
, DU1_DG5
),
1214 PINMUX_IPSR_DATA(IP8_8_6
, LCDOUT13
),
1215 PINMUX_IPSR_MODSEL_DATA(IP8_8_6
, VI1_DATA7_B
, SEL_VI1_1
),
1216 PINMUX_IPSR_MODSEL_DATA(IP8_8_6
, HCTS0_N_B
, SEL_HSCIF0_1
),
1217 PINMUX_IPSR_MODSEL_DATA(IP8_8_6
, SCIFB2_TXD_B
, SEL_SCIFB2_1
),
1218 PINMUX_IPSR_MODSEL_DATA(IP8_8_6
, SSI_SDATA8_B
, SEL_SSI8_1
),
1219 PINMUX_IPSR_DATA(IP8_11_9
, DU1_DG6
),
1220 PINMUX_IPSR_DATA(IP8_11_9
, LCDOUT14
),
1221 PINMUX_IPSR_MODSEL_DATA(IP8_11_9
, HRTS0_N_B
, SEL_HSCIF0_1
),
1222 PINMUX_IPSR_MODSEL_DATA(IP8_11_9
, SCIFB2_CTS_N_B
, SEL_SCIFB2_1
),
1223 PINMUX_IPSR_MODSEL_DATA(IP8_11_9
, SSI_SCK9_B
, SEL_SSI9_1
),
1224 PINMUX_IPSR_DATA(IP8_14_12
, DU1_DG7
),
1225 PINMUX_IPSR_DATA(IP8_14_12
, LCDOUT15
),
1226 PINMUX_IPSR_MODSEL_DATA(IP8_14_12
, HTX0_B
, SEL_HSCIF0_1
),
1227 PINMUX_IPSR_MODSEL_DATA(IP8_14_12
, SCIFB2_RTS_N_B
, SEL_SCIFB2_1
),
1228 PINMUX_IPSR_MODSEL_DATA(IP8_14_12
, SSI_WS9_B
, SEL_SSI9_1
),
1229 PINMUX_IPSR_DATA(IP8_17_15
, DU1_DB0
),
1230 PINMUX_IPSR_DATA(IP8_17_15
, LCDOUT16
),
1231 PINMUX_IPSR_MODSEL_DATA(IP8_17_15
, VI1_CLK_B
, SEL_VI1_1
),
1232 PINMUX_IPSR_MODSEL_DATA(IP8_17_15
, TX2_B
, SEL_SCIF2_1
),
1233 PINMUX_IPSR_MODSEL_DATA(IP8_17_15
, SCIFA2_TXD_B
, SEL_SCIFA2_1
),
1234 PINMUX_IPSR_MODSEL_DATA(IP8_17_15
, MSIOF2_TXD_B
, SEL_SOF2_1
),
1235 PINMUX_IPSR_DATA(IP8_20_18
, DU1_DB1
),
1236 PINMUX_IPSR_DATA(IP8_20_18
, LCDOUT17
),
1237 PINMUX_IPSR_MODSEL_DATA(IP8_20_18
, VI1_HSYNC_N_B
, SEL_VI1_1
),
1238 PINMUX_IPSR_MODSEL_DATA(IP8_20_18
, RX2_B
, SEL_SCIF2_1
),
1239 PINMUX_IPSR_MODSEL_DATA(IP8_20_18
, SCIFA2_RXD_B
, SEL_SCIFA2_1
),
1240 PINMUX_IPSR_MODSEL_DATA(IP8_20_18
, MSIOF2_RXD_B
, SEL_SOF2_1
),
1241 PINMUX_IPSR_DATA(IP8_23_21
, DU1_DB2
),
1242 PINMUX_IPSR_DATA(IP8_23_21
, LCDOUT18
),
1243 PINMUX_IPSR_MODSEL_DATA(IP8_23_21
, VI1_VSYNC_N_B
, SEL_VI1_1
),
1244 PINMUX_IPSR_DATA(IP8_23_21
, SCIF2_SCK_B
),
1245 PINMUX_IPSR_MODSEL_DATA(IP8_23_21
, SCIFA2_SCK
, SEL_SCIFA2_1
),
1246 PINMUX_IPSR_MODSEL_DATA(IP8_23_21
, SSI_SDATA9_B
, SEL_SSI9_1
),
1247 PINMUX_IPSR_DATA(IP8_25_24
, DU1_DB3
),
1248 PINMUX_IPSR_DATA(IP8_25_24
, LCDOUT19
),
1249 PINMUX_IPSR_MODSEL_DATA(IP8_25_24
, VI1_CLKENB_B
, SEL_VI1_1
),
1250 PINMUX_IPSR_DATA(IP8_27_26
, DU1_DB4
),
1251 PINMUX_IPSR_DATA(IP8_27_26
, LCDOUT20
),
1252 PINMUX_IPSR_MODSEL_DATA(IP8_27_26
, VI1_FIELD_B
, SEL_VI1_1
),
1253 PINMUX_IPSR_MODSEL_DATA(IP8_27_26
, CAN1_RX
, SEL_CAN1_0
),
1254 PINMUX_IPSR_DATA(IP8_30_28
, DU1_DB5
),
1255 PINMUX_IPSR_DATA(IP8_30_28
, LCDOUT21
),
1256 PINMUX_IPSR_MODSEL_DATA(IP8_30_28
, TX3
, SEL_SCIF3_0
),
1257 PINMUX_IPSR_MODSEL_DATA(IP8_30_28
, SCIFA3_TXD
, SEL_SCIFA3_0
),
1258 PINMUX_IPSR_MODSEL_DATA(IP8_30_28
, CAN1_TX
, SEL_CAN1_0
),
1261 PINMUX_IPSR_DATA(IP9_2_0
, DU1_DB6
),
1262 PINMUX_IPSR_DATA(IP9_2_0
, LCDOUT22
),
1263 PINMUX_IPSR_MODSEL_DATA(IP9_2_0
, SCL3_C
, SEL_IIC3_2
),
1264 PINMUX_IPSR_MODSEL_DATA(IP9_2_0
, RX3
, SEL_SCIF3_0
),
1265 PINMUX_IPSR_MODSEL_DATA(IP9_2_0
, SCIFA3_RXD
, SEL_SCIFA3_0
),
1266 PINMUX_IPSR_DATA(IP9_5_3
, DU1_DB7
),
1267 PINMUX_IPSR_DATA(IP9_5_3
, LCDOUT23
),
1268 PINMUX_IPSR_MODSEL_DATA(IP9_5_3
, SDA3_C
, SEL_IIC3_2
),
1269 PINMUX_IPSR_MODSEL_DATA(IP9_5_3
, SCIF3_SCK
, SEL_SCIF3_0
),
1270 PINMUX_IPSR_MODSEL_DATA(IP9_5_3
, SCIFA3_SCK
, SEL_SCIFA3_0
),
1271 PINMUX_IPSR_MODSEL_DATA(IP9_6
, DU1_DOTCLKIN
, SEL_DIS_0
),
1272 PINMUX_IPSR_DATA(IP9_6
, QSTVA_QVS
),
1273 PINMUX_IPSR_DATA(IP9_7
, DU1_DOTCLKOUT0
),
1274 PINMUX_IPSR_DATA(IP9_7
, QCLK
),
1275 PINMUX_IPSR_DATA(IP9_10_8
, DU1_DOTCLKOUT1
),
1276 PINMUX_IPSR_DATA(IP9_10_8
, QSTVB_QVE
),
1277 PINMUX_IPSR_MODSEL_DATA(IP9_10_8
, CAN0_TX
, SEL_CAN0_0
),
1278 PINMUX_IPSR_MODSEL_DATA(IP9_10_8
, TX3_B
, SEL_SCIF3_1
),
1279 PINMUX_IPSR_MODSEL_DATA(IP9_10_8
, SCL2_B
, SEL_IIC2_1
),
1280 PINMUX_IPSR_DATA(IP9_10_8
, PWM4
),
1281 PINMUX_IPSR_DATA(IP9_11
, DU1_EXHSYNC_DU1_HSYNC
),
1282 PINMUX_IPSR_DATA(IP9_11
, QSTH_QHS
),
1283 PINMUX_IPSR_DATA(IP9_12
, DU1_EXVSYNC_DU1_VSYNC
),
1284 PINMUX_IPSR_DATA(IP9_12
, QSTB_QHE
),
1285 PINMUX_IPSR_DATA(IP9_15_13
, DU1_EXODDF_DU1_ODDF_DISP_CDE
),
1286 PINMUX_IPSR_DATA(IP9_15_13
, QCPV_QDE
),
1287 PINMUX_IPSR_MODSEL_DATA(IP9_15_13
, CAN0_RX
, SEL_CAN0_0
),
1288 PINMUX_IPSR_MODSEL_DATA(IP9_15_13
, RX3_B
, SEL_SCIF3_1
),
1289 PINMUX_IPSR_MODSEL_DATA(IP9_15_13
, SDA2_B
, SEL_IIC2_1
),
1290 PINMUX_IPSR_DATA(IP9_16
, DU1_DISP
),
1291 PINMUX_IPSR_DATA(IP9_16
, QPOLA
),
1292 PINMUX_IPSR_DATA(IP9_18_17
, DU1_CDE
),
1293 PINMUX_IPSR_DATA(IP9_18_17
, QPOLB
),
1294 PINMUX_IPSR_DATA(IP9_18_17
, PWM4_B
),
1295 PINMUX_IPSR_DATA(IP9_20_19
, VI0_CLKENB
),
1296 PINMUX_IPSR_MODSEL_DATA(IP9_20_19
, TX4
, SEL_SCIF4_0
),
1297 PINMUX_IPSR_MODSEL_DATA(IP9_20_19
, SCIFA4_TXD
, SEL_SCIFA4_0
),
1298 PINMUX_IPSR_MODSEL_DATA(IP9_20_19
, TS_SDATA0_D
, SEL_TSIF0_3
),
1299 PINMUX_IPSR_DATA(IP9_22_21
, VI0_FIELD
),
1300 PINMUX_IPSR_MODSEL_DATA(IP9_22_21
, RX4
, SEL_SCIF4_0
),
1301 PINMUX_IPSR_MODSEL_DATA(IP9_22_21
, SCIFA4_RXD
, SEL_SCIFA4_0
),
1302 PINMUX_IPSR_MODSEL_DATA(IP9_22_21
, TS_SCK0_D
, SEL_TSIF0_3
),
1303 PINMUX_IPSR_DATA(IP9_24_23
, VI0_HSYNC_N
),
1304 PINMUX_IPSR_MODSEL_DATA(IP9_24_23
, TX5
, SEL_SCIF5_0
),
1305 PINMUX_IPSR_MODSEL_DATA(IP9_24_23
, SCIFA5_TXD
, SEL_SCIFA5_0
),
1306 PINMUX_IPSR_MODSEL_DATA(IP9_24_23
, TS_SDEN0_D
, SEL_TSIF0_3
),
1307 PINMUX_IPSR_DATA(IP9_26_25
, VI0_VSYNC_N
),
1308 PINMUX_IPSR_MODSEL_DATA(IP9_26_25
, RX5
, SEL_SCIF5_0
),
1309 PINMUX_IPSR_MODSEL_DATA(IP9_26_25
, SCIFA5_RXD
, SEL_SCIFA5_0
),
1310 PINMUX_IPSR_MODSEL_DATA(IP9_26_25
, TS_SPSYNC0_D
, SEL_TSIF0_3
),
1311 PINMUX_IPSR_DATA(IP9_28_27
, VI0_DATA3_VI0_B3
),
1312 PINMUX_IPSR_MODSEL_DATA(IP9_28_27
, SCIF3_SCK_B
, SEL_SCIF3_1
),
1313 PINMUX_IPSR_MODSEL_DATA(IP9_28_27
, SCIFA3_SCK_B
, SEL_SCIFA3_1
),
1314 PINMUX_IPSR_DATA(IP9_31_29
, VI0_G0
),
1315 PINMUX_IPSR_MODSEL_DATA(IP9_31_29
, SCL8
, SEL_IIC8_0
),
1316 PINMUX_IPSR_MODSEL_DATA(IP9_31_29
, STP_IVCXO27_0_C
, SEL_SSP_2
),
1317 PINMUX_IPSR_MODSEL_DATA(IP9_31_29
, SCL4
, SEL_IIC4_0
),
1318 PINMUX_IPSR_MODSEL_DATA(IP9_31_29
, HCTS2_N
, SEL_HSCIF2_0
),
1319 PINMUX_IPSR_MODSEL_DATA(IP9_31_29
, SCIFB2_CTS_N
, SEL_SCIFB2_0
),
1320 PINMUX_IPSR_DATA(IP9_31_29
, ATAWR1_N
),
1323 PINMUX_IPSR_DATA(IP10_2_0
, VI0_G1
),
1324 PINMUX_IPSR_MODSEL_DATA(IP10_2_0
, SDA8
, SEL_IIC8_0
),
1325 PINMUX_IPSR_MODSEL_DATA(IP10_2_0
, STP_ISCLK_0_C
, SEL_SSP_2
),
1326 PINMUX_IPSR_MODSEL_DATA(IP10_2_0
, SDA4
, SEL_IIC4_0
),
1327 PINMUX_IPSR_MODSEL_DATA(IP10_2_0
, HRTS2_N
, SEL_HSCIF2_0
),
1328 PINMUX_IPSR_MODSEL_DATA(IP10_2_0
, SCIFB2_RTS_N
, SEL_SCIFB2_0
),
1329 PINMUX_IPSR_DATA(IP10_2_0
, ATADIR1_N
),
1330 PINMUX_IPSR_DATA(IP10_5_3
, VI0_G2
),
1331 PINMUX_IPSR_DATA(IP10_5_3
, VI2_HSYNC_N
),
1332 PINMUX_IPSR_MODSEL_DATA(IP10_5_3
, STP_ISD_0_C
, SEL_SSP_2
),
1333 PINMUX_IPSR_MODSEL_DATA(IP10_5_3
, SCL3_B
, SEL_IIC3_1
),
1334 PINMUX_IPSR_MODSEL_DATA(IP10_5_3
, HSCK2
, SEL_HSCIF2_0
),
1335 PINMUX_IPSR_MODSEL_DATA(IP10_5_3
, SCIFB2_SCK
, SEL_SCIFB2_0
),
1336 PINMUX_IPSR_DATA(IP10_5_3
, ATARD1_N
),
1337 PINMUX_IPSR_DATA(IP10_8_6
, VI0_G3
),
1338 PINMUX_IPSR_DATA(IP10_8_6
, VI2_VSYNC_N
),
1339 PINMUX_IPSR_MODSEL_DATA(IP10_8_6
, STP_ISEN_0_C
, SEL_SSP_2
),
1340 PINMUX_IPSR_MODSEL_DATA(IP10_8_6
, SDA3_B
, SEL_IIC3_1
),
1341 PINMUX_IPSR_MODSEL_DATA(IP10_8_6
, HRX2
, SEL_HSCIF2_0
),
1342 PINMUX_IPSR_MODSEL_DATA(IP10_8_6
, SCIFB2_RXD
, SEL_SCIFB2_0
),
1343 PINMUX_IPSR_DATA(IP10_8_6
, ATACS01_N
),
1344 PINMUX_IPSR_DATA(IP10_11_9
, VI0_G4
),
1345 PINMUX_IPSR_DATA(IP10_11_9
, VI2_CLKENB
),
1346 PINMUX_IPSR_MODSEL_DATA(IP10_11_9
, STP_ISSYNC_0_C
, SEL_SSP_2
),
1347 PINMUX_IPSR_MODSEL_DATA(IP10_11_9
, HTX2
, SEL_HSCIF2_0
),
1348 PINMUX_IPSR_MODSEL_DATA(IP10_11_9
, SCIFB2_TXD
, SEL_SCIFB2_0
),
1349 PINMUX_IPSR_MODSEL_DATA(IP10_11_9
, SCIFB0_SCK_D
, SEL_SCIFB_3
),
1350 PINMUX_IPSR_DATA(IP10_14_12
, VI0_G5
),
1351 PINMUX_IPSR_DATA(IP10_14_12
, VI2_FIELD
),
1352 PINMUX_IPSR_MODSEL_DATA(IP10_14_12
, STP_OPWM_0_C
, SEL_SSP_2
),
1353 PINMUX_IPSR_MODSEL_DATA(IP10_14_12
, FMCLK_D
, SEL_FM_3
),
1354 PINMUX_IPSR_MODSEL_DATA(IP10_14_12
, CAN0_TX_E
, SEL_CAN0_4
),
1355 PINMUX_IPSR_MODSEL_DATA(IP10_14_12
, HTX1_D
, SEL_HSCIF1_3
),
1356 PINMUX_IPSR_MODSEL_DATA(IP10_14_12
, SCIFB0_TXD_D
, SEL_SCIFB_3
),
1357 PINMUX_IPSR_DATA(IP10_16_15
, VI0_G6
),
1358 PINMUX_IPSR_DATA(IP10_16_15
, VI2_CLK
),
1359 PINMUX_IPSR_MODSEL_DATA(IP10_16_15
, BPFCLK_D
, SEL_FM_3
),
1360 PINMUX_IPSR_DATA(IP10_18_17
, VI0_G7
),
1361 PINMUX_IPSR_DATA(IP10_18_17
, VI2_DATA0
),
1362 PINMUX_IPSR_MODSEL_DATA(IP10_18_17
, FMIN_D
, SEL_FM_3
),
1363 PINMUX_IPSR_DATA(IP10_21_19
, VI0_R0
),
1364 PINMUX_IPSR_DATA(IP10_21_19
, VI2_DATA1
),
1365 PINMUX_IPSR_MODSEL_DATA(IP10_21_19
, GLO_I0_B
, SEL_GPS_1
),
1366 PINMUX_IPSR_MODSEL_DATA(IP10_21_19
, TS_SDATA0_C
, SEL_TSIF0_2
),
1367 PINMUX_IPSR_DATA(IP10_21_19
, ATACS11_N
),
1368 PINMUX_IPSR_DATA(IP10_24_22
, VI0_R1
),
1369 PINMUX_IPSR_DATA(IP10_24_22
, VI2_DATA2
),
1370 PINMUX_IPSR_MODSEL_DATA(IP10_24_22
, GLO_I1_B
, SEL_GPS_1
),
1371 PINMUX_IPSR_MODSEL_DATA(IP10_24_22
, TS_SCK0_C
, SEL_TSIF0_2
),
1372 PINMUX_IPSR_DATA(IP10_24_22
, ATAG1_N
),
1373 PINMUX_IPSR_DATA(IP10_26_25
, VI0_R2
),
1374 PINMUX_IPSR_DATA(IP10_26_25
, VI2_DATA3
),
1375 PINMUX_IPSR_MODSEL_DATA(IP10_26_25
, GLO_Q0_B
, SEL_GPS_1
),
1376 PINMUX_IPSR_MODSEL_DATA(IP10_26_25
, TS_SDEN0_C
, SEL_TSIF0_2
),
1377 PINMUX_IPSR_DATA(IP10_28_27
, VI0_R3
),
1378 PINMUX_IPSR_DATA(IP10_28_27
, VI2_DATA4
),
1379 PINMUX_IPSR_MODSEL_DATA(IP10_28_27
, GLO_Q1_B
, SEL_GPS_1
),
1380 PINMUX_IPSR_MODSEL_DATA(IP10_28_27
, TS_SPSYNC0_C
, SEL_TSIF0_2
),
1381 PINMUX_IPSR_DATA(IP10_31_29
, VI0_R4
),
1382 PINMUX_IPSR_DATA(IP10_31_29
, VI2_DATA5
),
1383 PINMUX_IPSR_MODSEL_DATA(IP10_31_29
, GLO_SCLK_B
, SEL_GPS_1
),
1384 PINMUX_IPSR_MODSEL_DATA(IP10_31_29
, TX0_C
, SEL_SCIF0_2
),
1385 PINMUX_IPSR_MODSEL_DATA(IP10_31_29
, SCL1_D
, SEL_IIC1_3
),
1388 PINMUX_IPSR_DATA(IP11_2_0
, VI0_R5
),
1389 PINMUX_IPSR_DATA(IP11_2_0
, VI2_DATA6
),
1390 PINMUX_IPSR_MODSEL_DATA(IP11_2_0
, GLO_SDATA_B
, SEL_GPS_1
),
1391 PINMUX_IPSR_MODSEL_DATA(IP11_2_0
, RX0_C
, SEL_SCIF0_2
),
1392 PINMUX_IPSR_MODSEL_DATA(IP11_2_0
, SDA1_D
, SEL_IIC1_3
),
1393 PINMUX_IPSR_DATA(IP11_5_3
, VI0_R6
),
1394 PINMUX_IPSR_DATA(IP11_5_3
, VI2_DATA7
),
1395 PINMUX_IPSR_MODSEL_DATA(IP11_5_3
, GLO_SS_B
, SEL_GPS_1
),
1396 PINMUX_IPSR_MODSEL_DATA(IP11_5_3
, TX1_C
, SEL_SCIF1_2
),
1397 PINMUX_IPSR_MODSEL_DATA(IP11_5_3
, SCL4_B
, SEL_IIC4_1
),
1398 PINMUX_IPSR_DATA(IP11_8_6
, VI0_R7
),
1399 PINMUX_IPSR_MODSEL_DATA(IP11_8_6
, GLO_RFON_B
, SEL_GPS_1
),
1400 PINMUX_IPSR_MODSEL_DATA(IP11_8_6
, RX1_C
, SEL_SCIF1_2
),
1401 PINMUX_IPSR_MODSEL_DATA(IP11_8_6
, CAN0_RX_E
, SEL_CAN0_4
),
1402 PINMUX_IPSR_MODSEL_DATA(IP11_8_6
, SDA4_B
, SEL_IIC4_1
),
1403 PINMUX_IPSR_MODSEL_DATA(IP11_8_6
, HRX1_D
, SEL_HSCIF1_3
),
1404 PINMUX_IPSR_MODSEL_DATA(IP11_8_6
, SCIFB0_RXD_D
, SEL_SCIFB_3
),
1405 PINMUX_IPSR_MODSEL_DATA(IP11_11_9
, VI1_HSYNC_N
, SEL_VI1_0
),
1406 PINMUX_IPSR_DATA(IP11_11_9
, AVB_RXD0
),
1407 PINMUX_IPSR_MODSEL_DATA(IP11_11_9
, TS_SDATA0_B
, SEL_TSIF0_1
),
1408 PINMUX_IPSR_MODSEL_DATA(IP11_11_9
, TX4_B
, SEL_SCIF4_1
),
1409 PINMUX_IPSR_MODSEL_DATA(IP11_11_9
, SCIFA4_TXD_B
, SEL_SCIFA4_1
),
1410 PINMUX_IPSR_MODSEL_DATA(IP11_14_12
, VI1_VSYNC_N
, SEL_VI1_0
),
1411 PINMUX_IPSR_DATA(IP11_14_12
, AVB_RXD1
),
1412 PINMUX_IPSR_MODSEL_DATA(IP11_14_12
, TS_SCK0_B
, SEL_TSIF0_1
),
1413 PINMUX_IPSR_MODSEL_DATA(IP11_14_12
, RX4_B
, SEL_SCIF4_1
),
1414 PINMUX_IPSR_MODSEL_DATA(IP11_14_12
, SCIFA4_RXD_B
, SEL_SCIFA4_1
),
1415 PINMUX_IPSR_MODSEL_DATA(IP11_16_15
, VI1_CLKENB
, SEL_VI1_0
),
1416 PINMUX_IPSR_DATA(IP11_16_15
, AVB_RXD2
),
1417 PINMUX_IPSR_MODSEL_DATA(IP11_16_15
, TS_SDEN0_B
, SEL_TSIF0_1
),
1418 PINMUX_IPSR_MODSEL_DATA(IP11_18_17
, VI1_FIELD
, SEL_VI1_0
),
1419 PINMUX_IPSR_DATA(IP11_18_17
, AVB_RXD3
),
1420 PINMUX_IPSR_MODSEL_DATA(IP11_18_17
, TS_SPSYNC0_B
, SEL_TSIF0_1
),
1421 PINMUX_IPSR_MODSEL_DATA(IP11_19
, VI1_CLK
, SEL_VI1_0
),
1422 PINMUX_IPSR_DATA(IP11_19
, AVB_RXD4
),
1423 PINMUX_IPSR_MODSEL_DATA(IP11_20
, VI1_DATA0
, SEL_VI1_0
),
1424 PINMUX_IPSR_DATA(IP11_20
, AVB_RXD5
),
1425 PINMUX_IPSR_MODSEL_DATA(IP11_21
, VI1_DATA1
, SEL_VI1_0
),
1426 PINMUX_IPSR_DATA(IP11_21
, AVB_RXD6
),
1427 PINMUX_IPSR_MODSEL_DATA(IP11_22
, VI1_DATA2
, SEL_VI1_0
),
1428 PINMUX_IPSR_DATA(IP11_22
, AVB_RXD7
),
1429 PINMUX_IPSR_MODSEL_DATA(IP11_23
, VI1_DATA3
, SEL_VI1_0
),
1430 PINMUX_IPSR_DATA(IP11_23
, AVB_RX_ER
),
1431 PINMUX_IPSR_MODSEL_DATA(IP11_24
, VI1_DATA4
, SEL_VI1_0
),
1432 PINMUX_IPSR_DATA(IP11_24
, AVB_MDIO
),
1433 PINMUX_IPSR_MODSEL_DATA(IP11_25
, VI1_DATA5
, SEL_VI1_0
),
1434 PINMUX_IPSR_DATA(IP11_25
, AVB_RX_DV
),
1435 PINMUX_IPSR_MODSEL_DATA(IP11_26
, VI1_DATA6
, SEL_VI1_0
),
1436 PINMUX_IPSR_DATA(IP11_26
, AVB_MAGIC
),
1437 PINMUX_IPSR_MODSEL_DATA(IP11_27
, VI1_DATA7
, SEL_VI1_0
),
1438 PINMUX_IPSR_DATA(IP11_27
, AVB_MDC
),
1439 PINMUX_IPSR_DATA(IP11_29_28
, ETH_MDIO
),
1440 PINMUX_IPSR_DATA(IP11_29_28
, AVB_RX_CLK
),
1441 PINMUX_IPSR_MODSEL_DATA(IP11_29_28
, SCL2_C
, SEL_IIC2_2
),
1442 PINMUX_IPSR_DATA(IP11_31_30
, ETH_CRS_DV
),
1443 PINMUX_IPSR_DATA(IP11_31_30
, AVB_LINK
),
1444 PINMUX_IPSR_MODSEL_DATA(IP11_31_30
, SDA2_C
, SEL_IIC2_2
),
1447 PINMUX_IPSR_DATA(IP12_1_0
, ETH_RX_ER
),
1448 PINMUX_IPSR_DATA(IP12_1_0
, AVB_CRS
),
1449 PINMUX_IPSR_MODSEL_DATA(IP12_1_0
, SCL3
, SEL_IIC3_0
),
1450 PINMUX_IPSR_MODSEL_DATA(IP12_1_0
, SCL7
, SEL_IIC7_0
),
1451 PINMUX_IPSR_DATA(IP12_3_2
, ETH_RXD0
),
1452 PINMUX_IPSR_DATA(IP12_3_2
, AVB_PHY_INT
),
1453 PINMUX_IPSR_MODSEL_DATA(IP12_3_2
, SDA3
, SEL_IIC3_0
),
1454 PINMUX_IPSR_MODSEL_DATA(IP12_3_2
, SDA7
, SEL_IIC7_0
),
1455 PINMUX_IPSR_DATA(IP12_6_4
, ETH_RXD1
),
1456 PINMUX_IPSR_DATA(IP12_6_4
, AVB_GTXREFCLK
),
1457 PINMUX_IPSR_MODSEL_DATA(IP12_6_4
, CAN0_TX_C
, SEL_CAN0_2
),
1458 PINMUX_IPSR_MODSEL_DATA(IP12_6_4
, SCL2_D
, SEL_IIC2_3
),
1459 PINMUX_IPSR_MODSEL_DATA(IP12_6_4
, MSIOF1_RXD_E
, SEL_SOF1_4
),
1460 PINMUX_IPSR_DATA(IP12_9_7
, ETH_LINK
),
1461 PINMUX_IPSR_DATA(IP12_9_7
, AVB_TXD0
),
1462 PINMUX_IPSR_MODSEL_DATA(IP12_9_7
, CAN0_RX_C
, SEL_CAN0_2
),
1463 PINMUX_IPSR_MODSEL_DATA(IP12_9_7
, SDA2_D
, SEL_IIC2_3
),
1464 PINMUX_IPSR_MODSEL_DATA(IP12_9_7
, MSIOF1_SCK_E
, SEL_SOF1_4
),
1465 PINMUX_IPSR_DATA(IP12_12_10
, ETH_REFCLK
),
1466 PINMUX_IPSR_DATA(IP12_12_10
, AVB_TXD1
),
1467 PINMUX_IPSR_MODSEL_DATA(IP12_12_10
, SCIFA3_RXD_B
, SEL_SCIFA3_1
),
1468 PINMUX_IPSR_MODSEL_DATA(IP12_12_10
, CAN1_RX_C
, SEL_CAN1_2
),
1469 PINMUX_IPSR_MODSEL_DATA(IP12_12_10
, MSIOF1_SYNC_E
, SEL_SOF1_4
),
1470 PINMUX_IPSR_DATA(IP12_15_13
, ETH_TXD1
),
1471 PINMUX_IPSR_DATA(IP12_15_13
, AVB_TXD2
),
1472 PINMUX_IPSR_MODSEL_DATA(IP12_15_13
, SCIFA3_TXD_B
, SEL_SCIFA3_1
),
1473 PINMUX_IPSR_MODSEL_DATA(IP12_15_13
, CAN1_TX_C
, SEL_CAN1_2
),
1474 PINMUX_IPSR_MODSEL_DATA(IP12_15_13
, MSIOF1_TXD_E
, SEL_SOF1_4
),
1475 PINMUX_IPSR_DATA(IP12_17_16
, ETH_TX_EN
),
1476 PINMUX_IPSR_DATA(IP12_17_16
, AVB_TXD3
),
1477 PINMUX_IPSR_MODSEL_DATA(IP12_17_16
, TCLK1_B
, SEL_TMU1_0
),
1478 PINMUX_IPSR_MODSEL_DATA(IP12_17_16
, CAN_CLK_B
, SEL_CANCLK_1
),
1479 PINMUX_IPSR_DATA(IP12_19_18
, ETH_MAGIC
),
1480 PINMUX_IPSR_DATA(IP12_19_18
, AVB_TXD4
),
1481 PINMUX_IPSR_MODSEL_DATA(IP12_19_18
, IETX_C
, SEL_IEB_2
),
1482 PINMUX_IPSR_DATA(IP12_21_20
, ETH_TXD0
),
1483 PINMUX_IPSR_DATA(IP12_21_20
, AVB_TXD5
),
1484 PINMUX_IPSR_MODSEL_DATA(IP12_21_20
, IECLK_C
, SEL_IEB_2
),
1485 PINMUX_IPSR_DATA(IP12_23_22
, ETH_MDC
),
1486 PINMUX_IPSR_DATA(IP12_23_22
, AVB_TXD6
),
1487 PINMUX_IPSR_MODSEL_DATA(IP12_23_22
, IERX_C
, SEL_IEB_2
),
1488 PINMUX_IPSR_MODSEL_DATA(IP12_26_24
, STP_IVCXO27_0
, SEL_SSP_0
),
1489 PINMUX_IPSR_DATA(IP12_26_24
, AVB_TXD7
),
1490 PINMUX_IPSR_MODSEL_DATA(IP12_26_24
, SCIFB2_TXD_D
, SEL_SCIFB2_3
),
1491 PINMUX_IPSR_MODSEL_DATA(IP12_26_24
, ADIDATA_B
, SEL_RAD_1
),
1492 PINMUX_IPSR_MODSEL_DATA(IP12_26_24
, MSIOF0_SYNC_C
, SEL_SOF0_2
),
1493 PINMUX_IPSR_MODSEL_DATA(IP12_29_27
, STP_ISCLK_0
, SEL_SSP_0
),
1494 PINMUX_IPSR_DATA(IP12_29_27
, AVB_TX_EN
),
1495 PINMUX_IPSR_MODSEL_DATA(IP12_29_27
, SCIFB2_RXD_D
, SEL_SCIFB2_3
),
1496 PINMUX_IPSR_MODSEL_DATA(IP12_29_27
, ADICS_SAMP_B
, SEL_RAD_1
),
1497 PINMUX_IPSR_MODSEL_DATA(IP12_29_27
, MSIOF0_SCK_C
, SEL_SOF0_2
),
1500 PINMUX_IPSR_MODSEL_DATA(IP13_2_0
, STP_ISD_0
, SEL_SSP_0
),
1501 PINMUX_IPSR_DATA(IP13_2_0
, AVB_TX_ER
),
1502 PINMUX_IPSR_MODSEL_DATA(IP13_2_0
, SCIFB2_SCK_C
, SEL_SCIFB2_2
),
1503 PINMUX_IPSR_MODSEL_DATA(IP13_2_0
, ADICLK_B
, SEL_RAD_1
),
1504 PINMUX_IPSR_MODSEL_DATA(IP13_2_0
, MSIOF0_SS1_C
, SEL_SOF0_2
),
1505 PINMUX_IPSR_MODSEL_DATA(IP13_4_3
, STP_ISEN_0
, SEL_SSP_0
),
1506 PINMUX_IPSR_DATA(IP13_4_3
, AVB_TX_CLK
),
1507 PINMUX_IPSR_MODSEL_DATA(IP13_4_3
, ADICHS0_B
, SEL_RAD_1
),
1508 PINMUX_IPSR_MODSEL_DATA(IP13_4_3
, MSIOF0_SS2_C
, SEL_SOF0_2
),
1509 PINMUX_IPSR_MODSEL_DATA(IP13_6_5
, STP_ISSYNC_0
, SEL_SSP_0
),
1510 PINMUX_IPSR_DATA(IP13_6_5
, AVB_COL
),
1511 PINMUX_IPSR_MODSEL_DATA(IP13_6_5
, ADICHS1_B
, SEL_RAD_1
),
1512 PINMUX_IPSR_MODSEL_DATA(IP13_6_5
, MSIOF0_RXD_C
, SEL_SOF0_2
),
1513 PINMUX_IPSR_MODSEL_DATA(IP13_9_7
, STP_OPWM_0
, SEL_SSP_0
),
1514 PINMUX_IPSR_DATA(IP13_9_7
, AVB_GTX_CLK
),
1515 PINMUX_IPSR_DATA(IP13_9_7
, PWM0_B
),
1516 PINMUX_IPSR_MODSEL_DATA(IP13_9_7
, ADICHS2_B
, SEL_RAD_1
),
1517 PINMUX_IPSR_MODSEL_DATA(IP13_9_7
, MSIOF0_TXD_C
, SEL_SOF0_2
),
1518 PINMUX_IPSR_DATA(IP13_10
, SD0_CLK
),
1519 PINMUX_IPSR_MODSEL_DATA(IP13_10
, SPCLK_B
, SEL_QSP_1
),
1520 PINMUX_IPSR_DATA(IP13_11
, SD0_CMD
),
1521 PINMUX_IPSR_MODSEL_DATA(IP13_11
, MOSI_IO0_B
, SEL_QSP_1
),
1522 PINMUX_IPSR_DATA(IP13_12
, SD0_DATA0
),
1523 PINMUX_IPSR_MODSEL_DATA(IP13_12
, MISO_IO1_B
, SEL_QSP_1
),
1524 PINMUX_IPSR_DATA(IP13_13
, SD0_DATA1
),
1525 PINMUX_IPSR_MODSEL_DATA(IP13_13
, IO2_B
, SEL_QSP_1
),
1526 PINMUX_IPSR_DATA(IP13_14
, SD0_DATA2
),
1527 PINMUX_IPSR_MODSEL_DATA(IP13_14
, IO3_B
, SEL_QSP_1
),
1528 PINMUX_IPSR_DATA(IP13_15
, SD0_DATA3
),
1529 PINMUX_IPSR_MODSEL_DATA(IP13_15
, SSL_B
, SEL_QSP_1
),
1530 PINMUX_IPSR_DATA(IP13_18_16
, SD0_CD
),
1531 PINMUX_IPSR_MODSEL_DATA(IP13_18_16
, MMC_D6_B
, SEL_MMC_1
),
1532 PINMUX_IPSR_MODSEL_DATA(IP13_18_16
, SIM0_RST_B
, SEL_SIM_1
),
1533 PINMUX_IPSR_MODSEL_DATA(IP13_18_16
, CAN0_RX_F
, SEL_CAN0_5
),
1534 PINMUX_IPSR_MODSEL_DATA(IP13_18_16
, SCIFA5_TXD_B
, SEL_SCIFA5_1
),
1535 PINMUX_IPSR_MODSEL_DATA(IP13_18_16
, TX3_C
, SEL_SCIF3_2
),
1536 PINMUX_IPSR_DATA(IP13_21_19
, SD0_WP
),
1537 PINMUX_IPSR_MODSEL_DATA(IP13_21_19
, MMC_D7_B
, SEL_MMC_1
),
1538 PINMUX_IPSR_MODSEL_DATA(IP13_21_19
, SIM0_D_B
, SEL_SIM_1
),
1539 PINMUX_IPSR_MODSEL_DATA(IP13_21_19
, CAN0_TX_F
, SEL_CAN0_5
),
1540 PINMUX_IPSR_MODSEL_DATA(IP13_21_19
, SCIFA5_RXD_B
, SEL_SCIFA5_1
),
1541 PINMUX_IPSR_MODSEL_DATA(IP13_21_19
, RX3_C
, SEL_SCIF3_2
),
1542 PINMUX_IPSR_DATA(IP13_22
, SD1_CMD
),
1543 PINMUX_IPSR_MODSEL_DATA(IP13_22
, REMOCON_B
, SEL_RCN_1
),
1544 PINMUX_IPSR_DATA(IP13_24_23
, SD1_DATA0
),
1545 PINMUX_IPSR_MODSEL_DATA(IP13_24_23
, SPEEDIN_B
, SEL_RSP_1
),
1546 PINMUX_IPSR_DATA(IP13_25
, SD1_DATA1
),
1547 PINMUX_IPSR_MODSEL_DATA(IP13_25
, IETX_B
, SEL_IEB_1
),
1548 PINMUX_IPSR_DATA(IP13_26
, SD1_DATA2
),
1549 PINMUX_IPSR_MODSEL_DATA(IP13_26
, IECLK_B
, SEL_IEB_1
),
1550 PINMUX_IPSR_DATA(IP13_27
, SD1_DATA3
),
1551 PINMUX_IPSR_MODSEL_DATA(IP13_27
, IERX_B
, SEL_IEB_1
),
1552 PINMUX_IPSR_DATA(IP13_30_28
, SD1_CD
),
1553 PINMUX_IPSR_DATA(IP13_30_28
, PWM0
),
1554 PINMUX_IPSR_DATA(IP13_30_28
, TPU_TO0
),
1555 PINMUX_IPSR_MODSEL_DATA(IP13_30_28
, SCL1_C
, SEL_IIC1_2
),
1558 PINMUX_IPSR_DATA(IP14_1_0
, SD1_WP
),
1559 PINMUX_IPSR_DATA(IP14_1_0
, PWM1_B
),
1560 PINMUX_IPSR_MODSEL_DATA(IP14_1_0
, SDA1_C
, SEL_IIC1_2
),
1561 PINMUX_IPSR_DATA(IP14_2
, SD2_CLK
),
1562 PINMUX_IPSR_DATA(IP14_2
, MMC_CLK
),
1563 PINMUX_IPSR_DATA(IP14_3
, SD2_CMD
),
1564 PINMUX_IPSR_DATA(IP14_3
, MMC_CMD
),
1565 PINMUX_IPSR_DATA(IP14_4
, SD2_DATA0
),
1566 PINMUX_IPSR_DATA(IP14_4
, MMC_D0
),
1567 PINMUX_IPSR_DATA(IP14_5
, SD2_DATA1
),
1568 PINMUX_IPSR_DATA(IP14_5
, MMC_D1
),
1569 PINMUX_IPSR_DATA(IP14_6
, SD2_DATA2
),
1570 PINMUX_IPSR_DATA(IP14_6
, MMC_D2
),
1571 PINMUX_IPSR_DATA(IP14_7
, SD2_DATA3
),
1572 PINMUX_IPSR_DATA(IP14_7
, MMC_D3
),
1573 PINMUX_IPSR_DATA(IP14_10_8
, SD2_CD
),
1574 PINMUX_IPSR_DATA(IP14_10_8
, MMC_D4
),
1575 PINMUX_IPSR_MODSEL_DATA(IP14_10_8
, SCL8_C
, SEL_IIC8_2
),
1576 PINMUX_IPSR_MODSEL_DATA(IP14_10_8
, TX5_B
, SEL_SCIF5_1
),
1577 PINMUX_IPSR_MODSEL_DATA(IP14_10_8
, SCIFA5_TXD_C
, SEL_SCIFA5_2
),
1578 PINMUX_IPSR_DATA(IP14_13_11
, SD2_WP
),
1579 PINMUX_IPSR_DATA(IP14_13_11
, MMC_D5
),
1580 PINMUX_IPSR_MODSEL_DATA(IP14_13_11
, SDA8_C
, SEL_IIC8_2
),
1581 PINMUX_IPSR_MODSEL_DATA(IP14_13_11
, RX5_B
, SEL_SCIF5_1
),
1582 PINMUX_IPSR_MODSEL_DATA(IP14_13_11
, SCIFA5_RXD_C
, SEL_SCIFA5_2
),
1583 PINMUX_IPSR_MODSEL_DATA(IP14_16_14
, MSIOF0_SCK
, SEL_SOF0_0
),
1584 PINMUX_IPSR_MODSEL_DATA(IP14_16_14
, RX2_C
, SEL_SCIF2_2
),
1585 PINMUX_IPSR_MODSEL_DATA(IP14_16_14
, ADIDATA
, SEL_RAD_0
),
1586 PINMUX_IPSR_MODSEL_DATA(IP14_16_14
, VI1_CLK_C
, SEL_VI1_2
),
1587 PINMUX_IPSR_DATA(IP14_16_14
, VI1_G0_B
),
1588 PINMUX_IPSR_MODSEL_DATA(IP14_19_17
, MSIOF0_SYNC
, SEL_SOF0_0
),
1589 PINMUX_IPSR_MODSEL_DATA(IP14_19_17
, TX2_C
, SEL_SCIF2_2
),
1590 PINMUX_IPSR_MODSEL_DATA(IP14_19_17
, ADICS_SAMP
, SEL_RAD_0
),
1591 PINMUX_IPSR_MODSEL_DATA(IP14_19_17
, VI1_CLKENB_C
, SEL_VI1_2
),
1592 PINMUX_IPSR_DATA(IP14_19_17
, VI1_G1_B
),
1593 PINMUX_IPSR_MODSEL_DATA(IP14_22_20
, MSIOF0_TXD
, SEL_SOF0_0
),
1594 PINMUX_IPSR_MODSEL_DATA(IP14_22_20
, ADICLK
, SEL_RAD_0
),
1595 PINMUX_IPSR_MODSEL_DATA(IP14_22_20
, VI1_FIELD_C
, SEL_VI1_2
),
1596 PINMUX_IPSR_DATA(IP14_22_20
, VI1_G2_B
),
1597 PINMUX_IPSR_MODSEL_DATA(IP14_25_23
, MSIOF0_RXD
, SEL_SOF0_0
),
1598 PINMUX_IPSR_MODSEL_DATA(IP14_25_23
, ADICHS0
, SEL_RAD_0
),
1599 PINMUX_IPSR_MODSEL_DATA(IP14_25_23
, VI1_DATA0_C
, SEL_VI1_2
),
1600 PINMUX_IPSR_DATA(IP14_25_23
, VI1_G3_B
),
1601 PINMUX_IPSR_MODSEL_DATA(IP14_28_26
, MSIOF0_SS1
, SEL_SOF0_0
),
1602 PINMUX_IPSR_MODSEL_DATA(IP14_28_26
, MMC_D6
, SEL_MMC_0
),
1603 PINMUX_IPSR_MODSEL_DATA(IP14_28_26
, ADICHS1
, SEL_RAD_0
),
1604 PINMUX_IPSR_MODSEL_DATA(IP14_28_26
, TX0_E
, SEL_SCIF0_4
),
1605 PINMUX_IPSR_MODSEL_DATA(IP14_28_26
, VI1_HSYNC_N_C
, SEL_VI1_2
),
1606 PINMUX_IPSR_MODSEL_DATA(IP14_28_26
, SCL7_C
, SEL_IIC7_2
),
1607 PINMUX_IPSR_DATA(IP14_28_26
, VI1_G4_B
),
1608 PINMUX_IPSR_MODSEL_DATA(IP14_31_29
, MSIOF0_SS2
, SEL_SOF0_0
),
1609 PINMUX_IPSR_MODSEL_DATA(IP14_31_29
, MMC_D7
, SEL_MMC_0
),
1610 PINMUX_IPSR_MODSEL_DATA(IP14_31_29
, ADICHS2
, SEL_RAD_0
),
1611 PINMUX_IPSR_MODSEL_DATA(IP14_31_29
, RX0_E
, SEL_SCIF0_4
),
1612 PINMUX_IPSR_MODSEL_DATA(IP14_31_29
, VI1_VSYNC_N_C
, SEL_VI1_2
),
1613 PINMUX_IPSR_MODSEL_DATA(IP14_31_29
, SDA7_C
, SEL_IIC7_2
),
1614 PINMUX_IPSR_DATA(IP14_31_29
, VI1_G5_B
),
1617 PINMUX_IPSR_MODSEL_DATA(IP15_1_0
, SIM0_RST
, SEL_SIM_0
),
1618 PINMUX_IPSR_MODSEL_DATA(IP15_1_0
, IETX
, SEL_IEB_0
),
1619 PINMUX_IPSR_MODSEL_DATA(IP15_1_0
, CAN1_TX_D
, SEL_CAN1_3
),
1620 PINMUX_IPSR_DATA(IP15_3_2
, SIM0_CLK
),
1621 PINMUX_IPSR_MODSEL_DATA(IP15_3_2
, IECLK
, SEL_IEB_0
),
1622 PINMUX_IPSR_MODSEL_DATA(IP15_3_2
, CAN_CLK_C
, SEL_CANCLK_2
),
1623 PINMUX_IPSR_MODSEL_DATA(IP15_5_4
, SIM0_D
, SEL_SIM_0
),
1624 PINMUX_IPSR_MODSEL_DATA(IP15_5_4
, IERX
, SEL_IEB_0
),
1625 PINMUX_IPSR_MODSEL_DATA(IP15_5_4
, CAN1_RX_D
, SEL_CAN1_3
),
1626 PINMUX_IPSR_MODSEL_DATA(IP15_8_6
, GPS_CLK
, SEL_GPS_0
),
1627 PINMUX_IPSR_MODSEL_DATA(IP15_8_6
, DU1_DOTCLKIN_C
, SEL_DIS_2
),
1628 PINMUX_IPSR_MODSEL_DATA(IP15_8_6
, AUDIO_CLKB_B
, SEL_ADG_1
),
1629 PINMUX_IPSR_DATA(IP15_8_6
, PWM5_B
),
1630 PINMUX_IPSR_MODSEL_DATA(IP15_8_6
, SCIFA3_TXD_C
, SEL_SCIFA3_2
),
1631 PINMUX_IPSR_MODSEL_DATA(IP15_11_9
, GPS_SIGN
, SEL_GPS_0
),
1632 PINMUX_IPSR_MODSEL_DATA(IP15_11_9
, TX4_C
, SEL_SCIF4_2
),
1633 PINMUX_IPSR_MODSEL_DATA(IP15_11_9
, SCIFA4_TXD_C
, SEL_SCIFA4_2
),
1634 PINMUX_IPSR_DATA(IP15_11_9
, PWM5
),
1635 PINMUX_IPSR_DATA(IP15_11_9
, VI1_G6_B
),
1636 PINMUX_IPSR_MODSEL_DATA(IP15_11_9
, SCIFA3_RXD_C
, SEL_SCIFA3_2
),
1637 PINMUX_IPSR_MODSEL_DATA(IP15_14_12
, GPS_MAG
, SEL_GPS_0
),
1638 PINMUX_IPSR_MODSEL_DATA(IP15_14_12
, RX4_C
, SEL_SCIF4_2
),
1639 PINMUX_IPSR_MODSEL_DATA(IP15_14_12
, SCIFA4_RXD_C
, SEL_SCIFA4_2
),
1640 PINMUX_IPSR_DATA(IP15_14_12
, PWM6
),
1641 PINMUX_IPSR_DATA(IP15_14_12
, VI1_G7_B
),
1642 PINMUX_IPSR_MODSEL_DATA(IP15_14_12
, SCIFA3_SCK_C
, SEL_SCIFA3_2
),
1643 PINMUX_IPSR_MODSEL_DATA(IP15_17_15
, HCTS0_N
, SEL_HSCIF0_0
),
1644 PINMUX_IPSR_MODSEL_DATA(IP15_17_15
, SCIFB0_CTS_N
, SEL_SCIFB_0
),
1645 PINMUX_IPSR_MODSEL_DATA(IP15_17_15
, GLO_I0_C
, SEL_GPS_2
),
1646 PINMUX_IPSR_MODSEL_DATA(IP15_17_15
, TCLK1
, SEL_TMU1_0
),
1647 PINMUX_IPSR_MODSEL_DATA(IP15_17_15
, VI1_DATA1_C
, SEL_VI1_2
),
1648 PINMUX_IPSR_MODSEL_DATA(IP15_20_18
, HRTS0_N
, SEL_HSCIF0_0
),
1649 PINMUX_IPSR_MODSEL_DATA(IP15_20_18
, SCIFB0_RTS_N
, SEL_SCIFB_0
),
1650 PINMUX_IPSR_MODSEL_DATA(IP15_20_18
, GLO_I1_C
, SEL_GPS_2
),
1651 PINMUX_IPSR_MODSEL_DATA(IP15_20_18
, VI1_DATA2_C
, SEL_VI1_2
),
1652 PINMUX_IPSR_MODSEL_DATA(IP15_23_21
, HSCK0
, SEL_HSCIF0_0
),
1653 PINMUX_IPSR_MODSEL_DATA(IP15_23_21
, SCIFB0_SCK
, SEL_SCIFB_0
),
1654 PINMUX_IPSR_MODSEL_DATA(IP15_23_21
, GLO_Q0_C
, SEL_GPS_2
),
1655 PINMUX_IPSR_MODSEL_DATA(IP15_23_21
, CAN_CLK
, SEL_CANCLK_0
),
1656 PINMUX_IPSR_DATA(IP15_23_21
, TCLK2
),
1657 PINMUX_IPSR_MODSEL_DATA(IP15_23_21
, VI1_DATA3_C
, SEL_VI1_2
),
1658 PINMUX_IPSR_MODSEL_DATA(IP15_26_24
, HRX0
, SEL_HSCIF0_0
),
1659 PINMUX_IPSR_MODSEL_DATA(IP15_26_24
, SCIFB0_RXD
, SEL_SCIFB_0
),
1660 PINMUX_IPSR_MODSEL_DATA(IP15_26_24
, GLO_Q1_C
, SEL_GPS_2
),
1661 PINMUX_IPSR_MODSEL_DATA(IP15_26_24
, CAN0_RX_B
, SEL_CAN0_1
),
1662 PINMUX_IPSR_MODSEL_DATA(IP15_26_24
, VI1_DATA4_C
, SEL_VI1_2
),
1663 PINMUX_IPSR_MODSEL_DATA(IP15_29_27
, HTX0
, SEL_HSCIF0_0
),
1664 PINMUX_IPSR_MODSEL_DATA(IP15_29_27
, SCIFB0_TXD
, SEL_SCIFB_0
),
1665 PINMUX_IPSR_MODSEL_DATA(IP15_29_27
, GLO_SCLK_C
, SEL_GPS_2
),
1666 PINMUX_IPSR_MODSEL_DATA(IP15_29_27
, CAN0_TX_B
, SEL_CAN0_1
),
1667 PINMUX_IPSR_MODSEL_DATA(IP15_29_27
, VI1_DATA5_C
, SEL_VI1_2
),
1670 PINMUX_IPSR_MODSEL_DATA(IP16_2_0
, HRX1
, SEL_HSCIF1_0
),
1671 PINMUX_IPSR_MODSEL_DATA(IP16_2_0
, SCIFB1_RXD
, SEL_SCIFB1_0
),
1672 PINMUX_IPSR_DATA(IP16_2_0
, VI1_R0_B
),
1673 PINMUX_IPSR_MODSEL_DATA(IP16_2_0
, GLO_SDATA_C
, SEL_GPS_2
),
1674 PINMUX_IPSR_MODSEL_DATA(IP16_2_0
, VI1_DATA6_C
, SEL_VI1_2
),
1675 PINMUX_IPSR_MODSEL_DATA(IP16_5_3
, HTX1
, SEL_HSCIF1_0
),
1676 PINMUX_IPSR_MODSEL_DATA(IP16_5_3
, SCIFB1_TXD
, SEL_SCIFB1_0
),
1677 PINMUX_IPSR_DATA(IP16_5_3
, VI1_R1_B
),
1678 PINMUX_IPSR_MODSEL_DATA(IP16_5_3
, GLO_SS_C
, SEL_GPS_2
),
1679 PINMUX_IPSR_MODSEL_DATA(IP16_5_3
, VI1_DATA7_C
, SEL_VI1_2
),
1680 PINMUX_IPSR_MODSEL_DATA(IP16_7_6
, HSCK1
, SEL_HSCIF1_0
),
1681 PINMUX_IPSR_MODSEL_DATA(IP16_7_6
, SCIFB1_SCK
, SEL_SCIFB1_0
),
1682 PINMUX_IPSR_DATA(IP16_7_6
, MLB_CLK
),
1683 PINMUX_IPSR_MODSEL_DATA(IP16_7_6
, GLO_RFON_C
, SEL_GPS_2
),
1684 PINMUX_IPSR_MODSEL_DATA(IP16_9_8
, HCTS1_N
, SEL_HSCIF1_0
),
1685 PINMUX_IPSR_DATA(IP16_9_8
, SCIFB1_CTS_N
),
1686 PINMUX_IPSR_DATA(IP16_9_8
, MLB_SIG
),
1687 PINMUX_IPSR_MODSEL_DATA(IP16_9_8
, CAN1_TX_B
, SEL_CAN1_1
),
1688 PINMUX_IPSR_MODSEL_DATA(IP16_11_10
, HRTS1_N
, SEL_HSCIF1_0
),
1689 PINMUX_IPSR_DATA(IP16_11_10
, SCIFB1_RTS_N
),
1690 PINMUX_IPSR_DATA(IP16_11_10
, MLB_DAT
),
1691 PINMUX_IPSR_MODSEL_DATA(IP16_11_10
, CAN1_RX_B
, SEL_CAN1_1
),
1694 static const struct sh_pfc_pin pinmux_pins
[] = {
1695 PINMUX_GPIO_GP_ALL(),
1698 /* - Audio Clock ------------------------------------------------------------ */
1699 static const unsigned int audio_clk_a_pins
[] = {
1704 static const unsigned int audio_clk_a_mux
[] = {
1708 static const unsigned int audio_clk_b_pins
[] = {
1713 static const unsigned int audio_clk_b_mux
[] = {
1717 static const unsigned int audio_clk_b_b_pins
[] = {
1722 static const unsigned int audio_clk_b_b_mux
[] = {
1726 static const unsigned int audio_clk_c_pins
[] = {
1731 static const unsigned int audio_clk_c_mux
[] = {
1735 static const unsigned int audio_clkout_pins
[] = {
1740 static const unsigned int audio_clkout_mux
[] = {
1744 /* - CAN -------------------------------------------------------------------- */
1746 static const unsigned int can0_data_pins
[] = {
1748 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
1751 static const unsigned int can0_data_mux
[] = {
1752 CAN0_TX_MARK
, CAN0_RX_MARK
,
1755 static const unsigned int can0_data_b_pins
[] = {
1757 RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 3),
1760 static const unsigned int can0_data_b_mux
[] = {
1761 CAN0_TX_B_MARK
, CAN0_RX_B_MARK
,
1764 static const unsigned int can0_data_c_pins
[] = {
1766 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
1769 static const unsigned int can0_data_c_mux
[] = {
1770 CAN0_TX_C_MARK
, CAN0_RX_C_MARK
,
1773 static const unsigned int can0_data_d_pins
[] = {
1775 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27),
1778 static const unsigned int can0_data_d_mux
[] = {
1779 CAN0_TX_D_MARK
, CAN0_RX_D_MARK
,
1782 static const unsigned int can0_data_e_pins
[] = {
1784 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 28),
1787 static const unsigned int can0_data_e_mux
[] = {
1788 CAN0_TX_E_MARK
, CAN0_RX_E_MARK
,
1791 static const unsigned int can0_data_f_pins
[] = {
1793 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1796 static const unsigned int can0_data_f_mux
[] = {
1797 CAN0_TX_F_MARK
, CAN0_RX_F_MARK
,
1800 static const unsigned int can1_data_pins
[] = {
1802 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 20),
1805 static const unsigned int can1_data_mux
[] = {
1806 CAN1_TX_MARK
, CAN1_RX_MARK
,
1809 static const unsigned int can1_data_b_pins
[] = {
1811 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1814 static const unsigned int can1_data_b_mux
[] = {
1815 CAN1_TX_B_MARK
, CAN1_RX_B_MARK
,
1818 static const unsigned int can1_data_c_pins
[] = {
1820 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 19),
1823 static const unsigned int can1_data_c_mux
[] = {
1824 CAN1_TX_C_MARK
, CAN1_RX_C_MARK
,
1827 static const unsigned int can1_data_d_pins
[] = {
1829 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 31),
1832 static const unsigned int can1_data_d_mux
[] = {
1833 CAN1_TX_D_MARK
, CAN1_RX_D_MARK
,
1836 static const unsigned int can_clk_pins
[] = {
1841 static const unsigned int can_clk_mux
[] = {
1845 static const unsigned int can_clk_b_pins
[] = {
1850 static const unsigned int can_clk_b_mux
[] = {
1854 static const unsigned int can_clk_c_pins
[] = {
1859 static const unsigned int can_clk_c_mux
[] = {
1863 static const unsigned int can_clk_d_pins
[] = {
1868 static const unsigned int can_clk_d_mux
[] = {
1872 /* - DU --------------------------------------------------------------------- */
1873 static const unsigned int du_rgb666_pins
[] = {
1874 /* R[7:2], G[7:2], B[7:2] */
1875 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
1876 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
1877 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1878 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
1879 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
1880 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
1882 static const unsigned int du_rgb666_mux
[] = {
1883 DU1_DR7_MARK
, DU1_DR6_MARK
, DU1_DR5_MARK
, DU1_DR4_MARK
,
1884 DU1_DR3_MARK
, DU1_DR2_MARK
,
1885 DU1_DG7_MARK
, DU1_DG6_MARK
, DU1_DG5_MARK
, DU1_DG4_MARK
,
1886 DU1_DG3_MARK
, DU1_DG2_MARK
,
1887 DU1_DB7_MARK
, DU1_DB6_MARK
, DU1_DB5_MARK
, DU1_DB4_MARK
,
1888 DU1_DB3_MARK
, DU1_DB2_MARK
,
1890 static const unsigned int du_rgb888_pins
[] = {
1891 /* R[7:0], G[7:0], B[7:0] */
1892 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
1893 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
1894 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1895 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1896 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
1897 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
1898 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
1899 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
1900 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
1902 static const unsigned int du_rgb888_mux
[] = {
1903 DU1_DR7_MARK
, DU1_DR6_MARK
, DU1_DR5_MARK
, DU1_DR4_MARK
,
1904 DU1_DR3_MARK
, DU1_DR2_MARK
, DU1_DR1_MARK
, DU1_DR0_MARK
,
1905 DU1_DG7_MARK
, DU1_DG6_MARK
, DU1_DG5_MARK
, DU1_DG4_MARK
,
1906 DU1_DG3_MARK
, DU1_DG2_MARK
, DU1_DG1_MARK
, DU1_DG0_MARK
,
1907 DU1_DB7_MARK
, DU1_DB6_MARK
, DU1_DB5_MARK
, DU1_DB4_MARK
,
1908 DU1_DB3_MARK
, DU1_DB2_MARK
, DU1_DB1_MARK
, DU1_DB0_MARK
,
1910 static const unsigned int du_clk_out_0_pins
[] = {
1914 static const unsigned int du_clk_out_0_mux
[] = {
1917 static const unsigned int du_clk_out_1_pins
[] = {
1921 static const unsigned int du_clk_out_1_mux
[] = {
1924 static const unsigned int du_sync_pins
[] = {
1925 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1926 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
1928 static const unsigned int du_sync_mux
[] = {
1929 DU1_EXVSYNC_DU1_VSYNC_MARK
, DU1_EXHSYNC_DU1_HSYNC_MARK
1931 static const unsigned int du_oddf_pins
[] = {
1932 /* EXDISP/EXODDF/EXCDE */
1935 static const unsigned int du_oddf_mux
[] = {
1936 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
,
1938 static const unsigned int du_cde_pins
[] = {
1942 static const unsigned int du_cde_mux
[] = {
1945 static const unsigned int du_disp_pins
[] = {
1949 static const unsigned int du_disp_mux
[] = {
1952 static const unsigned int du0_clk_in_pins
[] = {
1956 static const unsigned int du0_clk_in_mux
[] = {
1959 static const unsigned int du1_clk_in_pins
[] = {
1963 static const unsigned int du1_clk_in_mux
[] = {
1966 static const unsigned int du1_clk_in_b_pins
[] = {
1970 static const unsigned int du1_clk_in_b_mux
[] = {
1971 DU1_DOTCLKIN_B_MARK
,
1973 static const unsigned int du1_clk_in_c_pins
[] = {
1977 static const unsigned int du1_clk_in_c_mux
[] = {
1978 DU1_DOTCLKIN_C_MARK
,
1980 /* - ETH -------------------------------------------------------------------- */
1981 static const unsigned int eth_link_pins
[] = {
1985 static const unsigned int eth_link_mux
[] = {
1988 static const unsigned int eth_magic_pins
[] = {
1992 static const unsigned int eth_magic_mux
[] = {
1995 static const unsigned int eth_mdio_pins
[] = {
1997 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13),
1999 static const unsigned int eth_mdio_mux
[] = {
2000 ETH_MDC_MARK
, ETH_MDIO_MARK
,
2002 static const unsigned int eth_rmii_pins
[] = {
2003 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
2004 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15),
2005 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20),
2006 RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19),
2008 static const unsigned int eth_rmii_mux
[] = {
2009 ETH_RXD0_MARK
, ETH_RXD1_MARK
, ETH_RX_ER_MARK
, ETH_CRS_DV_MARK
,
2010 ETH_TXD0_MARK
, ETH_TXD1_MARK
, ETH_TX_EN_MARK
, ETH_REFCLK_MARK
,
2013 /* - HSCIF0 ----------------------------------------------------------------- */
2014 static const unsigned int hscif0_data_pins
[] = {
2016 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
2018 static const unsigned int hscif0_data_mux
[] = {
2019 HRX0_MARK
, HTX0_MARK
,
2021 static const unsigned int hscif0_clk_pins
[] = {
2025 static const unsigned int hscif0_clk_mux
[] = {
2028 static const unsigned int hscif0_ctrl_pins
[] = {
2030 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
2032 static const unsigned int hscif0_ctrl_mux
[] = {
2033 HRTS0_N_MARK
, HCTS0_N_MARK
,
2035 static const unsigned int hscif0_data_b_pins
[] = {
2037 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
2039 static const unsigned int hscif0_data_b_mux
[] = {
2040 HRX0_B_MARK
, HTX0_B_MARK
,
2042 static const unsigned int hscif0_ctrl_b_pins
[] = {
2044 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2046 static const unsigned int hscif0_ctrl_b_mux
[] = {
2047 HRTS0_N_B_MARK
, HCTS0_N_B_MARK
,
2049 static const unsigned int hscif0_data_c_pins
[] = {
2051 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2053 static const unsigned int hscif0_data_c_mux
[] = {
2054 HRX0_C_MARK
, HTX0_C_MARK
,
2056 static const unsigned int hscif0_clk_c_pins
[] = {
2060 static const unsigned int hscif0_clk_c_mux
[] = {
2063 /* - HSCIF1 ----------------------------------------------------------------- */
2064 static const unsigned int hscif1_data_pins
[] = {
2066 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
2068 static const unsigned int hscif1_data_mux
[] = {
2069 HRX1_MARK
, HTX1_MARK
,
2071 static const unsigned int hscif1_clk_pins
[] = {
2075 static const unsigned int hscif1_clk_mux
[] = {
2078 static const unsigned int hscif1_ctrl_pins
[] = {
2080 RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
2082 static const unsigned int hscif1_ctrl_mux
[] = {
2083 HRTS1_N_MARK
, HCTS1_N_MARK
,
2085 static const unsigned int hscif1_data_b_pins
[] = {
2087 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
2089 static const unsigned int hscif1_data_b_mux
[] = {
2090 HRX1_B_MARK
, HTX1_B_MARK
,
2092 static const unsigned int hscif1_data_c_pins
[] = {
2094 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2096 static const unsigned int hscif1_data_c_mux
[] = {
2097 HRX1_C_MARK
, HTX1_C_MARK
,
2099 static const unsigned int hscif1_clk_c_pins
[] = {
2103 static const unsigned int hscif1_clk_c_mux
[] = {
2106 static const unsigned int hscif1_ctrl_c_pins
[] = {
2108 RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
2110 static const unsigned int hscif1_ctrl_c_mux
[] = {
2111 HRTS1_N_C_MARK
, HCTS1_N_C_MARK
,
2113 static const unsigned int hscif1_data_d_pins
[] = {
2115 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
2117 static const unsigned int hscif1_data_d_mux
[] = {
2118 HRX1_D_MARK
, HTX1_D_MARK
,
2120 static const unsigned int hscif1_data_e_pins
[] = {
2122 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2124 static const unsigned int hscif1_data_e_mux
[] = {
2125 HRX1_C_MARK
, HTX1_C_MARK
,
2127 static const unsigned int hscif1_clk_e_pins
[] = {
2131 static const unsigned int hscif1_clk_e_mux
[] = {
2134 static const unsigned int hscif1_ctrl_e_pins
[] = {
2136 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
2138 static const unsigned int hscif1_ctrl_e_mux
[] = {
2139 HRTS1_N_E_MARK
, HCTS1_N_E_MARK
,
2141 /* - HSCIF2 ----------------------------------------------------------------- */
2142 static const unsigned int hscif2_data_pins
[] = {
2144 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2146 static const unsigned int hscif2_data_mux
[] = {
2147 HRX2_MARK
, HTX2_MARK
,
2149 static const unsigned int hscif2_clk_pins
[] = {
2153 static const unsigned int hscif2_clk_mux
[] = {
2156 static const unsigned int hscif2_ctrl_pins
[] = {
2158 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
2160 static const unsigned int hscif2_ctrl_mux
[] = {
2161 HRTS2_N_MARK
, HCTS2_N_MARK
,
2163 static const unsigned int hscif2_data_b_pins
[] = {
2165 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 22),
2167 static const unsigned int hscif2_data_b_mux
[] = {
2168 HRX2_B_MARK
, HTX2_B_MARK
,
2170 static const unsigned int hscif2_ctrl_b_pins
[] = {
2172 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 21),
2174 static const unsigned int hscif2_ctrl_b_mux
[] = {
2175 HRTS2_N_B_MARK
, HCTS2_N_B_MARK
,
2177 static const unsigned int hscif2_data_c_pins
[] = {
2179 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2181 static const unsigned int hscif2_data_c_mux
[] = {
2182 HRX2_C_MARK
, HTX2_C_MARK
,
2184 static const unsigned int hscif2_clk_c_pins
[] = {
2188 static const unsigned int hscif2_clk_c_mux
[] = {
2191 static const unsigned int hscif2_data_d_pins
[] = {
2193 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(5, 31),
2195 static const unsigned int hscif2_data_d_mux
[] = {
2196 HRX2_B_MARK
, HTX2_D_MARK
,
2198 /* - I2C0 ------------------------------------------------------------------- */
2199 static const unsigned int i2c0_pins
[] = {
2201 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2203 static const unsigned int i2c0_mux
[] = {
2204 SCL0_MARK
, SDA0_MARK
,
2206 static const unsigned int i2c0_b_pins
[] = {
2208 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2210 static const unsigned int i2c0_b_mux
[] = {
2211 SCL0_B_MARK
, SDA0_B_MARK
,
2213 static const unsigned int i2c0_c_pins
[] = {
2215 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1),
2217 static const unsigned int i2c0_c_mux
[] = {
2218 SCL0_C_MARK
, SDA0_C_MARK
,
2220 /* - I2C1 ------------------------------------------------------------------- */
2221 static const unsigned int i2c1_pins
[] = {
2223 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
2225 static const unsigned int i2c1_mux
[] = {
2226 SCL1_MARK
, SDA1_MARK
,
2228 static const unsigned int i2c1_b_pins
[] = {
2230 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2232 static const unsigned int i2c1_b_mux
[] = {
2233 SCL1_B_MARK
, SDA1_B_MARK
,
2235 static const unsigned int i2c1_c_pins
[] = {
2237 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
2239 static const unsigned int i2c1_c_mux
[] = {
2240 SCL1_C_MARK
, SDA1_C_MARK
,
2242 static const unsigned int i2c1_d_pins
[] = {
2244 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2246 static const unsigned int i2c1_d_mux
[] = {
2247 SCL1_D_MARK
, SDA1_D_MARK
,
2249 static const unsigned int i2c1_e_pins
[] = {
2251 RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16),
2253 static const unsigned int i2c1_e_mux
[] = {
2254 SCL1_E_MARK
, SDA1_E_MARK
,
2256 /* - I2C2 ------------------------------------------------------------------- */
2257 static const unsigned int i2c2_pins
[] = {
2259 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
2261 static const unsigned int i2c2_mux
[] = {
2262 SCL2_MARK
, SDA2_MARK
,
2264 static const unsigned int i2c2_b_pins
[] = {
2266 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
2268 static const unsigned int i2c2_b_mux
[] = {
2269 SCL2_B_MARK
, SDA2_B_MARK
,
2271 static const unsigned int i2c2_c_pins
[] = {
2273 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2275 static const unsigned int i2c2_c_mux
[] = {
2276 SCL2_C_MARK
, SDA2_C_MARK
,
2278 static const unsigned int i2c2_d_pins
[] = {
2280 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
2282 static const unsigned int i2c2_d_mux
[] = {
2283 SCL2_D_MARK
, SDA2_D_MARK
,
2285 /* - I2C3 ------------------------------------------------------------------- */
2286 static const unsigned int i2c3_pins
[] = {
2288 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2290 static const unsigned int i2c3_mux
[] = {
2291 SCL3_MARK
, SDA3_MARK
,
2293 static const unsigned int i2c3_b_pins
[] = {
2295 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
2297 static const unsigned int i2c3_b_mux
[] = {
2298 SCL3_B_MARK
, SDA3_B_MARK
,
2300 static const unsigned int i2c3_c_pins
[] = {
2302 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2304 static const unsigned int i2c3_c_mux
[] = {
2305 SCL3_C_MARK
, SDA3_C_MARK
,
2307 static const unsigned int i2c3_d_pins
[] = {
2309 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
2311 static const unsigned int i2c3_d_mux
[] = {
2312 SCL3_D_MARK
, SDA3_D_MARK
,
2314 /* - I2C4 ------------------------------------------------------------------- */
2315 static const unsigned int i2c4_pins
[] = {
2317 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2319 static const unsigned int i2c4_mux
[] = {
2320 SCL4_MARK
, SDA4_MARK
,
2322 static const unsigned int i2c4_b_pins
[] = {
2324 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
2326 static const unsigned int i2c4_b_mux
[] = {
2327 SCL4_B_MARK
, SDA4_B_MARK
,
2329 static const unsigned int i2c4_c_pins
[] = {
2331 RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
2333 static const unsigned int i2c4_c_mux
[] = {
2334 SCL4_C_MARK
, SDA4_C_MARK
,
2336 /* - I2C7 ------------------------------------------------------------------- */
2337 static const unsigned int i2c7_pins
[] = {
2339 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2341 static const unsigned int i2c7_mux
[] = {
2342 SCL7_MARK
, SDA7_MARK
,
2344 static const unsigned int i2c7_b_pins
[] = {
2346 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2348 static const unsigned int i2c7_b_mux
[] = {
2349 SCL7_B_MARK
, SDA7_B_MARK
,
2351 static const unsigned int i2c7_c_pins
[] = {
2353 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2355 static const unsigned int i2c7_c_mux
[] = {
2356 SCL7_C_MARK
, SDA7_C_MARK
,
2358 /* - I2C8 ------------------------------------------------------------------- */
2359 static const unsigned int i2c8_pins
[] = {
2361 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2363 static const unsigned int i2c8_mux
[] = {
2364 SCL8_MARK
, SDA8_MARK
,
2366 static const unsigned int i2c8_b_pins
[] = {
2368 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2370 static const unsigned int i2c8_b_mux
[] = {
2371 SCL8_B_MARK
, SDA8_B_MARK
,
2373 static const unsigned int i2c8_c_pins
[] = {
2375 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2377 static const unsigned int i2c8_c_mux
[] = {
2378 SCL8_C_MARK
, SDA8_C_MARK
,
2380 /* - INTC ------------------------------------------------------------------- */
2381 static const unsigned int intc_irq0_pins
[] = {
2385 static const unsigned int intc_irq0_mux
[] = {
2388 static const unsigned int intc_irq1_pins
[] = {
2392 static const unsigned int intc_irq1_mux
[] = {
2395 static const unsigned int intc_irq2_pins
[] = {
2399 static const unsigned int intc_irq2_mux
[] = {
2402 static const unsigned int intc_irq3_pins
[] = {
2406 static const unsigned int intc_irq3_mux
[] = {
2409 /* - MLB+ ------------------------------------------------------------------- */
2410 static const unsigned int mlb_3pin_pins
[] = {
2411 RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
2413 static const unsigned int mlb_3pin_mux
[] = {
2414 MLB_CLK_MARK
, MLB_SIG_MARK
, MLB_DAT_MARK
,
2416 /* - MMCIF ------------------------------------------------------------------ */
2417 static const unsigned int mmc_data1_pins
[] = {
2421 static const unsigned int mmc_data1_mux
[] = {
2424 static const unsigned int mmc_data4_pins
[] = {
2426 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2427 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2429 static const unsigned int mmc_data4_mux
[] = {
2430 MMC_D0_MARK
, MMC_D1_MARK
, MMC_D2_MARK
, MMC_D3_MARK
,
2432 static const unsigned int mmc_data8_pins
[] = {
2434 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2435 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2436 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2437 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2439 static const unsigned int mmc_data8_mux
[] = {
2440 MMC_D0_MARK
, MMC_D1_MARK
, MMC_D2_MARK
, MMC_D3_MARK
,
2441 MMC_D4_MARK
, MMC_D5_MARK
, MMC_D6_MARK
, MMC_D7_MARK
,
2443 static const unsigned int mmc_ctrl_pins
[] = {
2445 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2447 static const unsigned int mmc_ctrl_mux
[] = {
2448 MMC_CLK_MARK
, MMC_CMD_MARK
,
2450 /* - MSIOF0 ----------------------------------------------------------------- */
2451 static const unsigned int msiof0_clk_pins
[] = {
2455 static const unsigned int msiof0_clk_mux
[] = {
2458 static const unsigned int msiof0_sync_pins
[] = {
2462 static const unsigned int msiof0_sync_mux
[] = {
2465 static const unsigned int msiof0_ss1_pins
[] = {
2469 static const unsigned int msiof0_ss1_mux
[] = {
2472 static const unsigned int msiof0_ss2_pins
[] = {
2476 static const unsigned int msiof0_ss2_mux
[] = {
2479 static const unsigned int msiof0_rx_pins
[] = {
2483 static const unsigned int msiof0_rx_mux
[] = {
2486 static const unsigned int msiof0_tx_pins
[] = {
2490 static const unsigned int msiof0_tx_mux
[] = {
2494 static const unsigned int msiof0_clk_b_pins
[] = {
2498 static const unsigned int msiof0_clk_b_mux
[] = {
2501 static const unsigned int msiof0_sync_b_pins
[] = {
2505 static const unsigned int msiof0_sync_b_mux
[] = {
2508 static const unsigned int msiof0_ss1_b_pins
[] = {
2512 static const unsigned int msiof0_ss1_b_mux
[] = {
2515 static const unsigned int msiof0_ss2_b_pins
[] = {
2519 static const unsigned int msiof0_ss2_b_mux
[] = {
2522 static const unsigned int msiof0_rx_b_pins
[] = {
2526 static const unsigned int msiof0_rx_b_mux
[] = {
2529 static const unsigned int msiof0_tx_b_pins
[] = {
2533 static const unsigned int msiof0_tx_b_mux
[] = {
2537 static const unsigned int msiof0_clk_c_pins
[] = {
2541 static const unsigned int msiof0_clk_c_mux
[] = {
2544 static const unsigned int msiof0_sync_c_pins
[] = {
2548 static const unsigned int msiof0_sync_c_mux
[] = {
2551 static const unsigned int msiof0_ss1_c_pins
[] = {
2555 static const unsigned int msiof0_ss1_c_mux
[] = {
2558 static const unsigned int msiof0_ss2_c_pins
[] = {
2562 static const unsigned int msiof0_ss2_c_mux
[] = {
2565 static const unsigned int msiof0_rx_c_pins
[] = {
2569 static const unsigned int msiof0_rx_c_mux
[] = {
2572 static const unsigned int msiof0_tx_c_pins
[] = {
2576 static const unsigned int msiof0_tx_c_mux
[] = {
2579 /* - MSIOF1 ----------------------------------------------------------------- */
2580 static const unsigned int msiof1_clk_pins
[] = {
2584 static const unsigned int msiof1_clk_mux
[] = {
2587 static const unsigned int msiof1_sync_pins
[] = {
2591 static const unsigned int msiof1_sync_mux
[] = {
2594 static const unsigned int msiof1_ss1_pins
[] = {
2598 static const unsigned int msiof1_ss1_mux
[] = {
2601 static const unsigned int msiof1_ss2_pins
[] = {
2605 static const unsigned int msiof1_ss2_mux
[] = {
2608 static const unsigned int msiof1_rx_pins
[] = {
2612 static const unsigned int msiof1_rx_mux
[] = {
2615 static const unsigned int msiof1_tx_pins
[] = {
2619 static const unsigned int msiof1_tx_mux
[] = {
2623 static const unsigned int msiof1_clk_b_pins
[] = {
2627 static const unsigned int msiof1_clk_b_mux
[] = {
2630 static const unsigned int msiof1_sync_b_pins
[] = {
2634 static const unsigned int msiof1_sync_b_mux
[] = {
2637 static const unsigned int msiof1_ss1_b_pins
[] = {
2641 static const unsigned int msiof1_ss1_b_mux
[] = {
2644 static const unsigned int msiof1_ss2_b_pins
[] = {
2648 static const unsigned int msiof1_ss2_b_mux
[] = {
2651 static const unsigned int msiof1_rx_b_pins
[] = {
2655 static const unsigned int msiof1_rx_b_mux
[] = {
2658 static const unsigned int msiof1_tx_b_pins
[] = {
2662 static const unsigned int msiof1_tx_b_mux
[] = {
2666 static const unsigned int msiof1_clk_c_pins
[] = {
2670 static const unsigned int msiof1_clk_c_mux
[] = {
2673 static const unsigned int msiof1_sync_c_pins
[] = {
2677 static const unsigned int msiof1_sync_c_mux
[] = {
2680 static const unsigned int msiof1_rx_c_pins
[] = {
2684 static const unsigned int msiof1_rx_c_mux
[] = {
2687 static const unsigned int msiof1_tx_c_pins
[] = {
2691 static const unsigned int msiof1_tx_c_mux
[] = {
2695 static const unsigned int msiof1_clk_d_pins
[] = {
2699 static const unsigned int msiof1_clk_d_mux
[] = {
2702 static const unsigned int msiof1_sync_d_pins
[] = {
2706 static const unsigned int msiof1_sync_d_mux
[] = {
2709 static const unsigned int msiof1_ss1_d_pins
[] = {
2713 static const unsigned int msiof1_ss1_d_mux
[] = {
2716 static const unsigned int msiof1_rx_d_pins
[] = {
2720 static const unsigned int msiof1_rx_d_mux
[] = {
2723 static const unsigned int msiof1_tx_d_pins
[] = {
2727 static const unsigned int msiof1_tx_d_mux
[] = {
2731 static const unsigned int msiof1_clk_e_pins
[] = {
2735 static const unsigned int msiof1_clk_e_mux
[] = {
2738 static const unsigned int msiof1_sync_e_pins
[] = {
2742 static const unsigned int msiof1_sync_e_mux
[] = {
2745 static const unsigned int msiof1_rx_e_pins
[] = {
2749 static const unsigned int msiof1_rx_e_mux
[] = {
2752 static const unsigned int msiof1_tx_e_pins
[] = {
2756 static const unsigned int msiof1_tx_e_mux
[] = {
2759 /* - MSIOF2 ----------------------------------------------------------------- */
2760 static const unsigned int msiof2_clk_pins
[] = {
2764 static const unsigned int msiof2_clk_mux
[] = {
2767 static const unsigned int msiof2_sync_pins
[] = {
2771 static const unsigned int msiof2_sync_mux
[] = {
2774 static const unsigned int msiof2_ss1_pins
[] = {
2778 static const unsigned int msiof2_ss1_mux
[] = {
2781 static const unsigned int msiof2_ss2_pins
[] = {
2785 static const unsigned int msiof2_ss2_mux
[] = {
2788 static const unsigned int msiof2_rx_pins
[] = {
2792 static const unsigned int msiof2_rx_mux
[] = {
2795 static const unsigned int msiof2_tx_pins
[] = {
2799 static const unsigned int msiof2_tx_mux
[] = {
2803 static const unsigned int msiof2_clk_b_pins
[] = {
2807 static const unsigned int msiof2_clk_b_mux
[] = {
2810 static const unsigned int msiof2_sync_b_pins
[] = {
2814 static const unsigned int msiof2_sync_b_mux
[] = {
2817 static const unsigned int msiof2_ss1_b_pins
[] = {
2821 static const unsigned int msiof2_ss1_b_mux
[] = {
2824 static const unsigned int msiof2_ss2_b_pins
[] = {
2828 static const unsigned int msiof2_ss2_b_mux
[] = {
2831 static const unsigned int msiof2_rx_b_pins
[] = {
2835 static const unsigned int msiof2_rx_b_mux
[] = {
2838 static const unsigned int msiof2_tx_b_pins
[] = {
2842 static const unsigned int msiof2_tx_b_mux
[] = {
2846 static const unsigned int msiof2_clk_c_pins
[] = {
2850 static const unsigned int msiof2_clk_c_mux
[] = {
2853 static const unsigned int msiof2_sync_c_pins
[] = {
2857 static const unsigned int msiof2_sync_c_mux
[] = {
2860 static const unsigned int msiof2_rx_c_pins
[] = {
2864 static const unsigned int msiof2_rx_c_mux
[] = {
2867 static const unsigned int msiof2_tx_c_pins
[] = {
2871 static const unsigned int msiof2_tx_c_mux
[] = {
2875 static const unsigned int msiof2_clk_d_pins
[] = {
2879 static const unsigned int msiof2_clk_d_mux
[] = {
2882 static const unsigned int msiof2_sync_d_pins
[] = {
2886 static const unsigned int msiof2_sync_d_mux
[] = {
2889 static const unsigned int msiof2_ss1_d_pins
[] = {
2893 static const unsigned int msiof2_ss1_d_mux
[] = {
2896 static const unsigned int msiof2_ss2_d_pins
[] = {
2900 static const unsigned int msiof2_ss2_d_mux
[] = {
2903 static const unsigned int msiof2_rx_d_pins
[] = {
2907 static const unsigned int msiof2_rx_d_mux
[] = {
2910 static const unsigned int msiof2_tx_d_pins
[] = {
2914 static const unsigned int msiof2_tx_d_mux
[] = {
2918 static const unsigned int msiof2_clk_e_pins
[] = {
2922 static const unsigned int msiof2_clk_e_mux
[] = {
2925 static const unsigned int msiof2_sync_e_pins
[] = {
2929 static const unsigned int msiof2_sync_e_mux
[] = {
2932 static const unsigned int msiof2_rx_e_pins
[] = {
2936 static const unsigned int msiof2_rx_e_mux
[] = {
2939 static const unsigned int msiof2_tx_e_pins
[] = {
2943 static const unsigned int msiof2_tx_e_mux
[] = {
2946 /* - PWM -------------------------------------------------------------------- */
2947 static const unsigned int pwm0_pins
[] = {
2950 static const unsigned int pwm0_mux
[] = {
2953 static const unsigned int pwm0_b_pins
[] = {
2956 static const unsigned int pwm0_b_mux
[] = {
2959 static const unsigned int pwm1_pins
[] = {
2962 static const unsigned int pwm1_mux
[] = {
2965 static const unsigned int pwm1_b_pins
[] = {
2968 static const unsigned int pwm1_b_mux
[] = {
2971 static const unsigned int pwm2_pins
[] = {
2974 static const unsigned int pwm2_mux
[] = {
2977 static const unsigned int pwm2_b_pins
[] = {
2980 static const unsigned int pwm2_b_mux
[] = {
2983 static const unsigned int pwm3_pins
[] = {
2986 static const unsigned int pwm3_mux
[] = {
2989 static const unsigned int pwm4_pins
[] = {
2992 static const unsigned int pwm4_mux
[] = {
2995 static const unsigned int pwm4_b_pins
[] = {
2998 static const unsigned int pwm4_b_mux
[] = {
3001 static const unsigned int pwm5_pins
[] = {
3004 static const unsigned int pwm5_mux
[] = {
3007 static const unsigned int pwm5_b_pins
[] = {
3010 static const unsigned int pwm5_b_mux
[] = {
3013 static const unsigned int pwm6_pins
[] = {
3016 static const unsigned int pwm6_mux
[] = {
3019 /* - QSPI ------------------------------------------------------------------- */
3020 static const unsigned int qspi_ctrl_pins
[] = {
3022 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
3024 static const unsigned int qspi_ctrl_mux
[] = {
3025 SPCLK_MARK
, SSL_MARK
,
3027 static const unsigned int qspi_data2_pins
[] = {
3028 /* MOSI_IO0, MISO_IO1 */
3029 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3031 static const unsigned int qspi_data2_mux
[] = {
3032 MOSI_IO0_MARK
, MISO_IO1_MARK
,
3034 static const unsigned int qspi_data4_pins
[] = {
3035 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
3036 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3039 static const unsigned int qspi_data4_mux
[] = {
3040 MOSI_IO0_MARK
, MISO_IO1_MARK
, IO2_MARK
, IO3_MARK
,
3043 static const unsigned int qspi_ctrl_b_pins
[] = {
3045 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
3047 static const unsigned int qspi_ctrl_b_mux
[] = {
3048 SPCLK_B_MARK
, SSL_B_MARK
,
3050 static const unsigned int qspi_data2_b_pins
[] = {
3051 /* MOSI_IO0, MISO_IO1 */
3052 RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
3054 static const unsigned int qspi_data2_b_mux
[] = {
3055 MOSI_IO0_B_MARK
, MISO_IO1_B_MARK
,
3057 static const unsigned int qspi_data4_b_pins
[] = {
3058 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
3059 RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3062 static const unsigned int qspi_data4_b_mux
[] = {
3063 SPCLK_B_MARK
, MOSI_IO0_B_MARK
, MISO_IO1_B_MARK
,
3064 IO2_B_MARK
, IO3_B_MARK
, SSL_B_MARK
,
3066 /* - SCIF0 ------------------------------------------------------------------ */
3067 static const unsigned int scif0_data_pins
[] = {
3069 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
3071 static const unsigned int scif0_data_mux
[] = {
3074 static const unsigned int scif0_data_b_pins
[] = {
3076 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3078 static const unsigned int scif0_data_b_mux
[] = {
3079 RX0_B_MARK
, TX0_B_MARK
,
3081 static const unsigned int scif0_data_c_pins
[] = {
3083 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25),
3085 static const unsigned int scif0_data_c_mux
[] = {
3086 RX0_C_MARK
, TX0_C_MARK
,
3088 static const unsigned int scif0_data_d_pins
[] = {
3090 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
3092 static const unsigned int scif0_data_d_mux
[] = {
3093 RX0_D_MARK
, TX0_D_MARK
,
3095 static const unsigned int scif0_data_e_pins
[] = {
3097 RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28),
3099 static const unsigned int scif0_data_e_mux
[] = {
3100 RX0_E_MARK
, TX0_E_MARK
,
3102 /* - SCIF1 ------------------------------------------------------------------ */
3103 static const unsigned int scif1_data_pins
[] = {
3105 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
3107 static const unsigned int scif1_data_mux
[] = {
3110 static const unsigned int scif1_data_b_pins
[] = {
3112 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
3114 static const unsigned int scif1_data_b_mux
[] = {
3115 RX1_B_MARK
, TX1_B_MARK
,
3117 static const unsigned int scif1_clk_b_pins
[] = {
3121 static const unsigned int scif1_clk_b_mux
[] = {
3124 static const unsigned int scif1_data_c_pins
[] = {
3126 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
3128 static const unsigned int scif1_data_c_mux
[] = {
3129 RX1_C_MARK
, TX1_C_MARK
,
3131 static const unsigned int scif1_data_d_pins
[] = {
3133 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3135 static const unsigned int scif1_data_d_mux
[] = {
3136 RX1_D_MARK
, TX1_D_MARK
,
3138 /* - SCIF2 ------------------------------------------------------------------ */
3139 static const unsigned int scif2_data_pins
[] = {
3141 RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
3143 static const unsigned int scif2_data_mux
[] = {
3146 static const unsigned int scif2_data_b_pins
[] = {
3148 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
3150 static const unsigned int scif2_data_b_mux
[] = {
3151 RX2_B_MARK
, TX2_B_MARK
,
3153 static const unsigned int scif2_clk_b_pins
[] = {
3157 static const unsigned int scif2_clk_b_mux
[] = {
3160 static const unsigned int scif2_data_c_pins
[] = {
3162 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3164 static const unsigned int scif2_data_c_mux
[] = {
3165 RX2_C_MARK
, TX2_C_MARK
,
3167 static const unsigned int scif2_data_e_pins
[] = {
3169 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3171 static const unsigned int scif2_data_e_mux
[] = {
3172 RX2_E_MARK
, TX2_E_MARK
,
3174 /* - SCIF3 ------------------------------------------------------------------ */
3175 static const unsigned int scif3_data_pins
[] = {
3177 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
3179 static const unsigned int scif3_data_mux
[] = {
3182 static const unsigned int scif3_clk_pins
[] = {
3186 static const unsigned int scif3_clk_mux
[] = {
3189 static const unsigned int scif3_data_b_pins
[] = {
3191 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26),
3193 static const unsigned int scif3_data_b_mux
[] = {
3194 RX3_B_MARK
, TX3_B_MARK
,
3196 static const unsigned int scif3_clk_b_pins
[] = {
3200 static const unsigned int scif3_clk_b_mux
[] = {
3203 static const unsigned int scif3_data_c_pins
[] = {
3205 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
3207 static const unsigned int scif3_data_c_mux
[] = {
3208 RX3_C_MARK
, TX3_C_MARK
,
3210 static const unsigned int scif3_data_d_pins
[] = {
3212 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26),
3214 static const unsigned int scif3_data_d_mux
[] = {
3215 RX3_D_MARK
, TX3_D_MARK
,
3217 /* - SCIF4 ------------------------------------------------------------------ */
3218 static const unsigned int scif4_data_pins
[] = {
3220 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
3222 static const unsigned int scif4_data_mux
[] = {
3225 static const unsigned int scif4_data_b_pins
[] = {
3227 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3229 static const unsigned int scif4_data_b_mux
[] = {
3230 RX4_B_MARK
, TX4_B_MARK
,
3232 static const unsigned int scif4_data_c_pins
[] = {
3234 RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
3236 static const unsigned int scif4_data_c_mux
[] = {
3237 RX4_C_MARK
, TX4_C_MARK
,
3239 /* - SCIF5 ------------------------------------------------------------------ */
3240 static const unsigned int scif5_data_pins
[] = {
3242 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
3244 static const unsigned int scif5_data_mux
[] = {
3247 static const unsigned int scif5_data_b_pins
[] = {
3249 RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
3251 static const unsigned int scif5_data_b_mux
[] = {
3252 RX5_B_MARK
, TX5_B_MARK
,
3254 /* - SCIFA0 ----------------------------------------------------------------- */
3255 static const unsigned int scifa0_data_pins
[] = {
3257 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
3259 static const unsigned int scifa0_data_mux
[] = {
3260 SCIFA0_RXD_MARK
, SCIFA0_TXD_MARK
,
3262 static const unsigned int scifa0_data_b_pins
[] = {
3264 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3266 static const unsigned int scifa0_data_b_mux
[] = {
3267 SCIFA0_RXD_B_MARK
, SCIFA0_TXD_B_MARK
3269 /* - SCIFA1 ----------------------------------------------------------------- */
3270 static const unsigned int scifa1_data_pins
[] = {
3272 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
3274 static const unsigned int scifa1_data_mux
[] = {
3275 SCIFA1_RXD_MARK
, SCIFA1_TXD_MARK
,
3277 static const unsigned int scifa1_clk_pins
[] = {
3281 static const unsigned int scifa1_clk_mux
[] = {
3284 static const unsigned int scifa1_data_b_pins
[] = {
3286 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
3288 static const unsigned int scifa1_data_b_mux
[] = {
3289 SCIFA1_RXD_B_MARK
, SCIFA1_TXD_B_MARK
,
3291 static const unsigned int scifa1_clk_b_pins
[] = {
3295 static const unsigned int scifa1_clk_b_mux
[] = {
3298 static const unsigned int scifa1_data_c_pins
[] = {
3300 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3302 static const unsigned int scifa1_data_c_mux
[] = {
3303 SCIFA1_RXD_C_MARK
, SCIFA1_TXD_C_MARK
,
3305 /* - SCIFA2 ----------------------------------------------------------------- */
3306 static const unsigned int scifa2_data_pins
[] = {
3308 RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
3310 static const unsigned int scifa2_data_mux
[] = {
3311 SCIFA2_RXD_MARK
, SCIFA2_TXD_MARK
,
3313 static const unsigned int scifa2_clk_pins
[] = {
3317 static const unsigned int scifa2_clk_mux
[] = {
3320 static const unsigned int scifa2_data_b_pins
[] = {
3322 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
3324 static const unsigned int scifa2_data_b_mux
[] = {
3325 SCIFA2_RXD_B_MARK
, SCIFA2_TXD_B_MARK
,
3327 /* - SCIFA3 ----------------------------------------------------------------- */
3328 static const unsigned int scifa3_data_pins
[] = {
3330 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
3332 static const unsigned int scifa3_data_mux
[] = {
3333 SCIFA3_RXD_MARK
, SCIFA3_TXD_MARK
,
3335 static const unsigned int scifa3_clk_pins
[] = {
3339 static const unsigned int scifa3_clk_mux
[] = {
3342 static const unsigned int scifa3_data_b_pins
[] = {
3344 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
3346 static const unsigned int scifa3_data_b_mux
[] = {
3347 SCIFA3_RXD_B_MARK
, SCIFA3_TXD_B_MARK
,
3349 static const unsigned int scifa3_clk_b_pins
[] = {
3353 static const unsigned int scifa3_clk_b_mux
[] = {
3356 static const unsigned int scifa3_data_c_pins
[] = {
3358 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20),
3360 static const unsigned int scifa3_data_c_mux
[] = {
3361 SCIFA3_RXD_C_MARK
, SCIFA3_TXD_C_MARK
,
3363 static const unsigned int scifa3_clk_c_pins
[] = {
3367 static const unsigned int scifa3_clk_c_mux
[] = {
3370 /* - SCIFA4 ----------------------------------------------------------------- */
3371 static const unsigned int scifa4_data_pins
[] = {
3373 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
3375 static const unsigned int scifa4_data_mux
[] = {
3376 SCIFA4_RXD_MARK
, SCIFA4_TXD_MARK
,
3378 static const unsigned int scifa4_data_b_pins
[] = {
3380 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3382 static const unsigned int scifa4_data_b_mux
[] = {
3383 SCIFA4_RXD_B_MARK
, SCIFA4_TXD_B_MARK
,
3385 static const unsigned int scifa4_data_c_pins
[] = {
3387 RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
3389 static const unsigned int scifa4_data_c_mux
[] = {
3390 SCIFA4_RXD_C_MARK
, SCIFA4_TXD_C_MARK
,
3392 /* - SCIFA5 ----------------------------------------------------------------- */
3393 static const unsigned int scifa5_data_pins
[] = {
3395 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
3397 static const unsigned int scifa5_data_mux
[] = {
3398 SCIFA5_RXD_MARK
, SCIFA5_TXD_MARK
,
3400 static const unsigned int scifa5_data_b_pins
[] = {
3402 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
3404 static const unsigned int scifa5_data_b_mux
[] = {
3405 SCIFA5_RXD_B_MARK
, SCIFA5_TXD_B_MARK
,
3407 static const unsigned int scifa5_data_c_pins
[] = {
3409 RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
3411 static const unsigned int scifa5_data_c_mux
[] = {
3412 SCIFA5_RXD_C_MARK
, SCIFA5_TXD_C_MARK
,
3414 /* - SCIFB0 ----------------------------------------------------------------- */
3415 static const unsigned int scifb0_data_pins
[] = {
3417 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
3419 static const unsigned int scifb0_data_mux
[] = {
3420 SCIFB0_RXD_MARK
, SCIFB0_TXD_MARK
,
3422 static const unsigned int scifb0_clk_pins
[] = {
3426 static const unsigned int scifb0_clk_mux
[] = {
3429 static const unsigned int scifb0_ctrl_pins
[] = {
3431 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
3433 static const unsigned int scifb0_ctrl_mux
[] = {
3434 SCIFB0_RTS_N_MARK
, SCIFB0_CTS_N_MARK
,
3436 static const unsigned int scifb0_data_b_pins
[] = {
3438 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
3440 static const unsigned int scifb0_data_b_mux
[] = {
3441 SCIFB0_RXD_B_MARK
, SCIFB0_TXD_B_MARK
,
3443 static const unsigned int scifb0_clk_b_pins
[] = {
3447 static const unsigned int scifb0_clk_b_mux
[] = {
3450 static const unsigned int scifb0_ctrl_b_pins
[] = {
3452 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23),
3454 static const unsigned int scifb0_ctrl_b_mux
[] = {
3455 SCIFB0_RTS_N_B_MARK
, SCIFB0_CTS_N_B_MARK
,
3457 static const unsigned int scifb0_data_c_pins
[] = {
3459 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3461 static const unsigned int scifb0_data_c_mux
[] = {
3462 SCIFB0_RXD_C_MARK
, SCIFB0_TXD_C_MARK
,
3464 static const unsigned int scifb0_clk_c_pins
[] = {
3468 static const unsigned int scifb0_clk_c_mux
[] = {
3471 static const unsigned int scifb0_data_d_pins
[] = {
3473 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
3475 static const unsigned int scifb0_data_d_mux
[] = {
3476 SCIFB0_RXD_D_MARK
, SCIFB0_TXD_D_MARK
,
3478 static const unsigned int scifb0_clk_d_pins
[] = {
3482 static const unsigned int scifb0_clk_d_mux
[] = {
3485 /* - SCIFB1 ----------------------------------------------------------------- */
3486 static const unsigned int scifb1_data_pins
[] = {
3488 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
3490 static const unsigned int scifb1_data_mux
[] = {
3491 SCIFB1_RXD_MARK
, SCIFB1_TXD_MARK
,
3493 static const unsigned int scifb1_clk_pins
[] = {
3497 static const unsigned int scifb1_clk_mux
[] = {
3500 static const unsigned int scifb1_ctrl_pins
[] = {
3502 RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
3504 static const unsigned int scifb1_ctrl_mux
[] = {
3505 SCIFB1_RTS_N_MARK
, SCIFB1_CTS_N_MARK
,
3507 static const unsigned int scifb1_data_b_pins
[] = {
3509 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3511 static const unsigned int scifb1_data_b_mux
[] = {
3512 SCIFB1_RXD_B_MARK
, SCIFB1_TXD_B_MARK
,
3514 static const unsigned int scifb1_clk_b_pins
[] = {
3518 static const unsigned int scifb1_clk_b_mux
[] = {
3521 static const unsigned int scifb1_data_c_pins
[] = {
3523 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3525 static const unsigned int scifb1_data_c_mux
[] = {
3526 SCIFB1_RXD_C_MARK
, SCIFB1_TXD_C_MARK
,
3528 static const unsigned int scifb1_clk_c_pins
[] = {
3532 static const unsigned int scifb1_clk_c_mux
[] = {
3535 static const unsigned int scifb1_data_d_pins
[] = {
3537 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12),
3539 static const unsigned int scifb1_data_d_mux
[] = {
3540 SCIFB1_RXD_D_MARK
, SCIFB1_TXD_D_MARK
,
3542 /* - SCIFB2 ----------------------------------------------------------------- */
3543 static const unsigned int scifb2_data_pins
[] = {
3545 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
3547 static const unsigned int scifb2_data_mux
[] = {
3548 SCIFB2_RXD_MARK
, SCIFB2_TXD_MARK
,
3550 static const unsigned int scifb2_clk_pins
[] = {
3554 static const unsigned int scifb2_clk_mux
[] = {
3557 static const unsigned int scifb2_ctrl_pins
[] = {
3559 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
3561 static const unsigned int scifb2_ctrl_mux
[] = {
3562 SCIFB2_RTS_N_MARK
, SCIFB2_CTS_N_MARK
,
3564 static const unsigned int scifb2_data_b_pins
[] = {
3566 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3568 static const unsigned int scifb2_data_b_mux
[] = {
3569 SCIFB2_RXD_B_MARK
, SCIFB2_TXD_B_MARK
,
3571 static const unsigned int scifb2_clk_b_pins
[] = {
3575 static const unsigned int scifb2_clk_b_mux
[] = {
3578 static const unsigned int scifb2_ctrl_b_pins
[] = {
3580 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
3582 static const unsigned int scifb2_ctrl_b_mux
[] = {
3583 SCIFB2_RTS_N_B_MARK
, SCIFB2_CTS_N_B_MARK
,
3585 static const unsigned int scifb2_data_c_pins
[] = {
3587 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3589 static const unsigned int scifb2_data_c_mux
[] = {
3590 SCIFB2_RXD_C_MARK
, SCIFB2_TXD_C_MARK
,
3592 static const unsigned int scifb2_clk_c_pins
[] = {
3596 static const unsigned int scifb2_clk_c_mux
[] = {
3599 static const unsigned int scifb2_data_d_pins
[] = {
3601 RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25),
3603 static const unsigned int scifb2_data_d_mux
[] = {
3604 SCIFB2_RXD_D_MARK
, SCIFB2_TXD_D_MARK
,
3606 /* - SDHI0 ------------------------------------------------------------------ */
3607 static const unsigned int sdhi0_data1_pins
[] = {
3611 static const unsigned int sdhi0_data1_mux
[] = {
3614 static const unsigned int sdhi0_data4_pins
[] = {
3616 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3617 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
3619 static const unsigned int sdhi0_data4_mux
[] = {
3620 SD0_DATA0_MARK
, SD0_DATA1_MARK
, SD0_DATA2_MARK
, SD0_DATA3_MARK
,
3622 static const unsigned int sdhi0_ctrl_pins
[] = {
3624 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3626 static const unsigned int sdhi0_ctrl_mux
[] = {
3627 SD0_CLK_MARK
, SD0_CMD_MARK
,
3629 static const unsigned int sdhi0_cd_pins
[] = {
3633 static const unsigned int sdhi0_cd_mux
[] = {
3636 static const unsigned int sdhi0_wp_pins
[] = {
3640 static const unsigned int sdhi0_wp_mux
[] = {
3643 /* - SDHI1 ------------------------------------------------------------------ */
3644 static const unsigned int sdhi1_data1_pins
[] = {
3648 static const unsigned int sdhi1_data1_mux
[] = {
3651 static const unsigned int sdhi1_data4_pins
[] = {
3653 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
3654 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
3656 static const unsigned int sdhi1_data4_mux
[] = {
3657 SD1_DATA0_MARK
, SD1_DATA1_MARK
, SD1_DATA2_MARK
, SD1_DATA3_MARK
,
3659 static const unsigned int sdhi1_ctrl_pins
[] = {
3661 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3663 static const unsigned int sdhi1_ctrl_mux
[] = {
3664 SD1_CLK_MARK
, SD1_CMD_MARK
,
3666 static const unsigned int sdhi1_cd_pins
[] = {
3670 static const unsigned int sdhi1_cd_mux
[] = {
3673 static const unsigned int sdhi1_wp_pins
[] = {
3677 static const unsigned int sdhi1_wp_mux
[] = {
3680 /* - SDHI2 ------------------------------------------------------------------ */
3681 static const unsigned int sdhi2_data1_pins
[] = {
3685 static const unsigned int sdhi2_data1_mux
[] = {
3688 static const unsigned int sdhi2_data4_pins
[] = {
3690 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
3691 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
3693 static const unsigned int sdhi2_data4_mux
[] = {
3694 SD2_DATA0_MARK
, SD2_DATA1_MARK
, SD2_DATA2_MARK
, SD2_DATA3_MARK
,
3696 static const unsigned int sdhi2_ctrl_pins
[] = {
3698 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
3700 static const unsigned int sdhi2_ctrl_mux
[] = {
3701 SD2_CLK_MARK
, SD2_CMD_MARK
,
3703 static const unsigned int sdhi2_cd_pins
[] = {
3707 static const unsigned int sdhi2_cd_mux
[] = {
3710 static const unsigned int sdhi2_wp_pins
[] = {
3714 static const unsigned int sdhi2_wp_mux
[] = {
3718 /* - SSI -------------------------------------------------------------------- */
3719 static const unsigned int ssi0_data_pins
[] = {
3724 static const unsigned int ssi0_data_mux
[] = {
3728 static const unsigned int ssi0_data_b_pins
[] = {
3733 static const unsigned int ssi0_data_b_mux
[] = {
3737 static const unsigned int ssi0129_ctrl_pins
[] = {
3739 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3742 static const unsigned int ssi0129_ctrl_mux
[] = {
3743 SSI_SCK0129_MARK
, SSI_WS0129_MARK
,
3746 static const unsigned int ssi0129_ctrl_b_pins
[] = {
3748 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3751 static const unsigned int ssi0129_ctrl_b_mux
[] = {
3752 SSI_SCK0129_B_MARK
, SSI_WS0129_B_MARK
,
3755 static const unsigned int ssi1_data_pins
[] = {
3760 static const unsigned int ssi1_data_mux
[] = {
3764 static const unsigned int ssi1_data_b_pins
[] = {
3769 static const unsigned int ssi1_data_b_mux
[] = {
3773 static const unsigned int ssi1_ctrl_pins
[] = {
3775 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3778 static const unsigned int ssi1_ctrl_mux
[] = {
3779 SSI_SCK1_MARK
, SSI_WS1_MARK
,
3782 static const unsigned int ssi1_ctrl_b_pins
[] = {
3784 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3787 static const unsigned int ssi1_ctrl_b_mux
[] = {
3788 SSI_SCK1_B_MARK
, SSI_WS1_B_MARK
,
3791 static const unsigned int ssi2_data_pins
[] = {
3796 static const unsigned int ssi2_data_mux
[] = {
3800 static const unsigned int ssi2_ctrl_pins
[] = {
3802 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3805 static const unsigned int ssi2_ctrl_mux
[] = {
3806 SSI_SCK2_MARK
, SSI_WS2_MARK
,
3809 static const unsigned int ssi3_data_pins
[] = {
3814 static const unsigned int ssi3_data_mux
[] = {
3818 static const unsigned int ssi34_ctrl_pins
[] = {
3820 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
3823 static const unsigned int ssi34_ctrl_mux
[] = {
3824 SSI_SCK34_MARK
, SSI_WS34_MARK
,
3827 static const unsigned int ssi4_data_pins
[] = {
3832 static const unsigned int ssi4_data_mux
[] = {
3836 static const unsigned int ssi4_ctrl_pins
[] = {
3838 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3841 static const unsigned int ssi4_ctrl_mux
[] = {
3842 SSI_SCK4_MARK
, SSI_WS4_MARK
,
3845 static const unsigned int ssi5_data_pins
[] = {
3850 static const unsigned int ssi5_data_mux
[] = {
3854 static const unsigned int ssi5_ctrl_pins
[] = {
3856 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
3859 static const unsigned int ssi5_ctrl_mux
[] = {
3860 SSI_SCK5_MARK
, SSI_WS5_MARK
,
3863 static const unsigned int ssi6_data_pins
[] = {
3868 static const unsigned int ssi6_data_mux
[] = {
3872 static const unsigned int ssi6_ctrl_pins
[] = {
3874 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
3877 static const unsigned int ssi6_ctrl_mux
[] = {
3878 SSI_SCK6_MARK
, SSI_WS6_MARK
,
3881 static const unsigned int ssi7_data_pins
[] = {
3886 static const unsigned int ssi7_data_mux
[] = {
3890 static const unsigned int ssi7_data_b_pins
[] = {
3895 static const unsigned int ssi7_data_b_mux
[] = {
3899 static const unsigned int ssi78_ctrl_pins
[] = {
3901 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
3904 static const unsigned int ssi78_ctrl_mux
[] = {
3905 SSI_SCK78_MARK
, SSI_WS78_MARK
,
3908 static const unsigned int ssi78_ctrl_b_pins
[] = {
3910 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3913 static const unsigned int ssi78_ctrl_b_mux
[] = {
3914 SSI_SCK78_B_MARK
, SSI_WS78_B_MARK
,
3917 static const unsigned int ssi8_data_pins
[] = {
3922 static const unsigned int ssi8_data_mux
[] = {
3926 static const unsigned int ssi8_data_b_pins
[] = {
3931 static const unsigned int ssi8_data_b_mux
[] = {
3935 static const unsigned int ssi9_data_pins
[] = {
3940 static const unsigned int ssi9_data_mux
[] = {
3944 static const unsigned int ssi9_data_b_pins
[] = {
3949 static const unsigned int ssi9_data_b_mux
[] = {
3953 static const unsigned int ssi9_ctrl_pins
[] = {
3955 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
3958 static const unsigned int ssi9_ctrl_mux
[] = {
3959 SSI_SCK9_MARK
, SSI_WS9_MARK
,
3962 static const unsigned int ssi9_ctrl_b_pins
[] = {
3964 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
3967 static const unsigned int ssi9_ctrl_b_mux
[] = {
3968 SSI_SCK9_B_MARK
, SSI_WS9_B_MARK
,
3971 /* - USB0 ------------------------------------------------------------------- */
3972 static const unsigned int usb0_pins
[] = {
3973 RCAR_GP_PIN(7, 23), /* PWEN */
3974 RCAR_GP_PIN(7, 24), /* OVC */
3976 static const unsigned int usb0_mux
[] = {
3980 /* - USB1 ------------------------------------------------------------------- */
3981 static const unsigned int usb1_pins
[] = {
3982 RCAR_GP_PIN(7, 25), /* PWEN */
3983 RCAR_GP_PIN(6, 30), /* OVC */
3985 static const unsigned int usb1_mux
[] = {
3991 unsigned int data24
[24];
3992 unsigned int data20
[20];
3993 unsigned int data16
[16];
3994 unsigned int data12
[12];
3995 unsigned int data10
[10];
3996 unsigned int data8
[8];
3999 #define VIN_DATA_PIN_GROUP(n, s) \
4002 .pins = n##_pins.data##s, \
4003 .mux = n##_mux.data##s, \
4004 .nr_pins = ARRAY_SIZE(n##_pins.data##s), \
4007 /* - VIN0 ------------------------------------------------------------------- */
4008 static const union vin_data vin0_data_pins
= {
4011 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
4012 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
4013 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
4014 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
4016 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
4017 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
4018 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4019 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4021 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
4022 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4023 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4024 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
4027 static const union vin_data vin0_data_mux
= {
4030 VI0_DATA0_VI0_B0_MARK
, VI0_DATA1_VI0_B1_MARK
,
4031 VI0_DATA2_VI0_B2_MARK
, VI0_DATA3_VI0_B3_MARK
,
4032 VI0_DATA4_VI0_B4_MARK
, VI0_DATA5_VI0_B5_MARK
,
4033 VI0_DATA6_VI0_B6_MARK
, VI0_DATA7_VI0_B7_MARK
,
4035 VI0_G0_MARK
, VI0_G1_MARK
,
4036 VI0_G2_MARK
, VI0_G3_MARK
,
4037 VI0_G4_MARK
, VI0_G5_MARK
,
4038 VI0_G6_MARK
, VI0_G7_MARK
,
4040 VI0_R0_MARK
, VI0_R1_MARK
,
4041 VI0_R2_MARK
, VI0_R3_MARK
,
4042 VI0_R4_MARK
, VI0_R5_MARK
,
4043 VI0_R6_MARK
, VI0_R7_MARK
,
4046 static const unsigned int vin0_data18_pins
[] = {
4048 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
4049 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
4050 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
4052 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
4053 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4054 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4056 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4057 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4058 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
4060 static const unsigned int vin0_data18_mux
[] = {
4062 VI0_DATA2_VI0_B2_MARK
, VI0_DATA3_VI0_B3_MARK
,
4063 VI0_DATA4_VI0_B4_MARK
, VI0_DATA5_VI0_B5_MARK
,
4064 VI0_DATA6_VI0_B6_MARK
, VI0_DATA7_VI0_B7_MARK
,
4066 VI0_G2_MARK
, VI0_G3_MARK
,
4067 VI0_G4_MARK
, VI0_G5_MARK
,
4068 VI0_G6_MARK
, VI0_G7_MARK
,
4070 VI0_R2_MARK
, VI0_R3_MARK
,
4071 VI0_R4_MARK
, VI0_R5_MARK
,
4072 VI0_R6_MARK
, VI0_R7_MARK
,
4074 static const unsigned int vin0_sync_pins
[] = {
4075 RCAR_GP_PIN(4, 3), /* HSYNC */
4076 RCAR_GP_PIN(4, 4), /* VSYNC */
4078 static const unsigned int vin0_sync_mux
[] = {
4082 static const unsigned int vin0_field_pins
[] = {
4085 static const unsigned int vin0_field_mux
[] = {
4088 static const unsigned int vin0_clkenb_pins
[] = {
4091 static const unsigned int vin0_clkenb_mux
[] = {
4094 static const unsigned int vin0_clk_pins
[] = {
4097 static const unsigned int vin0_clk_mux
[] = {
4100 /* - VIN1 ----------------------------------------------------------------- */
4101 static const unsigned int vin1_data8_pins
[] = {
4102 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
4103 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
4104 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
4105 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
4107 static const unsigned int vin1_data8_mux
[] = {
4108 VI1_DATA0_MARK
, VI1_DATA1_MARK
,
4109 VI1_DATA2_MARK
, VI1_DATA3_MARK
,
4110 VI1_DATA4_MARK
, VI1_DATA5_MARK
,
4111 VI1_DATA6_MARK
, VI1_DATA7_MARK
,
4113 static const unsigned int vin1_sync_pins
[] = {
4114 RCAR_GP_PIN(5, 0), /* HSYNC */
4115 RCAR_GP_PIN(5, 1), /* VSYNC */
4117 static const unsigned int vin1_sync_mux
[] = {
4121 static const unsigned int vin1_field_pins
[] = {
4124 static const unsigned int vin1_field_mux
[] = {
4127 static const unsigned int vin1_clkenb_pins
[] = {
4130 static const unsigned int vin1_clkenb_mux
[] = {
4133 static const unsigned int vin1_clk_pins
[] = {
4136 static const unsigned int vin1_clk_mux
[] = {
4139 static const union vin_data vin1_b_data_pins
= {
4142 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
4143 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4144 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4145 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4147 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
4148 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4149 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4150 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4152 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
4153 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4154 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4155 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4158 static const union vin_data vin1_b_data_mux
= {
4161 VI1_DATA0_B_MARK
, VI1_DATA1_B_MARK
,
4162 VI1_DATA2_B_MARK
, VI1_DATA3_B_MARK
,
4163 VI1_DATA4_B_MARK
, VI1_DATA5_B_MARK
,
4164 VI1_DATA6_B_MARK
, VI1_DATA7_B_MARK
,
4166 VI1_G0_B_MARK
, VI1_G1_B_MARK
,
4167 VI1_G2_B_MARK
, VI1_G3_B_MARK
,
4168 VI1_G4_B_MARK
, VI1_G5_B_MARK
,
4169 VI1_G6_B_MARK
, VI1_G7_B_MARK
,
4171 VI1_R0_B_MARK
, VI1_R1_B_MARK
,
4172 VI1_R2_B_MARK
, VI1_R3_B_MARK
,
4173 VI1_R4_B_MARK
, VI1_R5_B_MARK
,
4174 VI1_R6_B_MARK
, VI1_R7_B_MARK
,
4177 static const unsigned int vin1_b_data18_pins
[] = {
4179 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4180 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4181 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4183 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4184 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4185 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4187 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4188 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4189 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4191 static const unsigned int vin1_b_data18_mux
[] = {
4193 VI1_DATA0_B_MARK
, VI1_DATA1_B_MARK
,
4194 VI1_DATA2_B_MARK
, VI1_DATA3_B_MARK
,
4195 VI1_DATA4_B_MARK
, VI1_DATA5_B_MARK
,
4196 VI1_DATA6_B_MARK
, VI1_DATA7_B_MARK
,
4198 VI1_G0_B_MARK
, VI1_G1_B_MARK
,
4199 VI1_G2_B_MARK
, VI1_G3_B_MARK
,
4200 VI1_G4_B_MARK
, VI1_G5_B_MARK
,
4201 VI1_G6_B_MARK
, VI1_G7_B_MARK
,
4203 VI1_R0_B_MARK
, VI1_R1_B_MARK
,
4204 VI1_R2_B_MARK
, VI1_R3_B_MARK
,
4205 VI1_R4_B_MARK
, VI1_R5_B_MARK
,
4206 VI1_R6_B_MARK
, VI1_R7_B_MARK
,
4208 static const unsigned int vin1_b_sync_pins
[] = {
4209 RCAR_GP_PIN(3, 17), /* HSYNC */
4210 RCAR_GP_PIN(3, 18), /* VSYNC */
4212 static const unsigned int vin1_b_sync_mux
[] = {
4216 static const unsigned int vin1_b_field_pins
[] = {
4219 static const unsigned int vin1_b_field_mux
[] = {
4222 static const unsigned int vin1_b_clkenb_pins
[] = {
4225 static const unsigned int vin1_b_clkenb_mux
[] = {
4228 static const unsigned int vin1_b_clk_pins
[] = {
4231 static const unsigned int vin1_b_clk_mux
[] = {
4234 /* - VIN2 ----------------------------------------------------------------- */
4235 static const unsigned int vin2_data8_pins
[] = {
4236 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
4237 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
4238 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
4239 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
4241 static const unsigned int vin2_data8_mux
[] = {
4242 VI2_DATA0_MARK
, VI2_DATA1_MARK
,
4243 VI2_DATA2_MARK
, VI2_DATA3_MARK
,
4244 VI2_DATA4_MARK
, VI2_DATA5_MARK
,
4245 VI2_DATA6_MARK
, VI2_DATA7_MARK
,
4247 static const unsigned int vin2_sync_pins
[] = {
4248 RCAR_GP_PIN(4, 15), /* HSYNC */
4249 RCAR_GP_PIN(4, 16), /* VSYNC */
4251 static const unsigned int vin2_sync_mux
[] = {
4255 static const unsigned int vin2_field_pins
[] = {
4258 static const unsigned int vin2_field_mux
[] = {
4261 static const unsigned int vin2_clkenb_pins
[] = {
4264 static const unsigned int vin2_clkenb_mux
[] = {
4267 static const unsigned int vin2_clk_pins
[] = {
4270 static const unsigned int vin2_clk_mux
[] = {
4274 static const struct sh_pfc_pin_group pinmux_groups
[] = {
4275 SH_PFC_PIN_GROUP(audio_clk_a
),
4276 SH_PFC_PIN_GROUP(audio_clk_b
),
4277 SH_PFC_PIN_GROUP(audio_clk_b_b
),
4278 SH_PFC_PIN_GROUP(audio_clk_c
),
4279 SH_PFC_PIN_GROUP(audio_clkout
),
4280 SH_PFC_PIN_GROUP(can0_data
),
4281 SH_PFC_PIN_GROUP(can0_data_b
),
4282 SH_PFC_PIN_GROUP(can0_data_c
),
4283 SH_PFC_PIN_GROUP(can0_data_d
),
4284 SH_PFC_PIN_GROUP(can0_data_e
),
4285 SH_PFC_PIN_GROUP(can0_data_f
),
4286 SH_PFC_PIN_GROUP(can1_data
),
4287 SH_PFC_PIN_GROUP(can1_data_b
),
4288 SH_PFC_PIN_GROUP(can1_data_c
),
4289 SH_PFC_PIN_GROUP(can1_data_d
),
4290 SH_PFC_PIN_GROUP(can_clk
),
4291 SH_PFC_PIN_GROUP(can_clk_b
),
4292 SH_PFC_PIN_GROUP(can_clk_c
),
4293 SH_PFC_PIN_GROUP(can_clk_d
),
4294 SH_PFC_PIN_GROUP(du_rgb666
),
4295 SH_PFC_PIN_GROUP(du_rgb888
),
4296 SH_PFC_PIN_GROUP(du_clk_out_0
),
4297 SH_PFC_PIN_GROUP(du_clk_out_1
),
4298 SH_PFC_PIN_GROUP(du_sync
),
4299 SH_PFC_PIN_GROUP(du_oddf
),
4300 SH_PFC_PIN_GROUP(du_cde
),
4301 SH_PFC_PIN_GROUP(du_disp
),
4302 SH_PFC_PIN_GROUP(du0_clk_in
),
4303 SH_PFC_PIN_GROUP(du1_clk_in
),
4304 SH_PFC_PIN_GROUP(du1_clk_in_b
),
4305 SH_PFC_PIN_GROUP(du1_clk_in_c
),
4306 SH_PFC_PIN_GROUP(eth_link
),
4307 SH_PFC_PIN_GROUP(eth_magic
),
4308 SH_PFC_PIN_GROUP(eth_mdio
),
4309 SH_PFC_PIN_GROUP(eth_rmii
),
4310 SH_PFC_PIN_GROUP(hscif0_data
),
4311 SH_PFC_PIN_GROUP(hscif0_clk
),
4312 SH_PFC_PIN_GROUP(hscif0_ctrl
),
4313 SH_PFC_PIN_GROUP(hscif0_data_b
),
4314 SH_PFC_PIN_GROUP(hscif0_ctrl_b
),
4315 SH_PFC_PIN_GROUP(hscif0_data_c
),
4316 SH_PFC_PIN_GROUP(hscif0_clk_c
),
4317 SH_PFC_PIN_GROUP(hscif1_data
),
4318 SH_PFC_PIN_GROUP(hscif1_clk
),
4319 SH_PFC_PIN_GROUP(hscif1_ctrl
),
4320 SH_PFC_PIN_GROUP(hscif1_data_b
),
4321 SH_PFC_PIN_GROUP(hscif1_data_c
),
4322 SH_PFC_PIN_GROUP(hscif1_clk_c
),
4323 SH_PFC_PIN_GROUP(hscif1_ctrl_c
),
4324 SH_PFC_PIN_GROUP(hscif1_data_d
),
4325 SH_PFC_PIN_GROUP(hscif1_data_e
),
4326 SH_PFC_PIN_GROUP(hscif1_clk_e
),
4327 SH_PFC_PIN_GROUP(hscif1_ctrl_e
),
4328 SH_PFC_PIN_GROUP(hscif2_data
),
4329 SH_PFC_PIN_GROUP(hscif2_clk
),
4330 SH_PFC_PIN_GROUP(hscif2_ctrl
),
4331 SH_PFC_PIN_GROUP(hscif2_data_b
),
4332 SH_PFC_PIN_GROUP(hscif2_ctrl_b
),
4333 SH_PFC_PIN_GROUP(hscif2_data_c
),
4334 SH_PFC_PIN_GROUP(hscif2_clk_c
),
4335 SH_PFC_PIN_GROUP(hscif2_data_d
),
4336 SH_PFC_PIN_GROUP(i2c0
),
4337 SH_PFC_PIN_GROUP(i2c0_b
),
4338 SH_PFC_PIN_GROUP(i2c0_c
),
4339 SH_PFC_PIN_GROUP(i2c1
),
4340 SH_PFC_PIN_GROUP(i2c1_b
),
4341 SH_PFC_PIN_GROUP(i2c1_c
),
4342 SH_PFC_PIN_GROUP(i2c1_d
),
4343 SH_PFC_PIN_GROUP(i2c1_e
),
4344 SH_PFC_PIN_GROUP(i2c2
),
4345 SH_PFC_PIN_GROUP(i2c2_b
),
4346 SH_PFC_PIN_GROUP(i2c2_c
),
4347 SH_PFC_PIN_GROUP(i2c2_d
),
4348 SH_PFC_PIN_GROUP(i2c3
),
4349 SH_PFC_PIN_GROUP(i2c3_b
),
4350 SH_PFC_PIN_GROUP(i2c3_c
),
4351 SH_PFC_PIN_GROUP(i2c3_d
),
4352 SH_PFC_PIN_GROUP(i2c4
),
4353 SH_PFC_PIN_GROUP(i2c4_b
),
4354 SH_PFC_PIN_GROUP(i2c4_c
),
4355 SH_PFC_PIN_GROUP(i2c7
),
4356 SH_PFC_PIN_GROUP(i2c7_b
),
4357 SH_PFC_PIN_GROUP(i2c7_c
),
4358 SH_PFC_PIN_GROUP(i2c8
),
4359 SH_PFC_PIN_GROUP(i2c8_b
),
4360 SH_PFC_PIN_GROUP(i2c8_c
),
4361 SH_PFC_PIN_GROUP(intc_irq0
),
4362 SH_PFC_PIN_GROUP(intc_irq1
),
4363 SH_PFC_PIN_GROUP(intc_irq2
),
4364 SH_PFC_PIN_GROUP(intc_irq3
),
4365 SH_PFC_PIN_GROUP(mlb_3pin
),
4366 SH_PFC_PIN_GROUP(mmc_data1
),
4367 SH_PFC_PIN_GROUP(mmc_data4
),
4368 SH_PFC_PIN_GROUP(mmc_data8
),
4369 SH_PFC_PIN_GROUP(mmc_ctrl
),
4370 SH_PFC_PIN_GROUP(msiof0_clk
),
4371 SH_PFC_PIN_GROUP(msiof0_sync
),
4372 SH_PFC_PIN_GROUP(msiof0_ss1
),
4373 SH_PFC_PIN_GROUP(msiof0_ss2
),
4374 SH_PFC_PIN_GROUP(msiof0_rx
),
4375 SH_PFC_PIN_GROUP(msiof0_tx
),
4376 SH_PFC_PIN_GROUP(msiof0_clk_b
),
4377 SH_PFC_PIN_GROUP(msiof0_sync_b
),
4378 SH_PFC_PIN_GROUP(msiof0_ss1_b
),
4379 SH_PFC_PIN_GROUP(msiof0_ss2_b
),
4380 SH_PFC_PIN_GROUP(msiof0_rx_b
),
4381 SH_PFC_PIN_GROUP(msiof0_tx_b
),
4382 SH_PFC_PIN_GROUP(msiof0_clk_c
),
4383 SH_PFC_PIN_GROUP(msiof0_sync_c
),
4384 SH_PFC_PIN_GROUP(msiof0_ss1_c
),
4385 SH_PFC_PIN_GROUP(msiof0_ss2_c
),
4386 SH_PFC_PIN_GROUP(msiof0_rx_c
),
4387 SH_PFC_PIN_GROUP(msiof0_tx_c
),
4388 SH_PFC_PIN_GROUP(msiof1_clk
),
4389 SH_PFC_PIN_GROUP(msiof1_sync
),
4390 SH_PFC_PIN_GROUP(msiof1_ss1
),
4391 SH_PFC_PIN_GROUP(msiof1_ss2
),
4392 SH_PFC_PIN_GROUP(msiof1_rx
),
4393 SH_PFC_PIN_GROUP(msiof1_tx
),
4394 SH_PFC_PIN_GROUP(msiof1_clk_b
),
4395 SH_PFC_PIN_GROUP(msiof1_sync_b
),
4396 SH_PFC_PIN_GROUP(msiof1_ss1_b
),
4397 SH_PFC_PIN_GROUP(msiof1_ss2_b
),
4398 SH_PFC_PIN_GROUP(msiof1_rx_b
),
4399 SH_PFC_PIN_GROUP(msiof1_tx_b
),
4400 SH_PFC_PIN_GROUP(msiof1_clk_c
),
4401 SH_PFC_PIN_GROUP(msiof1_sync_c
),
4402 SH_PFC_PIN_GROUP(msiof1_rx_c
),
4403 SH_PFC_PIN_GROUP(msiof1_tx_c
),
4404 SH_PFC_PIN_GROUP(msiof1_clk_d
),
4405 SH_PFC_PIN_GROUP(msiof1_sync_d
),
4406 SH_PFC_PIN_GROUP(msiof1_ss1_d
),
4407 SH_PFC_PIN_GROUP(msiof1_rx_d
),
4408 SH_PFC_PIN_GROUP(msiof1_tx_d
),
4409 SH_PFC_PIN_GROUP(msiof1_clk_e
),
4410 SH_PFC_PIN_GROUP(msiof1_sync_e
),
4411 SH_PFC_PIN_GROUP(msiof1_rx_e
),
4412 SH_PFC_PIN_GROUP(msiof1_tx_e
),
4413 SH_PFC_PIN_GROUP(msiof2_clk
),
4414 SH_PFC_PIN_GROUP(msiof2_sync
),
4415 SH_PFC_PIN_GROUP(msiof2_ss1
),
4416 SH_PFC_PIN_GROUP(msiof2_ss2
),
4417 SH_PFC_PIN_GROUP(msiof2_rx
),
4418 SH_PFC_PIN_GROUP(msiof2_tx
),
4419 SH_PFC_PIN_GROUP(msiof2_clk_b
),
4420 SH_PFC_PIN_GROUP(msiof2_sync_b
),
4421 SH_PFC_PIN_GROUP(msiof2_ss1_b
),
4422 SH_PFC_PIN_GROUP(msiof2_ss2_b
),
4423 SH_PFC_PIN_GROUP(msiof2_rx_b
),
4424 SH_PFC_PIN_GROUP(msiof2_tx_b
),
4425 SH_PFC_PIN_GROUP(msiof2_clk_c
),
4426 SH_PFC_PIN_GROUP(msiof2_sync_c
),
4427 SH_PFC_PIN_GROUP(msiof2_rx_c
),
4428 SH_PFC_PIN_GROUP(msiof2_tx_c
),
4429 SH_PFC_PIN_GROUP(msiof2_clk_d
),
4430 SH_PFC_PIN_GROUP(msiof2_sync_d
),
4431 SH_PFC_PIN_GROUP(msiof2_ss1_d
),
4432 SH_PFC_PIN_GROUP(msiof2_ss2_d
),
4433 SH_PFC_PIN_GROUP(msiof2_rx_d
),
4434 SH_PFC_PIN_GROUP(msiof2_tx_d
),
4435 SH_PFC_PIN_GROUP(msiof2_clk_e
),
4436 SH_PFC_PIN_GROUP(msiof2_sync_e
),
4437 SH_PFC_PIN_GROUP(msiof2_rx_e
),
4438 SH_PFC_PIN_GROUP(msiof2_tx_e
),
4439 SH_PFC_PIN_GROUP(pwm0
),
4440 SH_PFC_PIN_GROUP(pwm0_b
),
4441 SH_PFC_PIN_GROUP(pwm1
),
4442 SH_PFC_PIN_GROUP(pwm1_b
),
4443 SH_PFC_PIN_GROUP(pwm2
),
4444 SH_PFC_PIN_GROUP(pwm2_b
),
4445 SH_PFC_PIN_GROUP(pwm3
),
4446 SH_PFC_PIN_GROUP(pwm4
),
4447 SH_PFC_PIN_GROUP(pwm4_b
),
4448 SH_PFC_PIN_GROUP(pwm5
),
4449 SH_PFC_PIN_GROUP(pwm5_b
),
4450 SH_PFC_PIN_GROUP(pwm6
),
4451 SH_PFC_PIN_GROUP(qspi_ctrl
),
4452 SH_PFC_PIN_GROUP(qspi_data2
),
4453 SH_PFC_PIN_GROUP(qspi_data4
),
4454 SH_PFC_PIN_GROUP(qspi_ctrl_b
),
4455 SH_PFC_PIN_GROUP(qspi_data2_b
),
4456 SH_PFC_PIN_GROUP(qspi_data4_b
),
4457 SH_PFC_PIN_GROUP(scif0_data
),
4458 SH_PFC_PIN_GROUP(scif0_data_b
),
4459 SH_PFC_PIN_GROUP(scif0_data_c
),
4460 SH_PFC_PIN_GROUP(scif0_data_d
),
4461 SH_PFC_PIN_GROUP(scif0_data_e
),
4462 SH_PFC_PIN_GROUP(scif1_data
),
4463 SH_PFC_PIN_GROUP(scif1_data_b
),
4464 SH_PFC_PIN_GROUP(scif1_clk_b
),
4465 SH_PFC_PIN_GROUP(scif1_data_c
),
4466 SH_PFC_PIN_GROUP(scif1_data_d
),
4467 SH_PFC_PIN_GROUP(scif2_data
),
4468 SH_PFC_PIN_GROUP(scif2_data_b
),
4469 SH_PFC_PIN_GROUP(scif2_clk_b
),
4470 SH_PFC_PIN_GROUP(scif2_data_c
),
4471 SH_PFC_PIN_GROUP(scif2_data_e
),
4472 SH_PFC_PIN_GROUP(scif3_data
),
4473 SH_PFC_PIN_GROUP(scif3_clk
),
4474 SH_PFC_PIN_GROUP(scif3_data_b
),
4475 SH_PFC_PIN_GROUP(scif3_clk_b
),
4476 SH_PFC_PIN_GROUP(scif3_data_c
),
4477 SH_PFC_PIN_GROUP(scif3_data_d
),
4478 SH_PFC_PIN_GROUP(scif4_data
),
4479 SH_PFC_PIN_GROUP(scif4_data_b
),
4480 SH_PFC_PIN_GROUP(scif4_data_c
),
4481 SH_PFC_PIN_GROUP(scif5_data
),
4482 SH_PFC_PIN_GROUP(scif5_data_b
),
4483 SH_PFC_PIN_GROUP(scifa0_data
),
4484 SH_PFC_PIN_GROUP(scifa0_data_b
),
4485 SH_PFC_PIN_GROUP(scifa1_data
),
4486 SH_PFC_PIN_GROUP(scifa1_clk
),
4487 SH_PFC_PIN_GROUP(scifa1_data_b
),
4488 SH_PFC_PIN_GROUP(scifa1_clk_b
),
4489 SH_PFC_PIN_GROUP(scifa1_data_c
),
4490 SH_PFC_PIN_GROUP(scifa2_data
),
4491 SH_PFC_PIN_GROUP(scifa2_clk
),
4492 SH_PFC_PIN_GROUP(scifa2_data_b
),
4493 SH_PFC_PIN_GROUP(scifa3_data
),
4494 SH_PFC_PIN_GROUP(scifa3_clk
),
4495 SH_PFC_PIN_GROUP(scifa3_data_b
),
4496 SH_PFC_PIN_GROUP(scifa3_clk_b
),
4497 SH_PFC_PIN_GROUP(scifa3_data_c
),
4498 SH_PFC_PIN_GROUP(scifa3_clk_c
),
4499 SH_PFC_PIN_GROUP(scifa4_data
),
4500 SH_PFC_PIN_GROUP(scifa4_data_b
),
4501 SH_PFC_PIN_GROUP(scifa4_data_c
),
4502 SH_PFC_PIN_GROUP(scifa5_data
),
4503 SH_PFC_PIN_GROUP(scifa5_data_b
),
4504 SH_PFC_PIN_GROUP(scifa5_data_c
),
4505 SH_PFC_PIN_GROUP(scifb0_data
),
4506 SH_PFC_PIN_GROUP(scifb0_clk
),
4507 SH_PFC_PIN_GROUP(scifb0_ctrl
),
4508 SH_PFC_PIN_GROUP(scifb0_data_b
),
4509 SH_PFC_PIN_GROUP(scifb0_clk_b
),
4510 SH_PFC_PIN_GROUP(scifb0_ctrl_b
),
4511 SH_PFC_PIN_GROUP(scifb0_data_c
),
4512 SH_PFC_PIN_GROUP(scifb0_clk_c
),
4513 SH_PFC_PIN_GROUP(scifb0_data_d
),
4514 SH_PFC_PIN_GROUP(scifb0_clk_d
),
4515 SH_PFC_PIN_GROUP(scifb1_data
),
4516 SH_PFC_PIN_GROUP(scifb1_clk
),
4517 SH_PFC_PIN_GROUP(scifb1_ctrl
),
4518 SH_PFC_PIN_GROUP(scifb1_data_b
),
4519 SH_PFC_PIN_GROUP(scifb1_clk_b
),
4520 SH_PFC_PIN_GROUP(scifb1_data_c
),
4521 SH_PFC_PIN_GROUP(scifb1_clk_c
),
4522 SH_PFC_PIN_GROUP(scifb1_data_d
),
4523 SH_PFC_PIN_GROUP(scifb2_data
),
4524 SH_PFC_PIN_GROUP(scifb2_clk
),
4525 SH_PFC_PIN_GROUP(scifb2_ctrl
),
4526 SH_PFC_PIN_GROUP(scifb2_data_b
),
4527 SH_PFC_PIN_GROUP(scifb2_clk_b
),
4528 SH_PFC_PIN_GROUP(scifb2_ctrl_b
),
4529 SH_PFC_PIN_GROUP(scifb2_data_c
),
4530 SH_PFC_PIN_GROUP(scifb2_clk_c
),
4531 SH_PFC_PIN_GROUP(scifb2_data_d
),
4532 SH_PFC_PIN_GROUP(sdhi0_data1
),
4533 SH_PFC_PIN_GROUP(sdhi0_data4
),
4534 SH_PFC_PIN_GROUP(sdhi0_ctrl
),
4535 SH_PFC_PIN_GROUP(sdhi0_cd
),
4536 SH_PFC_PIN_GROUP(sdhi0_wp
),
4537 SH_PFC_PIN_GROUP(sdhi1_data1
),
4538 SH_PFC_PIN_GROUP(sdhi1_data4
),
4539 SH_PFC_PIN_GROUP(sdhi1_ctrl
),
4540 SH_PFC_PIN_GROUP(sdhi1_cd
),
4541 SH_PFC_PIN_GROUP(sdhi1_wp
),
4542 SH_PFC_PIN_GROUP(sdhi2_data1
),
4543 SH_PFC_PIN_GROUP(sdhi2_data4
),
4544 SH_PFC_PIN_GROUP(sdhi2_ctrl
),
4545 SH_PFC_PIN_GROUP(sdhi2_cd
),
4546 SH_PFC_PIN_GROUP(sdhi2_wp
),
4547 SH_PFC_PIN_GROUP(ssi0_data
),
4548 SH_PFC_PIN_GROUP(ssi0_data_b
),
4549 SH_PFC_PIN_GROUP(ssi0129_ctrl
),
4550 SH_PFC_PIN_GROUP(ssi0129_ctrl_b
),
4551 SH_PFC_PIN_GROUP(ssi1_data
),
4552 SH_PFC_PIN_GROUP(ssi1_data_b
),
4553 SH_PFC_PIN_GROUP(ssi1_ctrl
),
4554 SH_PFC_PIN_GROUP(ssi1_ctrl_b
),
4555 SH_PFC_PIN_GROUP(ssi2_data
),
4556 SH_PFC_PIN_GROUP(ssi2_ctrl
),
4557 SH_PFC_PIN_GROUP(ssi3_data
),
4558 SH_PFC_PIN_GROUP(ssi34_ctrl
),
4559 SH_PFC_PIN_GROUP(ssi4_data
),
4560 SH_PFC_PIN_GROUP(ssi4_ctrl
),
4561 SH_PFC_PIN_GROUP(ssi5_data
),
4562 SH_PFC_PIN_GROUP(ssi5_ctrl
),
4563 SH_PFC_PIN_GROUP(ssi6_data
),
4564 SH_PFC_PIN_GROUP(ssi6_ctrl
),
4565 SH_PFC_PIN_GROUP(ssi7_data
),
4566 SH_PFC_PIN_GROUP(ssi7_data_b
),
4567 SH_PFC_PIN_GROUP(ssi78_ctrl
),
4568 SH_PFC_PIN_GROUP(ssi78_ctrl_b
),
4569 SH_PFC_PIN_GROUP(ssi8_data
),
4570 SH_PFC_PIN_GROUP(ssi8_data_b
),
4571 SH_PFC_PIN_GROUP(ssi9_data
),
4572 SH_PFC_PIN_GROUP(ssi9_data_b
),
4573 SH_PFC_PIN_GROUP(ssi9_ctrl
),
4574 SH_PFC_PIN_GROUP(ssi9_ctrl_b
),
4575 SH_PFC_PIN_GROUP(usb0
),
4576 SH_PFC_PIN_GROUP(usb1
),
4577 VIN_DATA_PIN_GROUP(vin0_data
, 24),
4578 VIN_DATA_PIN_GROUP(vin0_data
, 20),
4579 SH_PFC_PIN_GROUP(vin0_data18
),
4580 VIN_DATA_PIN_GROUP(vin0_data
, 16),
4581 VIN_DATA_PIN_GROUP(vin0_data
, 12),
4582 VIN_DATA_PIN_GROUP(vin0_data
, 10),
4583 VIN_DATA_PIN_GROUP(vin0_data
, 8),
4584 SH_PFC_PIN_GROUP(vin0_sync
),
4585 SH_PFC_PIN_GROUP(vin0_field
),
4586 SH_PFC_PIN_GROUP(vin0_clkenb
),
4587 SH_PFC_PIN_GROUP(vin0_clk
),
4588 SH_PFC_PIN_GROUP(vin1_data8
),
4589 SH_PFC_PIN_GROUP(vin1_sync
),
4590 SH_PFC_PIN_GROUP(vin1_field
),
4591 SH_PFC_PIN_GROUP(vin1_clkenb
),
4592 SH_PFC_PIN_GROUP(vin1_clk
),
4593 VIN_DATA_PIN_GROUP(vin1_b_data
, 24),
4594 VIN_DATA_PIN_GROUP(vin1_b_data
, 20),
4595 SH_PFC_PIN_GROUP(vin1_b_data18
),
4596 VIN_DATA_PIN_GROUP(vin1_b_data
, 16),
4597 VIN_DATA_PIN_GROUP(vin1_b_data
, 12),
4598 VIN_DATA_PIN_GROUP(vin1_b_data
, 10),
4599 VIN_DATA_PIN_GROUP(vin1_b_data
, 8),
4600 SH_PFC_PIN_GROUP(vin1_b_sync
),
4601 SH_PFC_PIN_GROUP(vin1_b_field
),
4602 SH_PFC_PIN_GROUP(vin1_b_clkenb
),
4603 SH_PFC_PIN_GROUP(vin1_b_clk
),
4604 SH_PFC_PIN_GROUP(vin2_data8
),
4605 SH_PFC_PIN_GROUP(vin2_sync
),
4606 SH_PFC_PIN_GROUP(vin2_field
),
4607 SH_PFC_PIN_GROUP(vin2_clkenb
),
4608 SH_PFC_PIN_GROUP(vin2_clk
),
4611 static const char * const audio_clk_groups
[] = {
4619 static const char * const can0_groups
[] = {
4632 static const char * const can1_groups
[] = {
4643 static const char * const du_groups
[] = {
4654 static const char * const du0_groups
[] = {
4658 static const char * const du1_groups
[] = {
4664 static const char * const eth_groups
[] = {
4671 static const char * const hscif0_groups
[] = {
4681 static const char * const hscif1_groups
[] = {
4695 static const char * const hscif2_groups
[] = {
4706 static const char * const i2c0_groups
[] = {
4712 static const char * const i2c1_groups
[] = {
4720 static const char * const i2c2_groups
[] = {
4727 static const char * const i2c3_groups
[] = {
4734 static const char * const i2c4_groups
[] = {
4740 static const char * const i2c7_groups
[] = {
4746 static const char * const i2c8_groups
[] = {
4752 static const char * const intc_groups
[] = {
4759 static const char * const mlb_groups
[] = {
4763 static const char * const mmc_groups
[] = {
4770 static const char * const msiof0_groups
[] = {
4791 static const char * const msiof1_groups
[] = {
4819 static const char * const msiof2_groups
[] = {
4848 static const char * const pwm0_groups
[] = {
4853 static const char * const pwm1_groups
[] = {
4858 static const char * const pwm2_groups
[] = {
4863 static const char * const pwm3_groups
[] = {
4867 static const char * const pwm4_groups
[] = {
4872 static const char * const pwm5_groups
[] = {
4877 static const char * const pwm6_groups
[] = {
4881 static const char * const qspi_groups
[] = {
4890 static const char * const scif0_groups
[] = {
4898 static const char * const scif1_groups
[] = {
4906 static const char * const scif2_groups
[] = {
4913 static const char * const scif3_groups
[] = {
4921 static const char * const scif4_groups
[] = {
4926 static const char * const scif5_groups
[] = {
4930 static const char * const scifa0_groups
[] = {
4934 static const char * const scifa1_groups
[] = {
4941 static const char * const scifa2_groups
[] = {
4946 static const char * const scifa3_groups
[] = {
4954 static const char * const scifa4_groups
[] = {
4959 static const char * const scifa5_groups
[] = {
4964 static const char * const scifb0_groups
[] = {
4976 static const char * const scifb1_groups
[] = {
4986 static const char * const scifb2_groups
[] = {
4998 static const char * const sdhi0_groups
[] = {
5006 static const char * const sdhi1_groups
[] = {
5014 static const char * const sdhi2_groups
[] = {
5022 static const char * const ssi_groups
[] = {
5053 static const char * const usb0_groups
[] = {
5056 static const char * const usb1_groups
[] = {
5060 static const char * const vin0_groups
[] = {
5074 static const char * const vin1_groups
[] = {
5093 static const char * const vin2_groups
[] = {
5101 static const struct sh_pfc_function pinmux_functions
[] = {
5102 SH_PFC_FUNCTION(audio_clk
),
5103 SH_PFC_FUNCTION(can0
),
5104 SH_PFC_FUNCTION(can1
),
5105 SH_PFC_FUNCTION(du
),
5106 SH_PFC_FUNCTION(du0
),
5107 SH_PFC_FUNCTION(du1
),
5108 SH_PFC_FUNCTION(eth
),
5109 SH_PFC_FUNCTION(hscif0
),
5110 SH_PFC_FUNCTION(hscif1
),
5111 SH_PFC_FUNCTION(hscif2
),
5112 SH_PFC_FUNCTION(i2c0
),
5113 SH_PFC_FUNCTION(i2c1
),
5114 SH_PFC_FUNCTION(i2c2
),
5115 SH_PFC_FUNCTION(i2c3
),
5116 SH_PFC_FUNCTION(i2c4
),
5117 SH_PFC_FUNCTION(i2c7
),
5118 SH_PFC_FUNCTION(i2c8
),
5119 SH_PFC_FUNCTION(intc
),
5120 SH_PFC_FUNCTION(mlb
),
5121 SH_PFC_FUNCTION(mmc
),
5122 SH_PFC_FUNCTION(msiof0
),
5123 SH_PFC_FUNCTION(msiof1
),
5124 SH_PFC_FUNCTION(msiof2
),
5125 SH_PFC_FUNCTION(pwm0
),
5126 SH_PFC_FUNCTION(pwm1
),
5127 SH_PFC_FUNCTION(pwm2
),
5128 SH_PFC_FUNCTION(pwm3
),
5129 SH_PFC_FUNCTION(pwm4
),
5130 SH_PFC_FUNCTION(pwm5
),
5131 SH_PFC_FUNCTION(pwm6
),
5132 SH_PFC_FUNCTION(qspi
),
5133 SH_PFC_FUNCTION(scif0
),
5134 SH_PFC_FUNCTION(scif1
),
5135 SH_PFC_FUNCTION(scif2
),
5136 SH_PFC_FUNCTION(scif3
),
5137 SH_PFC_FUNCTION(scif4
),
5138 SH_PFC_FUNCTION(scif5
),
5139 SH_PFC_FUNCTION(scifa0
),
5140 SH_PFC_FUNCTION(scifa1
),
5141 SH_PFC_FUNCTION(scifa2
),
5142 SH_PFC_FUNCTION(scifa3
),
5143 SH_PFC_FUNCTION(scifa4
),
5144 SH_PFC_FUNCTION(scifa5
),
5145 SH_PFC_FUNCTION(scifb0
),
5146 SH_PFC_FUNCTION(scifb1
),
5147 SH_PFC_FUNCTION(scifb2
),
5148 SH_PFC_FUNCTION(sdhi0
),
5149 SH_PFC_FUNCTION(sdhi1
),
5150 SH_PFC_FUNCTION(sdhi2
),
5151 SH_PFC_FUNCTION(ssi
),
5152 SH_PFC_FUNCTION(usb0
),
5153 SH_PFC_FUNCTION(usb1
),
5154 SH_PFC_FUNCTION(vin0
),
5155 SH_PFC_FUNCTION(vin1
),
5156 SH_PFC_FUNCTION(vin2
),
5159 static const struct pinmux_cfg_reg pinmux_config_regs
[] = {
5160 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
5161 GP_0_31_FN
, FN_IP1_22_20
,
5162 GP_0_30_FN
, FN_IP1_19_17
,
5163 GP_0_29_FN
, FN_IP1_16_14
,
5164 GP_0_28_FN
, FN_IP1_13_11
,
5165 GP_0_27_FN
, FN_IP1_10_8
,
5166 GP_0_26_FN
, FN_IP1_7_6
,
5167 GP_0_25_FN
, FN_IP1_5_4
,
5168 GP_0_24_FN
, FN_IP1_3_2
,
5169 GP_0_23_FN
, FN_IP1_1_0
,
5170 GP_0_22_FN
, FN_IP0_30_29
,
5171 GP_0_21_FN
, FN_IP0_28_27
,
5172 GP_0_20_FN
, FN_IP0_26_25
,
5173 GP_0_19_FN
, FN_IP0_24_23
,
5174 GP_0_18_FN
, FN_IP0_22_21
,
5175 GP_0_17_FN
, FN_IP0_20_19
,
5176 GP_0_16_FN
, FN_IP0_18_16
,
5177 GP_0_15_FN
, FN_IP0_15
,
5178 GP_0_14_FN
, FN_IP0_14
,
5179 GP_0_13_FN
, FN_IP0_13
,
5180 GP_0_12_FN
, FN_IP0_12
,
5181 GP_0_11_FN
, FN_IP0_11
,
5182 GP_0_10_FN
, FN_IP0_10
,
5183 GP_0_9_FN
, FN_IP0_9
,
5184 GP_0_8_FN
, FN_IP0_8
,
5185 GP_0_7_FN
, FN_IP0_7
,
5186 GP_0_6_FN
, FN_IP0_6
,
5187 GP_0_5_FN
, FN_IP0_5
,
5188 GP_0_4_FN
, FN_IP0_4
,
5189 GP_0_3_FN
, FN_IP0_3
,
5190 GP_0_2_FN
, FN_IP0_2
,
5191 GP_0_1_FN
, FN_IP0_1
,
5192 GP_0_0_FN
, FN_IP0_0
, }
5194 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
5201 GP_1_25_FN
, FN_IP3_21_20
,
5202 GP_1_24_FN
, FN_IP3_19_18
,
5203 GP_1_23_FN
, FN_IP3_17_16
,
5204 GP_1_22_FN
, FN_IP3_15_14
,
5205 GP_1_21_FN
, FN_IP3_13_12
,
5206 GP_1_20_FN
, FN_IP3_11_9
,
5207 GP_1_19_FN
, FN_RD_N
,
5208 GP_1_18_FN
, FN_IP3_8_6
,
5209 GP_1_17_FN
, FN_IP3_5_3
,
5210 GP_1_16_FN
, FN_IP3_2_0
,
5211 GP_1_15_FN
, FN_IP2_29_27
,
5212 GP_1_14_FN
, FN_IP2_26_25
,
5213 GP_1_13_FN
, FN_IP2_24_23
,
5214 GP_1_12_FN
, FN_EX_CS0_N
,
5215 GP_1_11_FN
, FN_IP2_22_21
,
5216 GP_1_10_FN
, FN_IP2_20_19
,
5217 GP_1_9_FN
, FN_IP2_18_16
,
5218 GP_1_8_FN
, FN_IP2_15_13
,
5219 GP_1_7_FN
, FN_IP2_12_10
,
5220 GP_1_6_FN
, FN_IP2_9_7
,
5221 GP_1_5_FN
, FN_IP2_6_5
,
5222 GP_1_4_FN
, FN_IP2_4_3
,
5223 GP_1_3_FN
, FN_IP2_2_0
,
5224 GP_1_2_FN
, FN_IP1_31_29
,
5225 GP_1_1_FN
, FN_IP1_28_26
,
5226 GP_1_0_FN
, FN_IP1_25_23
, }
5228 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
5229 GP_2_31_FN
, FN_IP6_7_6
,
5230 GP_2_30_FN
, FN_IP6_5_3
,
5231 GP_2_29_FN
, FN_IP6_2_0
,
5232 GP_2_28_FN
, FN_AUDIO_CLKA
,
5233 GP_2_27_FN
, FN_IP5_31_29
,
5234 GP_2_26_FN
, FN_IP5_28_26
,
5235 GP_2_25_FN
, FN_IP5_25_24
,
5236 GP_2_24_FN
, FN_IP5_23_22
,
5237 GP_2_23_FN
, FN_IP5_21_20
,
5238 GP_2_22_FN
, FN_IP5_19_17
,
5239 GP_2_21_FN
, FN_IP5_16_15
,
5240 GP_2_20_FN
, FN_IP5_14_12
,
5241 GP_2_19_FN
, FN_IP5_11_9
,
5242 GP_2_18_FN
, FN_IP5_8_6
,
5243 GP_2_17_FN
, FN_IP5_5_3
,
5244 GP_2_16_FN
, FN_IP5_2_0
,
5245 GP_2_15_FN
, FN_IP4_30_28
,
5246 GP_2_14_FN
, FN_IP4_27_26
,
5247 GP_2_13_FN
, FN_IP4_25_24
,
5248 GP_2_12_FN
, FN_IP4_23_22
,
5249 GP_2_11_FN
, FN_IP4_21
,
5250 GP_2_10_FN
, FN_IP4_20
,
5251 GP_2_9_FN
, FN_IP4_19
,
5252 GP_2_8_FN
, FN_IP4_18_16
,
5253 GP_2_7_FN
, FN_IP4_15_13
,
5254 GP_2_6_FN
, FN_IP4_12_10
,
5255 GP_2_5_FN
, FN_IP4_9_8
,
5256 GP_2_4_FN
, FN_IP4_7_5
,
5257 GP_2_3_FN
, FN_IP4_4_2
,
5258 GP_2_2_FN
, FN_IP4_1_0
,
5259 GP_2_1_FN
, FN_IP3_30_28
,
5260 GP_2_0_FN
, FN_IP3_27_25
}
5262 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
5263 GP_3_31_FN
, FN_IP9_18_17
,
5264 GP_3_30_FN
, FN_IP9_16
,
5265 GP_3_29_FN
, FN_IP9_15_13
,
5266 GP_3_28_FN
, FN_IP9_12
,
5267 GP_3_27_FN
, FN_IP9_11
,
5268 GP_3_26_FN
, FN_IP9_10_8
,
5269 GP_3_25_FN
, FN_IP9_7
,
5270 GP_3_24_FN
, FN_IP9_6
,
5271 GP_3_23_FN
, FN_IP9_5_3
,
5272 GP_3_22_FN
, FN_IP9_2_0
,
5273 GP_3_21_FN
, FN_IP8_30_28
,
5274 GP_3_20_FN
, FN_IP8_27_26
,
5275 GP_3_19_FN
, FN_IP8_25_24
,
5276 GP_3_18_FN
, FN_IP8_23_21
,
5277 GP_3_17_FN
, FN_IP8_20_18
,
5278 GP_3_16_FN
, FN_IP8_17_15
,
5279 GP_3_15_FN
, FN_IP8_14_12
,
5280 GP_3_14_FN
, FN_IP8_11_9
,
5281 GP_3_13_FN
, FN_IP8_8_6
,
5282 GP_3_12_FN
, FN_IP8_5_3
,
5283 GP_3_11_FN
, FN_IP8_2_0
,
5284 GP_3_10_FN
, FN_IP7_29_27
,
5285 GP_3_9_FN
, FN_IP7_26_24
,
5286 GP_3_8_FN
, FN_IP7_23_21
,
5287 GP_3_7_FN
, FN_IP7_20_19
,
5288 GP_3_6_FN
, FN_IP7_18_17
,
5289 GP_3_5_FN
, FN_IP7_16_15
,
5290 GP_3_4_FN
, FN_IP7_14_13
,
5291 GP_3_3_FN
, FN_IP7_12_11
,
5292 GP_3_2_FN
, FN_IP7_10_9
,
5293 GP_3_1_FN
, FN_IP7_8_6
,
5294 GP_3_0_FN
, FN_IP7_5_3
}
5296 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
5297 GP_4_31_FN
, FN_IP15_5_4
,
5298 GP_4_30_FN
, FN_IP15_3_2
,
5299 GP_4_29_FN
, FN_IP15_1_0
,
5300 GP_4_28_FN
, FN_IP11_8_6
,
5301 GP_4_27_FN
, FN_IP11_5_3
,
5302 GP_4_26_FN
, FN_IP11_2_0
,
5303 GP_4_25_FN
, FN_IP10_31_29
,
5304 GP_4_24_FN
, FN_IP10_28_27
,
5305 GP_4_23_FN
, FN_IP10_26_25
,
5306 GP_4_22_FN
, FN_IP10_24_22
,
5307 GP_4_21_FN
, FN_IP10_21_19
,
5308 GP_4_20_FN
, FN_IP10_18_17
,
5309 GP_4_19_FN
, FN_IP10_16_15
,
5310 GP_4_18_FN
, FN_IP10_14_12
,
5311 GP_4_17_FN
, FN_IP10_11_9
,
5312 GP_4_16_FN
, FN_IP10_8_6
,
5313 GP_4_15_FN
, FN_IP10_5_3
,
5314 GP_4_14_FN
, FN_IP10_2_0
,
5315 GP_4_13_FN
, FN_IP9_31_29
,
5316 GP_4_12_FN
, FN_VI0_DATA7_VI0_B7
,
5317 GP_4_11_FN
, FN_VI0_DATA6_VI0_B6
,
5318 GP_4_10_FN
, FN_VI0_DATA5_VI0_B5
,
5319 GP_4_9_FN
, FN_VI0_DATA4_VI0_B4
,
5320 GP_4_8_FN
, FN_IP9_28_27
,
5321 GP_4_7_FN
, FN_VI0_DATA2_VI0_B2
,
5322 GP_4_6_FN
, FN_VI0_DATA1_VI0_B1
,
5323 GP_4_5_FN
, FN_VI0_DATA0_VI0_B0
,
5324 GP_4_4_FN
, FN_IP9_26_25
,
5325 GP_4_3_FN
, FN_IP9_24_23
,
5326 GP_4_2_FN
, FN_IP9_22_21
,
5327 GP_4_1_FN
, FN_IP9_20_19
,
5328 GP_4_0_FN
, FN_VI0_CLK
}
5330 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
5331 GP_5_31_FN
, FN_IP3_24_22
,
5332 GP_5_30_FN
, FN_IP13_9_7
,
5333 GP_5_29_FN
, FN_IP13_6_5
,
5334 GP_5_28_FN
, FN_IP13_4_3
,
5335 GP_5_27_FN
, FN_IP13_2_0
,
5336 GP_5_26_FN
, FN_IP12_29_27
,
5337 GP_5_25_FN
, FN_IP12_26_24
,
5338 GP_5_24_FN
, FN_IP12_23_22
,
5339 GP_5_23_FN
, FN_IP12_21_20
,
5340 GP_5_22_FN
, FN_IP12_19_18
,
5341 GP_5_21_FN
, FN_IP12_17_16
,
5342 GP_5_20_FN
, FN_IP12_15_13
,
5343 GP_5_19_FN
, FN_IP12_12_10
,
5344 GP_5_18_FN
, FN_IP12_9_7
,
5345 GP_5_17_FN
, FN_IP12_6_4
,
5346 GP_5_16_FN
, FN_IP12_3_2
,
5347 GP_5_15_FN
, FN_IP12_1_0
,
5348 GP_5_14_FN
, FN_IP11_31_30
,
5349 GP_5_13_FN
, FN_IP11_29_28
,
5350 GP_5_12_FN
, FN_IP11_27
,
5351 GP_5_11_FN
, FN_IP11_26
,
5352 GP_5_10_FN
, FN_IP11_25
,
5353 GP_5_9_FN
, FN_IP11_24
,
5354 GP_5_8_FN
, FN_IP11_23
,
5355 GP_5_7_FN
, FN_IP11_22
,
5356 GP_5_6_FN
, FN_IP11_21
,
5357 GP_5_5_FN
, FN_IP11_20
,
5358 GP_5_4_FN
, FN_IP11_19
,
5359 GP_5_3_FN
, FN_IP11_18_17
,
5360 GP_5_2_FN
, FN_IP11_16_15
,
5361 GP_5_1_FN
, FN_IP11_14_12
,
5362 GP_5_0_FN
, FN_IP11_11_9
}
5364 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
5365 GP_6_31_FN
, FN_DU0_DOTCLKIN
,
5366 GP_6_30_FN
, FN_USB1_OVC
,
5367 GP_6_29_FN
, FN_IP14_31_29
,
5368 GP_6_28_FN
, FN_IP14_28_26
,
5369 GP_6_27_FN
, FN_IP14_25_23
,
5370 GP_6_26_FN
, FN_IP14_22_20
,
5371 GP_6_25_FN
, FN_IP14_19_17
,
5372 GP_6_24_FN
, FN_IP14_16_14
,
5373 GP_6_23_FN
, FN_IP14_13_11
,
5374 GP_6_22_FN
, FN_IP14_10_8
,
5375 GP_6_21_FN
, FN_IP14_7
,
5376 GP_6_20_FN
, FN_IP14_6
,
5377 GP_6_19_FN
, FN_IP14_5
,
5378 GP_6_18_FN
, FN_IP14_4
,
5379 GP_6_17_FN
, FN_IP14_3
,
5380 GP_6_16_FN
, FN_IP14_2
,
5381 GP_6_15_FN
, FN_IP14_1_0
,
5382 GP_6_14_FN
, FN_IP13_30_28
,
5383 GP_6_13_FN
, FN_IP13_27
,
5384 GP_6_12_FN
, FN_IP13_26
,
5385 GP_6_11_FN
, FN_IP13_25
,
5386 GP_6_10_FN
, FN_IP13_24_23
,
5387 GP_6_9_FN
, FN_IP13_22
,
5388 GP_6_8_FN
, FN_SD1_CLK
,
5389 GP_6_7_FN
, FN_IP13_21_19
,
5390 GP_6_6_FN
, FN_IP13_18_16
,
5391 GP_6_5_FN
, FN_IP13_15
,
5392 GP_6_4_FN
, FN_IP13_14
,
5393 GP_6_3_FN
, FN_IP13_13
,
5394 GP_6_2_FN
, FN_IP13_12
,
5395 GP_6_1_FN
, FN_IP13_11
,
5396 GP_6_0_FN
, FN_IP13_10
}
5398 { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
5405 GP_7_25_FN
, FN_USB1_PWEN
,
5406 GP_7_24_FN
, FN_USB0_OVC
,
5407 GP_7_23_FN
, FN_USB0_PWEN
,
5408 GP_7_22_FN
, FN_IP15_14_12
,
5409 GP_7_21_FN
, FN_IP15_11_9
,
5410 GP_7_20_FN
, FN_IP15_8_6
,
5411 GP_7_19_FN
, FN_IP7_2_0
,
5412 GP_7_18_FN
, FN_IP6_29_27
,
5413 GP_7_17_FN
, FN_IP6_26_24
,
5414 GP_7_16_FN
, FN_IP6_23_21
,
5415 GP_7_15_FN
, FN_IP6_20_19
,
5416 GP_7_14_FN
, FN_IP6_18_16
,
5417 GP_7_13_FN
, FN_IP6_15_14
,
5418 GP_7_12_FN
, FN_IP6_13_12
,
5419 GP_7_11_FN
, FN_IP6_11_10
,
5420 GP_7_10_FN
, FN_IP6_9_8
,
5421 GP_7_9_FN
, FN_IP16_11_10
,
5422 GP_7_8_FN
, FN_IP16_9_8
,
5423 GP_7_7_FN
, FN_IP16_7_6
,
5424 GP_7_6_FN
, FN_IP16_5_3
,
5425 GP_7_5_FN
, FN_IP16_2_0
,
5426 GP_7_4_FN
, FN_IP15_29_27
,
5427 GP_7_3_FN
, FN_IP15_26_24
,
5428 GP_7_2_FN
, FN_IP15_23_21
,
5429 GP_7_1_FN
, FN_IP15_20_18
,
5430 GP_7_0_FN
, FN_IP15_17_15
}
5432 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5433 1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1,
5434 1, 1, 1, 1, 1, 1, 1, 1) {
5438 FN_A6
, FN_MSIOF1_SCK
,
5441 FN_A5
, FN_MSIOF0_RXD_B
,
5444 FN_A4
, FN_MSIOF0_TXD_B
,
5447 FN_A3
, FN_MSIOF0_SS2_B
,
5450 FN_A2
, FN_MSIOF0_SS1_B
,
5453 FN_A1
, FN_MSIOF0_SYNC_B
,
5456 FN_A0
, FN_ATAWR0_N_C
, FN_MSIOF0_SCK_B
, FN_SCL0_C
, FN_PWM2_B
,
5491 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5492 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
5494 FN_A18
, FN_DREQ1
, FN_SCIFA1_RXD_C
, 0, FN_SCIFB1_RXD_C
,
5497 FN_A17
, FN_DACK2_B
, 0, FN_SDA0_C
,
5500 FN_A16
, FN_DREQ2_B
, FN_FMCLK_C
, 0, FN_SCIFA1_SCK_B
,
5503 FN_A15
, FN_BPFCLK_C
,
5506 FN_A14
, FN_ATADIR0_N_C
, FN_FMIN
, FN_FMIN_C
, FN_MSIOF1_SYNC_D
,
5509 FN_A13
, FN_ATAG0_N_C
, FN_BPFCLK
, FN_MSIOF1_SS1_D
,
5512 FN_A12
, FN_FMCLK
, FN_SDA3_D
, FN_MSIOF1_SCK_D
,
5515 FN_A11
, FN_MSIOF1_RXD
, FN_SCL3_D
, FN_MSIOF1_RXD_D
,
5518 FN_A10
, FN_MSIOF1_TXD
, 0, FN_MSIOF1_TXD_D
,
5520 FN_A9
, FN_MSIOF1_SS2
, FN_SDA0
, 0,
5522 FN_A8
, FN_MSIOF1_SS1
, FN_SCL0
, 0,
5524 FN_A7
, FN_MSIOF1_SYNC
,
5527 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5528 2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) {
5532 FN_EX_CS3_N
, FN_ATADIR0_N
, FN_MSIOF2_TXD
,
5533 FN_ATAG0_N
, 0, FN_EX_WAIT1
,
5536 FN_EX_CS2_N
, FN_ATAWR0_N
, FN_MSIOF2_SYNC
, 0,
5538 FN_EX_CS1_N
, FN_MSIOF2_SCK
, 0, 0,
5540 FN_CS1_N_A26
, FN_ATADIR0_N_B
, FN_SDA1
, 0,
5542 FN_CS0_N
, FN_ATAG0_N_B
, FN_SCL1
, 0,
5544 FN_A25
, FN_DACK2
, FN_SSL
, FN_DREQ1_C
, FN_RX1
, FN_SCIFA1_RXD
,
5547 FN_A24
, FN_DREQ2
, FN_IO3
, FN_TX1
, FN_SCIFA1_TXD
,
5550 FN_A23
, FN_IO2
, FN_BPFCLK_B
, FN_RX0
, FN_SCIFA0_RXD
,
5553 FN_A22
, FN_MISO_IO1
, FN_FMCLK_B
, FN_TX0
, FN_SCIFA0_TXD
,
5556 FN_A21
, FN_ATAWR0_N_B
, FN_MOSI_IO0
, 0,
5558 FN_A20
, FN_SPCLK
, 0, 0,
5560 FN_A19
, FN_DACK1
, FN_SCIFA1_TXD_C
, 0,
5561 FN_SCIFB1_TXD_C
, 0, FN_SCIFB1_SCK_B
, 0, }
5563 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5564 1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) {
5568 FN_SSI_WS0129
, FN_HTX0_C
, FN_HTX2_C
,
5569 FN_SCIFB0_TXD_C
, FN_SCIFB2_TXD_C
,
5572 FN_SSI_SCK0129
, FN_HRX0_C
, FN_HRX2_C
,
5573 FN_SCIFB0_RXD_C
, FN_SCIFB2_RXD_C
,
5576 FN_SPEEDIN
, 0, FN_HSCK0_C
, FN_HSCK2_C
, FN_SCIFB0_SCK_B
,
5577 FN_SCIFB2_SCK_B
, FN_DREQ2_C
, FN_HTX2_D
,
5579 FN_DACK0
, FN_DRACK0
, FN_REMOCON
, 0,
5581 FN_DREQ0
, FN_PWM3
, FN_TPU_TO3
, 0,
5583 FN_EX_WAIT0
, FN_HRTS2_N_B
, FN_SCIFB0_CTS_N_B
, 0,
5585 FN_WE1_N
, FN_ATARD0_N_B
, FN_HTX2_B
, FN_SCIFB0_RTS_N_B
,
5587 FN_WE0_N
, FN_HCTS2_N_B
, FN_SCIFB0_TXD_B
, 0,
5589 FN_RD_WR_N
, FN_HRX2_B
, FN_FMIN_B
, FN_SCIFB0_RXD_B
, FN_DREQ1_D
,
5592 FN_BS_N
, FN_ATACS10_N
, FN_MSIOF2_SS2
, FN_HTX1_B
,
5593 FN_SCIFB1_TXD_B
, FN_PWM2
, FN_TPU_TO2
, 0,
5595 FN_EX_CS5_N
, FN_ATACS00_N
, FN_MSIOF2_SS1
, FN_HRX1_B
,
5596 FN_SCIFB1_RXD_B
, FN_PWM1
, FN_TPU_TO1
, 0,
5598 FN_EX_CS4_N
, FN_ATARD0_N
, FN_MSIOF2_RXD
, 0, FN_EX_WAIT2
,
5601 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5602 1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) {
5606 FN_SSI_SCK5
, FN_MSIOF1_SCK_C
, FN_TS_SDATA0
, FN_GLO_I0
,
5607 FN_MSIOF2_SYNC_D
, FN_VI1_R2_B
,
5610 FN_SSI_SDATA4
, FN_MSIOF2_SCK_D
, 0, 0,
5612 FN_SSI_WS4
, FN_GLO_RFON_D
, 0, 0,
5614 FN_SSI_SCK4
, FN_GLO_SS_D
, 0, 0,
5622 FN_SSI_SDATA2
, FN_GPS_MAG_B
, FN_TX2_E
, FN_HRTS1_N_E
,
5625 FN_SSI_WS2
, FN_SDA2
, FN_GPS_SIGN_B
, FN_RX2_E
,
5626 FN_GLO_Q1_D
, FN_HCTS1_N_E
,
5629 FN_SSI_SCK2
, FN_SCL2
, FN_GPS_CLK_B
, FN_GLO_Q0_D
, FN_HSCK1_E
,
5632 FN_SSI_SDATA1
, FN_SDA1_B
, FN_SDA8_B
, FN_MSIOF2_RXD_C
,
5634 FN_SSI_WS1
, FN_SCL1_B
, FN_SCL8_B
, FN_MSIOF2_TXD_C
, FN_GLO_I1_D
,
5637 FN_SSI_SCK1
, FN_SDA0_B
, FN_SDA7_B
,
5638 FN_MSIOF2_SYNC_C
, FN_GLO_I0_D
,
5641 FN_SSI_SDATA0
, FN_SCL0_B
, FN_SCL7_B
, FN_MSIOF2_SCK_C
, }
5643 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5644 3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) {
5646 FN_SSI_SDATA9
, FN_RX3_D
, FN_CAN0_RX_D
,
5649 FN_SSI_WS9
, FN_TX3_D
, FN_CAN0_TX_D
, FN_GLO_SDATA_D
,
5652 FN_SSI_SCK9
, FN_RX1_D
, FN_GLO_SCLK_D
, 0,
5654 FN_SSI_SDATA8
, FN_TX1_D
, FN_STP_ISSYNC_0_B
, 0,
5656 FN_SSI_SDATA7
, FN_RX0_D
, FN_STP_ISEN_0_B
, 0,
5658 FN_SSI_WS78
, FN_TX0_D
, FN_STP_ISD_0_B
, FN_GLO_RFON
,
5661 FN_SSI_SCK78
, FN_STP_ISCLK_0_B
, FN_GLO_SS
, 0,
5663 FN_SSI_SDATA6
, FN_STP_IVCXO27_0_B
, FN_GLO_SDATA
, FN_VI1_R7_B
,
5666 FN_SSI_WS6
, FN_GLO_SCLK
, FN_MSIOF2_SS2_D
, FN_VI1_R6_B
,
5669 FN_SSI_SCK6
, FN_MSIOF1_RXD_C
, FN_TS_SPSYNC0
, FN_GLO_Q1
,
5670 FN_MSIOF2_RXD_D
, FN_VI1_R5_B
,
5673 FN_SSI_SDATA5
, FN_MSIOF1_TXD_C
, FN_TS_SDEN0
, FN_GLO_Q0
,
5674 FN_MSIOF2_SS1_D
, FN_VI1_R4_B
,
5677 FN_SSI_WS5
, FN_MSIOF1_SYNC_C
, FN_TS_SCK0
, FN_GLO_I1
,
5678 FN_MSIOF2_TXD_D
, FN_VI1_R3_B
,
5681 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5682 2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) {
5686 FN_IRQ8
, FN_HRTS1_N_C
, FN_MSIOF1_RXD_B
,
5687 FN_GPS_SIGN_C
, FN_GPS_SIGN_D
,
5690 FN_IRQ7
, FN_HCTS1_N_C
, FN_MSIOF1_TXD_B
,
5691 FN_GPS_CLK_C
, FN_GPS_CLK_D
,
5694 FN_IRQ6
, FN_HSCK1_C
, FN_MSIOF1_SS2_B
,
5695 FN_SDA1_E
, FN_MSIOF2_SYNC_E
,
5698 FN_IRQ5
, FN_HTX1_C
, FN_SCL1_E
, FN_MSIOF2_SCK_E
,
5700 FN_IRQ4
, FN_HRX1_C
, FN_SDA4_C
, FN_MSIOF2_RXD_E
, FN_INTC_IRQ4_N
,
5703 FN_IRQ3
, FN_SCL4_C
, FN_MSIOF2_TXD_E
, FN_INTC_IRQ3_N
,
5705 FN_IRQ2
, FN_SCIFB1_TXD_D
, FN_INTC_IRQ2_N
, 0,
5707 FN_IRQ1
, FN_SCIFB1_SCK_C
, FN_INTC_IRQ1_N
, 0,
5709 FN_IRQ0
, FN_SCIFB1_RXD_D
, FN_INTC_IRQ0_N
, 0,
5711 FN_AUDIO_CLKOUT
, FN_MSIOF1_SS1_B
, FN_TX2
, FN_SCIFA2_TXD
,
5713 FN_AUDIO_CLKC
, FN_SCIFB0_SCK_C
, FN_MSIOF1_SYNC_B
, FN_RX2
,
5714 FN_SCIFA2_RXD
, FN_FMIN_E
,
5717 FN_AUDIO_CLKB
, FN_STP_OPWM_0_B
, FN_MSIOF1_SCK_B
,
5718 FN_SCIF_CLK
, 0, FN_BPFCLK_E
,
5721 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5722 2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) {
5726 FN_DU1_DG2
, FN_LCDOUT10
, FN_VI1_DATA4_B
, FN_SCIF1_SCK_B
,
5727 FN_SCIFA1_SCK
, FN_SSI_SCK78_B
,
5730 FN_DU1_DG1
, FN_LCDOUT9
, FN_VI1_DATA3_B
, FN_RX1_B
,
5731 FN_SCIFA1_RXD_B
, FN_MSIOF2_SS2_B
,
5734 FN_DU1_DG0
, FN_LCDOUT8
, FN_VI1_DATA2_B
, FN_TX1_B
,
5735 FN_SCIFA1_TXD_B
, FN_MSIOF2_SS1_B
,
5738 FN_DU1_DR7
, FN_LCDOUT7
, FN_SSI_SDATA1_B
, 0,
5740 FN_DU1_DR6
, FN_LCDOUT6
, FN_SSI_WS1_B
, 0,
5742 FN_DU1_DR5
, FN_LCDOUT5
, FN_SSI_SCK1_B
, 0,
5744 FN_DU1_DR4
, FN_LCDOUT4
, FN_SSI_SDATA0_B
, 0,
5746 FN_DU1_DR3
, FN_LCDOUT3
, FN_SSI_WS0129_B
, 0,
5748 FN_DU1_DR2
, FN_LCDOUT2
, FN_SSI_SCK0129_B
, 0,
5750 FN_DU1_DR1
, FN_LCDOUT1
, FN_VI1_DATA1_B
, FN_RX0_B
,
5751 FN_SCIFA0_RXD_B
, FN_MSIOF2_SYNC_B
,
5754 FN_DU1_DR0
, FN_LCDOUT0
, FN_VI1_DATA0_B
, FN_TX0_B
,
5755 FN_SCIFA0_TXD_B
, FN_MSIOF2_SCK_B
,
5758 FN_IRQ9
, FN_DU1_DOTCLKIN_B
, FN_CAN_CLK_D
, FN_GPS_MAG_C
,
5759 FN_SCIF_CLK_B
, FN_GPS_MAG_D
,
5762 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5763 1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
5767 FN_DU1_DB5
, FN_LCDOUT21
, FN_TX3
, FN_SCIFA3_TXD
, FN_CAN1_TX
,
5770 FN_DU1_DB4
, FN_LCDOUT20
, FN_VI1_FIELD_B
, FN_CAN1_RX
,
5772 FN_DU1_DB3
, FN_LCDOUT19
, FN_VI1_CLKENB_B
, 0,
5774 FN_DU1_DB2
, FN_LCDOUT18
, FN_VI1_VSYNC_N_B
, FN_SCIF2_SCK_B
,
5775 FN_SCIFA2_SCK
, FN_SSI_SDATA9_B
,
5778 FN_DU1_DB1
, FN_LCDOUT17
, FN_VI1_HSYNC_N_B
, FN_RX2_B
,
5779 FN_SCIFA2_RXD_B
, FN_MSIOF2_RXD_B
,
5782 FN_DU1_DB0
, FN_LCDOUT16
, FN_VI1_CLK_B
, FN_TX2_B
,
5783 FN_SCIFA2_TXD_B
, FN_MSIOF2_TXD_B
,
5786 FN_DU1_DG7
, FN_LCDOUT15
, FN_HTX0_B
,
5787 FN_SCIFB2_RTS_N_B
, FN_SSI_WS9_B
,
5790 FN_DU1_DG6
, FN_LCDOUT14
, FN_HRTS0_N_B
,
5791 FN_SCIFB2_CTS_N_B
, FN_SSI_SCK9_B
,
5794 FN_DU1_DG5
, FN_LCDOUT13
, FN_VI1_DATA7_B
, FN_HCTS0_N_B
,
5795 FN_SCIFB2_TXD_B
, FN_SSI_SDATA8_B
,
5798 FN_DU1_DG4
, FN_LCDOUT12
, FN_VI1_DATA6_B
, FN_HRX0_B
,
5799 FN_SCIFB2_RXD_B
, FN_SSI_SDATA7_B
,
5802 FN_DU1_DG3
, FN_LCDOUT11
, FN_VI1_DATA5_B
, 0, FN_SSI_WS78_B
,
5805 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5806 3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) {
5808 FN_VI0_G0
, FN_SCL8
, FN_STP_IVCXO27_0_C
, FN_SCL4
,
5809 FN_HCTS2_N
, FN_SCIFB2_CTS_N
, FN_ATAWR1_N
, 0,
5811 FN_VI0_DATA3_VI0_B3
, FN_SCIF3_SCK_B
, FN_SCIFA3_SCK_B
, 0,
5813 FN_VI0_VSYNC_N
, FN_RX5
, FN_SCIFA5_RXD
, FN_TS_SPSYNC0_D
,
5815 FN_VI0_HSYNC_N
, FN_TX5
, FN_SCIFA5_TXD
, FN_TS_SDEN0_D
,
5817 FN_VI0_FIELD
, FN_RX4
, FN_SCIFA4_RXD
, FN_TS_SCK0_D
,
5819 FN_VI0_CLKENB
, FN_TX4
, FN_SCIFA4_TXD
, FN_TS_SDATA0_D
,
5821 FN_DU1_CDE
, FN_QPOLB
, FN_PWM4_B
, 0,
5823 FN_DU1_DISP
, FN_QPOLA
,
5825 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE
, FN_QCPV_QDE
,
5826 FN_CAN0_RX
, FN_RX3_B
, FN_SDA2_B
,
5829 FN_DU1_EXVSYNC_DU1_VSYNC
, FN_QSTB_QHE
,
5831 FN_DU1_EXHSYNC_DU1_HSYNC
, FN_QSTH_QHS
,
5833 FN_DU1_DOTCLKOUT1
, FN_QSTVB_QVE
, FN_CAN0_TX
,
5834 FN_TX3_B
, FN_SCL2_B
, FN_PWM4
,
5837 FN_DU1_DOTCLKOUT0
, FN_QCLK
,
5839 FN_DU1_DOTCLKIN
, FN_QSTVA_QVS
,
5841 FN_DU1_DB7
, FN_LCDOUT23
, FN_SDA3_C
,
5842 FN_SCIF3_SCK
, FN_SCIFA3_SCK
,
5845 FN_DU1_DB6
, FN_LCDOUT22
, FN_SCL3_C
, FN_RX3
, FN_SCIFA3_RXD
,
5848 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
5849 3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
5850 /* IP10_31_29 [3] */
5851 FN_VI0_R4
, FN_VI2_DATA5
, FN_GLO_SCLK_B
, FN_TX0_C
, FN_SCL1_D
,
5853 /* IP10_28_27 [2] */
5854 FN_VI0_R3
, FN_VI2_DATA4
, FN_GLO_Q1_B
, FN_TS_SPSYNC0_C
,
5855 /* IP10_26_25 [2] */
5856 FN_VI0_R2
, FN_VI2_DATA3
, FN_GLO_Q0_B
, FN_TS_SDEN0_C
,
5857 /* IP10_24_22 [3] */
5858 FN_VI0_R1
, FN_VI2_DATA2
, FN_GLO_I1_B
, FN_TS_SCK0_C
, FN_ATAG1_N
,
5860 /* IP10_21_29 [3] */
5861 FN_VI0_R0
, FN_VI2_DATA1
, FN_GLO_I0_B
,
5862 FN_TS_SDATA0_C
, FN_ATACS11_N
,
5864 /* IP10_18_17 [2] */
5865 FN_VI0_G7
, FN_VI2_DATA0
, FN_FMIN_D
, 0,
5866 /* IP10_16_15 [2] */
5867 FN_VI0_G6
, FN_VI2_CLK
, FN_BPFCLK_D
, 0,
5868 /* IP10_14_12 [3] */
5869 FN_VI0_G5
, FN_VI2_FIELD
, FN_STP_OPWM_0_C
, FN_FMCLK_D
,
5870 FN_CAN0_TX_E
, FN_HTX1_D
, FN_SCIFB0_TXD_D
, 0,
5872 FN_VI0_G4
, FN_VI2_CLKENB
, FN_STP_ISSYNC_0_C
,
5873 FN_HTX2
, FN_SCIFB2_TXD
, FN_SCIFB0_SCK_D
,
5876 FN_VI0_G3
, FN_VI2_VSYNC_N
, FN_STP_ISEN_0_C
, FN_SDA3_B
,
5877 FN_HRX2
, FN_SCIFB2_RXD
, FN_ATACS01_N
, 0,
5879 FN_VI0_G2
, FN_VI2_HSYNC_N
, FN_STP_ISD_0_C
, FN_SCL3_B
,
5880 FN_HSCK2
, FN_SCIFB2_SCK
, FN_ATARD1_N
, 0,
5882 FN_VI0_G1
, FN_SDA8
, FN_STP_ISCLK_0_C
, FN_SDA4
,
5883 FN_HRTS2_N
, FN_SCIFB2_RTS_N
, FN_ATADIR1_N
, 0, }
5885 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
5886 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
5888 /* IP11_31_30 [2] */
5889 FN_ETH_CRS_DV
, FN_AVB_LINK
, FN_SDA2_C
, 0,
5890 /* IP11_29_28 [2] */
5891 FN_ETH_MDIO
, FN_AVB_RX_CLK
, FN_SCL2_C
, 0,
5893 FN_VI1_DATA7
, FN_AVB_MDC
,
5895 FN_VI1_DATA6
, FN_AVB_MAGIC
,
5897 FN_VI1_DATA5
, FN_AVB_RX_DV
,
5899 FN_VI1_DATA4
, FN_AVB_MDIO
,
5901 FN_VI1_DATA3
, FN_AVB_RX_ER
,
5903 FN_VI1_DATA2
, FN_AVB_RXD7
,
5905 FN_VI1_DATA1
, FN_AVB_RXD6
,
5907 FN_VI1_DATA0
, FN_AVB_RXD5
,
5909 FN_VI1_CLK
, FN_AVB_RXD4
,
5910 /* IP11_18_17 [2] */
5911 FN_VI1_FIELD
, FN_AVB_RXD3
, FN_TS_SPSYNC0_B
, 0,
5912 /* IP11_16_15 [2] */
5913 FN_VI1_CLKENB
, FN_AVB_RXD2
, FN_TS_SDEN0_B
, 0,
5914 /* IP11_14_12 [3] */
5915 FN_VI1_VSYNC_N
, FN_AVB_RXD1
, FN_TS_SCK0_B
,
5916 FN_RX4_B
, FN_SCIFA4_RXD_B
,
5919 FN_VI1_HSYNC_N
, FN_AVB_RXD0
, FN_TS_SDATA0_B
,
5920 FN_TX4_B
, FN_SCIFA4_TXD_B
,
5923 FN_VI0_R7
, FN_GLO_RFON_B
, FN_RX1_C
, FN_CAN0_RX_E
,
5924 FN_SDA4_B
, FN_HRX1_D
, FN_SCIFB0_RXD_D
, 0,
5926 FN_VI0_R6
, FN_VI2_DATA7
, FN_GLO_SS_B
, FN_TX1_C
, FN_SCL4_B
,
5929 FN_VI0_R5
, FN_VI2_DATA6
, FN_GLO_SDATA_B
, FN_RX0_C
, FN_SDA1_D
,
5932 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
5933 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
5934 /* IP12_31_30 [2] */
5936 /* IP12_29_27 [3] */
5937 FN_STP_ISCLK_0
, FN_AVB_TX_EN
, FN_SCIFB2_RXD_D
,
5938 FN_ADICS_SAMP_B
, FN_MSIOF0_SCK_C
,
5940 /* IP12_26_24 [3] */
5941 FN_STP_IVCXO27_0
, FN_AVB_TXD7
, FN_SCIFB2_TXD_D
,
5942 FN_ADIDATA_B
, FN_MSIOF0_SYNC_C
,
5944 /* IP12_23_22 [2] */
5945 FN_ETH_MDC
, FN_AVB_TXD6
, FN_IERX_C
, 0,
5946 /* IP12_21_20 [2] */
5947 FN_ETH_TXD0
, FN_AVB_TXD5
, FN_IECLK_C
, 0,
5948 /* IP12_19_18 [2] */
5949 FN_ETH_MAGIC
, FN_AVB_TXD4
, FN_IETX_C
, 0,
5950 /* IP12_17_16 [2] */
5951 FN_ETH_TX_EN
, FN_AVB_TXD3
, FN_TCLK1_B
, FN_CAN_CLK_B
,
5952 /* IP12_15_13 [3] */
5953 FN_ETH_TXD1
, FN_AVB_TXD2
, FN_SCIFA3_TXD_B
,
5954 FN_CAN1_TX_C
, FN_MSIOF1_TXD_E
,
5956 /* IP12_12_10 [3] */
5957 FN_ETH_REFCLK
, FN_AVB_TXD1
, FN_SCIFA3_RXD_B
,
5958 FN_CAN1_RX_C
, FN_MSIOF1_SYNC_E
,
5961 FN_ETH_LINK
, FN_AVB_TXD0
, FN_CAN0_RX_C
,
5962 FN_SDA2_D
, FN_MSIOF1_SCK_E
,
5965 FN_ETH_RXD1
, FN_AVB_GTXREFCLK
, FN_CAN0_TX_C
,
5966 FN_SCL2_D
, FN_MSIOF1_RXD_E
,
5969 FN_ETH_RXD0
, FN_AVB_PHY_INT
, FN_SDA3
, FN_SDA7
,
5971 FN_ETH_RX_ER
, FN_AVB_CRS
, FN_SCL3
, FN_SCL7
, }
5973 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5974 1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1,
5978 /* IP13_30_28 [3] */
5979 FN_SD1_CD
, FN_PWM0
, FN_TPU_TO0
, FN_SCL1_C
,
5982 FN_SD1_DATA3
, FN_IERX_B
,
5984 FN_SD1_DATA2
, FN_IECLK_B
,
5986 FN_SD1_DATA1
, FN_IETX_B
,
5987 /* IP13_24_23 [2] */
5988 FN_SD1_DATA0
, FN_SPEEDIN_B
, 0, 0,
5990 FN_SD1_CMD
, FN_REMOCON_B
,
5991 /* IP13_21_19 [3] */
5992 FN_SD0_WP
, FN_MMC_D7_B
, FN_SIM0_D_B
, FN_CAN0_TX_F
,
5993 FN_SCIFA5_RXD_B
, FN_RX3_C
,
5995 /* IP13_18_16 [3] */
5996 FN_SD0_CD
, FN_MMC_D6_B
, FN_SIM0_RST_B
, FN_CAN0_RX_F
,
5997 FN_SCIFA5_TXD_B
, FN_TX3_C
,
6000 FN_SD0_DATA3
, FN_SSL_B
,
6002 FN_SD0_DATA2
, FN_IO3_B
,
6004 FN_SD0_DATA1
, FN_IO2_B
,
6006 FN_SD0_DATA0
, FN_MISO_IO1_B
,
6008 FN_SD0_CMD
, FN_MOSI_IO0_B
,
6010 FN_SD0_CLK
, FN_SPCLK_B
,
6012 FN_STP_OPWM_0
, FN_AVB_GTX_CLK
, FN_PWM0_B
,
6013 FN_ADICHS2_B
, FN_MSIOF0_TXD_C
,
6016 FN_STP_ISSYNC_0
, FN_AVB_COL
, FN_ADICHS1_B
, FN_MSIOF0_RXD_C
,
6018 FN_STP_ISEN_0
, FN_AVB_TX_CLK
, FN_ADICHS0_B
, FN_MSIOF0_SS2_C
,
6020 FN_STP_ISD_0
, FN_AVB_TX_ER
, FN_SCIFB2_SCK_C
,
6021 FN_ADICLK_B
, FN_MSIOF0_SS1_C
,
6024 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
6025 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) {
6026 /* IP14_31_29 [3] */
6027 FN_MSIOF0_SS2
, FN_MMC_D7
, FN_ADICHS2
, FN_RX0_E
,
6028 FN_VI1_VSYNC_N_C
, FN_SDA7_C
, FN_VI1_G5_B
, 0,
6029 /* IP14_28_26 [3] */
6030 FN_MSIOF0_SS1
, FN_MMC_D6
, FN_ADICHS1
, FN_TX0_E
,
6031 FN_VI1_HSYNC_N_C
, FN_SCL7_C
, FN_VI1_G4_B
, 0,
6032 /* IP14_25_23 [3] */
6033 FN_MSIOF0_RXD
, FN_ADICHS0
, 0, FN_VI1_DATA0_C
, FN_VI1_G3_B
,
6035 /* IP14_22_20 [3] */
6036 FN_MSIOF0_TXD
, FN_ADICLK
, 0, FN_VI1_FIELD_C
, FN_VI1_G2_B
,
6038 /* IP14_19_17 [3] */
6039 FN_MSIOF0_SYNC
, FN_TX2_C
, FN_ADICS_SAMP
, 0,
6040 FN_VI1_CLKENB_C
, FN_VI1_G1_B
,
6042 /* IP14_16_14 [3] */
6043 FN_MSIOF0_SCK
, FN_RX2_C
, FN_ADIDATA
, 0,
6044 FN_VI1_CLK_C
, FN_VI1_G0_B
,
6046 /* IP14_13_11 [3] */
6047 FN_SD2_WP
, FN_MMC_D5
, FN_SDA8_C
, FN_RX5_B
, FN_SCIFA5_RXD_C
,
6050 FN_SD2_CD
, FN_MMC_D4
, FN_SCL8_C
, FN_TX5_B
, FN_SCIFA5_TXD_C
,
6053 FN_SD2_DATA3
, FN_MMC_D3
,
6055 FN_SD2_DATA2
, FN_MMC_D2
,
6057 FN_SD2_DATA1
, FN_MMC_D1
,
6059 FN_SD2_DATA0
, FN_MMC_D0
,
6061 FN_SD2_CMD
, FN_MMC_CMD
,
6063 FN_SD2_CLK
, FN_MMC_CLK
,
6065 FN_SD1_WP
, FN_PWM1_B
, FN_SDA1_C
, 0, }
6067 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
6068 2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) {
6069 /* IP15_31_30 [2] */
6071 /* IP15_29_27 [3] */
6072 FN_HTX0
, FN_SCIFB0_TXD
, 0, FN_GLO_SCLK_C
,
6073 FN_CAN0_TX_B
, FN_VI1_DATA5_C
,
6075 /* IP15_26_24 [3] */
6076 FN_HRX0
, FN_SCIFB0_RXD
, 0, FN_GLO_Q1_C
,
6077 FN_CAN0_RX_B
, FN_VI1_DATA4_C
,
6079 /* IP15_23_21 [3] */
6080 FN_HSCK0
, FN_SCIFB0_SCK
, 0, FN_GLO_Q0_C
, FN_CAN_CLK
,
6081 FN_TCLK2
, FN_VI1_DATA3_C
, 0,
6082 /* IP15_20_18 [3] */
6083 FN_HRTS0_N
, FN_SCIFB0_RTS_N
, 0, FN_GLO_I1_C
, FN_VI1_DATA2_C
,
6085 /* IP15_17_15 [3] */
6086 FN_HCTS0_N
, FN_SCIFB0_CTS_N
, 0, FN_GLO_I0_C
,
6087 FN_TCLK1
, FN_VI1_DATA1_C
,
6089 /* IP15_14_12 [3] */
6090 FN_GPS_MAG
, FN_RX4_C
, FN_SCIFA4_RXD_C
, FN_PWM6
,
6091 FN_VI1_G7_B
, FN_SCIFA3_SCK_C
,
6094 FN_GPS_SIGN
, FN_TX4_C
, FN_SCIFA4_TXD_C
, FN_PWM5
,
6095 FN_VI1_G6_B
, FN_SCIFA3_RXD_C
,
6098 FN_GPS_CLK
, FN_DU1_DOTCLKIN_C
, FN_AUDIO_CLKB_B
,
6099 FN_PWM5_B
, FN_SCIFA3_TXD_C
,
6102 FN_SIM0_D
, FN_IERX
, FN_CAN1_RX_D
, 0,
6104 FN_SIM0_CLK
, FN_IECLK
, FN_CAN_CLK_C
, 0,
6106 FN_SIM0_RST
, FN_IETX
, FN_CAN1_TX_D
, 0, }
6108 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
6109 4, 4, 4, 4, 4, 2, 2, 2, 3, 3) {
6110 /* IP16_31_28 [4] */
6111 0, 0, 0, 0, 0, 0, 0, 0,
6112 0, 0, 0, 0, 0, 0, 0, 0,
6113 /* IP16_27_24 [4] */
6114 0, 0, 0, 0, 0, 0, 0, 0,
6115 0, 0, 0, 0, 0, 0, 0, 0,
6116 /* IP16_23_20 [4] */
6117 0, 0, 0, 0, 0, 0, 0, 0,
6118 0, 0, 0, 0, 0, 0, 0, 0,
6119 /* IP16_19_16 [4] */
6120 0, 0, 0, 0, 0, 0, 0, 0,
6121 0, 0, 0, 0, 0, 0, 0, 0,
6122 /* IP16_15_12 [4] */
6123 0, 0, 0, 0, 0, 0, 0, 0,
6124 0, 0, 0, 0, 0, 0, 0, 0,
6125 /* IP16_11_10 [2] */
6126 FN_HRTS1_N
, FN_SCIFB1_RTS_N
, FN_MLB_DAT
, FN_CAN1_RX_B
,
6128 FN_HCTS1_N
, FN_SCIFB1_CTS_N
, FN_MLB_SIG
, FN_CAN1_TX_B
,
6130 FN_HSCK1
, FN_SCIFB1_SCK
, FN_MLB_CLK
, FN_GLO_RFON_C
,
6132 FN_HTX1
, FN_SCIFB1_TXD
, FN_VI1_R1_B
,
6133 FN_GLO_SS_C
, FN_VI1_DATA7_C
,
6136 FN_HRX1
, FN_SCIFB1_RXD
, FN_VI1_R0_B
,
6137 FN_GLO_SDATA_C
, FN_VI1_DATA6_C
,
6140 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
6141 1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
6142 3, 2, 2, 2, 1, 2, 2, 2) {
6146 FN_SEL_SCIF1_0
, FN_SEL_SCIF1_1
, FN_SEL_SCIF1_2
, FN_SEL_SCIF1_3
,
6148 FN_SEL_SCIFB_0
, FN_SEL_SCIFB_1
, FN_SEL_SCIFB_2
, FN_SEL_SCIFB_3
,
6149 /* SEL_SCIFB2 [2] */
6150 FN_SEL_SCIFB2_0
, FN_SEL_SCIFB2_1
,
6151 FN_SEL_SCIFB2_2
, FN_SEL_SCIFB2_3
,
6152 /* SEL_SCIFB1 [3] */
6153 FN_SEL_SCIFB1_0
, FN_SEL_SCIFB1_1
,
6154 FN_SEL_SCIFB1_2
, FN_SEL_SCIFB1_3
,
6156 /* SEL_SCIFA1 [2] */
6157 FN_SEL_SCIFA1_0
, FN_SEL_SCIFA1_1
, FN_SEL_SCIFA1_2
, 0,
6159 FN_SEL_SSI9_0
, FN_SEL_SSI9_1
,
6161 FN_SEL_SCFA_0
, FN_SEL_SCFA_1
,
6163 FN_SEL_QSP_0
, FN_SEL_QSP_1
,
6165 FN_SEL_SSI7_0
, FN_SEL_SSI7_1
,
6166 /* SEL_HSCIF1 [3] */
6167 FN_SEL_HSCIF1_0
, FN_SEL_HSCIF1_1
, FN_SEL_HSCIF1_2
,
6168 FN_SEL_HSCIF1_3
, FN_SEL_HSCIF1_4
,
6173 FN_SEL_VI1_0
, FN_SEL_VI1_1
, FN_SEL_VI1_2
, 0,
6177 FN_SEL_TMU1_0
, FN_SEL_TMU1_1
,
6179 FN_SEL_LBS_0
, FN_SEL_LBS_1
, FN_SEL_LBS_2
, FN_SEL_LBS_3
,
6181 FN_SEL_TSIF0_0
, FN_SEL_TSIF0_1
, FN_SEL_TSIF0_2
, FN_SEL_TSIF0_3
,
6183 FN_SEL_SOF0_0
, FN_SEL_SOF0_1
, FN_SEL_SOF0_2
, 0, }
6185 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
6186 3, 1, 1, 3, 2, 1, 1, 2, 2,
6187 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
6189 FN_SEL_SCIF0_0
, FN_SEL_SCIF0_1
, FN_SEL_SCIF0_2
,
6190 FN_SEL_SCIF0_3
, FN_SEL_SCIF0_4
,
6195 FN_SEL_SCIF_0
, FN_SEL_SCIF_1
,
6197 FN_SEL_CAN0_0
, FN_SEL_CAN0_1
, FN_SEL_CAN0_2
, FN_SEL_CAN0_3
,
6198 FN_SEL_CAN0_4
, FN_SEL_CAN0_5
,
6201 FN_SEL_CAN1_0
, FN_SEL_CAN1_1
, FN_SEL_CAN1_2
, FN_SEL_CAN1_3
,
6204 /* SEL_SCIFA2 [1] */
6205 FN_SEL_SCIFA2_0
, FN_SEL_SCIFA2_1
,
6207 FN_SEL_SCIF4_0
, FN_SEL_SCIF4_1
, FN_SEL_SCIF4_2
, 0,
6211 FN_SEL_ADG_0
, FN_SEL_ADG_1
,
6213 FN_SEL_FM_0
, FN_SEL_FM_1
, FN_SEL_FM_2
,
6214 FN_SEL_FM_3
, FN_SEL_FM_4
,
6216 /* SEL_SCIFA5 [2] */
6217 FN_SEL_SCIFA5_0
, FN_SEL_SCIFA5_1
, FN_SEL_SCIFA5_2
, 0,
6221 FN_SEL_GPS_0
, FN_SEL_GPS_1
, FN_SEL_GPS_2
, FN_SEL_GPS_3
,
6222 /* SEL_SCIFA4 [2] */
6223 FN_SEL_SCIFA4_0
, FN_SEL_SCIFA4_1
, FN_SEL_SCIFA4_2
, 0,
6224 /* SEL_SCIFA3 [2] */
6225 FN_SEL_SCIFA3_0
, FN_SEL_SCIFA3_1
, FN_SEL_SCIFA3_2
, 0,
6227 FN_SEL_SIM_0
, FN_SEL_SIM_1
,
6231 FN_SEL_SSI8_0
, FN_SEL_SSI8_1
, }
6233 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
6234 2, 2, 2, 2, 2, 2, 2, 2,
6235 1, 1, 2, 2, 3, 2, 2, 2, 1) {
6236 /* SEL_HSCIF2 [2] */
6237 FN_SEL_HSCIF2_0
, FN_SEL_HSCIF2_1
,
6238 FN_SEL_HSCIF2_2
, FN_SEL_HSCIF2_3
,
6239 /* SEL_CANCLK [2] */
6240 FN_SEL_CANCLK_0
, FN_SEL_CANCLK_1
,
6241 FN_SEL_CANCLK_2
, FN_SEL_CANCLK_3
,
6243 FN_SEL_IIC8_0
, FN_SEL_IIC8_1
, FN_SEL_IIC8_2
, 0,
6245 FN_SEL_IIC7_0
, FN_SEL_IIC7_1
, FN_SEL_IIC7_2
, 0,
6247 FN_SEL_IIC4_0
, FN_SEL_IIC4_1
, FN_SEL_IIC4_2
, 0,
6249 FN_SEL_IIC3_0
, FN_SEL_IIC3_1
, FN_SEL_IIC3_2
, FN_SEL_IIC3_3
,
6251 FN_SEL_SCIF3_0
, FN_SEL_SCIF3_1
, FN_SEL_SCIF3_2
, FN_SEL_SCIF3_3
,
6253 FN_SEL_IEB_0
, FN_SEL_IEB_1
, FN_SEL_IEB_2
, 0,
6255 FN_SEL_MMC_0
, FN_SEL_MMC_1
,
6257 FN_SEL_SCIF5_0
, FN_SEL_SCIF5_1
,
6261 FN_SEL_IIC2_0
, FN_SEL_IIC2_1
, FN_SEL_IIC2_2
, FN_SEL_IIC2_3
,
6263 FN_SEL_IIC1_0
, FN_SEL_IIC1_1
, FN_SEL_IIC1_2
, FN_SEL_IIC1_3
,
6267 FN_SEL_IIC0_0
, FN_SEL_IIC0_1
, FN_SEL_IIC0_2
, 0,
6275 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
6276 3, 2, 2, 1, 1, 1, 1, 3, 2,
6277 2, 3, 1, 1, 1, 2, 2, 2, 2) {
6279 FN_SEL_SOF1_0
, FN_SEL_SOF1_1
, FN_SEL_SOF1_2
, FN_SEL_SOF1_3
,
6282 /* SEL_HSCIF0 [2] */
6283 FN_SEL_HSCIF0_0
, FN_SEL_HSCIF0_1
, FN_SEL_HSCIF0_2
, 0,
6285 FN_SEL_DIS_0
, FN_SEL_DIS_1
, FN_SEL_DIS_2
, 0,
6289 FN_SEL_RAD_0
, FN_SEL_RAD_1
,
6291 FN_SEL_RCN_0
, FN_SEL_RCN_1
,
6293 FN_SEL_RSP_0
, FN_SEL_RSP_1
,
6295 FN_SEL_SCIF2_0
, FN_SEL_SCIF2_1
, FN_SEL_SCIF2_2
,
6296 FN_SEL_SCIF2_3
, FN_SEL_SCIF2_4
,
6303 FN_SEL_SOF2_0
, FN_SEL_SOF2_1
, FN_SEL_SOF2_2
,
6304 FN_SEL_SOF2_3
, FN_SEL_SOF2_4
,
6309 FN_SEL_SSI1_0
, FN_SEL_SSI1_1
,
6311 FN_SEL_SSI0_0
, FN_SEL_SSI0_1
,
6313 FN_SEL_SSP_0
, FN_SEL_SSP_1
, FN_SEL_SSP_2
, 0,
6324 #ifdef CONFIG_PINCTRL_PFC_R8A7791
6325 const struct sh_pfc_soc_info r8a7791_pinmux_info
= {
6326 .name
= "r8a77910_pfc",
6327 .unlock_reg
= 0xe6060000, /* PMMR */
6329 .function
= { PINMUX_FUNCTION_BEGIN
, PINMUX_FUNCTION_END
},
6331 .pins
= pinmux_pins
,
6332 .nr_pins
= ARRAY_SIZE(pinmux_pins
),
6333 .groups
= pinmux_groups
,
6334 .nr_groups
= ARRAY_SIZE(pinmux_groups
),
6335 .functions
= pinmux_functions
,
6336 .nr_functions
= ARRAY_SIZE(pinmux_functions
),
6338 .cfg_regs
= pinmux_config_regs
,
6340 .gpio_data
= pinmux_data
,
6341 .gpio_data_size
= ARRAY_SIZE(pinmux_data
),
6345 #ifdef CONFIG_PINCTRL_PFC_R8A7793
6346 const struct sh_pfc_soc_info r8a7793_pinmux_info
= {
6347 .name
= "r8a77930_pfc",
6348 .unlock_reg
= 0xe6060000, /* PMMR */
6350 .function
= { PINMUX_FUNCTION_BEGIN
, PINMUX_FUNCTION_END
},
6352 .pins
= pinmux_pins
,
6353 .nr_pins
= ARRAY_SIZE(pinmux_pins
),
6354 .groups
= pinmux_groups
,
6355 .nr_groups
= ARRAY_SIZE(pinmux_groups
),
6356 .functions
= pinmux_functions
,
6357 .nr_functions
= ARRAY_SIZE(pinmux_functions
),
6359 .cfg_regs
= pinmux_config_regs
,
6361 .gpio_data
= pinmux_data
,
6362 .gpio_data_size
= ARRAY_SIZE(pinmux_data
),