drivers/pinctrl/sh-pfc/pfc-r8a7794.c

   1 /*
   2  * r8a7794 processor support - PFC hardware block.
   3  *
   4  * Copyright (C) 2014-2015 Renesas Electronics Corporation
   5  * Copyright (C) 2015 Renesas Solutions Corp.
   6  * Copyright (C) 2015-2016 Cogent Embedded, Inc., <source@cogentembedded.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2
  10  * as published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/kernel.h>
  14
  15 #include "core.h"
  16 #include "sh_pfc.h"
  17
  18 #define CPU_ALL_PORT(fn, sfx)                                           \
  19         PORT_GP_32(0, fn, sfx),                                         \
  20         PORT_GP_26(1, fn, sfx),                                         \
  21         PORT_GP_32(2, fn, sfx),                                         \
  22         PORT_GP_32(3, fn, sfx),                                         \
  23         PORT_GP_32(4, fn, sfx),                                         \
  24         PORT_GP_28(5, fn, sfx),                                         \
  25         PORT_GP_26(6, fn, sfx)
  26
  27 enum {
  28         PINMUX_RESERVED = 0,
  29
  30         PINMUX_DATA_BEGIN,
  31         GP_ALL(DATA),
  32         PINMUX_DATA_END,
  33
  34         PINMUX_FUNCTION_BEGIN,
  35         GP_ALL(FN),
  36
  37         /* GPSR0 */
  38         FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28,
  39         FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6,
  40         FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18,
  41         FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27,
  42         FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4,
  43         FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14,
  44         FN_IP2_17_16,
  45
  46         /* GPSR1 */
  47         FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30,
  48         FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10,
  49         FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18,
  50         FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31,
  51         FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0,
  52
  53         /* GPSR2 */
  54         FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12,
  55         FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23,
  56         FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2,
  57         FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14,
  58         FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24,
  59         FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2,
  60         FN_IP6_5_4, FN_IP6_7_6,
  61
  62         /* GPSR3 */
  63         FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13,
  64         FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20,
  65         FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3,
  66         FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
  67         FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3,
  68         FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17,
  69         FN_IP8_22_20,
  70
  71         /* GPSR4 */
  72         FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3,
  73         FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17,
  74         FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0,
  75         FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
  76         FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27,
  77         FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8,
  78         FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16,
  79
  80         /* GPSR5 */
  81         FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
  82         FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13,
  83         FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24,
  84         FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9,
  85         FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21,
  86         FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC,
  87
  88         /* GPSR6 */
  89         FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2,
  90         FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD,
  91         FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0,
  92         FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
  93         FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
  94
  95         /* IPSR0 */
  96         FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK,
  97         FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1,
  98         FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3,
  99         FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD,
 100         FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B,
 101         FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B,
 102         FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4,
 103         FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D,
 104
 105         /* IPSR1 */
 106         FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, FN_D7, FN_IRQ3, FN_TCLK1,
 107         FN_PWM6_B, FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, FN_D9, FN_HSCIF2_HTX,
 108         FN_I2C1_SDA_B, FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6,
 109         FN_PWM5_C, FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
 110         FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D, FN_D13,
 111         FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B, FN_D14, FN_SCIFA1_RXD,
 112         FN_IIC0_SCL_B, FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B, FN_A0,
 113         FN_SCIFB1_SCK, FN_PWM3_B, FN_A1, FN_SCIFB1_TXD, FN_A3, FN_SCIFB0_SCK,
 114         FN_A4, FN_SCIFB0_TXD, FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
 115         FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
 116
 117         /* IPSR2 */
 118         FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, FN_A8, FN_MSIOF1_RXD,
 119         FN_SCIFA0_RXD_B, FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, FN_A10,
 120         FN_MSIOF1_SCK, FN_IIC1_SCL_B, FN_A11, FN_MSIOF1_SYNC, FN_IIC1_SDA_B,
 121         FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, FN_A13, FN_MSIOF1_SS2,
 122         FN_SCIFA5_TXD_B, FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
 123         FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, FN_A16,
 124         FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_VSP, FN_CAN_CLK_C,
 125         FN_TPUTO2_B, FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
 126         FN_AVB_AVTP_CAPTURE_B, FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E,
 127         FN_CAN1_TX_B, FN_AVB_AVTP_MATCH_B, FN_A19, FN_MSIOF2_SS2, FN_PWM4,
 128         FN_TPUTO2, FN_MOUT0, FN_A20, FN_SPCLK, FN_MOUT1,
 129
 130         /* IPSR3 */
 131         FN_A21, FN_MOSI_IO0, FN_MOUT2, FN_A22, FN_MISO_IO1, FN_MOUT5,
 132         FN_ATADIR1_N, FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N, FN_A24, FN_IO3,
 133         FN_EX_WAIT2, FN_A25, FN_SSL, FN_ATARD1_N, FN_CS0_N, FN_VI1_DATA8,
 134         FN_CS1_N_A26, FN_VI1_DATA9, FN_EX_CS0_N, FN_VI1_DATA10, FN_EX_CS1_N,
 135         FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11, FN_EX_CS2_N, FN_PWM0,
 136         FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD,
 137         FN_SDATA_B, FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
 138         FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B, FN_EX_CS4_N,
 139         FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_RIF0_D0, FN_FMCLK,
 140         FN_SCIFB2_CTS_N, FN_SCKZ_B, FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E,
 141         FN_TS_SPSYNC_B, FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B,
 142         FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N, FN_MTS_N_B,
 143         FN_RD_N, FN_ATACS11_N, FN_RD_WR_N, FN_ATAG1_N,
 144
 145         /* IPSR4 */
 146         FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, FN_DU0_DR0,
 147         FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, FN_CC50_STATE0,
 148         FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D, FN_CC50_STATE1,
 149         FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, FN_DU0_DR3, FN_LCDOUT19,
 150         FN_CC50_STATE3, FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, FN_DU0_DR5,
 151         FN_LCDOUT21, FN_CC50_STATE5, FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6,
 152         FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, FN_DU0_DG0, FN_LCDOUT8,
 153         FN_SCIFA0_RXD_C, FN_I2C3_SCL_D, FN_CC50_STATE8, FN_DU0_DG1, FN_LCDOUT9,
 154         FN_SCIFA0_TXD_C, FN_I2C3_SDA_D, FN_CC50_STATE9, FN_DU0_DG2, FN_LCDOUT10,
 155         FN_CC50_STATE10, FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, FN_DU0_DG4,
 156         FN_LCDOUT12, FN_CC50_STATE12,
 157
 158         /* IPSR5 */
 159         FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, FN_DU0_DG6, FN_LCDOUT14,
 160         FN_CC50_STATE14, FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, FN_DU0_DB0,
 161         FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C,
 162         FN_CC50_STATE16, FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
 163         FN_CAN0_TX_C, FN_CC50_STATE17, FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18,
 164         FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, FN_DU0_DB4, FN_LCDOUT4,
 165         FN_CC50_STATE20, FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, FN_DU0_DB6,
 166         FN_LCDOUT6, FN_CC50_STATE22, FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23,
 167         FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, FN_DU0_DOTCLKOUT0,
 168         FN_QCLK, FN_CC50_STATE25, FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE,
 169         FN_CC50_STATE26, FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27,
 170
 171         /* IPSR6 */
 172         FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28,
 173         FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
 174         FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, FN_DU0_CDE, FN_QPOLB,
 175         FN_CC50_STATE31, FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0,
 176         FN_AVB_RX_DV, FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, FN_VI0_DATA2_VI0_B2,
 177         FN_AVB_RXD1, FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, FN_VI0_DATA4_VI0_B4,
 178         FN_AVB_RXD3, FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, FN_VI0_DATA6_VI0_B6,
 179         FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, FN_VI0_CLKENB,
 180         FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, FN_VI0_FIELD,
 181         FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, FN_VI0_HSYNC_N,
 182         FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, FN_VI0_VSYNC_N,
 183         FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN,
 184         FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, FN_AVB_TX_CLK,
 185         FN_ADIDATA, FN_AD_DI,
 186
 187         /* IPSR7 */
 188         FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, FN_AVB_TXD0,
 189         FN_ADICS_SAMP, FN_AD_DO, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B,
 190         FN_CAN0_RX_B, FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, FN_ETH_RXD0, FN_VI0_G3,
 191         FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N,
 192         FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
 193         FN_ADICHS1, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
 194         FN_AVB_TXD4, FN_ADICHS2, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C,
 195         FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C,
 196         FN_IIC1_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0,
 197         FN_SCIF2_TXD_C, FN_IIC1_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B,
 198         FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B,
 199         FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK,
 200         FN_SSI_WS6_B, FN_DREQ0_N, FN_SCIFB1_RXD,
 201
 202         /* IPSR8 */
 203         FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC,
 204         FN_SSI_SDATA6_B, FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C,
 205         FN_AUDIO_CLKA_B, FN_AVB_MDIO, FN_SSI_SCK78_B, FN_HSCIF0_HTX,
 206         FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK, FN_SSI_WS78_B,
 207         FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
 208         FN_AVB_MAGIC, FN_SSI_SDATA7_B, FN_HSCIF0_HRTS_N, FN_VI0_R7,
 209         FN_SCIF0_TXD_D, FN_I2C0_SDA_E, FN_AVB_PHY_INT, FN_SSI_SDATA8_B,
 210         FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
 211         FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
 212         FN_CAN1_RX_D, FN_TPUTO0_B, FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0,
 213         FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, FN_I2C1_SCL, FN_SCIF4_RXD,
 214         FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B,
 215         FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_RIF1_CLK_B,
 216         FN_TS_SCK_D, FN_BPFCLK_C, FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C,
 217         FN_DU1_DR2, FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
 218
 219         /* IPSR9 */
 220         FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_RIF1_D1_B,
 221         FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, FN_MSIOF0_SCK, FN_IRQ0,
 222         FN_TS_SDATA, FN_DU1_DR4, FN_RIF1_SYNC, FN_TPUTO1_C, FN_MSIOF0_SYNC,
 223         FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_RIF1_CLK, FN_BPFCLK_B, FN_MSIOF0_SS1,
 224         FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_RIF1_D0, FN_FMCLK_B,
 225         FN_RDS_CLK_B, FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
 226         FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, FN_HSCIF1_HRX, FN_I2C4_SCL,
 227         FN_PWM6, FN_DU1_DG0, FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
 228         FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B,
 229         FN_SPEEDIN_B, FN_VSP_B, FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK,
 230         FN_DU1_DG3, FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32,
 231         FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B,
 232         FN_CAN_STEP0, FN_CC50_STATE33, FN_SCIF1_SCK, FN_PWM3, FN_TCLK2,
 233         FN_DU1_DG5, FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34,
 234
 235         /* IPSR10 */
 236         FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, FN_CAN_DEBUGOUT0,
 237         FN_CC50_STATE35, FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
 238         FN_CAN_DEBUGOUT1, FN_CC50_STATE36, FN_SCIF2_RXD, FN_IIC1_SCL,
 239         FN_DU1_DB0, FN_SSI_SDATA2_B, FN_USB0_EXTLP, FN_CAN_DEBUGOUT2,
 240         FN_CC50_STATE37, FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
 241         FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, FN_SCIF2_SCK, FN_IRQ1,
 242         FN_DU1_DB2, FN_SSI_WS9_B, FN_USB0_IDIN, FN_CAN_DEBUGOUT4,
 243         FN_CC50_STATE39, FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
 244         FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT,
 245         FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C,
 246         FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C, FN_SCIF3_TXD,
 247         FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C, FN_SSI_WS4_B,
 248         FN_CAN_DEBUGOUT7, FN_RDS_DATA_C, FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6,
 249         FN_AUDIO_CLKC_C, FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, FN_I2C2_SDA,
 250         FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, FN_CAN_DEBUGOUT9,
 251         FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10,
 252
 253         /* IPSR11 */
 254         FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
 255         FN_CAN_DEBUGOUT11, FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C,
 256         FN_DU1_DOTCLKOUT1, FN_CAN_DEBUGOUT12, FN_SSI_SCK6, FN_SCIFA1_SCK_B,
 257         FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13, FN_SSI_WS6,
 258         FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
 259         FN_CAN_DEBUGOUT14, FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
 260         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, FN_SSI_SCK78,
 261         FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, FN_SSI_WS78,
 262         FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7,
 263         FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_PCMOE_N,
 264         FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
 265         FN_AD_DI_B, FN_PCMWE_N, FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D,
 266         FN_ADICS_SAMP_B, FN_AD_DO_B, FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B,
 267         FN_ADICLK_B, FN_AD_CLK_B,
 268
 269         /* IPSR12 */
 270         FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
 271         FN_AD_NCS_N_B, FN_DREQ1_N_B, FN_SSI_WS34, FN_MSIOF1_SS1_B,
 272         FN_SCIFA1_RXD_C, FN_ADICHS1_B, FN_CAN1_RX_C, FN_DACK1_B, FN_SSI_SDATA3,
 273         FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B, FN_CAN1_TX_C,
 274         FN_DREQ2_N, FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX, FN_SSI_WS4,
 275         FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX, FN_SSI_SDATA4, FN_MLB_DAT,
 276         FN_IERX_B, FN_IRD_SCK, FN_SSI_SDATA8, FN_SCIF1_SCK_B,
 277         FN_PWM1_B, FN_IRQ9, FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, FN_SSI_SCK1,
 278         FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D,
 279         FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, FN_SSI_WS1, FN_SCIF1_TXD_B,
 280         FN_IIC1_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH,
 281         FN_ETH_RX_ER_B, FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_SDATA, FN_VI1_DATA1,
 282         FN_ATAG0_N, FN_ETH_RXD0_B, FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2,
 283         FN_MDATA, FN_ATAWR0_N, FN_ETH_RXD1_B,
 284
 285         /* IPSR13 */
 286         FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, FN_SCKZ,
 287         FN_ATACS00_N, FN_ETH_LINK_B, FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B,
 288         FN_SCIFA0_TXD_D, FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B,
 289         FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_MTS_N,
 290         FN_EX_WAIT1, FN_ETH_TXD1_B, FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E,
 291         FN_VI1_DATA6, FN_ATARD0_N, FN_ETH_TX_EN_B, FN_SSI_SDATA9,
 292         FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7, FN_ATADIR0_N,
 293         FN_ETH_MAGIC_B, FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D,
 294         FN_VI1_CLKENB, FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B,
 295         FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
 296         FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B, FN_AUDIO_CLKC,
 297         FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N, FN_TS_SDEN_C,
 298         FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D, FN_AUDIO_CLKOUT, FN_I2C4_SDA_B,
 299         FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, FN_TS_SPSYNC_C, FN_RIF0_D1_B,
 300         FN_FMIN_E, FN_RDS_DATA_D,
 301
 302         /* MOD_SEL */
 303         FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
 304         FN_SEL_ADI_0, FN_SEL_ADI_1, FN_SEL_CAN_0, FN_SEL_CAN_1,
 305         FN_SEL_CAN_2, FN_SEL_CAN_3, FN_SEL_DARC_0, FN_SEL_DARC_1,
 306         FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, FN_SEL_DR0_0,
 307         FN_SEL_DR0_1, FN_SEL_DR1_0, FN_SEL_DR1_1, FN_SEL_DR2_0, FN_SEL_DR2_1,
 308         FN_SEL_DR3_0, FN_SEL_DR3_1, FN_SEL_ETH_0, FN_SEL_ETH_1, FN_SEL_FSN_0,
 309         FN_SEL_FSN_1, FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2,
 310         FN_SEL_I2C00_3, FN_SEL_I2C00_4, FN_SEL_I2C01_0, FN_SEL_I2C01_1,
 311         FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, FN_SEL_I2C02_0,
 312         FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, FN_SEL_I2C02_4,
 313         FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
 314         FN_SEL_I2C03_4, FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2,
 315         FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_IIC00_0, FN_SEL_IIC00_1,
 316         FN_SEL_IIC00_2, FN_SEL_IIC00_3, FN_SEL_AVB_0, FN_SEL_AVB_1,
 317
 318         /* MOD_SEL2 */
 319         FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC01_0,
 320         FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, FN_SEL_LBS_0,
 321         FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0,
 322         FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, FN_SEL_RCN_0,
 323         FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0,
 324         FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, FN_SEL_SCIFA1_0,
 325         FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
 326         FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1,
 327         FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1,
 328         FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, FN_SEL_SPDM_0, FN_SEL_SPDM_1,
 329         FN_SEL_TMU_0, FN_SEL_TMU_1, FN_SEL_TSIF0_0, FN_SEL_TSIF0_1,
 330         FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, FN_SEL_CAN0_0, FN_SEL_CAN0_1,
 331         FN_SEL_CAN0_2, FN_SEL_CAN0_3, FN_SEL_CAN1_0, FN_SEL_CAN1_1,
 332         FN_SEL_CAN1_2, FN_SEL_CAN1_3, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
 333         FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_RDS_0, FN_SEL_RDS_1,
 334         FN_SEL_RDS_2, FN_SEL_RDS_3,
 335
 336         /* MOD_SEL3 */
 337         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
 338         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0,
 339         FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
 340         FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
 341         FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2,
 342         FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0,
 343         FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0,
 344         FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0,
 345         FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0,
 346         FN_SEL_SSI9_1,
 347         PINMUX_FUNCTION_END,
 348
 349         PINMUX_MARK_BEGIN,
 350         A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK,
 351
 352         USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
 353
 354         SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK,
 355         SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK,
 356
 357         SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
 358         SD1_DATA2_MARK, SD1_DATA3_MARK,
 359
 360         /* IPSR0 */
 361         SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK,
 362         MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK,
 363         SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK,
 364         SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK,
 365         MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK,
 366         CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK,
 367         CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK,
 368         SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK,
 369         SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK,
 370         SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK,
 371
 372         /* IPSR1 */
 373         D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK, D7_MARK, IRQ3_MARK,
 374         TCLK1_MARK, PWM6_B_MARK, D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK,
 375         D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK, D10_MARK,
 376         HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
 377         D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK,
 378         D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK,
 379         D13_MARK, SCIFA1_SCK_MARK, TANS1_MARK, PWM2_C_MARK, TCLK2_B_MARK,
 380         D14_MARK, SCIFA1_RXD_MARK, IIC0_SCL_B_MARK, D15_MARK, SCIFA1_TXD_MARK,
 381         IIC0_SDA_B_MARK, A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK, A1_MARK,
 382         SCIFB1_TXD_MARK, A3_MARK, SCIFB0_SCK_MARK, A4_MARK, SCIFB0_TXD_MARK,
 383         A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK, A6_MARK,
 384         SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK,
 385
 386         /* IPSR2 */
 387         A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK, A8_MARK, MSIOF1_RXD_MARK,
 388         SCIFA0_RXD_B_MARK, A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK,
 389         A10_MARK, MSIOF1_SCK_MARK, IIC1_SCL_B_MARK, A11_MARK, MSIOF1_SYNC_MARK,
 390         IIC1_SDA_B_MARK, A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK,
 391         A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK, A14_MARK, MSIOF2_RXD_MARK,
 392         HSCIF0_HRX_B_MARK, DREQ1_N_MARK, A15_MARK, MSIOF2_TXD_MARK,
 393         HSCIF0_HTX_B_MARK, DACK1_MARK, A16_MARK, MSIOF2_SCK_MARK,
 394         HSCIF0_HSCK_B_MARK, SPEEDIN_MARK, VSP_MARK, CAN_CLK_C_MARK,
 395         TPUTO2_B_MARK, A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK,
 396         CAN1_RX_B_MARK, AVB_AVTP_CAPTURE_B_MARK, A18_MARK, MSIOF2_SS1_MARK,
 397         SCIF4_TXD_E_MARK, CAN1_TX_B_MARK, AVB_AVTP_MATCH_B_MARK, A19_MARK,
 398         MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK, MOUT0_MARK, A20_MARK,
 399         SPCLK_MARK, MOUT1_MARK,
 400
 401         /* IPSR3 */
 402         A21_MARK, MOSI_IO0_MARK, MOUT2_MARK, A22_MARK, MISO_IO1_MARK,
 403         MOUT5_MARK, ATADIR1_N_MARK, A23_MARK, IO2_MARK, MOUT6_MARK,
 404         ATAWR1_N_MARK, A24_MARK, IO3_MARK, EX_WAIT2_MARK, A25_MARK, SSL_MARK,
 405         ATARD1_N_MARK, CS0_N_MARK, VI1_DATA8_MARK, CS1_N_A26_MARK,
 406         VI1_DATA9_MARK, EX_CS0_N_MARK, VI1_DATA10_MARK, EX_CS1_N_MARK,
 407         TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK, EX_CS2_N_MARK,
 408         PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK, RIF0_SYNC_MARK,
 409         TPUTO3_MARK, SCIFB2_TXD_MARK, SDATA_B_MARK, EX_CS3_N_MARK,
 410         SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK, RIF0_CLK_MARK,
 411         BPFCLK_MARK, SCIFB2_SCK_MARK, MDATA_B_MARK, EX_CS4_N_MARK,
 412         SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK, RIF0_D0_MARK,
 413         FMCLK_MARK, SCIFB2_CTS_N_MARK, SCKZ_B_MARK, EX_CS5_N_MARK,
 414         SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK, RIF0_D1_MARK,
 415         FMIN_MARK, SCIFB2_RTS_N_MARK, STM_N_B_MARK, BS_N_MARK, DRACK0_MARK,
 416         PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK, MTS_N_B_MARK, RD_N_MARK,
 417         ATACS11_N_MARK, RD_WR_N_MARK, ATAG1_N_MARK,
 418
 419         /* IPSR4 */
 420         EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK, PWMFSW0_MARK,
 421         DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK,
 422         CC50_STATE0_MARK, DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK,
 423         I2C2_SDA_D_MARK, CC50_STATE1_MARK, DU0_DR2_MARK, LCDOUT18_MARK,
 424         CC50_STATE2_MARK, DU0_DR3_MARK, LCDOUT19_MARK, CC50_STATE3_MARK,
 425         DU0_DR4_MARK, LCDOUT20_MARK, CC50_STATE4_MARK, DU0_DR5_MARK,
 426         LCDOUT21_MARK, CC50_STATE5_MARK, DU0_DR6_MARK, LCDOUT22_MARK,
 427         CC50_STATE6_MARK, DU0_DR7_MARK, LCDOUT23_MARK, CC50_STATE7_MARK,
 428         DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK,
 429         CC50_STATE8_MARK, DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK,
 430         I2C3_SDA_D_MARK, CC50_STATE9_MARK, DU0_DG2_MARK, LCDOUT10_MARK,
 431         CC50_STATE10_MARK, DU0_DG3_MARK, LCDOUT11_MARK, CC50_STATE11_MARK,
 432         DU0_DG4_MARK, LCDOUT12_MARK, CC50_STATE12_MARK,
 433
 434         /* IPSR5 */
 435         DU0_DG5_MARK, LCDOUT13_MARK, CC50_STATE13_MARK, DU0_DG6_MARK,
 436         LCDOUT14_MARK, CC50_STATE14_MARK, DU0_DG7_MARK, LCDOUT15_MARK,
 437         CC50_STATE15_MARK, DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK,
 438         I2C4_SCL_D_MARK, CAN0_RX_C_MARK, CC50_STATE16_MARK, DU0_DB1_MARK,
 439         LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK, CAN0_TX_C_MARK,
 440         CC50_STATE17_MARK, DU0_DB2_MARK, LCDOUT2_MARK, CC50_STATE18_MARK,
 441         DU0_DB3_MARK, LCDOUT3_MARK, CC50_STATE19_MARK, DU0_DB4_MARK,
 442         LCDOUT4_MARK, CC50_STATE20_MARK, DU0_DB5_MARK, LCDOUT5_MARK,
 443         CC50_STATE21_MARK, DU0_DB6_MARK, LCDOUT6_MARK, CC50_STATE22_MARK,
 444         DU0_DB7_MARK, LCDOUT7_MARK, CC50_STATE23_MARK, DU0_DOTCLKIN_MARK,
 445         QSTVA_QVS_MARK, CC50_STATE24_MARK, DU0_DOTCLKOUT0_MARK,
 446         QCLK_MARK, CC50_STATE25_MARK, DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK,
 447         CC50_STATE26_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
 448         CC50_STATE27_MARK,
 449
 450         /* IPSR6 */
 451         DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, CC50_STATE28_MARK,
 452         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CC50_STATE29_MARK,
 453         DU0_DISP_MARK, QPOLA_MARK, CC50_STATE30_MARK, DU0_CDE_MARK, QPOLB_MARK,
 454         CC50_STATE31_MARK, VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK,
 455         AVB_RX_DV_MARK, VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
 456         VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, VI0_DATA3_VI0_B3_MARK,
 457         AVB_RXD2_MARK, VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
 458         VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, VI0_DATA6_VI0_B6_MARK,
 459         AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, VI0_CLKENB_MARK,
 460         I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, AVB_RXD7_MARK,
 461         VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
 462         AVB_RX_ER_MARK, VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK,
 463         IERX_C_MARK, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK,
 464         I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK,
 465         VI0_G0_MARK, MSIOF2_RXD_B_MARK, IIC0_SCL_D_MARK, AVB_TX_CLK_MARK,
 466         ADIDATA_MARK, AD_DI_MARK,
 467
 468         /* IPSR7 */
 469         ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, IIC0_SDA_D_MARK,
 470         AVB_TXD0_MARK, ADICS_SAMP_MARK, AD_DO_MARK, ETH_RX_ER_MARK, VI0_G2_MARK,
 471         MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, ADICLK_MARK,
 472         AD_CLK_MARK, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK,
 473         CAN0_TX_B_MARK, AVB_TXD2_MARK, ADICHS0_MARK, AD_NCS_N_MARK,
 474         ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
 475         AVB_TXD3_MARK, ADICHS1_MARK, ETH_LINK_MARK, VI0_G5_MARK,
 476         MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, AVB_TXD4_MARK, ADICHS2_MARK,
 477         ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
 478         SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK,
 479         IIC1_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK,
 480         VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC1_SDA_D_MARK, AVB_TXD7_MARK,
 481         SSI_SDATA5_B_MARK, ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK,
 482         AVB_TX_ER_MARK, SSI_SCK6_B_MARK, ETH_TXD0_MARK, VI0_R2_MARK,
 483         SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
 484         DREQ0_N_MARK, SCIFB1_RXD_MARK,
 485
 486         /* IPSR8 */
 487         ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK,
 488         AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK,
 489         I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK,
 490         HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK,
 491         AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK,
 492         SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK,
 493         HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK,
 494         AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK,
 495         HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK,
 496         I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK,
 497         AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
 498         SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
 499         CAN1_TX_D_MARK, I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK,
 500         DU1_DR0_MARK, RIF1_SYNC_B_MARK, TS_SDATA_D_MARK, TPUTO1_B_MARK,
 501         I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, RIF1_CLK_B_MARK,
 502         TS_SCK_D_MARK, BPFCLK_C_MARK, MSIOF0_RXD_MARK, SCIF5_RXD_MARK,
 503         I2C2_SCL_C_MARK, DU1_DR2_MARK, RIF1_D0_B_MARK, TS_SDEN_D_MARK,
 504         FMCLK_C_MARK, RDS_CLK_MARK,
 505
 506         /* IPSR9 */
 507         MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK,
 508         RIF1_D1_B_MARK, TS_SPSYNC_D_MARK, FMIN_C_MARK, RDS_DATA_MARK,
 509         MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, RIF1_SYNC_MARK,
 510         TPUTO1_C_MARK, MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK,
 511         RIF1_CLK_MARK, BPFCLK_B_MARK, MSIOF0_SS1_MARK, SCIFA0_RXD_MARK,
 512         TS_SDEN_MARK, DU1_DR6_MARK, RIF1_D0_MARK, FMCLK_B_MARK, RDS_CLK_B_MARK,
 513         MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK,
 514         RIF1_D1_MARK, FMIN_B_MARK, RDS_DATA_B_MARK, HSCIF1_HRX_MARK,
 515         I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK, HSCIF1_HTX_MARK,
 516         I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK, HSCIF1_HSCK_MARK,
 517         PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK, SPEEDIN_B_MARK,
 518         VSP_B_MARK, HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK,
 519         DU1_DG3_MARK, SSI_SCK1_B_MARK, CAN_DEBUG_HW_TRIGGER_MARK,
 520         CC50_STATE32_MARK, HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK,
 521         DU1_DG4_MARK, SSI_WS1_B_MARK, CAN_STEP0_MARK, CC50_STATE33_MARK,
 522         SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK,
 523         CAN_TXCLK_MARK, CC50_STATE34_MARK,
 524
 525         /* IPSR10 */
 526         SCIF1_RXD_MARK, IIC0_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK,
 527         CAN_DEBUGOUT0_MARK, CC50_STATE35_MARK, SCIF1_TXD_MARK, IIC0_SDA_MARK,
 528         DU1_DG7_MARK, SSI_WS2_B_MARK, CAN_DEBUGOUT1_MARK, CC50_STATE36_MARK,
 529         SCIF2_RXD_MARK, IIC1_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
 530         USB0_EXTLP_MARK, CAN_DEBUGOUT2_MARK, CC50_STATE37_MARK, SCIF2_TXD_MARK,
 531         IIC1_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK, USB0_OVC1_MARK,
 532         CAN_DEBUGOUT3_MARK, CC50_STATE38_MARK, SCIF2_SCK_MARK, IRQ1_MARK,
 533         DU1_DB2_MARK, SSI_WS9_B_MARK, USB0_IDIN_MARK, CAN_DEBUGOUT4_MARK,
 534         CC50_STATE39_MARK, SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK,
 535         DU1_DB3_MARK, SSI_SDATA9_B_MARK, TANS2_MARK, CAN_DEBUGOUT5_MARK,
 536         CC50_OSCOUT_MARK, SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK,
 537         DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK, CAN_DEBUGOUT6_MARK,
 538         RDS_CLK_C_MARK, SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK,
 539         DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK, CAN_DEBUGOUT7_MARK,
 540         RDS_DATA_C_MARK, I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK,
 541         AUDIO_CLKC_C_MARK, SSI_SDATA4_B_MARK, CAN_DEBUGOUT8_MARK, I2C2_SDA_MARK,
 542         SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK, CAN_DEBUGOUT9_MARK,
 543         SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK, CAN_DEBUGOUT10_MARK,
 544
 545         /* IPSR11 */
 546         SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
 547         CAN_DEBUGOUT11_MARK, SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK,
 548         DU1_DOTCLKOUT1_MARK, CAN_DEBUGOUT12_MARK, SSI_SCK6_MARK,
 549         SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, CAN_DEBUGOUT13_MARK,
 550         SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
 551         DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK, SSI_SDATA6_MARK,
 552         SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
 553         CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, IIC0_SDA_C_MARK,
 554         DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, IIC0_SCL_C_MARK,
 555         DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK,
 556         AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, PCMOE_N_MARK, SSI_SCK0129_MARK,
 557         MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, AD_DI_B_MARK,
 558         PCMWE_N_MARK, SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK,
 559         ADICS_SAMP_B_MARK, AD_DO_B_MARK, SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK,
 560         PWM0_B_MARK, ADICLK_B_MARK, AD_CLK_B_MARK,
 561
 562         /* IPSR12 */
 563         SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK,
 564         AD_NCS_N_B_MARK, DREQ1_N_B_MARK, SSI_WS34_MARK, MSIOF1_SS1_B_MARK,
 565         SCIFA1_RXD_C_MARK, ADICHS1_B_MARK, CAN1_RX_C_MARK, DACK1_B_MARK,
 566         SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK,
 567         CAN1_TX_C_MARK, DREQ2_N_MARK, SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK,
 568         IRD_TX_MARK, SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK, IRD_RX_MARK,
 569         SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK, IRD_SCK_MARK,
 570         SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK,
 571         DACK2_MARK, ETH_MDIO_B_MARK, SSI_SCK1_MARK, SCIF1_RXD_B_MARK,
 572         IIC1_SCL_C_MARK, VI1_CLK_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_MARK,
 573         ETH_CRS_DV_B_MARK, SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC1_SDA_C_MARK,
 574         VI1_DATA0_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_MARK, ETH_RX_ER_B_MARK,
 575         SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, SDATA_MARK,
 576         ATAG0_N_MARK, ETH_RXD0_B_MARK, SSI_SCK2_MARK, HSCIF1_HTX_B_MARK,
 577         VI1_DATA2_MARK, MDATA_MARK, ATAWR0_N_MARK, ETH_RXD1_B_MARK,
 578
 579         /* IPSR13 */
 580         SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK,
 581         SCKZ_MARK, ATACS00_N_MARK, ETH_LINK_B_MARK, SSI_SDATA2_MARK,
 582         HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK, VI1_DATA4_MARK, STM_N_MARK,
 583         ATACS10_N_MARK, ETH_REFCLK_B_MARK, SSI_SCK9_MARK, SCIF2_SCK_B_MARK,
 584         PWM2_B_MARK, VI1_DATA5_MARK, MTS_N_MARK, EX_WAIT1_MARK,
 585         ETH_TXD1_B_MARK, SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK,
 586         VI1_DATA6_MARK, ATARD0_N_MARK, ETH_TX_EN_B_MARK, SSI_SDATA9_MARK,
 587         SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK, ATADIR0_N_MARK,
 588         ETH_MAGIC_B_MARK, AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK,
 589         VI1_CLKENB_MARK, TS_SDATA_C_MARK, RIF0_SYNC_B_MARK, ETH_TXD0_B_MARK,
 590         AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK,
 591         TS_SCK_C_MARK, RIF0_CLK_B_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK,
 592         AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK,
 593         TS_SDEN_C_MARK, RIF0_D0_B_MARK, FMCLK_E_MARK, RDS_CLK_D_MARK,
 594         AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK,
 595         TS_SPSYNC_C_MARK, RIF0_D1_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK,
 596         PINMUX_MARK_END,
 597 };
 598
 599 static const u16 pinmux_data[] = {
 600         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 601
 602         PINMUX_SINGLE(A2),
 603         PINMUX_SINGLE(WE0_N),
 604         PINMUX_SINGLE(WE1_N),
 605         PINMUX_SINGLE(DACK0),
 606         PINMUX_SINGLE(USB0_PWEN),
 607         PINMUX_SINGLE(USB0_OVC),
 608         PINMUX_SINGLE(USB1_PWEN),
 609         PINMUX_SINGLE(USB1_OVC),
 610         PINMUX_SINGLE(SD0_CLK),
 611         PINMUX_SINGLE(SD0_CMD),
 612         PINMUX_SINGLE(SD0_DATA0),
 613         PINMUX_SINGLE(SD0_DATA1),
 614         PINMUX_SINGLE(SD0_DATA2),
 615         PINMUX_SINGLE(SD0_DATA3),
 616         PINMUX_SINGLE(SD0_CD),
 617         PINMUX_SINGLE(SD0_WP),
 618         PINMUX_SINGLE(SD1_CLK),
 619         PINMUX_SINGLE(SD1_CMD),
 620         PINMUX_SINGLE(SD1_DATA0),
 621         PINMUX_SINGLE(SD1_DATA1),
 622         PINMUX_SINGLE(SD1_DATA2),
 623         PINMUX_SINGLE(SD1_DATA3),
 624
 625         /* IPSR0 */
 626         PINMUX_IPSR_GPSR(IP0_0, SD1_CD),
 627         PINMUX_IPSR_MSEL(IP0_0, CAN0_RX, SEL_CAN0_0),
 628         PINMUX_IPSR_GPSR(IP0_9_8, SD1_WP),
 629         PINMUX_IPSR_GPSR(IP0_9_8, IRQ7),
 630         PINMUX_IPSR_MSEL(IP0_9_8, CAN0_TX, SEL_CAN0_0),
 631         PINMUX_IPSR_GPSR(IP0_10, MMC_CLK),
 632         PINMUX_IPSR_GPSR(IP0_10, SD2_CLK),
 633         PINMUX_IPSR_GPSR(IP0_11, MMC_CMD),
 634         PINMUX_IPSR_GPSR(IP0_11, SD2_CMD),
 635         PINMUX_IPSR_GPSR(IP0_12, MMC_D0),
 636         PINMUX_IPSR_GPSR(IP0_12, SD2_DATA0),
 637         PINMUX_IPSR_GPSR(IP0_13, MMC_D1),
 638         PINMUX_IPSR_GPSR(IP0_13, SD2_DATA1),
 639         PINMUX_IPSR_GPSR(IP0_14, MMC_D2),
 640         PINMUX_IPSR_GPSR(IP0_14, SD2_DATA2),
 641         PINMUX_IPSR_GPSR(IP0_15, MMC_D3),
 642         PINMUX_IPSR_GPSR(IP0_15, SD2_DATA3),
 643         PINMUX_IPSR_GPSR(IP0_16, MMC_D4),
 644         PINMUX_IPSR_GPSR(IP0_16, SD2_CD),
 645         PINMUX_IPSR_GPSR(IP0_17, MMC_D5),
 646         PINMUX_IPSR_GPSR(IP0_17, SD2_WP),
 647         PINMUX_IPSR_GPSR(IP0_19_18, MMC_D6),
 648         PINMUX_IPSR_MSEL(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0),
 649         PINMUX_IPSR_MSEL(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1),
 650         PINMUX_IPSR_MSEL(IP0_19_18, CAN1_RX, SEL_CAN1_0),
 651         PINMUX_IPSR_GPSR(IP0_21_20, MMC_D7),
 652         PINMUX_IPSR_MSEL(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0),
 653         PINMUX_IPSR_MSEL(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1),
 654         PINMUX_IPSR_MSEL(IP0_21_20, CAN1_TX, SEL_CAN1_0),
 655         PINMUX_IPSR_GPSR(IP0_23_22, D0),
 656         PINMUX_IPSR_MSEL(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1),
 657         PINMUX_IPSR_GPSR(IP0_23_22, IRQ4),
 658         PINMUX_IPSR_GPSR(IP0_24, D1),
 659         PINMUX_IPSR_MSEL(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1),
 660         PINMUX_IPSR_GPSR(IP0_25, D2),
 661         PINMUX_IPSR_MSEL(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1),
 662         PINMUX_IPSR_GPSR(IP0_27_26, D3),
 663         PINMUX_IPSR_MSEL(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1),
 664         PINMUX_IPSR_MSEL(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1),
 665         PINMUX_IPSR_GPSR(IP0_29_28, D4),
 666         PINMUX_IPSR_MSEL(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1),
 667         PINMUX_IPSR_MSEL(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1),
 668         PINMUX_IPSR_GPSR(IP0_31_30, D5),
 669         PINMUX_IPSR_MSEL(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1),
 670         PINMUX_IPSR_MSEL(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3),
 671
 672         /* IPSR1 */
 673         PINMUX_IPSR_GPSR(IP1_1_0, D6),
 674         PINMUX_IPSR_MSEL(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1),
 675         PINMUX_IPSR_MSEL(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3),
 676         PINMUX_IPSR_GPSR(IP1_3_2, D7),
 677         PINMUX_IPSR_GPSR(IP1_3_2, IRQ3),
 678         PINMUX_IPSR_MSEL(IP1_3_2, TCLK1, SEL_TMU_0),
 679         PINMUX_IPSR_GPSR(IP1_3_2, PWM6_B),
 680         PINMUX_IPSR_GPSR(IP1_5_4, D8),
 681         PINMUX_IPSR_GPSR(IP1_5_4, HSCIF2_HRX),
 682         PINMUX_IPSR_MSEL(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1),
 683         PINMUX_IPSR_GPSR(IP1_7_6, D9),
 684         PINMUX_IPSR_GPSR(IP1_7_6, HSCIF2_HTX),
 685         PINMUX_IPSR_MSEL(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1),
 686         PINMUX_IPSR_GPSR(IP1_10_8, D10),
 687         PINMUX_IPSR_GPSR(IP1_10_8, HSCIF2_HSCK),
 688         PINMUX_IPSR_MSEL(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2),
 689         PINMUX_IPSR_GPSR(IP1_10_8, IRQ6),
 690         PINMUX_IPSR_GPSR(IP1_10_8, PWM5_C),
 691         PINMUX_IPSR_GPSR(IP1_12_11, D11),
 692         PINMUX_IPSR_GPSR(IP1_12_11, HSCIF2_HCTS_N),
 693         PINMUX_IPSR_MSEL(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2),
 694         PINMUX_IPSR_MSEL(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3),
 695         PINMUX_IPSR_GPSR(IP1_14_13, D12),
 696         PINMUX_IPSR_GPSR(IP1_14_13, HSCIF2_HRTS_N),
 697         PINMUX_IPSR_MSEL(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2),
 698         PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3),
 699         PINMUX_IPSR_GPSR(IP1_17_15, D13),
 700         PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0),
 701         PINMUX_IPSR_GPSR(IP1_17_15, TANS1),
 702         PINMUX_IPSR_GPSR(IP1_17_15, PWM2_C),
 703         PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1),
 704         PINMUX_IPSR_GPSR(IP1_19_18, D14),
 705         PINMUX_IPSR_MSEL(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0),
 706         PINMUX_IPSR_MSEL(IP1_19_18, IIC0_SCL_B, SEL_IIC00_1),
 707         PINMUX_IPSR_GPSR(IP1_21_20, D15),
 708         PINMUX_IPSR_MSEL(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0),
 709         PINMUX_IPSR_MSEL(IP1_21_20, IIC0_SDA_B, SEL_IIC00_1),
 710         PINMUX_IPSR_GPSR(IP1_23_22, A0),
 711         PINMUX_IPSR_GPSR(IP1_23_22, SCIFB1_SCK),
 712         PINMUX_IPSR_GPSR(IP1_23_22, PWM3_B),
 713         PINMUX_IPSR_GPSR(IP1_24, A1),
 714         PINMUX_IPSR_GPSR(IP1_24, SCIFB1_TXD),
 715         PINMUX_IPSR_GPSR(IP1_26, A3),
 716         PINMUX_IPSR_GPSR(IP1_26, SCIFB0_SCK),
 717         PINMUX_IPSR_GPSR(IP1_27, A4),
 718         PINMUX_IPSR_GPSR(IP1_27, SCIFB0_TXD),
 719         PINMUX_IPSR_GPSR(IP1_29_28, A5),
 720         PINMUX_IPSR_GPSR(IP1_29_28, SCIFB0_RXD),
 721         PINMUX_IPSR_GPSR(IP1_29_28, PWM4_B),
 722         PINMUX_IPSR_GPSR(IP1_29_28, TPUTO3_C),
 723         PINMUX_IPSR_GPSR(IP1_31_30, A6),
 724         PINMUX_IPSR_GPSR(IP1_31_30, SCIFB0_CTS_N),
 725         PINMUX_IPSR_MSEL(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1),
 726         PINMUX_IPSR_GPSR(IP1_31_30, TPUTO2_C),
 727
 728         /* IPSR2 */
 729         PINMUX_IPSR_GPSR(IP2_1_0, A7),
 730         PINMUX_IPSR_GPSR(IP2_1_0, SCIFB0_RTS_N),
 731         PINMUX_IPSR_MSEL(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1),
 732         PINMUX_IPSR_GPSR(IP2_3_2, A8),
 733         PINMUX_IPSR_MSEL(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0),
 734         PINMUX_IPSR_MSEL(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1),
 735         PINMUX_IPSR_GPSR(IP2_5_4, A9),
 736         PINMUX_IPSR_MSEL(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0),
 737         PINMUX_IPSR_MSEL(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1),
 738         PINMUX_IPSR_GPSR(IP2_7_6, A10),
 739         PINMUX_IPSR_MSEL(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0),
 740         PINMUX_IPSR_MSEL(IP2_7_6, IIC1_SCL_B, SEL_IIC01_1),
 741         PINMUX_IPSR_GPSR(IP2_9_8, A11),
 742         PINMUX_IPSR_MSEL(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0),
 743         PINMUX_IPSR_MSEL(IP2_9_8, IIC1_SDA_B, SEL_IIC01_1),
 744         PINMUX_IPSR_GPSR(IP2_11_10, A12),
 745         PINMUX_IPSR_MSEL(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0),
 746         PINMUX_IPSR_MSEL(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1),
 747         PINMUX_IPSR_GPSR(IP2_13_12, A13),
 748         PINMUX_IPSR_MSEL(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0),
 749         PINMUX_IPSR_MSEL(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1),
 750         PINMUX_IPSR_GPSR(IP2_15_14, A14),
 751         PINMUX_IPSR_MSEL(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0),
 752         PINMUX_IPSR_MSEL(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1),
 753         PINMUX_IPSR_MSEL(IP2_15_14, DREQ1_N, SEL_LBS_0),
 754         PINMUX_IPSR_GPSR(IP2_17_16, A15),
 755         PINMUX_IPSR_MSEL(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0),
 756         PINMUX_IPSR_MSEL(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1),
 757         PINMUX_IPSR_MSEL(IP2_17_16, DACK1, SEL_LBS_0),
 758         PINMUX_IPSR_GPSR(IP2_20_18, A16),
 759         PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0),
 760         PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1),
 761         PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0),
 762         PINMUX_IPSR_MSEL(IP2_20_18, VSP, SEL_SPDM_0),
 763         PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2),
 764         PINMUX_IPSR_GPSR(IP2_20_18, TPUTO2_B),
 765         PINMUX_IPSR_GPSR(IP2_23_21, A17),
 766         PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0),
 767         PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4),
 768         PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1),
 769         PINMUX_IPSR_MSEL(IP2_23_21, AVB_AVTP_CAPTURE_B, SEL_AVB_1),
 770         PINMUX_IPSR_GPSR(IP2_26_24, A18),
 771         PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0),
 772         PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4),
 773         PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1),
 774         PINMUX_IPSR_MSEL(IP2_26_24, AVB_AVTP_MATCH_B, SEL_AVB_1),
 775         PINMUX_IPSR_GPSR(IP2_29_27, A19),
 776         PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0),
 777         PINMUX_IPSR_GPSR(IP2_29_27, PWM4),
 778         PINMUX_IPSR_GPSR(IP2_29_27, TPUTO2),
 779         PINMUX_IPSR_GPSR(IP2_29_27, MOUT0),
 780         PINMUX_IPSR_GPSR(IP2_31_30, A20),
 781         PINMUX_IPSR_GPSR(IP2_31_30, SPCLK),
 782         PINMUX_IPSR_GPSR(IP2_29_27, MOUT1),
 783
 784         /* IPSR3 */
 785         PINMUX_IPSR_GPSR(IP3_1_0, A21),
 786         PINMUX_IPSR_GPSR(IP3_1_0, MOSI_IO0),
 787         PINMUX_IPSR_GPSR(IP3_1_0, MOUT2),
 788         PINMUX_IPSR_GPSR(IP3_3_2, A22),
 789         PINMUX_IPSR_GPSR(IP3_3_2, MISO_IO1),
 790         PINMUX_IPSR_GPSR(IP3_3_2, MOUT5),
 791         PINMUX_IPSR_GPSR(IP3_3_2, ATADIR1_N),
 792         PINMUX_IPSR_GPSR(IP3_5_4, A23),
 793         PINMUX_IPSR_GPSR(IP3_5_4, IO2),
 794         PINMUX_IPSR_GPSR(IP3_5_4, MOUT6),
 795         PINMUX_IPSR_GPSR(IP3_5_4, ATAWR1_N),
 796         PINMUX_IPSR_GPSR(IP3_7_6, A24),
 797         PINMUX_IPSR_GPSR(IP3_7_6, IO3),
 798         PINMUX_IPSR_GPSR(IP3_7_6, EX_WAIT2),
 799         PINMUX_IPSR_GPSR(IP3_9_8, A25),
 800         PINMUX_IPSR_GPSR(IP3_9_8, SSL),
 801         PINMUX_IPSR_GPSR(IP3_9_8, ATARD1_N),
 802         PINMUX_IPSR_GPSR(IP3_10, CS0_N),
 803         PINMUX_IPSR_GPSR(IP3_10, VI1_DATA8),
 804         PINMUX_IPSR_GPSR(IP3_11, CS1_N_A26),
 805         PINMUX_IPSR_GPSR(IP3_11, VI1_DATA9),
 806         PINMUX_IPSR_GPSR(IP3_12, EX_CS0_N),
 807         PINMUX_IPSR_GPSR(IP3_12, VI1_DATA10),
 808         PINMUX_IPSR_GPSR(IP3_14_13, EX_CS1_N),
 809         PINMUX_IPSR_GPSR(IP3_14_13, TPUTO3_B),
 810         PINMUX_IPSR_GPSR(IP3_14_13, SCIFB2_RXD),
 811         PINMUX_IPSR_GPSR(IP3_14_13, VI1_DATA11),
 812         PINMUX_IPSR_GPSR(IP3_17_15, EX_CS2_N),
 813         PINMUX_IPSR_GPSR(IP3_17_15, PWM0),
 814         PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2),
 815         PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1),
 816         PINMUX_IPSR_MSEL(IP3_17_15, RIF0_SYNC, SEL_DR0_0),
 817         PINMUX_IPSR_GPSR(IP3_17_15, TPUTO3),
 818         PINMUX_IPSR_GPSR(IP3_17_15, SCIFB2_TXD),
 819         PINMUX_IPSR_MSEL(IP3_17_15, SDATA_B, SEL_FSN_1),
 820         PINMUX_IPSR_GPSR(IP3_20_18, EX_CS3_N),
 821         PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0),
 822         PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2),
 823         PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1),
 824         PINMUX_IPSR_MSEL(IP3_20_18, RIF0_CLK, SEL_DR0_0),
 825         PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0),
 826         PINMUX_IPSR_GPSR(IP3_20_18, SCIFB2_SCK),
 827         PINMUX_IPSR_MSEL(IP3_20_18, MDATA_B, SEL_FSN_1),
 828         PINMUX_IPSR_GPSR(IP3_23_21, EX_CS4_N),
 829         PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0),
 830         PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4),
 831         PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1),
 832         PINMUX_IPSR_MSEL(IP3_23_21, RIF0_D0, SEL_DR0_0),
 833         PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0),
 834         PINMUX_IPSR_GPSR(IP3_23_21, SCIFB2_CTS_N),
 835         PINMUX_IPSR_MSEL(IP3_23_21, SCKZ_B, SEL_FSN_1),
 836         PINMUX_IPSR_GPSR(IP3_26_24, EX_CS5_N),
 837         PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0),
 838         PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4),
 839         PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1),
 840         PINMUX_IPSR_MSEL(IP3_26_24, RIF0_D1, SEL_DR1_0),
 841         PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0),
 842         PINMUX_IPSR_GPSR(IP3_26_24, SCIFB2_RTS_N),
 843         PINMUX_IPSR_MSEL(IP3_26_24, STM_N_B, SEL_FSN_1),
 844         PINMUX_IPSR_GPSR(IP3_29_27, BS_N),
 845         PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
 846         PINMUX_IPSR_GPSR(IP3_29_27, PWM1_C),
 847         PINMUX_IPSR_GPSR(IP3_29_27, TPUTO0_C),
 848         PINMUX_IPSR_GPSR(IP3_29_27, ATACS01_N),
 849         PINMUX_IPSR_MSEL(IP3_29_27, MTS_N_B, SEL_FSN_1),
 850         PINMUX_IPSR_GPSR(IP3_30, RD_N),
 851         PINMUX_IPSR_GPSR(IP3_30, ATACS11_N),
 852         PINMUX_IPSR_GPSR(IP3_31, RD_WR_N),
 853         PINMUX_IPSR_GPSR(IP3_31, ATAG1_N),
 854
 855         /* IPSR4 */
 856         PINMUX_IPSR_GPSR(IP4_1_0, EX_WAIT0),
 857         PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1),
 858         PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0),
 859         PINMUX_IPSR_GPSR(IP4_1_0, PWMFSW0),
 860         PINMUX_IPSR_GPSR(IP4_4_2, DU0_DR0),
 861         PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16),
 862         PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2),
 863         PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3),
 864         PINMUX_IPSR_GPSR(IP4_4_2, CC50_STATE0),
 865         PINMUX_IPSR_GPSR(IP4_7_5, DU0_DR1),
 866         PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17),
 867         PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2),
 868         PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3),
 869         PINMUX_IPSR_GPSR(IP4_9_8, CC50_STATE1),
 870         PINMUX_IPSR_GPSR(IP4_9_8, DU0_DR2),
 871         PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18),
 872         PINMUX_IPSR_GPSR(IP4_9_8, CC50_STATE2),
 873         PINMUX_IPSR_GPSR(IP4_11_10, DU0_DR3),
 874         PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19),
 875         PINMUX_IPSR_GPSR(IP4_11_10, CC50_STATE3),
 876         PINMUX_IPSR_GPSR(IP4_13_12, DU0_DR4),
 877         PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20),
 878         PINMUX_IPSR_GPSR(IP4_13_12, CC50_STATE4),
 879         PINMUX_IPSR_GPSR(IP4_15_14, DU0_DR5),
 880         PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21),
 881         PINMUX_IPSR_GPSR(IP4_15_14, CC50_STATE5),
 882         PINMUX_IPSR_GPSR(IP4_17_16, DU0_DR6),
 883         PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22),
 884         PINMUX_IPSR_GPSR(IP4_17_16, CC50_STATE6),
 885         PINMUX_IPSR_GPSR(IP4_19_18, DU0_DR7),
 886         PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23),
 887         PINMUX_IPSR_GPSR(IP4_19_18, CC50_STATE7),
 888         PINMUX_IPSR_GPSR(IP4_22_20, DU0_DG0),
 889         PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8),
 890         PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2),
 891         PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3),
 892         PINMUX_IPSR_GPSR(IP4_22_20, CC50_STATE8),
 893         PINMUX_IPSR_GPSR(IP4_25_23, DU0_DG1),
 894         PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9),
 895         PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2),
 896         PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3),
 897         PINMUX_IPSR_GPSR(IP4_25_23, CC50_STATE9),
 898         PINMUX_IPSR_GPSR(IP4_27_26, DU0_DG2),
 899         PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10),
 900         PINMUX_IPSR_GPSR(IP4_27_26, CC50_STATE10),
 901         PINMUX_IPSR_GPSR(IP4_29_28, DU0_DG3),
 902         PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11),
 903         PINMUX_IPSR_GPSR(IP4_29_28, CC50_STATE11),
 904         PINMUX_IPSR_GPSR(IP4_31_30, DU0_DG4),
 905         PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12),
 906         PINMUX_IPSR_GPSR(IP4_31_30, CC50_STATE12),
 907
 908         /* IPSR5 */
 909         PINMUX_IPSR_GPSR(IP5_1_0, DU0_DG5),
 910         PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13),
 911         PINMUX_IPSR_GPSR(IP5_1_0, CC50_STATE13),
 912         PINMUX_IPSR_GPSR(IP5_3_2, DU0_DG6),
 913         PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14),
 914         PINMUX_IPSR_GPSR(IP5_3_2, CC50_STATE14),
 915         PINMUX_IPSR_GPSR(IP5_5_4, DU0_DG7),
 916         PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15),
 917         PINMUX_IPSR_GPSR(IP5_5_4, CC50_STATE15),
 918         PINMUX_IPSR_GPSR(IP5_8_6, DU0_DB0),
 919         PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0),
 920         PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2),
 921         PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3),
 922         PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2),
 923         PINMUX_IPSR_GPSR(IP5_8_6, CC50_STATE16),
 924         PINMUX_IPSR_GPSR(IP5_11_9, DU0_DB1),
 925         PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1),
 926         PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
 927         PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3),
 928         PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2),
 929         PINMUX_IPSR_GPSR(IP5_11_9, CC50_STATE17),
 930         PINMUX_IPSR_GPSR(IP5_13_12, DU0_DB2),
 931         PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2),
 932         PINMUX_IPSR_GPSR(IP5_13_12, CC50_STATE18),
 933         PINMUX_IPSR_GPSR(IP5_15_14, DU0_DB3),
 934         PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3),
 935         PINMUX_IPSR_GPSR(IP5_15_14, CC50_STATE19),
 936         PINMUX_IPSR_GPSR(IP5_17_16, DU0_DB4),
 937         PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4),
 938         PINMUX_IPSR_GPSR(IP5_17_16, CC50_STATE20),
 939         PINMUX_IPSR_GPSR(IP5_19_18, DU0_DB5),
 940         PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5),
 941         PINMUX_IPSR_GPSR(IP5_19_18, CC50_STATE21),
 942         PINMUX_IPSR_GPSR(IP5_21_20, DU0_DB6),
 943         PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6),
 944         PINMUX_IPSR_GPSR(IP5_21_20, CC50_STATE22),
 945         PINMUX_IPSR_GPSR(IP5_23_22, DU0_DB7),
 946         PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7),
 947         PINMUX_IPSR_GPSR(IP5_23_22, CC50_STATE23),
 948         PINMUX_IPSR_GPSR(IP5_25_24, DU0_DOTCLKIN),
 949         PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS),
 950         PINMUX_IPSR_GPSR(IP5_25_24, CC50_STATE24),
 951         PINMUX_IPSR_GPSR(IP5_27_26, DU0_DOTCLKOUT0),
 952         PINMUX_IPSR_GPSR(IP5_27_26, QCLK),
 953         PINMUX_IPSR_GPSR(IP5_27_26, CC50_STATE25),
 954         PINMUX_IPSR_GPSR(IP5_29_28, DU0_DOTCLKOUT1),
 955         PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE),
 956         PINMUX_IPSR_GPSR(IP5_29_28, CC50_STATE26),
 957         PINMUX_IPSR_GPSR(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC),
 958         PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS),
 959         PINMUX_IPSR_GPSR(IP5_31_30, CC50_STATE27),
 960
 961         /* IPSR6 */
 962         PINMUX_IPSR_GPSR(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
 963         PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE),
 964         PINMUX_IPSR_GPSR(IP6_1_0, CC50_STATE28),
 965         PINMUX_IPSR_GPSR(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
 966         PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE),
 967         PINMUX_IPSR_GPSR(IP6_3_2, CC50_STATE29),
 968         PINMUX_IPSR_GPSR(IP6_5_4, DU0_DISP),
 969         PINMUX_IPSR_GPSR(IP6_5_4, QPOLA),
 970         PINMUX_IPSR_GPSR(IP6_5_4, CC50_STATE30),
 971         PINMUX_IPSR_GPSR(IP6_7_6, DU0_CDE),
 972         PINMUX_IPSR_GPSR(IP6_7_6, QPOLB),
 973         PINMUX_IPSR_GPSR(IP6_7_6, CC50_STATE31),
 974         PINMUX_IPSR_GPSR(IP6_8, VI0_CLK),
 975         PINMUX_IPSR_GPSR(IP6_8, AVB_RX_CLK),
 976         PINMUX_IPSR_GPSR(IP6_9, VI0_DATA0_VI0_B0),
 977         PINMUX_IPSR_GPSR(IP6_9, AVB_RX_DV),
 978         PINMUX_IPSR_GPSR(IP6_10, VI0_DATA1_VI0_B1),
 979         PINMUX_IPSR_GPSR(IP6_10, AVB_RXD0),
 980         PINMUX_IPSR_GPSR(IP6_11, VI0_DATA2_VI0_B2),
 981         PINMUX_IPSR_GPSR(IP6_11, AVB_RXD1),
 982         PINMUX_IPSR_GPSR(IP6_12, VI0_DATA3_VI0_B3),
 983         PINMUX_IPSR_GPSR(IP6_12, AVB_RXD2),
 984         PINMUX_IPSR_GPSR(IP6_13, VI0_DATA4_VI0_B4),
 985         PINMUX_IPSR_GPSR(IP6_13, AVB_RXD3),
 986         PINMUX_IPSR_GPSR(IP6_14, VI0_DATA5_VI0_B5),
 987         PINMUX_IPSR_GPSR(IP6_14, AVB_RXD4),
 988         PINMUX_IPSR_GPSR(IP6_15, VI0_DATA6_VI0_B6),
 989         PINMUX_IPSR_GPSR(IP6_15, AVB_RXD5),
 990         PINMUX_IPSR_GPSR(IP6_16, VI0_DATA7_VI0_B7),
 991         PINMUX_IPSR_GPSR(IP6_16, AVB_RXD6),
 992         PINMUX_IPSR_GPSR(IP6_19_17, VI0_CLKENB),
 993         PINMUX_IPSR_MSEL(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
 994         PINMUX_IPSR_MSEL(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
 995         PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2),
 996         PINMUX_IPSR_GPSR(IP6_19_17, AVB_RXD7),
 997         PINMUX_IPSR_GPSR(IP6_22_20, VI0_FIELD),
 998         PINMUX_IPSR_MSEL(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
 999         PINMUX_IPSR_MSEL(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
1000         PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2),
1001         PINMUX_IPSR_GPSR(IP6_22_20, AVB_RX_ER),
1002         PINMUX_IPSR_GPSR(IP6_25_23, VI0_HSYNC_N),
1003         PINMUX_IPSR_MSEL(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
1004         PINMUX_IPSR_MSEL(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
1005         PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2),
1006         PINMUX_IPSR_GPSR(IP6_25_23, AVB_COL),
1007         PINMUX_IPSR_GPSR(IP6_28_26, VI0_VSYNC_N),
1008         PINMUX_IPSR_MSEL(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
1009         PINMUX_IPSR_MSEL(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2),
1010         PINMUX_IPSR_MSEL(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1),
1011         PINMUX_IPSR_GPSR(IP6_28_26, AVB_TX_EN),
1012         PINMUX_IPSR_MSEL(IP6_31_29, ETH_MDIO, SEL_ETH_0),
1013         PINMUX_IPSR_GPSR(IP6_31_29, VI0_G0),
1014         PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
1015         PINMUX_IPSR_MSEL(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3),
1016         PINMUX_IPSR_GPSR(IP6_31_29, AVB_TX_CLK),
1017         PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0),
1018         PINMUX_IPSR_MSEL(IP6_31_29, AD_DI, SEL_ADI_0),
1019
1020         /* IPSR7 */
1021         PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
1022         PINMUX_IPSR_GPSR(IP7_2_0, VI0_G1),
1023         PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
1024         PINMUX_IPSR_MSEL(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3),
1025         PINMUX_IPSR_GPSR(IP7_2_0, AVB_TXD0),
1026         PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
1027         PINMUX_IPSR_MSEL(IP7_2_0, AD_DO, SEL_ADI_0),
1028         PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
1029         PINMUX_IPSR_GPSR(IP7_5_3, VI0_G2),
1030         PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
1031         PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
1032         PINMUX_IPSR_GPSR(IP7_5_3, AVB_TXD1),
1033         PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0),
1034         PINMUX_IPSR_MSEL(IP7_5_3, AD_CLK, SEL_ADI_0),
1035         PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0),
1036         PINMUX_IPSR_GPSR(IP7_8_6, VI0_G3),
1037         PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
1038         PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
1039         PINMUX_IPSR_GPSR(IP7_8_6, AVB_TXD2),
1040         PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0),
1041         PINMUX_IPSR_MSEL(IP7_8_6, AD_NCS_N, SEL_ADI_0),
1042         PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0),
1043         PINMUX_IPSR_GPSR(IP7_11_9, VI0_G4),
1044         PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
1045         PINMUX_IPSR_MSEL(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
1046         PINMUX_IPSR_GPSR(IP7_11_9, AVB_TXD3),
1047         PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0),
1048         PINMUX_IPSR_MSEL(IP7_14_12, ETH_LINK, SEL_ETH_0),
1049         PINMUX_IPSR_GPSR(IP7_14_12, VI0_G5),
1050         PINMUX_IPSR_MSEL(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
1051         PINMUX_IPSR_MSEL(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
1052         PINMUX_IPSR_GPSR(IP7_14_12, AVB_TXD4),
1053         PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0),
1054         PINMUX_IPSR_MSEL(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
1055         PINMUX_IPSR_GPSR(IP7_17_15, VI0_G6),
1056         PINMUX_IPSR_MSEL(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
1057         PINMUX_IPSR_GPSR(IP7_17_15, AVB_TXD5),
1058         PINMUX_IPSR_MSEL(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1),
1059         PINMUX_IPSR_MSEL(IP7_20_18, ETH_TXD1, SEL_ETH_0),
1060         PINMUX_IPSR_GPSR(IP7_20_18, VI0_G7),
1061         PINMUX_IPSR_MSEL(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
1062         PINMUX_IPSR_MSEL(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3),
1063         PINMUX_IPSR_GPSR(IP7_20_18, AVB_TXD6),
1064         PINMUX_IPSR_MSEL(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
1065         PINMUX_IPSR_MSEL(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
1066         PINMUX_IPSR_GPSR(IP7_23_21, VI0_R0),
1067         PINMUX_IPSR_MSEL(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
1068         PINMUX_IPSR_MSEL(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3),
1069         PINMUX_IPSR_GPSR(IP7_23_21, AVB_TXD7),
1070         PINMUX_IPSR_MSEL(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
1071         PINMUX_IPSR_MSEL(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
1072         PINMUX_IPSR_GPSR(IP7_26_24, VI0_R1),
1073         PINMUX_IPSR_MSEL(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1),
1074         PINMUX_IPSR_GPSR(IP7_26_24, AVB_TX_ER),
1075         PINMUX_IPSR_MSEL(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1),
1076         PINMUX_IPSR_MSEL(IP7_29_27, ETH_TXD0, SEL_ETH_0),
1077         PINMUX_IPSR_GPSR(IP7_29_27, VI0_R2),
1078         PINMUX_IPSR_MSEL(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1),
1079         PINMUX_IPSR_MSEL(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4),
1080         PINMUX_IPSR_GPSR(IP7_29_27, AVB_GTX_CLK),
1081         PINMUX_IPSR_MSEL(IP7_29_27, SSI_WS6_B, SEL_SSI6_1),
1082         PINMUX_IPSR_GPSR(IP7_31, DREQ0_N),
1083         PINMUX_IPSR_GPSR(IP7_31, SCIFB1_RXD),
1084
1085         /* IPSR8 */
1086         PINMUX_IPSR_MSEL(IP8_2_0, ETH_MDC, SEL_ETH_0),
1087         PINMUX_IPSR_GPSR(IP8_2_0, VI0_R3),
1088         PINMUX_IPSR_MSEL(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1),
1089         PINMUX_IPSR_MSEL(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4),
1090         PINMUX_IPSR_GPSR(IP8_2_0, AVB_MDC),
1091         PINMUX_IPSR_MSEL(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1),
1092         PINMUX_IPSR_MSEL(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0),
1093         PINMUX_IPSR_GPSR(IP8_5_3, VI0_R4),
1094         PINMUX_IPSR_MSEL(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2),
1095         PINMUX_IPSR_MSEL(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1),
1096         PINMUX_IPSR_GPSR(IP8_5_3, AVB_MDIO),
1097         PINMUX_IPSR_MSEL(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1),
1098         PINMUX_IPSR_MSEL(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0),
1099         PINMUX_IPSR_GPSR(IP8_8_6, VI0_R5),
1100         PINMUX_IPSR_MSEL(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2),
1101         PINMUX_IPSR_MSEL(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1102         PINMUX_IPSR_GPSR(IP8_5_3, AVB_LINK),
1103         PINMUX_IPSR_MSEL(IP8_8_6, SSI_WS78_B, SEL_SSI7_1),
1104         PINMUX_IPSR_GPSR(IP8_11_9, HSCIF0_HCTS_N),
1105         PINMUX_IPSR_GPSR(IP8_11_9, VI0_R6),
1106         PINMUX_IPSR_MSEL(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3),
1107         PINMUX_IPSR_MSEL(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4),
1108         PINMUX_IPSR_GPSR(IP8_11_9, AVB_MAGIC),
1109         PINMUX_IPSR_MSEL(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1),
1110         PINMUX_IPSR_GPSR(IP8_14_12, HSCIF0_HRTS_N),
1111         PINMUX_IPSR_GPSR(IP8_14_12, VI0_R7),
1112         PINMUX_IPSR_MSEL(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3),
1113         PINMUX_IPSR_MSEL(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4),
1114         PINMUX_IPSR_GPSR(IP8_14_12, AVB_PHY_INT),
1115         PINMUX_IPSR_MSEL(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1),
1116         PINMUX_IPSR_MSEL(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0),
1117         PINMUX_IPSR_MSEL(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1),
1118         PINMUX_IPSR_GPSR(IP8_16_15, AVB_CRS),
1119         PINMUX_IPSR_MSEL(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1),
1120         PINMUX_IPSR_MSEL(IP8_19_17, I2C0_SCL, SEL_I2C00_0),
1121         PINMUX_IPSR_MSEL(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2),
1122         PINMUX_IPSR_GPSR(IP8_19_17, PWM5),
1123         PINMUX_IPSR_MSEL(IP8_19_17, TCLK1_B, SEL_TMU_1),
1124         PINMUX_IPSR_GPSR(IP8_19_17, AVB_GTXREFCLK),
1125         PINMUX_IPSR_MSEL(IP8_19_17, CAN1_RX_D, SEL_CAN1_3),
1126         PINMUX_IPSR_GPSR(IP8_19_17, TPUTO0_B),
1127         PINMUX_IPSR_MSEL(IP8_22_20, I2C0_SDA, SEL_I2C00_0),
1128         PINMUX_IPSR_MSEL(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2),
1129         PINMUX_IPSR_GPSR(IP8_22_20, TPUTO0),
1130         PINMUX_IPSR_MSEL(IP8_22_20, CAN_CLK, SEL_CAN_0),
1131         PINMUX_IPSR_GPSR(IP8_22_20, DVC_MUTE),
1132         PINMUX_IPSR_MSEL(IP8_22_20, CAN1_TX_D, SEL_CAN1_3),
1133         PINMUX_IPSR_MSEL(IP8_25_23, I2C1_SCL, SEL_I2C01_0),
1134         PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
1135         PINMUX_IPSR_GPSR(IP8_25_23, PWM5_B),
1136         PINMUX_IPSR_GPSR(IP8_25_23, DU1_DR0),
1137         PINMUX_IPSR_MSEL(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1),
1138         PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
1139         PINMUX_IPSR_GPSR(IP8_25_23, TPUTO1_B),
1140         PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
1141         PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
1142         PINMUX_IPSR_GPSR(IP8_28_26, IRQ5),
1143         PINMUX_IPSR_GPSR(IP8_28_26, DU1_DR1),
1144         PINMUX_IPSR_MSEL(IP8_28_26, RIF1_CLK_B, SEL_DR2_1),
1145         PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
1146         PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2),
1147         PINMUX_IPSR_GPSR(IP8_31_29, MSIOF0_RXD),
1148         PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
1149         PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
1150         PINMUX_IPSR_GPSR(IP8_31_29, DU1_DR2),
1151         PINMUX_IPSR_MSEL(IP8_31_29, RIF1_D0_B, SEL_DR2_1),
1152         PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
1153         PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2),
1154         PINMUX_IPSR_MSEL(IP8_31_29, RDS_CLK, SEL_RDS_0),
1155
1156         /* IPSR9 */
1157         PINMUX_IPSR_GPSR(IP9_2_0, MSIOF0_TXD),
1158         PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0),
1159         PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2),
1160         PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR3),
1161         PINMUX_IPSR_MSEL(IP9_2_0, RIF1_D1_B, SEL_DR3_1),
1162         PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3),
1163         PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2),
1164         PINMUX_IPSR_MSEL(IP9_2_0, RDS_DATA, SEL_RDS_0),
1165         PINMUX_IPSR_GPSR(IP9_5_3, MSIOF0_SCK),
1166         PINMUX_IPSR_GPSR(IP9_5_3, IRQ0),
1167         PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0),
1168         PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR4),
1169         PINMUX_IPSR_MSEL(IP9_5_3, RIF1_SYNC, SEL_DR2_0),
1170         PINMUX_IPSR_GPSR(IP9_5_3, TPUTO1_C),
1171         PINMUX_IPSR_GPSR(IP9_8_6, MSIOF0_SYNC),
1172         PINMUX_IPSR_GPSR(IP9_8_6, PWM1),
1173         PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0),
1174         PINMUX_IPSR_GPSR(IP9_8_6, DU1_DR5),
1175         PINMUX_IPSR_MSEL(IP9_8_6, RIF1_CLK, SEL_DR2_0),
1176         PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1),
1177         PINMUX_IPSR_GPSR(IP9_11_9, MSIOF0_SS1),
1178         PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0),
1179         PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0),
1180         PINMUX_IPSR_GPSR(IP9_11_9, DU1_DR6),
1181         PINMUX_IPSR_MSEL(IP9_11_9, RIF1_D0, SEL_DR2_0),
1182         PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1),
1183         PINMUX_IPSR_MSEL(IP9_11_9, RDS_CLK_B, SEL_RDS_1),
1184         PINMUX_IPSR_GPSR(IP9_14_12, MSIOF0_SS2),
1185         PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0),
1186         PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0),
1187         PINMUX_IPSR_GPSR(IP9_14_12, DU1_DR7),
1188         PINMUX_IPSR_MSEL(IP9_14_12, RIF1_D1, SEL_DR3_0),
1189         PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1),
1190         PINMUX_IPSR_MSEL(IP9_14_12, RDS_DATA_B, SEL_RDS_1),
1191         PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0),
1192         PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0),
1193         PINMUX_IPSR_GPSR(IP9_16_15, PWM6),
1194         PINMUX_IPSR_GPSR(IP9_16_15, DU1_DG0),
1195         PINMUX_IPSR_MSEL(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0),
1196         PINMUX_IPSR_MSEL(IP9_18_17, I2C4_SDA, SEL_I2C04_0),
1197         PINMUX_IPSR_GPSR(IP9_18_17, TPUTO1),
1198         PINMUX_IPSR_GPSR(IP9_18_17, DU1_DG1),
1199         PINMUX_IPSR_GPSR(IP9_21_19, HSCIF1_HSCK),
1200         PINMUX_IPSR_GPSR(IP9_21_19, PWM2),
1201         PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0),
1202         PINMUX_IPSR_GPSR(IP9_21_19, DU1_DG2),
1203         PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1),
1204         PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1),
1205         PINMUX_IPSR_MSEL(IP9_21_19, VSP_B, SEL_SPDM_1),
1206         PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0),
1207         PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0),
1208         PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0),
1209         PINMUX_IPSR_GPSR(IP9_24_22, DU1_DG3),
1210         PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1),
1211         PINMUX_IPSR_GPSR(IP9_24_22, CAN_DEBUG_HW_TRIGGER),
1212         PINMUX_IPSR_GPSR(IP9_24_22, CC50_STATE32),
1213         PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0),
1214         PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0),
1215         PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0),
1216         PINMUX_IPSR_GPSR(IP9_27_25, DU1_DG4),
1217         PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1),
1218         PINMUX_IPSR_GPSR(IP9_27_25, CAN_STEP0),
1219         PINMUX_IPSR_GPSR(IP9_27_25, CC50_STATE33),
1220         PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0),
1221         PINMUX_IPSR_GPSR(IP9_30_28, PWM3),
1222         PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0),
1223         PINMUX_IPSR_GPSR(IP9_30_28, DU1_DG5),
1224         PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1),
1225         PINMUX_IPSR_GPSR(IP9_30_28, CAN_TXCLK),
1226         PINMUX_IPSR_GPSR(IP9_30_28, CC50_STATE34),
1227
1228         /* IPSR10 */
1229         PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0),
1230         PINMUX_IPSR_MSEL(IP10_2_0, IIC0_SCL, SEL_IIC00_0),
1231         PINMUX_IPSR_GPSR(IP10_2_0, DU1_DG6),
1232         PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1),
1233         PINMUX_IPSR_GPSR(IP10_2_0, CAN_DEBUGOUT0),
1234         PINMUX_IPSR_GPSR(IP10_2_0, CC50_STATE35),
1235         PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0),
1236         PINMUX_IPSR_MSEL(IP10_5_3, IIC0_SDA, SEL_IIC00_0),
1237         PINMUX_IPSR_GPSR(IP10_5_3, DU1_DG7),
1238         PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1),
1239         PINMUX_IPSR_GPSR(IP10_5_3, CAN_DEBUGOUT1),
1240         PINMUX_IPSR_GPSR(IP10_5_3, CC50_STATE36),
1241         PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0),
1242         PINMUX_IPSR_MSEL(IP10_8_6, IIC1_SCL, SEL_IIC01_0),
1243         PINMUX_IPSR_GPSR(IP10_8_6, DU1_DB0),
1244         PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1),
1245         PINMUX_IPSR_GPSR(IP10_8_6, USB0_EXTLP),
1246         PINMUX_IPSR_GPSR(IP10_8_6, CAN_DEBUGOUT2),
1247         PINMUX_IPSR_GPSR(IP10_8_6, CC50_STATE37),
1248         PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0),
1249         PINMUX_IPSR_MSEL(IP10_11_9, IIC1_SDA, SEL_IIC01_0),
1250         PINMUX_IPSR_GPSR(IP10_11_9, DU1_DB1),
1251         PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1),
1252         PINMUX_IPSR_GPSR(IP10_11_9, USB0_OVC1),
1253         PINMUX_IPSR_GPSR(IP10_11_9, CAN_DEBUGOUT3),
1254         PINMUX_IPSR_GPSR(IP10_11_9, CC50_STATE38),
1255         PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0),
1256         PINMUX_IPSR_GPSR(IP10_14_12, IRQ1),
1257         PINMUX_IPSR_GPSR(IP10_14_12, DU1_DB2),
1258         PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1),
1259         PINMUX_IPSR_GPSR(IP10_14_12, USB0_IDIN),
1260         PINMUX_IPSR_GPSR(IP10_14_12, CAN_DEBUGOUT4),
1261         PINMUX_IPSR_GPSR(IP10_14_12, CC50_STATE39),
1262         PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0),
1263         PINMUX_IPSR_GPSR(IP10_17_15, IRQ2),
1264         PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3),
1265         PINMUX_IPSR_GPSR(IP10_17_15, DU1_DB3),
1266         PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1),
1267         PINMUX_IPSR_GPSR(IP10_17_15, TANS2),
1268         PINMUX_IPSR_GPSR(IP10_17_15, CAN_DEBUGOUT5),
1269         PINMUX_IPSR_GPSR(IP10_17_15, CC50_OSCOUT),
1270         PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0),
1271         PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4),
1272         PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3),
1273         PINMUX_IPSR_GPSR(IP10_20_18, DU1_DB4),
1274         PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2),
1275         PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1),
1276         PINMUX_IPSR_GPSR(IP10_20_18, CAN_DEBUGOUT6),
1277         PINMUX_IPSR_MSEL(IP10_20_18, RDS_CLK_C, SEL_RDS_2),
1278         PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0),
1279         PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4),
1280         PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3),
1281         PINMUX_IPSR_GPSR(IP10_23_21, DU1_DB5),
1282         PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2),
1283         PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1),
1284         PINMUX_IPSR_GPSR(IP10_23_21, CAN_DEBUGOUT7),
1285         PINMUX_IPSR_MSEL(IP10_23_21, RDS_DATA_C, SEL_RDS_2),
1286         PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0),
1287         PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0),
1288         PINMUX_IPSR_GPSR(IP10_26_24, DU1_DB6),
1289         PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2),
1290         PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1),
1291         PINMUX_IPSR_GPSR(IP10_26_24, CAN_DEBUGOUT8),
1292         PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0),
1293         PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0),
1294         PINMUX_IPSR_GPSR(IP10_29_27, DU1_DB7),
1295         PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2),
1296         PINMUX_IPSR_GPSR(IP10_29_27, CAN_DEBUGOUT9),
1297         PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0),
1298         PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0),
1299         PINMUX_IPSR_GPSR(IP10_31_30, DU1_DOTCLKIN),
1300         PINMUX_IPSR_GPSR(IP10_31_30, CAN_DEBUGOUT10),
1301
1302         /* IPSR11 */
1303         PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0),
1304         PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1305         PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
1306         PINMUX_IPSR_GPSR(IP11_2_0, DU1_DOTCLKOUT0),
1307         PINMUX_IPSR_GPSR(IP11_2_0, CAN_DEBUGOUT11),
1308         PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
1309         PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
1310         PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
1311         PINMUX_IPSR_GPSR(IP11_5_3, DU1_DOTCLKOUT1),
1312         PINMUX_IPSR_GPSR(IP11_5_3, CAN_DEBUGOUT12),
1313         PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
1314         PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
1315         PINMUX_IPSR_GPSR(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
1316         PINMUX_IPSR_GPSR(IP11_7_6, CAN_DEBUGOUT13),
1317         PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0),
1318         PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
1319         PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
1320         PINMUX_IPSR_GPSR(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
1321         PINMUX_IPSR_GPSR(IP11_10_8, CAN_DEBUGOUT14),
1322         PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
1323         PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
1324         PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
1325         PINMUX_IPSR_GPSR(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1326         PINMUX_IPSR_GPSR(IP11_13_11, CAN_DEBUGOUT15),
1327         PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
1328         PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
1329         PINMUX_IPSR_MSEL(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2),
1330         PINMUX_IPSR_GPSR(IP11_15_14, DU1_DISP),
1331         PINMUX_IPSR_MSEL(IP11_17_16, SSI_WS78, SEL_SSI7_0),
1332         PINMUX_IPSR_MSEL(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
1333         PINMUX_IPSR_MSEL(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2),
1334         PINMUX_IPSR_GPSR(IP11_17_16, DU1_CDE),
1335         PINMUX_IPSR_MSEL(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
1336         PINMUX_IPSR_MSEL(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
1337         PINMUX_IPSR_GPSR(IP11_20_18, IRQ8),
1338         PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
1339         PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
1340         PINMUX_IPSR_GPSR(IP11_20_18, PCMOE_N),
1341         PINMUX_IPSR_GPSR(IP11_23_21, SSI_SCK0129),
1342         PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
1343         PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
1344         PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1),
1345         PINMUX_IPSR_MSEL(IP11_23_21, AD_DI_B, SEL_ADI_1),
1346         PINMUX_IPSR_GPSR(IP11_23_21, PCMWE_N),
1347         PINMUX_IPSR_GPSR(IP11_26_24, SSI_WS0129),
1348         PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
1349         PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
1350         PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
1351         PINMUX_IPSR_MSEL(IP11_26_24, AD_DO_B, SEL_ADI_1),
1352         PINMUX_IPSR_GPSR(IP11_29_27, SSI_SDATA0),
1353         PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
1354         PINMUX_IPSR_GPSR(IP11_29_27, PWM0_B),
1355         PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1),
1356         PINMUX_IPSR_MSEL(IP11_29_27, AD_CLK_B, SEL_ADI_1),
1357
1358         /* IPSR12 */
1359         PINMUX_IPSR_GPSR(IP12_2_0, SSI_SCK34),
1360         PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1),
1361         PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2),
1362         PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1),
1363         PINMUX_IPSR_MSEL(IP12_2_0, AD_NCS_N_B, SEL_ADI_1),
1364         PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1),
1365         PINMUX_IPSR_GPSR(IP12_5_3, SSI_WS34),
1366         PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1),
1367         PINMUX_IPSR_MSEL(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2),
1368         PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1),
1369         PINMUX_IPSR_MSEL(IP12_5_3, CAN1_RX_C, SEL_CAN1_2),
1370         PINMUX_IPSR_MSEL(IP12_5_3, DACK1_B, SEL_LBS_1),
1371         PINMUX_IPSR_GPSR(IP12_8_6, SSI_SDATA3),
1372         PINMUX_IPSR_MSEL(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1),
1373         PINMUX_IPSR_MSEL(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2),
1374         PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1),
1375         PINMUX_IPSR_MSEL(IP12_8_6, CAN1_TX_C, SEL_CAN1_2),
1376         PINMUX_IPSR_GPSR(IP12_8_6, DREQ2_N),
1377         PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0),
1378         PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK),
1379         PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1),
1380         PINMUX_IPSR_GPSR(IP12_10_9, IRD_TX),
1381         PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0),
1382         PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG),
1383         PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1),
1384         PINMUX_IPSR_GPSR(IP12_12_11, IRD_RX),
1385         PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0),
1386         PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT),
1387         PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1),
1388         PINMUX_IPSR_GPSR(IP12_14_13, IRD_SCK),
1389         PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0),
1390         PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1),
1391         PINMUX_IPSR_GPSR(IP12_17_15, PWM1_B),
1392         PINMUX_IPSR_GPSR(IP12_17_15, IRQ9),
1393         PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0),
1394         PINMUX_IPSR_GPSR(IP12_17_15, DACK2),
1395         PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1),
1396         PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0),
1397         PINMUX_IPSR_MSEL(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1),
1398         PINMUX_IPSR_MSEL(IP12_20_18, IIC1_SCL_C, SEL_IIC01_2),
1399         PINMUX_IPSR_GPSR(IP12_20_18, VI1_CLK),
1400         PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3),
1401         PINMUX_IPSR_MSEL(IP12_20_18, AVB_AVTP_CAPTURE, SEL_AVB_0),
1402         PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1),
1403         PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0),
1404         PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1),
1405         PINMUX_IPSR_MSEL(IP12_23_21, IIC1_SDA_C, SEL_IIC01_2),
1406         PINMUX_IPSR_GPSR(IP12_23_21, VI1_DATA0),
1407         PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3),
1408         PINMUX_IPSR_MSEL(IP12_23_21, AVB_AVTP_MATCH, SEL_AVB_0),
1409         PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1),
1410         PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0),
1411         PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1),
1412         PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1),
1413         PINMUX_IPSR_MSEL(IP12_26_24, SDATA, SEL_FSN_0),
1414         PINMUX_IPSR_GPSR(IP12_26_24, ATAG0_N),
1415         PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1),
1416         PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0),
1417         PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1),
1418         PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2),
1419         PINMUX_IPSR_MSEL(IP12_29_27, MDATA, SEL_FSN_0),
1420         PINMUX_IPSR_GPSR(IP12_29_27, ATAWR0_N),
1421         PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1),
1422
1423         /* IPSR13 */
1424         PINMUX_IPSR_MSEL(IP13_2_0, SSI_WS2, SEL_SSI2_0),
1425         PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1),
1426         PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3),
1427         PINMUX_IPSR_GPSR(IP13_2_0, VI1_DATA3),
1428         PINMUX_IPSR_MSEL(IP13_2_0, SCKZ, SEL_FSN_0),
1429         PINMUX_IPSR_GPSR(IP13_2_0, ATACS00_N),
1430         PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1),
1431         PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0),
1432         PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1),
1433         PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3),
1434         PINMUX_IPSR_GPSR(IP13_5_3, VI1_DATA4),
1435         PINMUX_IPSR_MSEL(IP13_5_3, STM_N, SEL_FSN_0),
1436         PINMUX_IPSR_GPSR(IP13_5_3, ATACS10_N),
1437         PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1),
1438         PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0),
1439         PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1),
1440         PINMUX_IPSR_GPSR(IP13_8_6, PWM2_B),
1441         PINMUX_IPSR_GPSR(IP13_8_6, VI1_DATA5),
1442         PINMUX_IPSR_MSEL(IP13_8_6, MTS_N, SEL_FSN_0),
1443         PINMUX_IPSR_GPSR(IP13_8_6, EX_WAIT1),
1444         PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1),
1445         PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0),
1446         PINMUX_IPSR_MSEL(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1),
1447         PINMUX_IPSR_MSEL(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4),
1448         PINMUX_IPSR_GPSR(IP13_11_9, VI1_DATA6),
1449         PINMUX_IPSR_GPSR(IP13_11_9, ATARD0_N),
1450         PINMUX_IPSR_MSEL(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1),
1451         PINMUX_IPSR_MSEL(IP13_14_12, SSI_SDATA9, SEL_SSI9_0),
1452         PINMUX_IPSR_MSEL(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1),
1453         PINMUX_IPSR_MSEL(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4),
1454         PINMUX_IPSR_GPSR(IP13_14_12, VI1_DATA7),
1455         PINMUX_IPSR_GPSR(IP13_14_12, ATADIR0_N),
1456         PINMUX_IPSR_MSEL(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1),
1457         PINMUX_IPSR_MSEL(IP13_17_15, AUDIO_CLKA, SEL_ADG_0),
1458         PINMUX_IPSR_MSEL(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1),
1459         PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3),
1460         PINMUX_IPSR_GPSR(IP13_17_15, VI1_CLKENB),
1461         PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2),
1462         PINMUX_IPSR_MSEL(IP13_17_15, RIF0_SYNC_B, SEL_DR0_1),
1463         PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1),
1464         PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0),
1465         PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1),
1466         PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3),
1467         PINMUX_IPSR_GPSR(IP13_20_18, VI1_FIELD),
1468         PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2),
1469         PINMUX_IPSR_MSEL(IP13_20_18, RIF0_CLK_B, SEL_DR0_1),
1470         PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4),
1471         PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1),
1472         PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0),
1473         PINMUX_IPSR_MSEL(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1),
1474         PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3),
1475         PINMUX_IPSR_GPSR(IP13_23_21, VI1_HSYNC_N),
1476         PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2),
1477         PINMUX_IPSR_MSEL(IP13_23_21, RIF0_D0_B, SEL_DR0_1),
1478         PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4),
1479         PINMUX_IPSR_MSEL(IP13_23_21, RDS_CLK_D, SEL_RDS_3),
1480         PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0),
1481         PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1),
1482         PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3),
1483         PINMUX_IPSR_GPSR(IP13_26_24, VI1_VSYNC_N),
1484         PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2),
1485         PINMUX_IPSR_MSEL(IP13_26_24, RIF0_D1_B, SEL_DR1_1),
1486         PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4),
1487         PINMUX_IPSR_MSEL(IP13_26_24, RDS_DATA_D, SEL_RDS_3),
1488 };
1489
1490 static const struct sh_pfc_pin pinmux_pins[] = {
1491         PINMUX_GPIO_GP_ALL(),
1492 };
1493
1494 /* - ETH -------------------------------------------------------------------- */
1495 static const unsigned int eth_link_pins[] = {
1496         /* LINK */
1497         RCAR_GP_PIN(3, 18),
1498 };
1499 static const unsigned int eth_link_mux[] = {
1500         ETH_LINK_MARK,
1501 };
1502 static const unsigned int eth_magic_pins[] = {
1503         /* MAGIC */
1504         RCAR_GP_PIN(3, 22),
1505 };
1506 static const unsigned int eth_magic_mux[] = {
1507         ETH_MAGIC_MARK,
1508 };
1509 static const unsigned int eth_mdio_pins[] = {
1510         /* MDC, MDIO */
1511         RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 13),
1512 };
1513 static const unsigned int eth_mdio_mux[] = {
1514         ETH_MDC_MARK, ETH_MDIO_MARK,
1515 };
1516 static const unsigned int eth_rmii_pins[] = {
1517         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1518         RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 15),
1519         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 20),
1520         RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 19),
1521 };
1522 static const unsigned int eth_rmii_mux[] = {
1523         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1524         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
1525 };
1526 static const unsigned int eth_link_b_pins[] = {
1527         /* LINK */
1528         RCAR_GP_PIN(5, 15),
1529 };
1530 static const unsigned int eth_link_b_mux[] = {
1531         ETH_LINK_B_MARK,
1532 };
1533 static const unsigned int eth_magic_b_pins[] = {
1534         /* MAGIC */
1535         RCAR_GP_PIN(5, 19),
1536 };
1537 static const unsigned int eth_magic_b_mux[] = {
1538         ETH_MAGIC_B_MARK,
1539 };
1540 static const unsigned int eth_mdio_b_pins[] = {
1541         /* MDC, MDIO */
1542         RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 10),
1543 };
1544 static const unsigned int eth_mdio_b_mux[] = {
1545         ETH_MDC_B_MARK, ETH_MDIO_B_MARK,
1546 };
1547 static const unsigned int eth_rmii_b_pins[] = {
1548         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1549         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 12),
1550         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 17),
1551         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 16),
1552 };
1553 static const unsigned int eth_rmii_b_mux[] = {
1554         ETH_RXD0_B_MARK, ETH_RXD1_B_MARK, ETH_RX_ER_B_MARK, ETH_CRS_DV_B_MARK,
1555         ETH_TXD0_B_MARK, ETH_TXD1_B_MARK, ETH_TX_EN_B_MARK, ETH_REFCLK_B_MARK,
1556 };
1557 /* - HSCIF0 ----------------------------------------------------------------- */
1558 static const unsigned int hscif0_data_pins[] = {
1559         /* RX, TX */
1560         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1561 };
1562 static const unsigned int hscif0_data_mux[] = {
1563         HSCIF0_HRX_MARK, HSCIF0_HTX_MARK,
1564 };
1565 static const unsigned int hscif0_clk_pins[] = {
1566         /* SCK */
1567         RCAR_GP_PIN(3, 29),
1568 };
1569 static const unsigned int hscif0_clk_mux[] = {
1570         HSCIF0_HSCK_MARK,
1571 };
1572 static const unsigned int hscif0_ctrl_pins[] = {
1573         /* RTS, CTS */
1574         RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
1575 };
1576 static const unsigned int hscif0_ctrl_mux[] = {
1577         HSCIF0_HRTS_N_MARK, HSCIF0_HCTS_N_MARK,
1578 };
1579 static const unsigned int hscif0_data_b_pins[] = {
1580         /* RX, TX */
1581         RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31),
1582 };
1583 static const unsigned int hscif0_data_b_mux[] = {
1584         HSCIF0_HRX_B_MARK, HSCIF0_HTX_B_MARK,
1585 };
1586 static const unsigned int hscif0_clk_b_pins[] = {
1587         /* SCK */
1588         RCAR_GP_PIN(1, 0),
1589 };
1590 static const unsigned int hscif0_clk_b_mux[] = {
1591         HSCIF0_HSCK_B_MARK,
1592 };
1593 /* - HSCIF1 ----------------------------------------------------------------- */
1594 static const unsigned int hscif1_data_pins[] = {
1595         /* RX, TX */
1596         RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1597 };
1598 static const unsigned int hscif1_data_mux[] = {
1599         HSCIF1_HRX_MARK, HSCIF1_HTX_MARK,
1600 };
1601 static const unsigned int hscif1_clk_pins[] = {
1602         /* SCK */
1603         RCAR_GP_PIN(4, 10),
1604 };
1605 static const unsigned int hscif1_clk_mux[] = {
1606         HSCIF1_HSCK_MARK,
1607 };
1608 static const unsigned int hscif1_ctrl_pins[] = {
1609         /* RTS, CTS */
1610         RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
1611 };
1612 static const unsigned int hscif1_ctrl_mux[] = {
1613         HSCIF1_HRTS_N_MARK, HSCIF1_HCTS_N_MARK,
1614 };
1615 static const unsigned int hscif1_data_b_pins[] = {
1616         /* RX, TX */
1617         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1618 };
1619 static const unsigned int hscif1_data_b_mux[] = {
1620         HSCIF1_HRX_B_MARK, HSCIF1_HTX_B_MARK,
1621 };
1622 static const unsigned int hscif1_ctrl_b_pins[] = {
1623         /* RTS, CTS */
1624         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
1625 };
1626 static const unsigned int hscif1_ctrl_b_mux[] = {
1627         HSCIF1_HRTS_N_B_MARK, HSCIF1_HCTS_N_B_MARK,
1628 };
1629 /* - HSCIF2 ----------------------------------------------------------------- */
1630 static const unsigned int hscif2_data_pins[] = {
1631         /* RX, TX */
1632         RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
1633 };
1634 static const unsigned int hscif2_data_mux[] = {
1635         HSCIF2_HRX_MARK, HSCIF2_HTX_MARK,
1636 };
1637 static const unsigned int hscif2_clk_pins[] = {
1638         /* SCK */
1639         RCAR_GP_PIN(0, 10),
1640 };
1641 static const unsigned int hscif2_clk_mux[] = {
1642         HSCIF2_HSCK_MARK,
1643 };
1644 static const unsigned int hscif2_ctrl_pins[] = {
1645         /* RTS, CTS */
1646         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
1647 };
1648 static const unsigned int hscif2_ctrl_mux[] = {
1649         HSCIF2_HRTS_N_MARK, HSCIF2_HCTS_N_MARK,
1650 };
1651 /* - I2C0 ------------------------------------------------------------------- */
1652 static const unsigned int i2c0_pins[] = {
1653         /* SCL, SDA */
1654         RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
1655 };
1656 static const unsigned int i2c0_mux[] = {
1657         I2C0_SCL_MARK, I2C0_SDA_MARK,
1658 };
1659 static const unsigned int i2c0_b_pins[] = {
1660         /* SCL, SDA */
1661         RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
1662 };
1663 static const unsigned int i2c0_b_mux[] = {
1664         I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
1665 };
1666 static const unsigned int i2c0_c_pins[] = {
1667         /* SCL, SDA */
1668         RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1669 };
1670 static const unsigned int i2c0_c_mux[] = {
1671         I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
1672 };
1673 static const unsigned int i2c0_d_pins[] = {
1674         /* SCL, SDA */
1675         RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
1676 };
1677 static const unsigned int i2c0_d_mux[] = {
1678         I2C0_SCL_D_MARK, I2C0_SDA_D_MARK,
1679 };
1680 static const unsigned int i2c0_e_pins[] = {
1681         /* SCL, SDA */
1682         RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
1683 };
1684 static const unsigned int i2c0_e_mux[] = {
1685         I2C0_SCL_E_MARK, I2C0_SDA_E_MARK,
1686 };
1687 /* - I2C1 ------------------------------------------------------------------- */
1688 static const unsigned int i2c1_pins[] = {
1689         /* SCL, SDA */
1690         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
1691 };
1692 static const unsigned int i2c1_mux[] = {
1693         I2C1_SCL_MARK, I2C1_SDA_MARK,
1694 };
1695 static const unsigned int i2c1_b_pins[] = {
1696         /* SCL, SDA */
1697         RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
1698 };
1699 static const unsigned int i2c1_b_mux[] = {
1700         I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
1701 };
1702 static const unsigned int i2c1_c_pins[] = {
1703         /* SCL, SDA */
1704         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1705 };
1706 static const unsigned int i2c1_c_mux[] = {
1707         I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
1708 };
1709 static const unsigned int i2c1_d_pins[] = {
1710         /* SCL, SDA */
1711         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
1712 };
1713 static const unsigned int i2c1_d_mux[] = {
1714         I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
1715 };
1716 static const unsigned int i2c1_e_pins[] = {
1717         /* SCL, SDA */
1718         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
1719 };
1720 static const unsigned int i2c1_e_mux[] = {
1721         I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
1722 };
1723 /* - I2C2 ------------------------------------------------------------------- */
1724 static const unsigned int i2c2_pins[] = {
1725         /* SCL, SDA */
1726         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
1727 };
1728 static const unsigned int i2c2_mux[] = {
1729         I2C2_SCL_MARK, I2C2_SDA_MARK,
1730 };
1731 static const unsigned int i2c2_b_pins[] = {
1732         /* SCL, SDA */
1733         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
1734 };
1735 static const unsigned int i2c2_b_mux[] = {
1736         I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
1737 };
1738 static const unsigned int i2c2_c_pins[] = {
1739         /* SCL, SDA */
1740         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1741 };
1742 static const unsigned int i2c2_c_mux[] = {
1743         I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
1744 };
1745 static const unsigned int i2c2_d_pins[] = {
1746         /* SCL, SDA */
1747         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1748 };
1749 static const unsigned int i2c2_d_mux[] = {
1750         I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
1751 };
1752 static const unsigned int i2c2_e_pins[] = {
1753         /* SCL, SDA */
1754         RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
1755 };
1756 static const unsigned int i2c2_e_mux[] = {
1757         I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
1758 };
1759 /* - I2C3 ------------------------------------------------------------------- */
1760 static const unsigned int i2c3_pins[] = {
1761         /* SCL, SDA */
1762         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
1763 };
1764 static const unsigned int i2c3_mux[] = {
1765         I2C3_SCL_MARK, I2C3_SDA_MARK,
1766 };
1767 static const unsigned int i2c3_b_pins[] = {
1768         /* SCL, SDA */
1769         RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
1770 };
1771 static const unsigned int i2c3_b_mux[] = {
1772         I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
1773 };
1774 static const unsigned int i2c3_c_pins[] = {
1775         /* SCL, SDA */
1776         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
1777 };
1778 static const unsigned int i2c3_c_mux[] = {
1779         I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
1780 };
1781 static const unsigned int i2c3_d_pins[] = {
1782         /* SCL, SDA */
1783         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1784 };
1785 static const unsigned int i2c3_d_mux[] = {
1786         I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
1787 };
1788 static const unsigned int i2c3_e_pins[] = {
1789         /* SCL, SDA */
1790         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
1791 };
1792 static const unsigned int i2c3_e_mux[] = {
1793         I2C3_SCL_E_MARK, I2C3_SDA_E_MARK,
1794 };
1795 /* - I2C4 ------------------------------------------------------------------- */
1796 static const unsigned int i2c4_pins[] = {
1797         /* SCL, SDA */
1798         RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1799 };
1800 static const unsigned int i2c4_mux[] = {
1801         I2C4_SCL_MARK, I2C4_SDA_MARK,
1802 };
1803 static const unsigned int i2c4_b_pins[] = {
1804         /* SCL, SDA */
1805         RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
1806 };
1807 static const unsigned int i2c4_b_mux[] = {
1808         I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
1809 };
1810 static const unsigned int i2c4_c_pins[] = {
1811         /* SCL, SDA */
1812         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
1813 };
1814 static const unsigned int i2c4_c_mux[] = {
1815         I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
1816 };
1817 static const unsigned int i2c4_d_pins[] = {
1818         /* SCL, SDA */
1819         RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
1820 };
1821 static const unsigned int i2c4_d_mux[] = {
1822         I2C4_SCL_D_MARK, I2C4_SDA_D_MARK,
1823 };
1824 static const unsigned int i2c4_e_pins[] = {
1825         /* SCL, SDA */
1826         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
1827 };
1828 static const unsigned int i2c4_e_mux[] = {
1829         I2C4_SCL_E_MARK, I2C4_SDA_E_MARK,
1830 };
1831 /* - INTC ------------------------------------------------------------------- */
1832 static const unsigned int intc_irq0_pins[] = {
1833         /* IRQ0 */
1834         RCAR_GP_PIN(4, 4),
1835 };
1836 static const unsigned int intc_irq0_mux[] = {
1837         IRQ0_MARK,
1838 };
1839 static const unsigned int intc_irq1_pins[] = {
1840         /* IRQ1 */
1841         RCAR_GP_PIN(4, 18),
1842 };
1843 static const unsigned int intc_irq1_mux[] = {
1844         IRQ1_MARK,
1845 };
1846 static const unsigned int intc_irq2_pins[] = {
1847         /* IRQ2 */
1848         RCAR_GP_PIN(4, 19),
1849 };
1850 static const unsigned int intc_irq2_mux[] = {
1851         IRQ2_MARK,
1852 };
1853 static const unsigned int intc_irq3_pins[] = {
1854         /* IRQ3 */
1855         RCAR_GP_PIN(0, 7),
1856 };
1857 static const unsigned int intc_irq3_mux[] = {
1858         IRQ3_MARK,
1859 };
1860 static const unsigned int intc_irq4_pins[] = {
1861         /* IRQ4 */
1862         RCAR_GP_PIN(0, 0),
1863 };
1864 static const unsigned int intc_irq4_mux[] = {
1865         IRQ4_MARK,
1866 };
1867 static const unsigned int intc_irq5_pins[] = {
1868         /* IRQ5 */
1869         RCAR_GP_PIN(4, 1),
1870 };
1871 static const unsigned int intc_irq5_mux[] = {
1872         IRQ5_MARK,
1873 };
1874 static const unsigned int intc_irq6_pins[] = {
1875         /* IRQ6 */
1876         RCAR_GP_PIN(0, 10),
1877 };
1878 static const unsigned int intc_irq6_mux[] = {
1879         IRQ6_MARK,
1880 };
1881 static const unsigned int intc_irq7_pins[] = {
1882         /* IRQ7 */
1883         RCAR_GP_PIN(6, 15),
1884 };
1885 static const unsigned int intc_irq7_mux[] = {
1886         IRQ7_MARK,
1887 };
1888 static const unsigned int intc_irq8_pins[] = {
1889         /* IRQ8 */
1890         RCAR_GP_PIN(5, 0),
1891 };
1892 static const unsigned int intc_irq8_mux[] = {
1893         IRQ8_MARK,
1894 };
1895 static const unsigned int intc_irq9_pins[] = {
1896         /* IRQ9 */
1897         RCAR_GP_PIN(5, 10),
1898 };
1899 static const unsigned int intc_irq9_mux[] = {
1900         IRQ9_MARK,
1901 };
1902 /* - MMCIF ------------------------------------------------------------------ */
1903 static const unsigned int mmc_data1_pins[] = {
1904         /* D[0] */
1905         RCAR_GP_PIN(6, 18),
1906 };
1907 static const unsigned int mmc_data1_mux[] = {
1908         MMC_D0_MARK,
1909 };
1910 static const unsigned int mmc_data4_pins[] = {
1911         /* D[0:3] */
1912         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
1913         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
1914 };
1915 static const unsigned int mmc_data4_mux[] = {
1916         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
1917 };
1918 static const unsigned int mmc_data8_pins[] = {
1919         /* D[0:7] */
1920         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
1921         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
1922         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
1923         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
1924 };
1925 static const unsigned int mmc_data8_mux[] = {
1926         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
1927         MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
1928 };
1929 static const unsigned int mmc_ctrl_pins[] = {
1930         /* CLK, CMD */
1931         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
1932 };
1933 static const unsigned int mmc_ctrl_mux[] = {
1934         MMC_CLK_MARK, MMC_CMD_MARK,
1935 };
1936 /* - MSIOF0 ----------------------------------------------------------------- */
1937 static const unsigned int msiof0_clk_pins[] = {
1938         /* SCK */
1939         RCAR_GP_PIN(4, 4),
1940 };
1941 static const unsigned int msiof0_clk_mux[] = {
1942         MSIOF0_SCK_MARK,
1943 };
1944 static const unsigned int msiof0_sync_pins[] = {
1945         /* SYNC */
1946         RCAR_GP_PIN(4, 5),
1947 };
1948 static const unsigned int msiof0_sync_mux[] = {
1949         MSIOF0_SYNC_MARK,
1950 };
1951 static const unsigned int msiof0_ss1_pins[] = {
1952         /* SS1 */
1953         RCAR_GP_PIN(4, 6),
1954 };
1955 static const unsigned int msiof0_ss1_mux[] = {
1956         MSIOF0_SS1_MARK,
1957 };
1958 static const unsigned int msiof0_ss2_pins[] = {
1959         /* SS2 */
1960         RCAR_GP_PIN(4, 7),
1961 };
1962 static const unsigned int msiof0_ss2_mux[] = {
1963         MSIOF0_SS2_MARK,
1964 };
1965 static const unsigned int msiof0_rx_pins[] = {
1966         /* RXD */
1967         RCAR_GP_PIN(4, 2),
1968 };
1969 static const unsigned int msiof0_rx_mux[] = {
1970         MSIOF0_RXD_MARK,
1971 };
1972 static const unsigned int msiof0_tx_pins[] = {
1973         /* TXD */
1974         RCAR_GP_PIN(4, 3),
1975 };
1976 static const unsigned int msiof0_tx_mux[] = {
1977         MSIOF0_TXD_MARK,
1978 };
1979 /* - MSIOF1 ----------------------------------------------------------------- */
1980 static const unsigned int msiof1_clk_pins[] = {
1981         /* SCK */
1982         RCAR_GP_PIN(0, 26),
1983 };
1984 static const unsigned int msiof1_clk_mux[] = {
1985         MSIOF1_SCK_MARK,
1986 };
1987 static const unsigned int msiof1_sync_pins[] = {
1988         /* SYNC */
1989         RCAR_GP_PIN(0, 27),
1990 };
1991 static const unsigned int msiof1_sync_mux[] = {
1992         MSIOF1_SYNC_MARK,
1993 };
1994 static const unsigned int msiof1_ss1_pins[] = {
1995         /* SS1 */
1996         RCAR_GP_PIN(0, 28),
1997 };
1998 static const unsigned int msiof1_ss1_mux[] = {
1999         MSIOF1_SS1_MARK,
2000 };
2001 static const unsigned int msiof1_ss2_pins[] = {
2002         /* SS2 */
2003         RCAR_GP_PIN(0, 29),
2004 };
2005 static const unsigned int msiof1_ss2_mux[] = {
2006         MSIOF1_SS2_MARK,
2007 };
2008 static const unsigned int msiof1_rx_pins[] = {
2009         /* RXD */
2010         RCAR_GP_PIN(0, 24),
2011 };
2012 static const unsigned int msiof1_rx_mux[] = {
2013         MSIOF1_RXD_MARK,
2014 };
2015 static const unsigned int msiof1_tx_pins[] = {
2016         /* TXD */
2017         RCAR_GP_PIN(0, 25),
2018 };
2019 static const unsigned int msiof1_tx_mux[] = {
2020         MSIOF1_TXD_MARK,
2021 };
2022 static const unsigned int msiof1_clk_b_pins[] = {
2023         /* SCK */
2024         RCAR_GP_PIN(5, 3),
2025 };
2026 static const unsigned int msiof1_clk_b_mux[] = {
2027         MSIOF1_SCK_B_MARK,
2028 };
2029 static const unsigned int msiof1_sync_b_pins[] = {
2030         /* SYNC */
2031         RCAR_GP_PIN(5, 4),
2032 };
2033 static const unsigned int msiof1_sync_b_mux[] = {
2034         MSIOF1_SYNC_B_MARK,
2035 };
2036 static const unsigned int msiof1_ss1_b_pins[] = {
2037         /* SS1 */
2038         RCAR_GP_PIN(5, 5),
2039 };
2040 static const unsigned int msiof1_ss1_b_mux[] = {
2041         MSIOF1_SS1_B_MARK,
2042 };
2043 static const unsigned int msiof1_ss2_b_pins[] = {
2044         /* SS2 */
2045         RCAR_GP_PIN(5, 6),
2046 };
2047 static const unsigned int msiof1_ss2_b_mux[] = {
2048         MSIOF1_SS2_B_MARK,
2049 };
2050 static const unsigned int msiof1_rx_b_pins[] = {
2051         /* RXD */
2052         RCAR_GP_PIN(5, 1),
2053 };
2054 static const unsigned int msiof1_rx_b_mux[] = {
2055         MSIOF1_RXD_B_MARK,
2056 };
2057 static const unsigned int msiof1_tx_b_pins[] = {
2058         /* TXD */
2059         RCAR_GP_PIN(5, 2),
2060 };
2061 static const unsigned int msiof1_tx_b_mux[] = {
2062         MSIOF1_TXD_B_MARK,
2063 };
2064 /* - MSIOF2 ----------------------------------------------------------------- */
2065 static const unsigned int msiof2_clk_pins[] = {
2066         /* SCK */
2067         RCAR_GP_PIN(1, 0),
2068 };
2069 static const unsigned int msiof2_clk_mux[] = {
2070         MSIOF2_SCK_MARK,
2071 };
2072 static const unsigned int msiof2_sync_pins[] = {
2073         /* SYNC */
2074         RCAR_GP_PIN(1, 1),
2075 };
2076 static const unsigned int msiof2_sync_mux[] = {
2077         MSIOF2_SYNC_MARK,
2078 };
2079 static const unsigned int msiof2_ss1_pins[] = {
2080         /* SS1 */
2081         RCAR_GP_PIN(1, 2),
2082 };
2083 static const unsigned int msiof2_ss1_mux[] = {
2084         MSIOF2_SS1_MARK,
2085 };
2086 static const unsigned int msiof2_ss2_pins[] = {
2087         /* SS2 */
2088         RCAR_GP_PIN(1, 3),
2089 };
2090 static const unsigned int msiof2_ss2_mux[] = {
2091         MSIOF2_SS2_MARK,
2092 };
2093 static const unsigned int msiof2_rx_pins[] = {
2094         /* RXD */
2095         RCAR_GP_PIN(0, 30),
2096 };
2097 static const unsigned int msiof2_rx_mux[] = {
2098         MSIOF2_RXD_MARK,
2099 };
2100 static const unsigned int msiof2_tx_pins[] = {
2101         /* TXD */
2102         RCAR_GP_PIN(0, 31),
2103 };
2104 static const unsigned int msiof2_tx_mux[] = {
2105         MSIOF2_TXD_MARK,
2106 };
2107 static const unsigned int msiof2_clk_b_pins[] = {
2108         /* SCK */
2109         RCAR_GP_PIN(3, 15),
2110 };
2111 static const unsigned int msiof2_clk_b_mux[] = {
2112         MSIOF2_SCK_B_MARK,
2113 };
2114 static const unsigned int msiof2_sync_b_pins[] = {
2115         /* SYNC */
2116         RCAR_GP_PIN(3, 16),
2117 };
2118 static const unsigned int msiof2_sync_b_mux[] = {
2119         MSIOF2_SYNC_B_MARK,
2120 };
2121 static const unsigned int msiof2_ss1_b_pins[] = {
2122         /* SS1 */
2123         RCAR_GP_PIN(3, 17),
2124 };
2125 static const unsigned int msiof2_ss1_b_mux[] = {
2126         MSIOF2_SS1_B_MARK,
2127 };
2128 static const unsigned int msiof2_ss2_b_pins[] = {
2129         /* SS2 */
2130         RCAR_GP_PIN(3, 18),
2131 };
2132 static const unsigned int msiof2_ss2_b_mux[] = {
2133         MSIOF2_SS2_B_MARK,
2134 };
2135 static const unsigned int msiof2_rx_b_pins[] = {
2136         /* RXD */
2137         RCAR_GP_PIN(3, 13),
2138 };
2139 static const unsigned int msiof2_rx_b_mux[] = {
2140         MSIOF2_RXD_B_MARK,
2141 };
2142 static const unsigned int msiof2_tx_b_pins[] = {
2143         /* TXD */
2144         RCAR_GP_PIN(3, 14),
2145 };
2146 static const unsigned int msiof2_tx_b_mux[] = {
2147         MSIOF2_TXD_B_MARK,
2148 };
2149 /* - QSPI ------------------------------------------------------------------- */
2150 static const unsigned int qspi_ctrl_pins[] = {
2151         /* SPCLK, SSL */
2152         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2153 };
2154 static const unsigned int qspi_ctrl_mux[] = {
2155         SPCLK_MARK, SSL_MARK,
2156 };
2157 static const unsigned int qspi_data2_pins[] = {
2158         /* MOSI_IO0, MISO_IO1 */
2159         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2160 };
2161 static const unsigned int qspi_data2_mux[] = {
2162         MOSI_IO0_MARK, MISO_IO1_MARK,
2163 };
2164 static const unsigned int qspi_data4_pins[] = {
2165         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2166         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2167         RCAR_GP_PIN(1, 8),
2168 };
2169 static const unsigned int qspi_data4_mux[] = {
2170         MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2171 };
2172 /* - SCIF0 ------------------------------------------------------------------ */
2173 static const unsigned int scif0_data_pins[] = {
2174         /* RX, TX */
2175         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2176 };
2177 static const unsigned int scif0_data_mux[] = {
2178         SCIF0_RXD_MARK, SCIF0_TXD_MARK,
2179 };
2180 static const unsigned int scif0_data_b_pins[] = {
2181         /* RX, TX */
2182         RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
2183 };
2184 static const unsigned int scif0_data_b_mux[] = {
2185         SCIF0_RXD_B_MARK, SCIF0_TXD_B_MARK,
2186 };
2187 static const unsigned int scif0_data_c_pins[] = {
2188         /* RX, TX */
2189         RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2190 };
2191 static const unsigned int scif0_data_c_mux[] = {
2192         SCIF0_RXD_C_MARK, SCIF0_TXD_C_MARK,
2193 };
2194 static const unsigned int scif0_data_d_pins[] = {
2195         /* RX, TX */
2196         RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
2197 };
2198 static const unsigned int scif0_data_d_mux[] = {
2199         SCIF0_RXD_D_MARK, SCIF0_TXD_D_MARK,
2200 };
2201 /* - SCIF1 ------------------------------------------------------------------ */
2202 static const unsigned int scif1_data_pins[] = {
2203         /* RX, TX */
2204         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
2205 };
2206 static const unsigned int scif1_data_mux[] = {
2207         SCIF1_RXD_MARK, SCIF1_TXD_MARK,
2208 };
2209 static const unsigned int scif1_clk_pins[] = {
2210         /* SCK */
2211         RCAR_GP_PIN(4, 13),
2212 };
2213 static const unsigned int scif1_clk_mux[] = {
2214         SCIF1_SCK_MARK,
2215 };
2216 static const unsigned int scif1_data_b_pins[] = {
2217         /* RX, TX */
2218         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
2219 };
2220 static const unsigned int scif1_data_b_mux[] = {
2221         SCIF1_RXD_B_MARK, SCIF1_TXD_B_MARK,
2222 };
2223 static const unsigned int scif1_clk_b_pins[] = {
2224         /* SCK */
2225         RCAR_GP_PIN(5, 10),
2226 };
2227 static const unsigned int scif1_clk_b_mux[] = {
2228         SCIF1_SCK_B_MARK,
2229 };
2230 static const unsigned int scif1_data_c_pins[] = {
2231         /* RX, TX */
2232         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
2233 };
2234 static const unsigned int scif1_data_c_mux[] = {
2235         SCIF1_RXD_C_MARK, SCIF1_TXD_C_MARK,
2236 };
2237 static const unsigned int scif1_clk_c_pins[] = {
2238         /* SCK */
2239         RCAR_GP_PIN(0, 10),
2240 };
2241 static const unsigned int scif1_clk_c_mux[] = {
2242         SCIF1_SCK_C_MARK,
2243 };
2244 /* - SCIF2 ------------------------------------------------------------------ */
2245 static const unsigned int scif2_data_pins[] = {
2246         /* RX, TX */
2247         RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2248 };
2249 static const unsigned int scif2_data_mux[] = {
2250         SCIF2_RXD_MARK, SCIF2_TXD_MARK,
2251 };
2252 static const unsigned int scif2_clk_pins[] = {
2253         /* SCK */
2254         RCAR_GP_PIN(4, 18),
2255 };
2256 static const unsigned int scif2_clk_mux[] = {
2257         SCIF2_SCK_MARK,
2258 };
2259 static const unsigned int scif2_data_b_pins[] = {
2260         /* RX, TX */
2261         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
2262 };
2263 static const unsigned int scif2_data_b_mux[] = {
2264         SCIF2_RXD_B_MARK, SCIF2_TXD_B_MARK,
2265 };
2266 static const unsigned int scif2_clk_b_pins[] = {
2267         /* SCK */
2268         RCAR_GP_PIN(5, 17),
2269 };
2270 static const unsigned int scif2_clk_b_mux[] = {
2271         SCIF2_SCK_B_MARK,
2272 };
2273 static const unsigned int scif2_data_c_pins[] = {
2274         /* RX, TX */
2275         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2276 };
2277 static const unsigned int scif2_data_c_mux[] = {
2278         SCIF2_RXD_C_MARK, SCIF2_TXD_C_MARK,
2279 };
2280 static const unsigned int scif2_clk_c_pins[] = {
2281         /* SCK */
2282         RCAR_GP_PIN(3, 19),
2283 };
2284 static const unsigned int scif2_clk_c_mux[] = {
2285         SCIF2_SCK_C_MARK,
2286 };
2287 /* - SCIF3 ------------------------------------------------------------------ */
2288 static const unsigned int scif3_data_pins[] = {
2289         /* RX, TX */
2290         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
2291 };
2292 static const unsigned int scif3_data_mux[] = {
2293         SCIF3_RXD_MARK, SCIF3_TXD_MARK,
2294 };
2295 static const unsigned int scif3_clk_pins[] = {
2296         /* SCK */
2297         RCAR_GP_PIN(4, 19),
2298 };
2299 static const unsigned int scif3_clk_mux[] = {
2300         SCIF3_SCK_MARK,
2301 };
2302 static const unsigned int scif3_data_b_pins[] = {
2303         /* RX, TX */
2304         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
2305 };
2306 static const unsigned int scif3_data_b_mux[] = {
2307         SCIF3_RXD_B_MARK, SCIF3_TXD_B_MARK,
2308 };
2309 static const unsigned int scif3_clk_b_pins[] = {
2310         /* SCK */
2311         RCAR_GP_PIN(3, 22),
2312 };
2313 static const unsigned int scif3_clk_b_mux[] = {
2314         SCIF3_SCK_B_MARK,
2315 };
2316 /* - SCIF4 ------------------------------------------------------------------ */
2317 static const unsigned int scif4_data_pins[] = {
2318         /* RX, TX */
2319         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2320 };
2321 static const unsigned int scif4_data_mux[] = {
2322         SCIF4_RXD_MARK, SCIF4_TXD_MARK,
2323 };
2324 static const unsigned int scif4_data_b_pins[] = {
2325         /* RX, TX */
2326         RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2327 };
2328 static const unsigned int scif4_data_b_mux[] = {
2329         SCIF4_RXD_B_MARK, SCIF4_TXD_B_MARK,
2330 };
2331 static const unsigned int scif4_data_c_pins[] = {
2332         /* RX, TX */
2333         RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
2334 };
2335 static const unsigned int scif4_data_c_mux[] = {
2336         SCIF4_RXD_C_MARK, SCIF4_TXD_C_MARK,
2337 };
2338 static const unsigned int scif4_data_d_pins[] = {
2339         /* RX, TX */
2340         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
2341 };
2342 static const unsigned int scif4_data_d_mux[] = {
2343         SCIF4_RXD_D_MARK, SCIF4_TXD_D_MARK,
2344 };
2345 static const unsigned int scif4_data_e_pins[] = {
2346         /* RX, TX */
2347         RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
2348 };
2349 static const unsigned int scif4_data_e_mux[] = {
2350         SCIF4_RXD_E_MARK, SCIF4_TXD_E_MARK,
2351 };
2352 /* - SCIF5 ------------------------------------------------------------------ */
2353 static const unsigned int scif5_data_pins[] = {
2354         /* RX, TX */
2355         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2356 };
2357 static const unsigned int scif5_data_mux[] = {
2358         SCIF5_RXD_MARK, SCIF5_TXD_MARK,
2359 };
2360 static const unsigned int scif5_data_b_pins[] = {
2361         /* RX, TX */
2362         RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
2363 };
2364 static const unsigned int scif5_data_b_mux[] = {
2365         SCIF5_RXD_B_MARK, SCIF5_TXD_B_MARK,
2366 };
2367 static const unsigned int scif5_data_c_pins[] = {
2368         /* RX, TX */
2369         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 11),
2370 };
2371 static const unsigned int scif5_data_c_mux[] = {
2372         SCIF5_RXD_C_MARK, SCIF5_TXD_C_MARK,
2373 };
2374 static const unsigned int scif5_data_d_pins[] = {
2375         /* RX, TX */
2376         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2377 };
2378 static const unsigned int scif5_data_d_mux[] = {
2379         SCIF5_RXD_D_MARK, SCIF5_TXD_D_MARK,
2380 };
2381 /* - SCIFA0 ----------------------------------------------------------------- */
2382 static const unsigned int scifa0_data_pins[] = {
2383         /* RXD, TXD */
2384         RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
2385 };
2386 static const unsigned int scifa0_data_mux[] = {
2387         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2388 };
2389 static const unsigned int scifa0_data_b_pins[] = {
2390         /* RXD, TXD */
2391         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2392 };
2393 static const unsigned int scifa0_data_b_mux[] = {
2394         SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2395 };
2396 static const unsigned int scifa0_data_c_pins[] = {
2397         /* RXD, TXD */
2398         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
2399 };
2400 static const unsigned int scifa0_data_c_mux[] = {
2401         SCIFA0_RXD_C_MARK, SCIFA0_TXD_C_MARK
2402 };
2403 static const unsigned int scifa0_data_d_pins[] = {
2404         /* RXD, TXD */
2405         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2406 };
2407 static const unsigned int scifa0_data_d_mux[] = {
2408         SCIFA0_RXD_D_MARK, SCIFA0_TXD_D_MARK
2409 };
2410 /* - SCIFA1 ----------------------------------------------------------------- */
2411 static const unsigned int scifa1_data_pins[] = {
2412         /* RXD, TXD */
2413         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2414 };
2415 static const unsigned int scifa1_data_mux[] = {
2416         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2417 };
2418 static const unsigned int scifa1_clk_pins[] = {
2419         /* SCK */
2420         RCAR_GP_PIN(0, 13),
2421 };
2422 static const unsigned int scifa1_clk_mux[] = {
2423         SCIFA1_SCK_MARK,
2424 };
2425 static const unsigned int scifa1_data_b_pins[] = {
2426         /* RXD, TXD */
2427         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2428 };
2429 static const unsigned int scifa1_data_b_mux[] = {
2430         SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2431 };
2432 static const unsigned int scifa1_clk_b_pins[] = {
2433         /* SCK */
2434         RCAR_GP_PIN(4, 27),
2435 };
2436 static const unsigned int scifa1_clk_b_mux[] = {
2437         SCIFA1_SCK_B_MARK,
2438 };
2439 static const unsigned int scifa1_data_c_pins[] = {
2440         /* RXD, TXD */
2441         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2442 };
2443 static const unsigned int scifa1_data_c_mux[] = {
2444         SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2445 };
2446 static const unsigned int scifa1_clk_c_pins[] = {
2447         /* SCK */
2448         RCAR_GP_PIN(5, 4),
2449 };
2450 static const unsigned int scifa1_clk_c_mux[] = {
2451         SCIFA1_SCK_C_MARK,
2452 };
2453 /* - SCIFA2 ----------------------------------------------------------------- */
2454 static const unsigned int scifa2_data_pins[] = {
2455         /* RXD, TXD */
2456         RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2457 };
2458 static const unsigned int scifa2_data_mux[] = {
2459         SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2460 };
2461 static const unsigned int scifa2_clk_pins[] = {
2462         /* SCK */
2463         RCAR_GP_PIN(1, 15),
2464 };
2465 static const unsigned int scifa2_clk_mux[] = {
2466         SCIFA2_SCK_MARK,
2467 };
2468 static const unsigned int scifa2_data_b_pins[] = {
2469         /* RXD, TXD */
2470         RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 0),
2471 };
2472 static const unsigned int scifa2_data_b_mux[] = {
2473         SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
2474 };
2475 static const unsigned int scifa2_clk_b_pins[] = {
2476         /* SCK */
2477         RCAR_GP_PIN(4, 30),
2478 };
2479 static const unsigned int scifa2_clk_b_mux[] = {
2480         SCIFA2_SCK_B_MARK,
2481 };
2482 /* - SCIFA3 ----------------------------------------------------------------- */
2483 static const unsigned int scifa3_data_pins[] = {
2484         /* RXD, TXD */
2485         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2486 };
2487 static const unsigned int scifa3_data_mux[] = {
2488         SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
2489 };
2490 static const unsigned int scifa3_clk_pins[] = {
2491         /* SCK */
2492         RCAR_GP_PIN(4, 24),
2493 };
2494 static const unsigned int scifa3_clk_mux[] = {
2495         SCIFA3_SCK_MARK,
2496 };
2497 static const unsigned int scifa3_data_b_pins[] = {
2498         /* RXD, TXD */
2499         RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
2500 };
2501 static const unsigned int scifa3_data_b_mux[] = {
2502         SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
2503 };
2504 static const unsigned int scifa3_clk_b_pins[] = {
2505         /* SCK */
2506         RCAR_GP_PIN(0, 0),
2507 };
2508 static const unsigned int scifa3_clk_b_mux[] = {
2509         SCIFA3_SCK_B_MARK,
2510 };
2511 /* - SCIFA4 ----------------------------------------------------------------- */
2512 static const unsigned int scifa4_data_pins[] = {
2513         /* RXD, TXD */
2514         RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 12),
2515 };
2516 static const unsigned int scifa4_data_mux[] = {
2517         SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
2518 };
2519 static const unsigned int scifa4_data_b_pins[] = {
2520         /* RXD, TXD */
2521         RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 23),
2522 };
2523 static const unsigned int scifa4_data_b_mux[] = {
2524         SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
2525 };
2526 static const unsigned int scifa4_data_c_pins[] = {
2527         /* RXD, TXD */
2528         RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
2529 };
2530 static const unsigned int scifa4_data_c_mux[] = {
2531         SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
2532 };
2533 static const unsigned int scifa4_data_d_pins[] = {
2534         /* RXD, TXD */
2535         RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
2536 };
2537 static const unsigned int scifa4_data_d_mux[] = {
2538         SCIFA4_RXD_D_MARK, SCIFA4_TXD_D_MARK,
2539 };
2540 /* - SCIFA5 ----------------------------------------------------------------- */
2541 static const unsigned int scifa5_data_pins[] = {
2542         /* RXD, TXD */
2543         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
2544 };
2545 static const unsigned int scifa5_data_mux[] = {
2546         SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
2547 };
2548 static const unsigned int scifa5_data_b_pins[] = {
2549         /* RXD, TXD */
2550         RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 29),
2551 };
2552 static const unsigned int scifa5_data_b_mux[] = {
2553         SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
2554 };
2555 static const unsigned int scifa5_data_c_pins[] = {
2556         /* RXD, TXD */
2557         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
2558 };
2559 static const unsigned int scifa5_data_c_mux[] = {
2560         SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
2561 };
2562 static const unsigned int scifa5_data_d_pins[] = {
2563         /* RXD, TXD */
2564         RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
2565 };
2566 static const unsigned int scifa5_data_d_mux[] = {
2567         SCIFA5_RXD_D_MARK, SCIFA5_TXD_D_MARK,
2568 };
2569 /* - SCIFB0 ----------------------------------------------------------------- */
2570 static const unsigned int scifb0_data_pins[] = {
2571         /* RXD, TXD */
2572         RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 20),
2573 };
2574 static const unsigned int scifb0_data_mux[] = {
2575         SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
2576 };
2577 static const unsigned int scifb0_clk_pins[] = {
2578         /* SCK */
2579         RCAR_GP_PIN(0, 19),
2580 };
2581 static const unsigned int scifb0_clk_mux[] = {
2582         SCIFB0_SCK_MARK,
2583 };
2584 static const unsigned int scifb0_ctrl_pins[] = {
2585         /* RTS, CTS */
2586         RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22),
2587 };
2588 static const unsigned int scifb0_ctrl_mux[] = {
2589         SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
2590 };
2591 /* - SCIFB1 ----------------------------------------------------------------- */
2592 static const unsigned int scifb1_data_pins[] = {
2593         /* RXD, TXD */
2594         RCAR_GP_PIN(1, 24), RCAR_GP_PIN(0, 17),
2595 };
2596 static const unsigned int scifb1_data_mux[] = {
2597         SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
2598 };
2599 static const unsigned int scifb1_clk_pins[] = {
2600         /* SCK */
2601         RCAR_GP_PIN(0, 16),
2602 };
2603 static const unsigned int scifb1_clk_mux[] = {
2604         SCIFB1_SCK_MARK,
2605 };
2606 /* - SCIFB2 ----------------------------------------------------------------- */
2607 static const unsigned int scifb2_data_pins[] = {
2608         /* RXD, TXD */
2609         RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
2610 };
2611 static const unsigned int scifb2_data_mux[] = {
2612         SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
2613 };
2614 static const unsigned int scifb2_clk_pins[] = {
2615         /* SCK */
2616         RCAR_GP_PIN(1, 15),
2617 };
2618 static const unsigned int scifb2_clk_mux[] = {
2619         SCIFB2_SCK_MARK,
2620 };
2621 static const unsigned int scifb2_ctrl_pins[] = {
2622         /* RTS, CTS */
2623         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2624 };
2625 static const unsigned int scifb2_ctrl_mux[] = {
2626         SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
2627 };
2628 /* - SCIF Clock ------------------------------------------------------------- */
2629 static const unsigned int scif_clk_pins[] = {
2630         /* SCIF_CLK */
2631         RCAR_GP_PIN(1, 23),
2632 };
2633 static const unsigned int scif_clk_mux[] = {
2634         SCIF_CLK_MARK,
2635 };
2636 static const unsigned int scif_clk_b_pins[] = {
2637         /* SCIF_CLK */
2638         RCAR_GP_PIN(3, 29),
2639 };
2640 static const unsigned int scif_clk_b_mux[] = {
2641         SCIF_CLK_B_MARK,
2642 };
2643 /* - SDHI0 ------------------------------------------------------------------ */
2644 static const unsigned int sdhi0_data1_pins[] = {
2645         /* D0 */
2646         RCAR_GP_PIN(6, 2),
2647 };
2648 static const unsigned int sdhi0_data1_mux[] = {
2649         SD0_DATA0_MARK,
2650 };
2651 static const unsigned int sdhi0_data4_pins[] = {
2652         /* D[0:3] */
2653         RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
2654         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
2655 };
2656 static const unsigned int sdhi0_data4_mux[] = {
2657         SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
2658 };
2659 static const unsigned int sdhi0_ctrl_pins[] = {
2660         /* CLK, CMD */
2661         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
2662 };
2663 static const unsigned int sdhi0_ctrl_mux[] = {
2664         SD0_CLK_MARK, SD0_CMD_MARK,
2665 };
2666 static const unsigned int sdhi0_cd_pins[] = {
2667         /* CD */
2668         RCAR_GP_PIN(6, 6),
2669 };
2670 static const unsigned int sdhi0_cd_mux[] = {
2671         SD0_CD_MARK,
2672 };
2673 static const unsigned int sdhi0_wp_pins[] = {
2674         /* WP */
2675         RCAR_GP_PIN(6, 7),
2676 };
2677 static const unsigned int sdhi0_wp_mux[] = {
2678         SD0_WP_MARK,
2679 };
2680 /* - SDHI1 ------------------------------------------------------------------ */
2681 static const unsigned int sdhi1_data1_pins[] = {
2682         /* D0 */
2683         RCAR_GP_PIN(6, 10),
2684 };
2685 static const unsigned int sdhi1_data1_mux[] = {
2686         SD1_DATA0_MARK,
2687 };
2688 static const unsigned int sdhi1_data4_pins[] = {
2689         /* D[0:3] */
2690         RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
2691         RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
2692 };
2693 static const unsigned int sdhi1_data4_mux[] = {
2694         SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
2695 };
2696 static const unsigned int sdhi1_ctrl_pins[] = {
2697         /* CLK, CMD */
2698         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2699 };
2700 static const unsigned int sdhi1_ctrl_mux[] = {
2701         SD1_CLK_MARK, SD1_CMD_MARK,
2702 };
2703 static const unsigned int sdhi1_cd_pins[] = {
2704         /* CD */
2705         RCAR_GP_PIN(6, 14),
2706 };
2707 static const unsigned int sdhi1_cd_mux[] = {
2708         SD1_CD_MARK,
2709 };
2710 static const unsigned int sdhi1_wp_pins[] = {
2711         /* WP */
2712         RCAR_GP_PIN(6, 15),
2713 };
2714 static const unsigned int sdhi1_wp_mux[] = {
2715         SD1_WP_MARK,
2716 };
2717 /* - SDHI2 ------------------------------------------------------------------ */
2718 static const unsigned int sdhi2_data1_pins[] = {
2719         /* D0 */
2720         RCAR_GP_PIN(6, 18),
2721 };
2722 static const unsigned int sdhi2_data1_mux[] = {
2723         SD2_DATA0_MARK,
2724 };
2725 static const unsigned int sdhi2_data4_pins[] = {
2726         /* D[0:3] */
2727         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2728         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2729 };
2730 static const unsigned int sdhi2_data4_mux[] = {
2731         SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
2732 };
2733 static const unsigned int sdhi2_ctrl_pins[] = {
2734         /* CLK, CMD */
2735         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2736 };
2737 static const unsigned int sdhi2_ctrl_mux[] = {
2738         SD2_CLK_MARK, SD2_CMD_MARK,
2739 };
2740 static const unsigned int sdhi2_cd_pins[] = {
2741         /* CD */
2742         RCAR_GP_PIN(6, 22),
2743 };
2744 static const unsigned int sdhi2_cd_mux[] = {
2745         SD2_CD_MARK,
2746 };
2747 static const unsigned int sdhi2_wp_pins[] = {
2748         /* WP */
2749         RCAR_GP_PIN(6, 23),
2750 };
2751 static const unsigned int sdhi2_wp_mux[] = {
2752         SD2_WP_MARK,
2753 };
2754 /* - SSI -------------------------------------------------------------------- */
2755 static const unsigned int ssi0_data_pins[] = {
2756         /* SDATA0 */
2757         RCAR_GP_PIN(5, 3),
2758 };
2759 static const unsigned int ssi0_data_mux[] = {
2760         SSI_SDATA0_MARK,
2761 };
2762 static const unsigned int ssi0129_ctrl_pins[] = {
2763         /* SCK0129, WS0129 */
2764         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2765 };
2766 static const unsigned int ssi0129_ctrl_mux[] = {
2767         SSI_SCK0129_MARK, SSI_WS0129_MARK,
2768 };
2769 static const unsigned int ssi1_data_pins[] = {
2770         /* SDATA1 */
2771         RCAR_GP_PIN(5, 13),
2772 };
2773 static const unsigned int ssi1_data_mux[] = {
2774         SSI_SDATA1_MARK,
2775 };
2776 static const unsigned int ssi1_ctrl_pins[] = {
2777         /* SCK1, WS1 */
2778         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
2779 };
2780 static const unsigned int ssi1_ctrl_mux[] = {
2781         SSI_SCK1_MARK, SSI_WS1_MARK,
2782 };
2783 static const unsigned int ssi1_data_b_pins[] = {
2784         /* SDATA1 */
2785         RCAR_GP_PIN(4, 13),
2786 };
2787 static const unsigned int ssi1_data_b_mux[] = {
2788         SSI_SDATA1_B_MARK,
2789 };
2790 static const unsigned int ssi1_ctrl_b_pins[] = {
2791         /* SCK1, WS1 */
2792         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
2793 };
2794 static const unsigned int ssi1_ctrl_b_mux[] = {
2795         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
2796 };
2797 static const unsigned int ssi2_data_pins[] = {
2798         /* SDATA2 */
2799         RCAR_GP_PIN(5, 16),
2800 };
2801 static const unsigned int ssi2_data_mux[] = {
2802         SSI_SDATA2_MARK,
2803 };
2804 static const unsigned int ssi2_ctrl_pins[] = {
2805         /* SCK2, WS2 */
2806         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
2807 };
2808 static const unsigned int ssi2_ctrl_mux[] = {
2809         SSI_SCK2_MARK, SSI_WS2_MARK,
2810 };
2811 static const unsigned int ssi2_data_b_pins[] = {
2812         /* SDATA2 */
2813         RCAR_GP_PIN(4, 16),
2814 };
2815 static const unsigned int ssi2_data_b_mux[] = {
2816         SSI_SDATA2_B_MARK,
2817 };
2818 static const unsigned int ssi2_ctrl_b_pins[] = {
2819         /* SCK2, WS2 */
2820         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
2821 };
2822 static const unsigned int ssi2_ctrl_b_mux[] = {
2823         SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
2824 };
2825 static const unsigned int ssi3_data_pins[] = {
2826         /* SDATA3 */
2827         RCAR_GP_PIN(5, 6),
2828 };
2829 static const unsigned int ssi3_data_mux[] = {
2830         SSI_SDATA3_MARK
2831 };
2832 static const unsigned int ssi34_ctrl_pins[] = {
2833         /* SCK34, WS34 */
2834         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
2835 };
2836 static const unsigned int ssi34_ctrl_mux[] = {
2837         SSI_SCK34_MARK, SSI_WS34_MARK,
2838 };
2839 static const unsigned int ssi4_data_pins[] = {
2840         /* SDATA4 */
2841         RCAR_GP_PIN(5, 9),
2842 };
2843 static const unsigned int ssi4_data_mux[] = {
2844         SSI_SDATA4_MARK,
2845 };
2846 static const unsigned int ssi4_ctrl_pins[] = {
2847         /* SCK4, WS4 */
2848         RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
2849 };
2850 static const unsigned int ssi4_ctrl_mux[] = {
2851         SSI_SCK4_MARK, SSI_WS4_MARK,
2852 };
2853 static const unsigned int ssi4_data_b_pins[] = {
2854         /* SDATA4 */
2855         RCAR_GP_PIN(4, 22),
2856 };
2857 static const unsigned int ssi4_data_b_mux[] = {
2858         SSI_SDATA4_B_MARK,
2859 };
2860 static const unsigned int ssi4_ctrl_b_pins[] = {
2861         /* SCK4, WS4 */
2862         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
2863 };
2864 static const unsigned int ssi4_ctrl_b_mux[] = {
2865         SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
2866 };
2867 static const unsigned int ssi5_data_pins[] = {
2868         /* SDATA5 */
2869         RCAR_GP_PIN(4, 26),
2870 };
2871 static const unsigned int ssi5_data_mux[] = {
2872         SSI_SDATA5_MARK,
2873 };
2874 static const unsigned int ssi5_ctrl_pins[] = {
2875         /* SCK5, WS5 */
2876         RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
2877 };
2878 static const unsigned int ssi5_ctrl_mux[] = {
2879         SSI_SCK5_MARK, SSI_WS5_MARK,
2880 };
2881 static const unsigned int ssi5_data_b_pins[] = {
2882         /* SDATA5 */
2883         RCAR_GP_PIN(3, 21),
2884 };
2885 static const unsigned int ssi5_data_b_mux[] = {
2886         SSI_SDATA5_B_MARK,
2887 };
2888 static const unsigned int ssi5_ctrl_b_pins[] = {
2889         /* SCK5, WS5 */
2890         RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
2891 };
2892 static const unsigned int ssi5_ctrl_b_mux[] = {
2893         SSI_SCK5_B_MARK, SSI_WS5_B_MARK,
2894 };
2895 static const unsigned int ssi6_data_pins[] = {
2896         /* SDATA6 */
2897         RCAR_GP_PIN(4, 29),
2898 };
2899 static const unsigned int ssi6_data_mux[] = {
2900         SSI_SDATA6_MARK,
2901 };
2902 static const unsigned int ssi6_ctrl_pins[] = {
2903         /* SCK6, WS6 */
2904         RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
2905 };
2906 static const unsigned int ssi6_ctrl_mux[] = {
2907         SSI_SCK6_MARK, SSI_WS6_MARK,
2908 };
2909 static const unsigned int ssi6_data_b_pins[] = {
2910         /* SDATA6 */
2911         RCAR_GP_PIN(3, 24),
2912 };
2913 static const unsigned int ssi6_data_b_mux[] = {
2914         SSI_SDATA6_B_MARK,
2915 };
2916 static const unsigned int ssi6_ctrl_b_pins[] = {
2917         /* SCK6, WS6 */
2918         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2919 };
2920 static const unsigned int ssi6_ctrl_b_mux[] = {
2921         SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
2922 };
2923 static const unsigned int ssi7_data_pins[] = {
2924         /* SDATA7 */
2925         RCAR_GP_PIN(5, 0),
2926 };
2927 static const unsigned int ssi7_data_mux[] = {
2928         SSI_SDATA7_MARK,
2929 };
2930 static const unsigned int ssi78_ctrl_pins[] = {
2931         /* SCK78, WS78 */
2932         RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 31),
2933 };
2934 static const unsigned int ssi78_ctrl_mux[] = {
2935         SSI_SCK78_MARK, SSI_WS78_MARK,
2936 };
2937 static const unsigned int ssi7_data_b_pins[] = {
2938         /* SDATA7 */
2939         RCAR_GP_PIN(3, 27),
2940 };
2941 static const unsigned int ssi7_data_b_mux[] = {
2942         SSI_SDATA7_B_MARK,
2943 };
2944 static const unsigned int ssi78_ctrl_b_pins[] = {
2945         /* SCK78, WS78 */
2946         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
2947 };
2948 static const unsigned int ssi78_ctrl_b_mux[] = {
2949         SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
2950 };
2951 static const unsigned int ssi8_data_pins[] = {
2952         /* SDATA8 */
2953         RCAR_GP_PIN(5, 10),
2954 };
2955 static const unsigned int ssi8_data_mux[] = {
2956         SSI_SDATA8_MARK,
2957 };
2958 static const unsigned int ssi8_data_b_pins[] = {
2959         /* SDATA8 */
2960         RCAR_GP_PIN(3, 28),
2961 };
2962 static const unsigned int ssi8_data_b_mux[] = {
2963         SSI_SDATA8_B_MARK,
2964 };
2965 static const unsigned int ssi9_data_pins[] = {
2966         /* SDATA9 */
2967         RCAR_GP_PIN(5, 19),
2968 };
2969 static const unsigned int ssi9_data_mux[] = {
2970         SSI_SDATA9_MARK,
2971 };
2972 static const unsigned int ssi9_ctrl_pins[] = {
2973         /* SCK9, WS9 */
2974         RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
2975 };
2976 static const unsigned int ssi9_ctrl_mux[] = {
2977         SSI_SCK9_MARK, SSI_WS9_MARK,
2978 };
2979 static const unsigned int ssi9_data_b_pins[] = {
2980         /* SDATA9 */
2981         RCAR_GP_PIN(4, 19),
2982 };
2983 static const unsigned int ssi9_data_b_mux[] = {
2984         SSI_SDATA9_B_MARK,
2985 };
2986 static const unsigned int ssi9_ctrl_b_pins[] = {
2987         /* SCK9, WS9 */
2988         RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
2989 };
2990 static const unsigned int ssi9_ctrl_b_mux[] = {
2991         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
2992 };
2993 /* - USB0 ------------------------------------------------------------------- */
2994 static const unsigned int usb0_pins[] = {
2995         RCAR_GP_PIN(5, 24), /* PWEN */
2996         RCAR_GP_PIN(5, 25), /* OVC */
2997 };
2998 static const unsigned int usb0_mux[] = {
2999         USB0_PWEN_MARK,
3000         USB0_OVC_MARK,
3001 };
3002 /* - USB1 ------------------------------------------------------------------- */
3003 static const unsigned int usb1_pins[] = {
3004         RCAR_GP_PIN(5, 26), /* PWEN */
3005         RCAR_GP_PIN(5, 27), /* OVC */
3006 };
3007 static const unsigned int usb1_mux[] = {
3008         USB1_PWEN_MARK,
3009         USB1_OVC_MARK,
3010 };
3011 /* - VIN0 ------------------------------------------------------------------- */
3012 static const union vin_data vin0_data_pins = {
3013         .data24 = {
3014                 /* B */
3015                 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
3016                 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
3017                 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3018                 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
3019                 /* G */
3020                 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
3021                 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
3022                 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
3023                 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3024                 /* R */
3025                 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22),
3026                 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
3027                 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3028                 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
3029         },
3030 };
3031 static const union vin_data vin0_data_mux = {
3032         .data24 = {
3033                 /* B */
3034                 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3035                 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3036                 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3037                 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3038                 /* G */
3039                 VI0_G0_MARK, VI0_G1_MARK,
3040                 VI0_G2_MARK, VI0_G3_MARK,
3041                 VI0_G4_MARK, VI0_G5_MARK,
3042                 VI0_G6_MARK, VI0_G7_MARK,
3043                 /* R */
3044                 VI0_R0_MARK, VI0_R1_MARK,
3045                 VI0_R2_MARK, VI0_R3_MARK,
3046                 VI0_R4_MARK, VI0_R5_MARK,
3047                 VI0_R6_MARK, VI0_R7_MARK,
3048         },
3049 };
3050 static const unsigned int vin0_data18_pins[] = {
3051         /* B */
3052         RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
3053         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3054         RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
3055         /* G */
3056         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
3057         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
3058         RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3059         /* R */
3060         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
3061         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3062         RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
3063 };
3064 static const unsigned int vin0_data18_mux[] = {
3065         /* B */
3066         VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3067         VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3068         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3069         /* G */
3070         VI0_G2_MARK, VI0_G3_MARK,
3071         VI0_G4_MARK, VI0_G5_MARK,
3072         VI0_G6_MARK, VI0_G7_MARK,
3073         /* R */
3074         VI0_R2_MARK, VI0_R3_MARK,
3075         VI0_R4_MARK, VI0_R5_MARK,
3076         VI0_R6_MARK, VI0_R7_MARK,
3077 };
3078 static const unsigned int vin0_sync_pins[] = {
3079         RCAR_GP_PIN(3, 11), /* HSYNC */
3080         RCAR_GP_PIN(3, 12), /* VSYNC */
3081 };
3082 static const unsigned int vin0_sync_mux[] = {
3083         VI0_HSYNC_N_MARK,
3084         VI0_VSYNC_N_MARK,
3085 };
3086 static const unsigned int vin0_field_pins[] = {
3087         RCAR_GP_PIN(3, 10),
3088 };
3089 static const unsigned int vin0_field_mux[] = {
3090         VI0_FIELD_MARK,
3091 };
3092 static const unsigned int vin0_clkenb_pins[] = {
3093         RCAR_GP_PIN(3, 9),
3094 };
3095 static const unsigned int vin0_clkenb_mux[] = {
3096         VI0_CLKENB_MARK,
3097 };
3098 static const unsigned int vin0_clk_pins[] = {
3099         RCAR_GP_PIN(3, 0),
3100 };
3101 static const unsigned int vin0_clk_mux[] = {
3102         VI0_CLK_MARK,
3103 };
3104 /* - VIN1 ------------------------------------------------------------------- */
3105 static const union vin_data vin1_data_pins = {
3106         .data12 = {
3107                 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
3108                 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
3109                 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17),
3110                 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
3111                 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
3112                 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3113         },
3114 };
3115 static const union vin_data vin1_data_mux = {
3116         .data12 = {
3117                 VI1_DATA0_MARK, VI1_DATA1_MARK,
3118                 VI1_DATA2_MARK, VI1_DATA3_MARK,
3119                 VI1_DATA4_MARK, VI1_DATA5_MARK,
3120                 VI1_DATA6_MARK, VI1_DATA7_MARK,
3121                 VI1_DATA8_MARK, VI1_DATA9_MARK,
3122                 VI1_DATA10_MARK, VI1_DATA11_MARK,
3123         },
3124 };
3125 static const unsigned int vin1_sync_pins[] = {
3126         RCAR_GP_PIN(5, 22), /* HSYNC */
3127         RCAR_GP_PIN(5, 23), /* VSYNC */
3128 };
3129 static const unsigned int vin1_sync_mux[] = {
3130         VI1_HSYNC_N_MARK,
3131         VI1_VSYNC_N_MARK,
3132 };
3133 static const unsigned int vin1_field_pins[] = {
3134         RCAR_GP_PIN(5, 21),
3135 };
3136 static const unsigned int vin1_field_mux[] = {
3137         VI1_FIELD_MARK,
3138 };
3139 static const unsigned int vin1_clkenb_pins[] = {
3140         RCAR_GP_PIN(5, 20),
3141 };
3142 static const unsigned int vin1_clkenb_mux[] = {
3143         VI1_CLKENB_MARK,
3144 };
3145 static const unsigned int vin1_clk_pins[] = {
3146         RCAR_GP_PIN(5, 11),
3147 };
3148 static const unsigned int vin1_clk_mux[] = {
3149         VI1_CLK_MARK,
3150 };
3151
3152 static const struct sh_pfc_pin_group pinmux_groups[] = {
3153         SH_PFC_PIN_GROUP(eth_link),
3154         SH_PFC_PIN_GROUP(eth_magic),
3155         SH_PFC_PIN_GROUP(eth_mdio),
3156         SH_PFC_PIN_GROUP(eth_rmii),
3157         SH_PFC_PIN_GROUP(eth_link_b),
3158         SH_PFC_PIN_GROUP(eth_magic_b),
3159         SH_PFC_PIN_GROUP(eth_mdio_b),
3160         SH_PFC_PIN_GROUP(eth_rmii_b),
3161         SH_PFC_PIN_GROUP(hscif0_data),
3162         SH_PFC_PIN_GROUP(hscif0_clk),
3163         SH_PFC_PIN_GROUP(hscif0_ctrl),
3164         SH_PFC_PIN_GROUP(hscif0_data_b),
3165         SH_PFC_PIN_GROUP(hscif0_clk_b),
3166         SH_PFC_PIN_GROUP(hscif1_data),
3167         SH_PFC_PIN_GROUP(hscif1_clk),
3168         SH_PFC_PIN_GROUP(hscif1_ctrl),
3169         SH_PFC_PIN_GROUP(hscif1_data_b),
3170         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3171         SH_PFC_PIN_GROUP(hscif2_data),
3172         SH_PFC_PIN_GROUP(hscif2_clk),
3173         SH_PFC_PIN_GROUP(hscif2_ctrl),
3174         SH_PFC_PIN_GROUP(i2c0),
3175         SH_PFC_PIN_GROUP(i2c0_b),
3176         SH_PFC_PIN_GROUP(i2c0_c),
3177         SH_PFC_PIN_GROUP(i2c0_d),
3178         SH_PFC_PIN_GROUP(i2c0_e),
3179         SH_PFC_PIN_GROUP(i2c1),
3180         SH_PFC_PIN_GROUP(i2c1_b),
3181         SH_PFC_PIN_GROUP(i2c1_c),
3182         SH_PFC_PIN_GROUP(i2c1_d),
3183         SH_PFC_PIN_GROUP(i2c1_e),
3184         SH_PFC_PIN_GROUP(i2c2),
3185         SH_PFC_PIN_GROUP(i2c2_b),
3186         SH_PFC_PIN_GROUP(i2c2_c),
3187         SH_PFC_PIN_GROUP(i2c2_d),
3188         SH_PFC_PIN_GROUP(i2c2_e),
3189         SH_PFC_PIN_GROUP(i2c3),
3190         SH_PFC_PIN_GROUP(i2c3_b),
3191         SH_PFC_PIN_GROUP(i2c3_c),
3192         SH_PFC_PIN_GROUP(i2c3_d),
3193         SH_PFC_PIN_GROUP(i2c3_e),
3194         SH_PFC_PIN_GROUP(i2c4),
3195         SH_PFC_PIN_GROUP(i2c4_b),
3196         SH_PFC_PIN_GROUP(i2c4_c),
3197         SH_PFC_PIN_GROUP(i2c4_d),
3198         SH_PFC_PIN_GROUP(i2c4_e),
3199         SH_PFC_PIN_GROUP(intc_irq0),
3200         SH_PFC_PIN_GROUP(intc_irq1),
3201         SH_PFC_PIN_GROUP(intc_irq2),
3202         SH_PFC_PIN_GROUP(intc_irq3),
3203         SH_PFC_PIN_GROUP(intc_irq4),
3204         SH_PFC_PIN_GROUP(intc_irq5),
3205         SH_PFC_PIN_GROUP(intc_irq6),
3206         SH_PFC_PIN_GROUP(intc_irq7),
3207         SH_PFC_PIN_GROUP(intc_irq8),
3208         SH_PFC_PIN_GROUP(intc_irq9),
3209         SH_PFC_PIN_GROUP(mmc_data1),
3210         SH_PFC_PIN_GROUP(mmc_data4),
3211         SH_PFC_PIN_GROUP(mmc_data8),
3212         SH_PFC_PIN_GROUP(mmc_ctrl),
3213         SH_PFC_PIN_GROUP(msiof0_clk),
3214         SH_PFC_PIN_GROUP(msiof0_sync),
3215         SH_PFC_PIN_GROUP(msiof0_ss1),
3216         SH_PFC_PIN_GROUP(msiof0_ss2),
3217         SH_PFC_PIN_GROUP(msiof0_rx),
3218         SH_PFC_PIN_GROUP(msiof0_tx),
3219         SH_PFC_PIN_GROUP(msiof1_clk),
3220         SH_PFC_PIN_GROUP(msiof1_sync),
3221         SH_PFC_PIN_GROUP(msiof1_ss1),
3222         SH_PFC_PIN_GROUP(msiof1_ss2),
3223         SH_PFC_PIN_GROUP(msiof1_rx),
3224         SH_PFC_PIN_GROUP(msiof1_tx),
3225         SH_PFC_PIN_GROUP(msiof1_clk_b),
3226         SH_PFC_PIN_GROUP(msiof1_sync_b),
3227         SH_PFC_PIN_GROUP(msiof1_ss1_b),
3228         SH_PFC_PIN_GROUP(msiof1_ss2_b),
3229         SH_PFC_PIN_GROUP(msiof1_rx_b),
3230         SH_PFC_PIN_GROUP(msiof1_tx_b),
3231         SH_PFC_PIN_GROUP(msiof2_clk),
3232         SH_PFC_PIN_GROUP(msiof2_sync),
3233         SH_PFC_PIN_GROUP(msiof2_ss1),
3234         SH_PFC_PIN_GROUP(msiof2_ss2),
3235         SH_PFC_PIN_GROUP(msiof2_rx),
3236         SH_PFC_PIN_GROUP(msiof2_tx),
3237         SH_PFC_PIN_GROUP(msiof2_clk_b),
3238         SH_PFC_PIN_GROUP(msiof2_sync_b),
3239         SH_PFC_PIN_GROUP(msiof2_ss1_b),
3240         SH_PFC_PIN_GROUP(msiof2_ss2_b),
3241         SH_PFC_PIN_GROUP(msiof2_rx_b),
3242         SH_PFC_PIN_GROUP(msiof2_tx_b),
3243         SH_PFC_PIN_GROUP(qspi_ctrl),
3244         SH_PFC_PIN_GROUP(qspi_data2),
3245         SH_PFC_PIN_GROUP(qspi_data4),
3246         SH_PFC_PIN_GROUP(scif0_data),
3247         SH_PFC_PIN_GROUP(scif0_data_b),
3248         SH_PFC_PIN_GROUP(scif0_data_c),
3249         SH_PFC_PIN_GROUP(scif0_data_d),
3250         SH_PFC_PIN_GROUP(scif1_data),
3251         SH_PFC_PIN_GROUP(scif1_clk),
3252         SH_PFC_PIN_GROUP(scif1_data_b),
3253         SH_PFC_PIN_GROUP(scif1_clk_b),
3254         SH_PFC_PIN_GROUP(scif1_data_c),
3255         SH_PFC_PIN_GROUP(scif1_clk_c),
3256         SH_PFC_PIN_GROUP(scif2_data),
3257         SH_PFC_PIN_GROUP(scif2_clk),
3258         SH_PFC_PIN_GROUP(scif2_data_b),
3259         SH_PFC_PIN_GROUP(scif2_clk_b),
3260         SH_PFC_PIN_GROUP(scif2_data_c),
3261         SH_PFC_PIN_GROUP(scif2_clk_c),
3262         SH_PFC_PIN_GROUP(scif3_data),
3263         SH_PFC_PIN_GROUP(scif3_clk),
3264         SH_PFC_PIN_GROUP(scif3_data_b),
3265         SH_PFC_PIN_GROUP(scif3_clk_b),
3266         SH_PFC_PIN_GROUP(scif4_data),
3267         SH_PFC_PIN_GROUP(scif4_data_b),
3268         SH_PFC_PIN_GROUP(scif4_data_c),
3269         SH_PFC_PIN_GROUP(scif4_data_d),
3270         SH_PFC_PIN_GROUP(scif4_data_e),
3271         SH_PFC_PIN_GROUP(scif5_data),
3272         SH_PFC_PIN_GROUP(scif5_data_b),
3273         SH_PFC_PIN_GROUP(scif5_data_c),
3274         SH_PFC_PIN_GROUP(scif5_data_d),
3275         SH_PFC_PIN_GROUP(scifa0_data),
3276         SH_PFC_PIN_GROUP(scifa0_data_b),
3277         SH_PFC_PIN_GROUP(scifa0_data_c),
3278         SH_PFC_PIN_GROUP(scifa0_data_d),
3279         SH_PFC_PIN_GROUP(scifa1_data),
3280         SH_PFC_PIN_GROUP(scifa1_clk),
3281         SH_PFC_PIN_GROUP(scifa1_data_b),
3282         SH_PFC_PIN_GROUP(scifa1_clk_b),
3283         SH_PFC_PIN_GROUP(scifa1_data_c),
3284         SH_PFC_PIN_GROUP(scifa1_clk_c),
3285         SH_PFC_PIN_GROUP(scifa2_data),
3286         SH_PFC_PIN_GROUP(scifa2_clk),
3287         SH_PFC_PIN_GROUP(scifa2_data_b),
3288         SH_PFC_PIN_GROUP(scifa2_clk_b),
3289         SH_PFC_PIN_GROUP(scifa3_data),
3290         SH_PFC_PIN_GROUP(scifa3_clk),
3291         SH_PFC_PIN_GROUP(scifa3_data_b),
3292         SH_PFC_PIN_GROUP(scifa3_clk_b),
3293         SH_PFC_PIN_GROUP(scifa4_data),
3294         SH_PFC_PIN_GROUP(scifa4_data_b),
3295         SH_PFC_PIN_GROUP(scifa4_data_c),
3296         SH_PFC_PIN_GROUP(scifa4_data_d),
3297         SH_PFC_PIN_GROUP(scifa5_data),
3298         SH_PFC_PIN_GROUP(scifa5_data_b),
3299         SH_PFC_PIN_GROUP(scifa5_data_c),
3300         SH_PFC_PIN_GROUP(scifa5_data_d),
3301         SH_PFC_PIN_GROUP(scifb0_data),
3302         SH_PFC_PIN_GROUP(scifb0_clk),
3303         SH_PFC_PIN_GROUP(scifb0_ctrl),
3304         SH_PFC_PIN_GROUP(scifb1_data),
3305         SH_PFC_PIN_GROUP(scifb1_clk),
3306         SH_PFC_PIN_GROUP(scifb2_data),
3307         SH_PFC_PIN_GROUP(scifb2_clk),
3308         SH_PFC_PIN_GROUP(scifb2_ctrl),
3309         SH_PFC_PIN_GROUP(scif_clk),
3310         SH_PFC_PIN_GROUP(scif_clk_b),
3311         SH_PFC_PIN_GROUP(sdhi0_data1),
3312         SH_PFC_PIN_GROUP(sdhi0_data4),
3313         SH_PFC_PIN_GROUP(sdhi0_ctrl),
3314         SH_PFC_PIN_GROUP(sdhi0_cd),
3315         SH_PFC_PIN_GROUP(sdhi0_wp),
3316         SH_PFC_PIN_GROUP(sdhi1_data1),
3317         SH_PFC_PIN_GROUP(sdhi1_data4),
3318         SH_PFC_PIN_GROUP(sdhi1_ctrl),
3319         SH_PFC_PIN_GROUP(sdhi1_cd),
3320         SH_PFC_PIN_GROUP(sdhi1_wp),
3321         SH_PFC_PIN_GROUP(sdhi2_data1),
3322         SH_PFC_PIN_GROUP(sdhi2_data4),
3323         SH_PFC_PIN_GROUP(sdhi2_ctrl),
3324         SH_PFC_PIN_GROUP(sdhi2_cd),
3325         SH_PFC_PIN_GROUP(sdhi2_wp),
3326         SH_PFC_PIN_GROUP(ssi0_data),
3327         SH_PFC_PIN_GROUP(ssi0129_ctrl),
3328         SH_PFC_PIN_GROUP(ssi1_data),
3329         SH_PFC_PIN_GROUP(ssi1_ctrl),
3330         SH_PFC_PIN_GROUP(ssi1_data_b),
3331         SH_PFC_PIN_GROUP(ssi1_ctrl_b),
3332         SH_PFC_PIN_GROUP(ssi2_data),
3333         SH_PFC_PIN_GROUP(ssi2_ctrl),
3334         SH_PFC_PIN_GROUP(ssi2_data_b),
3335         SH_PFC_PIN_GROUP(ssi2_ctrl_b),
3336         SH_PFC_PIN_GROUP(ssi3_data),
3337         SH_PFC_PIN_GROUP(ssi34_ctrl),
3338         SH_PFC_PIN_GROUP(ssi4_data),
3339         SH_PFC_PIN_GROUP(ssi4_ctrl),
3340         SH_PFC_PIN_GROUP(ssi4_data_b),
3341         SH_PFC_PIN_GROUP(ssi4_ctrl_b),
3342         SH_PFC_PIN_GROUP(ssi5_data),
3343         SH_PFC_PIN_GROUP(ssi5_ctrl),
3344         SH_PFC_PIN_GROUP(ssi5_data_b),
3345         SH_PFC_PIN_GROUP(ssi5_ctrl_b),
3346         SH_PFC_PIN_GROUP(ssi6_data),
3347         SH_PFC_PIN_GROUP(ssi6_ctrl),
3348         SH_PFC_PIN_GROUP(ssi6_data_b),
3349         SH_PFC_PIN_GROUP(ssi6_ctrl_b),
3350         SH_PFC_PIN_GROUP(ssi7_data),
3351         SH_PFC_PIN_GROUP(ssi78_ctrl),
3352         SH_PFC_PIN_GROUP(ssi7_data_b),
3353         SH_PFC_PIN_GROUP(ssi78_ctrl_b),
3354         SH_PFC_PIN_GROUP(ssi8_data),
3355         SH_PFC_PIN_GROUP(ssi8_data_b),
3356         SH_PFC_PIN_GROUP(ssi9_data),
3357         SH_PFC_PIN_GROUP(ssi9_ctrl),
3358         SH_PFC_PIN_GROUP(ssi9_data_b),
3359         SH_PFC_PIN_GROUP(ssi9_ctrl_b),
3360         SH_PFC_PIN_GROUP(usb0),
3361         SH_PFC_PIN_GROUP(usb1),
3362         VIN_DATA_PIN_GROUP(vin0_data, 24),
3363         VIN_DATA_PIN_GROUP(vin0_data, 20),
3364         SH_PFC_PIN_GROUP(vin0_data18),
3365         VIN_DATA_PIN_GROUP(vin0_data, 16),
3366         VIN_DATA_PIN_GROUP(vin0_data, 12),
3367         VIN_DATA_PIN_GROUP(vin0_data, 10),
3368         VIN_DATA_PIN_GROUP(vin0_data, 8),
3369         SH_PFC_PIN_GROUP(vin0_sync),
3370         SH_PFC_PIN_GROUP(vin0_field),
3371         SH_PFC_PIN_GROUP(vin0_clkenb),
3372         SH_PFC_PIN_GROUP(vin0_clk),
3373         VIN_DATA_PIN_GROUP(vin1_data, 12),
3374         VIN_DATA_PIN_GROUP(vin1_data, 10),
3375         VIN_DATA_PIN_GROUP(vin1_data, 8),
3376         SH_PFC_PIN_GROUP(vin1_sync),
3377         SH_PFC_PIN_GROUP(vin1_field),
3378         SH_PFC_PIN_GROUP(vin1_clkenb),
3379         SH_PFC_PIN_GROUP(vin1_clk),
3380 };
3381
3382 static const char * const eth_groups[] = {
3383         "eth_link",
3384         "eth_magic",
3385         "eth_mdio",
3386         "eth_rmii",
3387         "eth_link_b",
3388         "eth_magic_b",
3389         "eth_mdio_b",
3390         "eth_rmii_b",
3391 };
3392
3393 static const char * const hscif0_groups[] = {
3394         "hscif0_data",
3395         "hscif0_clk",
3396         "hscif0_ctrl",
3397         "hscif0_data_b",
3398         "hscif0_clk_b",
3399 };
3400
3401 static const char * const hscif1_groups[] = {
3402         "hscif1_data",
3403         "hscif1_clk",
3404         "hscif1_ctrl",
3405         "hscif1_data_b",
3406         "hscif1_ctrl_b",
3407 };
3408
3409 static const char * const hscif2_groups[] = {
3410         "hscif2_data",
3411         "hscif2_clk",
3412         "hscif2_ctrl",
3413 };
3414
3415 static const char * const i2c0_groups[] = {
3416         "i2c0",
3417         "i2c0_b",
3418         "i2c0_c",
3419         "i2c0_d",
3420         "i2c0_e",
3421 };
3422
3423 static const char * const i2c1_groups[] = {
3424         "i2c1",
3425         "i2c1_b",
3426         "i2c1_c",
3427         "i2c1_d",
3428         "i2c1_e",
3429 };
3430
3431 static const char * const i2c2_groups[] = {
3432         "i2c2",
3433         "i2c2_b",
3434         "i2c2_c",
3435         "i2c2_d",
3436         "i2c2_e",
3437 };
3438
3439 static const char * const i2c3_groups[] = {
3440         "i2c3",
3441         "i2c3_b",
3442         "i2c3_c",
3443         "i2c3_d",
3444         "i2c3_e",
3445 };
3446
3447 static const char * const i2c4_groups[] = {
3448         "i2c4",
3449         "i2c4_b",
3450         "i2c4_c",
3451         "i2c4_d",
3452         "i2c4_e",
3453 };
3454
3455 static const char * const intc_groups[] = {
3456         "intc_irq0",
3457         "intc_irq1",
3458         "intc_irq2",
3459         "intc_irq3",
3460         "intc_irq4",
3461         "intc_irq5",
3462         "intc_irq6",
3463         "intc_irq7",
3464         "intc_irq8",
3465         "intc_irq9",
3466 };
3467
3468 static const char * const mmc_groups[] = {
3469         "mmc_data1",
3470         "mmc_data4",
3471         "mmc_data8",
3472         "mmc_ctrl",
3473 };
3474
3475 static const char * const msiof0_groups[] = {
3476         "msiof0_clk",
3477         "msiof0_sync",
3478         "msiof0_ss1",
3479         "msiof0_ss2",
3480         "msiof0_rx",
3481         "msiof0_tx",
3482 };
3483
3484 static const char * const msiof1_groups[] = {
3485         "msiof1_clk",
3486         "msiof1_sync",
3487         "msiof1_ss1",
3488         "msiof1_ss2",
3489         "msiof1_rx",
3490         "msiof1_tx",
3491         "msiof1_clk_b",
3492         "msiof1_sync_b",
3493         "msiof1_ss1_b",
3494         "msiof1_ss2_b",
3495         "msiof1_rx_b",
3496         "msiof1_tx_b",
3497 };
3498
3499 static const char * const msiof2_groups[] = {
3500         "msiof2_clk",
3501         "msiof2_sync",
3502         "msiof2_ss1",
3503         "msiof2_ss2",
3504         "msiof2_rx",
3505         "msiof2_tx",
3506         "msiof2_clk_b",
3507         "msiof2_sync_b",
3508         "msiof2_ss1_b",
3509         "msiof2_ss2_b",
3510         "msiof2_rx_b",
3511         "msiof2_tx_b",
3512 };
3513
3514 static const char * const qspi_groups[] = {
3515         "qspi_ctrl",
3516         "qspi_data2",
3517         "qspi_data4",
3518 };
3519
3520 static const char * const scif0_groups[] = {
3521         "scif0_data",
3522         "scif0_data_b",
3523         "scif0_data_c",
3524         "scif0_data_d",
3525 };
3526
3527 static const char * const scif1_groups[] = {
3528         "scif1_data",
3529         "scif1_clk",
3530         "scif1_data_b",
3531         "scif1_clk_b",
3532         "scif1_data_c",
3533         "scif1_clk_c",
3534 };
3535
3536 static const char * const scif2_groups[] = {
3537         "scif2_data",
3538         "scif2_clk",
3539         "scif2_data_b",
3540         "scif2_clk_b",
3541         "scif2_data_c",
3542         "scif2_clk_c",
3543 };
3544
3545 static const char * const scif3_groups[] = {
3546         "scif3_data",
3547         "scif3_clk",
3548         "scif3_data_b",
3549         "scif3_clk_b",
3550 };
3551
3552 static const char * const scif4_groups[] = {
3553         "scif4_data",
3554         "scif4_data_b",
3555         "scif4_data_c",
3556         "scif4_data_d",
3557         "scif4_data_e",
3558 };
3559
3560 static const char * const scif5_groups[] = {
3561         "scif5_data",
3562         "scif5_data_b",
3563         "scif5_data_c",
3564         "scif5_data_d",
3565 };
3566
3567 static const char * const scifa0_groups[] = {
3568         "scifa0_data",
3569         "scifa0_data_b",
3570         "scifa0_data_c",
3571         "scifa0_data_d",
3572 };
3573
3574 static const char * const scifa1_groups[] = {
3575         "scifa1_data",
3576         "scifa1_clk",
3577         "scifa1_data_b",
3578         "scifa1_clk_b",
3579         "scifa1_data_c",
3580         "scifa1_clk_c",
3581 };
3582
3583 static const char * const scifa2_groups[] = {
3584         "scifa2_data",
3585         "scifa2_clk",
3586         "scifa2_data_b",
3587         "scifa2_clk_b",
3588 };
3589
3590 static const char * const scifa3_groups[] = {
3591         "scifa3_data",
3592         "scifa3_clk",
3593         "scifa3_data_b",
3594         "scifa3_clk_b",
3595 };
3596
3597 static const char * const scifa4_groups[] = {
3598         "scifa4_data",
3599         "scifa4_data_b",
3600         "scifa4_data_c",
3601         "scifa4_data_d",
3602 };
3603
3604 static const char * const scifa5_groups[] = {
3605         "scifa5_data",
3606         "scifa5_data_b",
3607         "scifa5_data_c",
3608         "scifa5_data_d",
3609 };
3610
3611 static const char * const scifb0_groups[] = {
3612         "scifb0_data",
3613         "scifb0_clk",
3614         "scifb0_ctrl",
3615 };
3616
3617 static const char * const scifb1_groups[] = {
3618         "scifb1_data",
3619         "scifb1_clk",
3620 };
3621
3622 static const char * const scifb2_groups[] = {
3623         "scifb2_data",
3624         "scifb2_clk",
3625         "scifb2_ctrl",
3626 };
3627
3628 static const char * const scif_clk_groups[] = {
3629         "scif_clk",
3630         "scif_clk_b",
3631 };
3632
3633 static const char * const sdhi0_groups[] = {
3634         "sdhi0_data1",
3635         "sdhi0_data4",
3636         "sdhi0_ctrl",
3637         "sdhi0_cd",
3638         "sdhi0_wp",
3639 };
3640
3641 static const char * const sdhi1_groups[] = {
3642         "sdhi1_data1",
3643         "sdhi1_data4",
3644         "sdhi1_ctrl",
3645         "sdhi1_cd",
3646         "sdhi1_wp",
3647 };
3648
3649 static const char * const sdhi2_groups[] = {
3650         "sdhi2_data1",
3651         "sdhi2_data4",
3652         "sdhi2_ctrl",
3653         "sdhi2_cd",
3654         "sdhi2_wp",
3655 };
3656
3657 static const char * const ssi_groups[] = {
3658         "ssi0_data",
3659         "ssi0129_ctrl",
3660         "ssi1_data",
3661         "ssi1_ctrl",
3662         "ssi1_data_b",
3663         "ssi1_ctrl_b",
3664         "ssi2_data",
3665         "ssi2_ctrl",
3666         "ssi2_data_b",
3667         "ssi2_ctrl_b",
3668         "ssi3_data",
3669         "ssi34_ctrl",
3670         "ssi4_data",
3671         "ssi4_ctrl",
3672         "ssi4_data_b",
3673         "ssi4_ctrl_b",
3674         "ssi5_data",
3675         "ssi5_ctrl",
3676         "ssi5_data_b",
3677         "ssi5_ctrl_b",
3678         "ssi6_data",
3679         "ssi6_ctrl",
3680         "ssi6_data_b",
3681         "ssi6_ctrl_b",
3682         "ssi7_data",
3683         "ssi78_ctrl",
3684         "ssi7_data_b",
3685         "ssi78_ctrl_b",
3686         "ssi8_data",
3687         "ssi8_data_b",
3688         "ssi9_data",
3689         "ssi9_ctrl",
3690         "ssi9_data_b",
3691         "ssi9_ctrl_b",
3692 };
3693
3694 static const char * const usb0_groups[] = {
3695         "usb0",
3696 };
3697
3698 static const char * const usb1_groups[] = {
3699         "usb1",
3700 };
3701
3702 static const char * const vin0_groups[] = {
3703         "vin0_data24",
3704         "vin0_data20",
3705         "vin0_data18",
3706         "vin0_data16",
3707         "vin0_data12",
3708         "vin0_data10",
3709         "vin0_data8",
3710         "vin0_sync",
3711         "vin0_field",
3712         "vin0_clkenb",
3713         "vin0_clk",
3714 };
3715
3716 static const char * const vin1_groups[] = {
3717         "vin1_data12",
3718         "vin1_data10",
3719         "vin1_data8",
3720         "vin1_sync",
3721         "vin1_field",
3722         "vin1_clkenb",
3723         "vin1_clk",
3724 };
3725
3726 static const struct sh_pfc_function pinmux_functions[] = {
3727         SH_PFC_FUNCTION(eth),
3728         SH_PFC_FUNCTION(hscif0),
3729         SH_PFC_FUNCTION(hscif1),
3730         SH_PFC_FUNCTION(hscif2),
3731         SH_PFC_FUNCTION(i2c0),
3732         SH_PFC_FUNCTION(i2c1),
3733         SH_PFC_FUNCTION(i2c2),
3734         SH_PFC_FUNCTION(i2c3),
3735         SH_PFC_FUNCTION(i2c4),
3736         SH_PFC_FUNCTION(intc),
3737         SH_PFC_FUNCTION(mmc),
3738         SH_PFC_FUNCTION(msiof0),
3739         SH_PFC_FUNCTION(msiof1),
3740         SH_PFC_FUNCTION(msiof2),
3741         SH_PFC_FUNCTION(qspi),
3742         SH_PFC_FUNCTION(scif0),
3743         SH_PFC_FUNCTION(scif1),
3744         SH_PFC_FUNCTION(scif2),
3745         SH_PFC_FUNCTION(scif3),
3746         SH_PFC_FUNCTION(scif4),
3747         SH_PFC_FUNCTION(scif5),
3748         SH_PFC_FUNCTION(scifa0),
3749         SH_PFC_FUNCTION(scifa1),
3750         SH_PFC_FUNCTION(scifa2),
3751         SH_PFC_FUNCTION(scifa3),
3752         SH_PFC_FUNCTION(scifa4),
3753         SH_PFC_FUNCTION(scifa5),
3754         SH_PFC_FUNCTION(scifb0),
3755         SH_PFC_FUNCTION(scifb1),
3756         SH_PFC_FUNCTION(scifb2),
3757         SH_PFC_FUNCTION(scif_clk),
3758         SH_PFC_FUNCTION(sdhi0),
3759         SH_PFC_FUNCTION(sdhi1),
3760         SH_PFC_FUNCTION(sdhi2),
3761         SH_PFC_FUNCTION(ssi),
3762         SH_PFC_FUNCTION(usb0),
3763         SH_PFC_FUNCTION(usb1),
3764         SH_PFC_FUNCTION(vin0),
3765         SH_PFC_FUNCTION(vin1),
3766 };
3767
3768 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3769         { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
3770                 GP_0_31_FN, FN_IP2_17_16,
3771                 GP_0_30_FN, FN_IP2_15_14,
3772                 GP_0_29_FN, FN_IP2_13_12,
3773                 GP_0_28_FN, FN_IP2_11_10,
3774                 GP_0_27_FN, FN_IP2_9_8,
3775                 GP_0_26_FN, FN_IP2_7_6,
3776                 GP_0_25_FN, FN_IP2_5_4,
3777                 GP_0_24_FN, FN_IP2_3_2,
3778                 GP_0_23_FN, FN_IP2_1_0,
3779                 GP_0_22_FN, FN_IP1_31_30,
3780                 GP_0_21_FN, FN_IP1_29_28,
3781                 GP_0_20_FN, FN_IP1_27,
3782                 GP_0_19_FN, FN_IP1_26,
3783                 GP_0_18_FN, FN_A2,
3784                 GP_0_17_FN, FN_IP1_24,
3785                 GP_0_16_FN, FN_IP1_23_22,
3786                 GP_0_15_FN, FN_IP1_21_20,
3787                 GP_0_14_FN, FN_IP1_19_18,
3788                 GP_0_13_FN, FN_IP1_17_15,
3789                 GP_0_12_FN, FN_IP1_14_13,
3790                 GP_0_11_FN, FN_IP1_12_11,
3791                 GP_0_10_FN, FN_IP1_10_8,
3792                 GP_0_9_FN, FN_IP1_7_6,
3793                 GP_0_8_FN, FN_IP1_5_4,
3794                 GP_0_7_FN, FN_IP1_3_2,
3795                 GP_0_6_FN, FN_IP1_1_0,
3796                 GP_0_5_FN, FN_IP0_31_30,
3797                 GP_0_4_FN, FN_IP0_29_28,
3798                 GP_0_3_FN, FN_IP0_27_26,
3799                 GP_0_2_FN, FN_IP0_25,
3800                 GP_0_1_FN, FN_IP0_24,
3801                 GP_0_0_FN, FN_IP0_23_22, }
3802         },
3803         { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
3804                 0, 0,
3805                 0, 0,
3806                 0, 0,
3807                 0, 0,
3808                 0, 0,
3809                 0, 0,
3810                 GP_1_25_FN, FN_DACK0,
3811                 GP_1_24_FN, FN_IP7_31,
3812                 GP_1_23_FN, FN_IP4_1_0,
3813                 GP_1_22_FN, FN_WE1_N,
3814                 GP_1_21_FN, FN_WE0_N,
3815                 GP_1_20_FN, FN_IP3_31,
3816                 GP_1_19_FN, FN_IP3_30,
3817                 GP_1_18_FN, FN_IP3_29_27,
3818                 GP_1_17_FN, FN_IP3_26_24,
3819                 GP_1_16_FN, FN_IP3_23_21,
3820                 GP_1_15_FN, FN_IP3_20_18,
3821                 GP_1_14_FN, FN_IP3_17_15,
3822                 GP_1_13_FN, FN_IP3_14_13,
3823                 GP_1_12_FN, FN_IP3_12,
3824                 GP_1_11_FN, FN_IP3_11,
3825                 GP_1_10_FN, FN_IP3_10,
3826                 GP_1_9_FN, FN_IP3_9_8,
3827                 GP_1_8_FN, FN_IP3_7_6,
3828                 GP_1_7_FN, FN_IP3_5_4,
3829                 GP_1_6_FN, FN_IP3_3_2,
3830                 GP_1_5_FN, FN_IP3_1_0,
3831                 GP_1_4_FN, FN_IP2_31_30,
3832                 GP_1_3_FN, FN_IP2_29_27,
3833                 GP_1_2_FN, FN_IP2_26_24,
3834                 GP_1_1_FN, FN_IP2_23_21,
3835                 GP_1_0_FN, FN_IP2_20_18, }
3836         },
3837         { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
3838                 GP_2_31_FN, FN_IP6_7_6,
3839                 GP_2_30_FN, FN_IP6_5_4,
3840                 GP_2_29_FN, FN_IP6_3_2,
3841                 GP_2_28_FN, FN_IP6_1_0,
3842                 GP_2_27_FN, FN_IP5_31_30,
3843                 GP_2_26_FN, FN_IP5_29_28,
3844                 GP_2_25_FN, FN_IP5_27_26,
3845                 GP_2_24_FN, FN_IP5_25_24,
3846                 GP_2_23_FN, FN_IP5_23_22,
3847                 GP_2_22_FN, FN_IP5_21_20,
3848                 GP_2_21_FN, FN_IP5_19_18,
3849                 GP_2_20_FN, FN_IP5_17_16,
3850                 GP_2_19_FN, FN_IP5_15_14,
3851                 GP_2_18_FN, FN_IP5_13_12,
3852                 GP_2_17_FN, FN_IP5_11_9,
3853                 GP_2_16_FN, FN_IP5_8_6,
3854                 GP_2_15_FN, FN_IP5_5_4,
3855                 GP_2_14_FN, FN_IP5_3_2,
3856                 GP_2_13_FN, FN_IP5_1_0,
3857                 GP_2_12_FN, FN_IP4_31_30,
3858                 GP_2_11_FN, FN_IP4_29_28,
3859                 GP_2_10_FN, FN_IP4_27_26,
3860                 GP_2_9_FN, FN_IP4_25_23,
3861                 GP_2_8_FN, FN_IP4_22_20,
3862                 GP_2_7_FN, FN_IP4_19_18,
3863                 GP_2_6_FN, FN_IP4_17_16,
3864                 GP_2_5_FN, FN_IP4_15_14,
3865                 GP_2_4_FN, FN_IP4_13_12,
3866                 GP_2_3_FN, FN_IP4_11_10,
3867                 GP_2_2_FN, FN_IP4_9_8,
3868                 GP_2_1_FN, FN_IP4_7_5,
3869                 GP_2_0_FN, FN_IP4_4_2 }
3870         },
3871         { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
3872                 GP_3_31_FN, FN_IP8_22_20,
3873                 GP_3_30_FN, FN_IP8_19_17,
3874                 GP_3_29_FN, FN_IP8_16_15,
3875                 GP_3_28_FN, FN_IP8_14_12,
3876                 GP_3_27_FN, FN_IP8_11_9,
3877                 GP_3_26_FN, FN_IP8_8_6,
3878                 GP_3_25_FN, FN_IP8_5_3,
3879                 GP_3_24_FN, FN_IP8_2_0,
3880                 GP_3_23_FN, FN_IP7_29_27,
3881                 GP_3_22_FN, FN_IP7_26_24,
3882                 GP_3_21_FN, FN_IP7_23_21,
3883                 GP_3_20_FN, FN_IP7_20_18,
3884                 GP_3_19_FN, FN_IP7_17_15,
3885                 GP_3_18_FN, FN_IP7_14_12,
3886                 GP_3_17_FN, FN_IP7_11_9,
3887                 GP_3_16_FN, FN_IP7_8_6,
3888                 GP_3_15_FN, FN_IP7_5_3,
3889                 GP_3_14_FN, FN_IP7_2_0,
3890                 GP_3_13_FN, FN_IP6_31_29,
3891                 GP_3_12_FN, FN_IP6_28_26,
3892                 GP_3_11_FN, FN_IP6_25_23,
3893                 GP_3_10_FN, FN_IP6_22_20,
3894                 GP_3_9_FN, FN_IP6_19_17,
3895                 GP_3_8_FN, FN_IP6_16,
3896                 GP_3_7_FN, FN_IP6_15,
3897                 GP_3_6_FN, FN_IP6_14,
3898                 GP_3_5_FN, FN_IP6_13,
3899                 GP_3_4_FN, FN_IP6_12,
3900                 GP_3_3_FN, FN_IP6_11,
3901                 GP_3_2_FN, FN_IP6_10,
3902                 GP_3_1_FN, FN_IP6_9,
3903                 GP_3_0_FN, FN_IP6_8 }
3904         },
3905         { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
3906                 GP_4_31_FN, FN_IP11_17_16,
3907                 GP_4_30_FN, FN_IP11_15_14,
3908                 GP_4_29_FN, FN_IP11_13_11,
3909                 GP_4_28_FN, FN_IP11_10_8,
3910                 GP_4_27_FN, FN_IP11_7_6,
3911                 GP_4_26_FN, FN_IP11_5_3,
3912                 GP_4_25_FN, FN_IP11_2_0,
3913                 GP_4_24_FN, FN_IP10_31_30,
3914                 GP_4_23_FN, FN_IP10_29_27,
3915                 GP_4_22_FN, FN_IP10_26_24,
3916                 GP_4_21_FN, FN_IP10_23_21,
3917                 GP_4_20_FN, FN_IP10_20_18,
3918                 GP_4_19_FN, FN_IP10_17_15,
3919                 GP_4_18_FN, FN_IP10_14_12,
3920                 GP_4_17_FN, FN_IP10_11_9,
3921                 GP_4_16_FN, FN_IP10_8_6,
3922                 GP_4_15_FN, FN_IP10_5_3,
3923                 GP_4_14_FN, FN_IP10_2_0,
3924                 GP_4_13_FN, FN_IP9_30_28,
3925                 GP_4_12_FN, FN_IP9_27_25,
3926                 GP_4_11_FN, FN_IP9_24_22,
3927                 GP_4_10_FN, FN_IP9_21_19,
3928                 GP_4_9_FN, FN_IP9_18_17,
3929                 GP_4_8_FN, FN_IP9_16_15,
3930                 GP_4_7_FN, FN_IP9_14_12,
3931                 GP_4_6_FN, FN_IP9_11_9,
3932                 GP_4_5_FN, FN_IP9_8_6,
3933                 GP_4_4_FN, FN_IP9_5_3,
3934                 GP_4_3_FN, FN_IP9_2_0,
3935                 GP_4_2_FN, FN_IP8_31_29,
3936                 GP_4_1_FN, FN_IP8_28_26,
3937                 GP_4_0_FN, FN_IP8_25_23 }
3938         },
3939         { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
3940                 0, 0,
3941                 0, 0,
3942                 0, 0,
3943                 0, 0,
3944                 GP_5_27_FN, FN_USB1_OVC,
3945                 GP_5_26_FN, FN_USB1_PWEN,
3946                 GP_5_25_FN, FN_USB0_OVC,
3947                 GP_5_24_FN, FN_USB0_PWEN,
3948                 GP_5_23_FN, FN_IP13_26_24,
3949                 GP_5_22_FN, FN_IP13_23_21,
3950                 GP_5_21_FN, FN_IP13_20_18,
3951                 GP_5_20_FN, FN_IP13_17_15,
3952                 GP_5_19_FN, FN_IP13_14_12,
3953                 GP_5_18_FN, FN_IP13_11_9,
3954                 GP_5_17_FN, FN_IP13_8_6,
3955                 GP_5_16_FN, FN_IP13_5_3,
3956                 GP_5_15_FN, FN_IP13_2_0,
3957                 GP_5_14_FN, FN_IP12_29_27,
3958                 GP_5_13_FN, FN_IP12_26_24,
3959                 GP_5_12_FN, FN_IP12_23_21,
3960                 GP_5_11_FN, FN_IP12_20_18,
3961                 GP_5_10_FN, FN_IP12_17_15,
3962                 GP_5_9_FN, FN_IP12_14_13,
3963                 GP_5_8_FN, FN_IP12_12_11,
3964                 GP_5_7_FN, FN_IP12_10_9,
3965                 GP_5_6_FN, FN_IP12_8_6,
3966                 GP_5_5_FN, FN_IP12_5_3,
3967                 GP_5_4_FN, FN_IP12_2_0,
3968                 GP_5_3_FN, FN_IP11_29_27,
3969                 GP_5_2_FN, FN_IP11_26_24,
3970                 GP_5_1_FN, FN_IP11_23_21,
3971                 GP_5_0_FN, FN_IP11_20_18 }
3972         },
3973         { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
3974                 0, 0,
3975                 0, 0,
3976                 0, 0,
3977                 0, 0,
3978                 0, 0,
3979                 0, 0,
3980                 GP_6_25_FN, FN_IP0_21_20,
3981                 GP_6_24_FN, FN_IP0_19_18,
3982                 GP_6_23_FN, FN_IP0_17,
3983                 GP_6_22_FN, FN_IP0_16,
3984                 GP_6_21_FN, FN_IP0_15,
3985                 GP_6_20_FN, FN_IP0_14,
3986                 GP_6_19_FN, FN_IP0_13,
3987                 GP_6_18_FN, FN_IP0_12,
3988                 GP_6_17_FN, FN_IP0_11,
3989                 GP_6_16_FN, FN_IP0_10,
3990                 GP_6_15_FN, FN_IP0_9_8,
3991                 GP_6_14_FN, FN_IP0_0,
3992                 GP_6_13_FN, FN_SD1_DATA3,
3993                 GP_6_12_FN, FN_SD1_DATA2,
3994                 GP_6_11_FN, FN_SD1_DATA1,
3995                 GP_6_10_FN, FN_SD1_DATA0,
3996                 GP_6_9_FN, FN_SD1_CMD,
3997                 GP_6_8_FN, FN_SD1_CLK,
3998                 GP_6_7_FN, FN_SD0_WP,
3999                 GP_6_6_FN, FN_SD0_CD,
4000                 GP_6_5_FN, FN_SD0_DATA3,
4001                 GP_6_4_FN, FN_SD0_DATA2,
4002                 GP_6_3_FN, FN_SD0_DATA1,
4003                 GP_6_2_FN, FN_SD0_DATA0,
4004                 GP_6_1_FN, FN_SD0_CMD,
4005                 GP_6_0_FN, FN_SD0_CLK }
4006         },
4007         { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4008                              2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1,
4009                              2, 1, 1, 1, 1, 1, 1, 1, 1) {
4010                 /* IP0_31_30 [2] */
4011                 FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
4012                 /* IP0_29_28 [2] */
4013                 FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0,
4014                 /* IP0_27_26 [2] */
4015                 FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0,
4016                 /* IP0_25 [1] */
4017                 FN_D2, FN_SCIFA3_TXD_B,
4018                 /* IP0_24 [1] */
4019                 FN_D1, FN_SCIFA3_RXD_B,
4020                 /* IP0_23_22 [2] */
4021                 FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0,
4022                 /* IP0_21_20 [2] */
4023                 FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX,
4024                 /* IP0_19_18 [2] */
4025                 FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX,
4026                 /* IP0_17 [1] */
4027                 FN_MMC_D5, FN_SD2_WP,
4028                 /* IP0_16 [1] */
4029                 FN_MMC_D4, FN_SD2_CD,
4030                 /* IP0_15 [1] */
4031                 FN_MMC_D3, FN_SD2_DATA3,
4032                 /* IP0_14 [1] */
4033                 FN_MMC_D2, FN_SD2_DATA2,
4034                 /* IP0_13 [1] */
4035                 FN_MMC_D1, FN_SD2_DATA1,
4036                 /* IP0_12 [1] */
4037                 FN_MMC_D0, FN_SD2_DATA0,
4038                 /* IP0_11 [1] */
4039                 FN_MMC_CMD, FN_SD2_CMD,
4040                 /* IP0_10 [1] */
4041                 FN_MMC_CLK, FN_SD2_CLK,
4042                 /* IP0_9_8 [2] */
4043                 FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0,
4044                 /* IP0_7 [1] */
4045                 0, 0,
4046                 /* IP0_6 [1] */
4047                 0, 0,
4048                 /* IP0_5 [1] */
4049                 0, 0,
4050                 /* IP0_4 [1] */
4051                 0, 0,
4052                 /* IP0_3 [1] */
4053                 0, 0,
4054                 /* IP0_2 [1] */
4055                 0, 0,
4056                 /* IP0_1 [1] */
4057                 0, 0,
4058                 /* IP0_0 [1] */
4059                 FN_SD1_CD, FN_CAN0_RX, }
4060         },
4061         { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4062                              2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2, 3, 2, 2,
4063                              2, 2) {
4064                 /* IP1_31_30 [2] */
4065                 FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
4066                 /* IP1_29_28 [2] */
4067                 FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
4068                 /* IP1_27 [1] */
4069                 FN_A4, FN_SCIFB0_TXD,
4070                 /* IP1_26 [1] */
4071                 FN_A3, FN_SCIFB0_SCK,
4072                 /* IP1_25 [1] */
4073                 0, 0,
4074                 /* IP1_24 [1] */
4075                 FN_A1, FN_SCIFB1_TXD,
4076                 /* IP1_23_22 [2] */
4077                 FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 0,
4078                 /* IP1_21_20 [2] */
4079                 FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B, 0,
4080                 /* IP1_19_18 [2] */
4081                 FN_D14, FN_SCIFA1_RXD, FN_IIC0_SCL_B, 0,
4082                 /* IP1_17_15 [3] */
4083                 FN_D13, FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B,
4084                 0, 0, 0,
4085                 /* IP1_14_13 [2] */
4086                 FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
4087                 /* IP1_12_11 [2] */
4088                 FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
4089                 /* IP1_10_8 [3] */
4090                 FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
4091                 0, 0, 0,
4092                 /* IP1_7_6 [2] */
4093                 FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B, 0,
4094                 /* IP1_5_4 [2] */
4095                 FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, 0,
4096                 /* IP1_3_2 [2] */
4097                 FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
4098                 /* IP1_1_0 [2] */
4099                 FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, }
4100         },
4101         { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
4102                              2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2) {
4103                 /* IP2_31_30 [2] */
4104                 FN_A20, FN_SPCLK, FN_MOUT1, 0,
4105                 /* IP2_29_27 [3] */
4106                 FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
4107                 FN_MOUT0, 0, 0, 0,
4108                 /* IP2_26_24 [3] */
4109                 FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
4110                 FN_AVB_AVTP_MATCH_B, 0, 0, 0,
4111                 /* IP2_23_21 [3] */
4112                 FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
4113                 FN_AVB_AVTP_CAPTURE_B, 0, 0, 0,
4114                 /* IP2_20_18 [3] */
4115                 FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN,
4116                 FN_VSP, FN_CAN_CLK_C, FN_TPUTO2_B, 0,
4117                 /* IP2_17_16 [2] */
4118                 FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
4119                 /* IP2_15_14 [2] */
4120                 FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
4121                 /* IP2_13_12 [2] */
4122                 FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, 0,
4123                 /* IP2_11_10 [2] */
4124                 FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 0,
4125                 /* IP2_9_8 [2] */
4126                 FN_A11, FN_MSIOF1_SYNC, FN_IIC1_SDA_B, 0,
4127                 /* IP2_7_6 [2] */
4128                 FN_A10, FN_MSIOF1_SCK, FN_IIC1_SCL_B, 0,
4129                 /* IP2_5_4 [2] */
4130                 FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 0,
4131                 /* IP2_3_2 [2] */
4132                 FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0,
4133                 /* IP2_1_0 [2] */
4134                 FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, }
4135         },
4136         { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
4137                              1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2, 2, 2, 2, 2) {
4138                 /* IP3_31 [1] */
4139                 FN_RD_WR_N, FN_ATAG1_N,
4140                 /* IP3_30 [1] */
4141                 FN_RD_N, FN_ATACS11_N,
4142                 /* IP3_29_27 [3] */
4143                 FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
4144                 FN_MTS_N_B, 0, 0,
4145                 /* IP3_26_24 [3] */
4146                 FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B,
4147                 FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B,
4148                 /* IP3_23_21 [3] */
4149                 FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B,
4150                 FN_RIF0_D0, FN_FMCLK, FN_SCIFB2_CTS_N, FN_SCKZ_B,
4151                 /* IP3_20_18 [3] */
4152                 FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
4153                 FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B,
4154                 /* IP3_17_15 [3] */
4155                 FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B,
4156                 FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD, FN_SDATA_B,
4157                 /* IP3_14_13 [2] */
4158                 FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
4159                 /* IP3_12 [1] */
4160                 FN_EX_CS0_N, FN_VI1_DATA10,
4161                 /* IP3_11 [1] */
4162                 FN_CS1_N_A26, FN_VI1_DATA9,
4163                 /* IP3_10 [1] */
4164                 FN_CS0_N, FN_VI1_DATA8,
4165                 /* IP3_9_8 [2] */
4166                 FN_A25, FN_SSL, FN_ATARD1_N, 0,
4167                 /* IP3_7_6 [2] */
4168                 FN_A24, FN_IO3, FN_EX_WAIT2, 0,
4169                 /* IP3_5_4 [2] */
4170                 FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N,
4171                 /* IP3_3_2 [2] */
4172                 FN_A22, FN_MISO_IO1, FN_MOUT5, FN_ATADIR1_N,
4173                 /* IP3_1_0 [2] */
4174                 FN_A21, FN_MOSI_IO0, FN_MOUT2, 0, }
4175         },
4176         { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
4177                              2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2) {
4178                 /* IP4_31_30 [2] */
4179                 FN_DU0_DG4, FN_LCDOUT12, FN_CC50_STATE12, 0,
4180                 /* IP4_29_28 [2] */
4181                 FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, 0,
4182                 /* IP4_27_26 [2] */
4183                 FN_DU0_DG2, FN_LCDOUT10, FN_CC50_STATE10, 0,
4184                 /* IP4_25_23 [3] */
4185                 FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
4186                 FN_CC50_STATE9, 0, 0, 0,
4187                 /* IP4_22_20 [3] */
4188                 FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
4189                 FN_CC50_STATE8, 0, 0, 0,
4190                 /* IP4_19_18 [2] */
4191                 FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, 0,
4192                 /* IP4_17_16 [2] */
4193                 FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6, 0,
4194                 /* IP4_15_14 [2] */
4195                 FN_DU0_DR5, FN_LCDOUT21, FN_CC50_STATE5, 0,
4196                 /* IP4_13_12 [2] */
4197                 FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, 0,
4198                 /* IP4_11_10 [2] */
4199                 FN_DU0_DR3, FN_LCDOUT19, FN_CC50_STATE3, 0,
4200                 /* IP4_9_8 [2] */
4201                 FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, 0,
4202                 /* IP4_7_5 [3] */
4203                 FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
4204                 FN_CC50_STATE1, 0, 0, 0,
4205                 /* IP4_4_2 [3] */
4206                 FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
4207                 FN_CC50_STATE0, 0, 0, 0,
4208                 /* IP4_1_0 [2] */
4209                 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, }
4210         },
4211         { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
4212                              2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2) {
4213                 /* IP5_31_30 [2] */
4214                 FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27, 0,
4215                 /* IP5_29_28 [2] */
4216                 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_CC50_STATE26, 0,
4217                 /* IP5_27_26 [2] */
4218                 FN_DU0_DOTCLKOUT0, FN_QCLK, FN_CC50_STATE25, 0,
4219                 /* IP5_25_24 [2] */
4220                 FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, 0,
4221                 /* IP5_23_22 [2] */
4222                 FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23, 0,
4223                 /* IP5_21_20 [2] */
4224                 FN_DU0_DB6, FN_LCDOUT6, FN_CC50_STATE22, 0,
4225                 /* IP5_19_18 [2] */
4226                 FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, 0,
4227                 /* IP5_17_16 [2] */
4228                 FN_DU0_DB4, FN_LCDOUT4, FN_CC50_STATE20, 0,
4229                 /* IP5_15_14 [2] */
4230                 FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, 0,
4231                 /* IP5_13_12 [2] */
4232                 FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18, 0,
4233                 /* IP5_11_9 [3] */
4234                 FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
4235                 FN_CAN0_TX_C, FN_CC50_STATE17, 0, 0,
4236                 /* IP5_8_6 [3] */
4237                 FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D,
4238                 FN_CAN0_RX_C, FN_CC50_STATE16, 0, 0,
4239                 /* IP5_5_4 [2] */
4240                 FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, 0,
4241                 /* IP5_3_2 [2] */
4242                 FN_DU0_DG6, FN_LCDOUT14, FN_CC50_STATE14, 0,
4243                 /* IP5_1_0 [2] */
4244                 FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, 0, }
4245         },
4246         { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
4247                              3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
4248                              2, 2) {
4249                 /* IP6_31_29 [3] */
4250                 FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D,
4251                 FN_AVB_TX_CLK, FN_ADIDATA, FN_AD_DI, 0,
4252                 /* IP6_28_26 [3] */
4253                 FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C,
4254                 FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0,
4255                 /* IP6_25_23 [3] */
4256                 FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C,
4257                 FN_AVB_COL, 0, 0, 0,
4258                 /* IP6_22_20 [3] */
4259                 FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C,
4260                 FN_AVB_RX_ER, 0, 0, 0,
4261                 /* IP6_19_17 [3] */
4262                 FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C,
4263                 FN_AVB_RXD7, 0, 0, 0,
4264                 /* IP6_16 [1] */
4265                 FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
4266                 /* IP6_15 [1] */
4267                 FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
4268                 /* IP6_14 [1] */
4269                 FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
4270                 /* IP6_13 [1] */
4271                 FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
4272                 /* IP6_12 [1] */
4273                 FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
4274                 /* IP6_11 [1] */
4275                 FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
4276                 /* IP6_10 [1] */
4277                 FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
4278                 /* IP6_9 [1] */
4279                 FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
4280                 /* IP6_8 [1] */
4281                 FN_VI0_CLK, FN_AVB_RX_CLK,
4282                 /* IP6_7_6 [2] */
4283                 FN_DU0_CDE, FN_QPOLB, FN_CC50_STATE31, 0,
4284                 /* IP6_5_4 [2] */
4285                 FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, 0,
4286                 /* IP6_3_2 [2] */
4287                 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
4288                 /* IP6_1_0 [2] */
4289                 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 0, }
4290         },
4291         { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
4292                              1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
4293                 /* IP7_31 [1] */
4294                 FN_DREQ0_N, FN_SCIFB1_RXD,
4295                 /* IP7_30 [1] */
4296                 0, 0,
4297                 /* IP7_29_27 [3] */
4298                 FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E,
4299                 FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
4300                 /* IP7_26_24 [3] */
4301                 FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER,
4302                 FN_SSI_SCK6_B, 0, 0, 0,
4303                 /* IP7_23_21 [3] */
4304                 FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC1_SDA_D,
4305                 FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0,
4306                 /* IP7_20_18 [3] */
4307                 FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC1_SCL_D,
4308                 FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0,
4309                 /* IP7_17_15 [3] */
4310                 FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5,
4311                 FN_SSI_SCK5_B, 0, 0, 0,
4312                 /* IP7_14_12 [3] */
4313                 FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
4314                 FN_AVB_TXD4, FN_ADICHS2, 0, 0,
4315                 /* IP7_11_9 [3] */
4316                 FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D,
4317                 FN_AVB_TXD3, FN_ADICHS1, 0, 0,
4318                 /* IP7_8_6 [3] */
4319                 FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B,
4320                 FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, 0,
4321                 /* IP7_5_3 [3] */
4322                 FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B,
4323                 FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, 0,
4324                 /* IP7_2_0 [3] */
4325                 FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D,
4326                 FN_AVB_TXD0, FN_ADICS_SAMP, FN_AD_DO, 0, }
4327         },
4328         { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
4329                              3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) {
4330                 /* IP8_31_29 [3] */
4331                 FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
4332                 FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
4333                 /* IP8_28_26 [3] */
4334                 FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
4335                 FN_RIF1_CLK_B, FN_TS_SCK_D, FN_BPFCLK_C, 0,
4336                 /* IP8_25_23 [3] */
4337                 FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0,
4338                 FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
4339                 /* IP8_22_20 [3] */
4340                 FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK,
4341                 FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0,
4342                 /* IP8_19_17 [3] */
4343                 FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B,
4344                 FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0,
4345                 /* IP8_16_15 [2] */
4346                 FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
4347                 /* IP8_14_12 [3] */
4348                 FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
4349                 FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0,
4350                 /* IP8_11_9 [3] */
4351                 FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
4352                 FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0,
4353                 /* IP8_8_6 [3] */
4354                 FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B,
4355                 FN_AVB_LINK, FN_SSI_WS78_B, 0, 0,
4356                 /* IP8_5_3 [3] */
4357                 FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B,
4358                 FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
4359                 /* IP8_2_0 [3] */
4360                 FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
4361                 FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, }
4362         },
4363         { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
4364                              1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3, 3) {
4365                 /* IP9_31 [1] */
4366                 0, 0,
4367                 /* IP9_30_28 [3] */
4368                 FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5,
4369                 FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34, 0,
4370                 /* IP9_27_25 [3] */
4371                 FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4,
4372                 FN_SSI_WS1_B, FN_CAN_STEP0, FN_CC50_STATE33, 0,
4373                 /* IP9_24_22 [3] */
4374                 FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3,
4375                 FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32, 0,
4376                 /* IP9_21_19 [3] */
4377                 FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2,
4378                 FN_REMOCON_B, FN_SPEEDIN_B, FN_VSP_B, 0,
4379                 /* IP9_18_17 [2] */
4380                 FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
4381                 /* IP9_16_15 [2] */
4382                 FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
4383                 /* IP9_14_12 [3] */
4384                 FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
4385                 FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, 0,
4386                 /* IP9_11_9 [3] */
4387                 FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6,
4388                 FN_RIF1_D0, FN_FMCLK_B, FN_RDS_CLK_B, 0,
4389                 /* IP9_8_6 [3] */
4390                 FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5,
4391                 FN_RIF1_CLK, FN_BPFCLK_B, 0, 0,
4392                 /* IP9_5_3 [3] */
4393                 FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4,
4394                 FN_RIF1_SYNC, FN_TPUTO1_C, 0, 0,
4395                 /* IP9_2_0 [3] */
4396                 FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3,
4397                 FN_RIF1_D1_B, FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, }
4398         },
4399         { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
4400                              2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
4401                 /* IP10_31_30 [2] */
4402                 FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10,
4403                 /* IP10_29_27 [3] */
4404                 FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
4405                 FN_CAN_DEBUGOUT9, 0, 0, 0,
4406                 /* IP10_26_24 [3] */
4407                 FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
4408                 FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, 0, 0,
4409                 /* IP10_23_21 [3] */
4410                 FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5,
4411                 FN_AUDIO_CLKB_C, FN_SSI_WS4_B, FN_CAN_DEBUGOUT7, FN_RDS_DATA_C,
4412                 /* IP10_20_18 [3] */
4413                 FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4,
4414                 FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C,
4415                 /* IP10_17_15 [3] */
4416                 FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
4417                 FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT,
4418                 /* IP10_14_12 [3] */
4419                 FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
4420                 FN_USB0_IDIN, FN_CAN_DEBUGOUT4, FN_CC50_STATE39, 0,
4421                 /* IP10_11_9 [3] */
4422                 FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
4423                 FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, 0,
4424                 /* IP10_8_6 [3] */
4425                 FN_SCIF2_RXD, FN_IIC1_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
4426                 FN_USB0_EXTLP, FN_CAN_DEBUGOUT2, FN_CC50_STATE37, 0,
4427                 /* IP10_5_3 [3] */
4428                 FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
4429                 FN_CAN_DEBUGOUT1, FN_CC50_STATE36, 0, 0,
4430                 /* IP10_2_0 [3] */
4431                 FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
4432                 FN_CAN_DEBUGOUT0, FN_CC50_STATE35, 0, 0, }
4433         },
4434         { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
4435                              2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) {
4436                 /* IP11_31_30 [2] */
4437                 0, 0, 0, 0,
4438                 /* IP11_29_27 [3] */
4439                 FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
4440                 FN_AD_CLK_B, 0, 0, 0,
4441                 /* IP11_26_24 [3] */
4442                 FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
4443                 FN_AD_DO_B, 0, 0, 0,
4444                 /* IP11_23_21 [3] */
4445                 FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
4446                 FN_AD_DI_B, FN_PCMWE_N, 0, 0,
4447                 /* IP11_20_18 [3] */
4448                 FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D,
4449                 FN_CAN_CLK_D, FN_PCMOE_N, 0, 0,
4450                 /* IP11_17_16 [2] */
4451                 FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE,
4452                 /* IP11_15_14 [2] */
4453                 FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP,
4454                 /* IP11_13_11 [3] */
4455                 FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
4456                 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, 0, 0, 0,
4457                 /* IP11_10_8 [3] */
4458                 FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C,
4459                 FN_DU1_EXVSYNC_DU1_VSYNC, FN_CAN_DEBUGOUT14, 0, 0, 0,
4460                 /* IP11_7_6 [2] */
4461                 FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC,
4462                 FN_CAN_DEBUGOUT13,
4463                 /* IP11_5_3 [3] */
4464                 FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
4465                 FN_CAN_DEBUGOUT12, 0, 0, 0,
4466                 /* IP11_2_0 [3] */
4467                 FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
4468                 FN_CAN_DEBUGOUT11, 0, 0, 0, }
4469         },
4470         { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
4471                              2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3) {
4472                 /* IP12_31_30 [2] */
4473                 0, 0, 0, 0,
4474                 /* IP12_29_27 [3] */
4475                 FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_MDATA,
4476                 FN_ATAWR0_N, FN_ETH_RXD1_B, 0, 0,
4477                 /* IP12_26_24 [3] */
4478                 FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_SDATA,
4479                 FN_ATAG0_N, FN_ETH_RXD0_B, 0, 0,
4480                 /* IP12_23_21 [3] */
4481                 FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC1_SDA_C, FN_VI1_DATA0,
4482                 FN_CAN0_TX_D, FN_AVB_AVTP_MATCH, FN_ETH_RX_ER_B, 0,
4483                 /* IP12_20_18 [3] */
4484                 FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK,
4485                 FN_CAN0_RX_D, FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, 0,
4486                 /* IP12_17_15 [3] */
4487                 FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9,
4488                 FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0,
4489                 /* IP12_14_13 [2] */
4490                 FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, FN_IRD_SCK,
4491                 /* IP12_12_11 [2] */
4492                 FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX,
4493                 /* IP12_10_9 [2] */
4494                 FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX,
4495                 /* IP12_8_6 [3] */
4496                 FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
4497                 FN_CAN1_TX_C, FN_DREQ2_N, 0, 0,
4498                 /* IP12_5_3 [3] */
4499                 FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
4500                 FN_CAN1_RX_C, FN_DACK1_B, 0, 0,
4501                 /* IP12_2_0 [3] */
4502                 FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
4503                 FN_AD_NCS_N_B, FN_DREQ1_N_B, 0, 0, }
4504         },
4505         { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
4506                              1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
4507                 /* IP13_31 [1] */
4508                 0, 0,
4509                 /* IP13_30 [1] */
4510                 0, 0,
4511                 /* IP13_29 [1] */
4512                 0, 0,
4513                 /* IP13_28 [1] */
4514                 0, 0,
4515                 /* IP13_27 [1] */
4516                 0, 0,
4517                 /* IP13_26_24 [3] */
4518                 FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
4519                 FN_TS_SPSYNC_C, FN_RIF0_D1_B, FN_FMIN_E, FN_RDS_DATA_D,
4520                 /* IP13_23_21 [3] */
4521                 FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
4522                 FN_TS_SDEN_C, FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D,
4523                 /* IP13_20_18 [3] */
4524                 FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
4525                 FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B,
4526                 /* IP13_17_15 [3] */
4527                 FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
4528                 FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B, 0,
4529                 /* IP13_14_12 [3] */
4530                 FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
4531                 FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0,
4532                 /* IP13_11_9 [3] */
4533                 FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6,
4534                 FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0,
4535                 /* IP13_8_6 [3] */
4536                 FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5,
4537                 FN_MTS_N, FN_EX_WAIT1, FN_ETH_TXD1_B, 0,
4538                 /* IP13_5_3 [2] */
4539                 FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D,
4540                 FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B, 0,
4541                 /* IP13_2_0 [3] */
4542                 FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
4543                 FN_SCKZ, FN_ATACS00_N, FN_ETH_LINK_B, 0, }
4544         },
4545         { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
4546                              2, 1, 2, 3, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3,
4547                              2, 1) {
4548                 /* SEL_ADG [2] */
4549                 FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
4550                 /* SEL_ADI [1] */
4551                 FN_SEL_ADI_0, FN_SEL_ADI_1,
4552                 /* SEL_CAN [2] */
4553                 FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
4554                 /* SEL_DARC [3] */
4555                 FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
4556                 FN_SEL_DARC_4, 0, 0, 0,
4557                 /* SEL_DR0 [1] */
4558                 FN_SEL_DR0_0, FN_SEL_DR0_1,
4559                 /* SEL_DR1 [1] */
4560                 FN_SEL_DR1_0, FN_SEL_DR1_1,
4561                 /* SEL_DR2 [1] */
4562                 FN_SEL_DR2_0, FN_SEL_DR2_1,
4563                 /* SEL_DR3 [1] */
4564                 FN_SEL_DR3_0, FN_SEL_DR3_1,
4565                 /* SEL_ETH [1] */
4566                 FN_SEL_ETH_0, FN_SEL_ETH_1,
4567                 /* SLE_FSN [1] */
4568                 FN_SEL_FSN_0, FN_SEL_FSN_1,
4569                 /* SEL_IC200 [3] */
4570                 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
4571                 FN_SEL_I2C00_4, 0, 0, 0,
4572                 /* SEL_I2C01 [3] */
4573                 FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
4574                 FN_SEL_I2C01_4, 0, 0, 0,
4575                 /* SEL_I2C02 [3] */
4576                 FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
4577                 FN_SEL_I2C02_4, 0, 0, 0,
4578                 /* SEL_I2C03 [3] */
4579                 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
4580                 FN_SEL_I2C03_4, 0, 0, 0,
4581                 /* SEL_I2C04 [3] */
4582                 FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
4583                 FN_SEL_I2C04_4, 0, 0, 0,
4584                 /* SEL_IIC00 [2] */
4585                 FN_SEL_IIC00_0, FN_SEL_IIC00_1, FN_SEL_IIC00_2, FN_SEL_IIC00_3,
4586                 /* SEL_AVB [1] */
4587                 FN_SEL_AVB_0, FN_SEL_AVB_1, }
4588         },
4589         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
4590                              2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1,
4591                              2, 2, 2, 1, 1, 2) {
4592                 /* SEL_IEB [2] */
4593                 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
4594                 /* SEL_IIC0 [2] */
4595                 FN_SEL_IIC01_0, FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3,
4596                 /* SEL_LBS [1] */
4597                 FN_SEL_LBS_0, FN_SEL_LBS_1,
4598                 /* SEL_MSI1 [1] */
4599                 FN_SEL_MSI1_0, FN_SEL_MSI1_1,
4600                 /* SEL_MSI2 [1] */
4601                 FN_SEL_MSI2_0, FN_SEL_MSI2_1,
4602                 /* SEL_RAD [1] */
4603                 FN_SEL_RAD_0, FN_SEL_RAD_1,
4604                 /* SEL_RCN [1] */
4605                 FN_SEL_RCN_0, FN_SEL_RCN_1,
4606                 /* SEL_RSP [1] */
4607                 FN_SEL_RSP_0, FN_SEL_RSP_1,
4608                 /* SEL_SCIFA0 [2] */
4609                 FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2,
4610                 FN_SEL_SCIFA0_3,
4611                 /* SEL_SCIFA1 [2] */
4612                 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
4613                 /* SEL_SCIFA2 [1] */
4614                 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
4615                 /* SEL_SCIFA3 [1] */
4616                 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
4617                 /* SEL_SCIFA4 [2] */
4618                 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
4619                 FN_SEL_SCIFA4_3,
4620                 /* SEL_SCIFA5 [2] */
4621                 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
4622                 FN_SEL_SCIFA5_3,
4623                 /* SEL_SPDM [1] */
4624                 FN_SEL_SPDM_0, FN_SEL_SPDM_1,
4625                 /* SEL_TMU [1] */
4626                 FN_SEL_TMU_0, FN_SEL_TMU_1,
4627                 /* SEL_TSIF0 [2] */
4628                 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
4629                 /* SEL_CAN0 [2] */
4630                 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
4631                 /* SEL_CAN1 [2] */
4632                 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
4633                 /* SEL_HSCIF0 [1] */
4634                 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
4635                 /* SEL_HSCIF1 [1] */
4636                 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
4637                 /* SEL_RDS [2] */
4638                 FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, }
4639         },
4640         { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
4641                              2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
4642                              1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
4643                 /* SEL_SCIF0 [2] */
4644                 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
4645                 /* SEL_SCIF1 [2] */
4646                 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
4647                 /* SEL_SCIF2 [2] */
4648                 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
4649                 /* SEL_SCIF3 [1] */
4650                 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
4651                 /* SEL_SCIF4 [3] */
4652                 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
4653                 FN_SEL_SCIF4_4, 0, 0, 0,
4654                 /* SEL_SCIF5 [2] */
4655                 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
4656                 /* SEL_SSI1 [1] */
4657                 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
4658                 /* SEL_SSI2 [1] */
4659                 FN_SEL_SSI2_0, FN_SEL_SSI2_1,
4660                 /* SEL_SSI4 [1] */
4661                 FN_SEL_SSI4_0, FN_SEL_SSI4_1,
4662                 /* SEL_SSI5 [1] */
4663                 FN_SEL_SSI5_0, FN_SEL_SSI5_1,
4664                 /* SEL_SSI6 [1] */
4665                 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
4666                 /* SEL_SSI7 [1] */
4667                 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
4668                 /* SEL_SSI8 [1] */
4669                 FN_SEL_SSI8_0, FN_SEL_SSI8_1,
4670                 /* SEL_SSI9 [1] */
4671                 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
4672                 /* RESERVED [1] */
4673                 0, 0,
4674                 /* RESERVED [1] */
4675                 0, 0,
4676                 /* RESERVED [1] */
4677                 0, 0,
4678                 /* RESERVED [1] */
4679                 0, 0,
4680                 /* RESERVED [1] */
4681                 0, 0,
4682                 /* RESERVED [1] */
4683                 0, 0,
4684                 /* RESERVED [1] */
4685                 0, 0,
4686                 /* RESERVED [1] */
4687                 0, 0,
4688                 /* RESERVED [1] */
4689                 0, 0,
4690                 /* RESERVED [1] */
4691                 0, 0,
4692                 /* RESERVED [1] */
4693                 0, 0,
4694                 /* RESERVED [1] */
4695                 0, 0, }
4696         },
4697         { },
4698 };
4699
4700 const struct sh_pfc_soc_info r8a7794_pinmux_info = {
4701         .name = "r8a77940_pfc",
4702         .unlock_reg = 0xe6060000, /* PMMR */
4703
4704         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4705
4706         .pins = pinmux_pins,
4707         .nr_pins = ARRAY_SIZE(pinmux_pins),
4708         .groups = pinmux_groups,
4709         .nr_groups = ARRAY_SIZE(pinmux_groups),
4710         .functions = pinmux_functions,
4711         .nr_functions = ARRAY_SIZE(pinmux_functions),
4712
4713         .cfg_regs = pinmux_config_regs,
4714
4715         .pinmux_data = pinmux_data,
4716         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
4717 };