drivers/pinctrl/sh-pfc/sh_pfc.h

   1 /*
   2  * SuperH Pin Function Controller Support
   3  *
   4  * Copyright (c) 2008 Magnus Damm
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10
  11 #ifndef __SH_PFC_H
  12 #define __SH_PFC_H
  13
  14 #include <linux/bug.h>
  15 #include <linux/pinctrl/pinconf-generic.h>
  16 #include <linux/stringify.h>
  17
  18 enum {
  19         PINMUX_TYPE_NONE,
  20         PINMUX_TYPE_FUNCTION,
  21         PINMUX_TYPE_GPIO,
  22         PINMUX_TYPE_OUTPUT,
  23         PINMUX_TYPE_INPUT,
  24 };
  25
  26 #define SH_PFC_PIN_CFG_INPUT            (1 << 0)
  27 #define SH_PFC_PIN_CFG_OUTPUT           (1 << 1)
  28 #define SH_PFC_PIN_CFG_PULL_UP          (1 << 2)
  29 #define SH_PFC_PIN_CFG_PULL_DOWN        (1 << 3)
  30 #define SH_PFC_PIN_CFG_IO_VOLTAGE       (1 << 4)
  31 #define SH_PFC_PIN_CFG_DRIVE_STRENGTH   (1 << 5)
  32 #define SH_PFC_PIN_CFG_NO_GPIO          (1 << 31)
  33
  34 struct sh_pfc_pin {
  35         u16 pin;
  36         u16 enum_id;
  37         const char *name;
  38         unsigned int configs;
  39 };
  40
  41 #define SH_PFC_PIN_GROUP(n)                             \
  42         {                                               \
  43                 .name = #n,                             \
  44                 .pins = n##_pins,                       \
  45                 .mux = n##_mux,                         \
  46                 .nr_pins = ARRAY_SIZE(n##_pins),        \
  47         }
  48
  49 struct sh_pfc_pin_group {
  50         const char *name;
  51         const unsigned int *pins;
  52         const unsigned int *mux;
  53         unsigned int nr_pins;
  54 };
  55
  56 /*
  57  * Using union vin_data saves memory occupied by the VIN data pins.
  58  * VIN_DATA_PIN_GROUP() is  a macro  used  to describe the VIN pin groups
  59  * in this case.
  60  */
  61 #define VIN_DATA_PIN_GROUP(n, s)                                \
  62         {                                                       \
  63                 .name = #n#s,                                   \
  64                 .pins = n##_pins.data##s,                       \
  65                 .mux = n##_mux.data##s,                         \
  66                 .nr_pins = ARRAY_SIZE(n##_pins.data##s),        \
  67         }
  68
  69 union vin_data {
  70         unsigned int data24[24];
  71         unsigned int data20[20];
  72         unsigned int data16[16];
  73         unsigned int data12[12];
  74         unsigned int data10[10];
  75         unsigned int data8[8];
  76         unsigned int data4[4];
  77 };
  78
  79 #define SH_PFC_FUNCTION(n)                              \
  80         {                                               \
  81                 .name = #n,                             \
  82                 .groups = n##_groups,                   \
  83                 .nr_groups = ARRAY_SIZE(n##_groups),    \
  84         }
  85
  86 struct sh_pfc_function {
  87         const char *name;
  88         const char * const *groups;
  89         unsigned int nr_groups;
  90 };
  91
  92 struct pinmux_func {
  93         u16 enum_id;
  94         const char *name;
  95 };
  96
  97 struct pinmux_cfg_reg {
  98         u32 reg;
  99         u8 reg_width, field_width;
 100         const u16 *enum_ids;
 101         const u8 *var_field_width;
 102 };
 103
 104 /*
 105  * Describe a config register consisting of several fields of the same width
 106  *   - name: Register name (unused, for documentation purposes only)
 107  *   - r: Physical register address
 108  *   - r_width: Width of the register (in bits)
 109  *   - f_width: Width of the fixed-width register fields (in bits)
 110  * This macro must be followed by initialization data: For each register field
 111  * (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified,
 112  * one for each possible combination of the register field bit values.
 113  */
 114 #define PINMUX_CFG_REG(name, r, r_width, f_width) \
 115         .reg = r, .reg_width = r_width, .field_width = f_width,         \
 116         .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
 117
 118 /*
 119  * Describe a config register consisting of several fields of different widths
 120  *   - name: Register name (unused, for documentation purposes only)
 121  *   - r: Physical register address
 122  *   - r_width: Width of the register (in bits)
 123  *   - var_fw0, var_fwn...: List of widths of the register fields (in bits),
 124  *                          From left to right (i.e. MSB to LSB)
 125  * This macro must be followed by initialization data: For each register field
 126  * (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified,
 127  * one for each possible combination of the register field bit values.
 128  */
 129 #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
 130         .reg = r, .reg_width = r_width, \
 131         .var_field_width = (const u8 [r_width]) \
 132                 { var_fw0, var_fwn, 0 }, \
 133         .enum_ids = (const u16 [])
 134
 135 struct pinmux_drive_reg_field {
 136         u16 pin;
 137         u8 offset;
 138         u8 size;
 139 };
 140
 141 struct pinmux_drive_reg {
 142         u32 reg;
 143         const struct pinmux_drive_reg_field fields[8];
 144 };
 145
 146 #define PINMUX_DRIVE_REG(name, r) \
 147         .reg = r, \
 148         .fields =
 149
 150 struct pinmux_data_reg {
 151         u32 reg;
 152         u8 reg_width;
 153         const u16 *enum_ids;
 154 };
 155
 156 /*
 157  * Describe a data register
 158  *   - name: Register name (unused, for documentation purposes only)
 159  *   - r: Physical register address
 160  *   - r_width: Width of the register (in bits)
 161  * This macro must be followed by initialization data: For each register bit
 162  * (from left to right, i.e. MSB to LSB), one enum ID must be specified.
 163  */
 164 #define PINMUX_DATA_REG(name, r, r_width) \
 165         .reg = r, .reg_width = r_width, \
 166         .enum_ids = (const u16 [r_width]) \
 167
 168 struct pinmux_irq {
 169         const short *gpios;
 170 };
 171
 172 /*
 173  * Describe the mapping from GPIOs to a single IRQ
 174  *   - ids...: List of GPIOs that are mapped to the same IRQ
 175  */
 176 #define PINMUX_IRQ(ids...)                         \
 177         { .gpios = (const short []) { ids, -1 } }
 178
 179 struct pinmux_range {
 180         u16 begin;
 181         u16 end;
 182         u16 force;
 183 };
 184
 185 struct sh_pfc;
 186
 187 struct sh_pfc_soc_operations {
 188         int (*init)(struct sh_pfc *pfc);
 189         unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
 190         void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
 191                          unsigned int bias);
 192         int (*get_io_voltage)(struct sh_pfc *pfc, unsigned int pin);
 193         int (*set_io_voltage)(struct sh_pfc *pfc, unsigned int pin,
 194                               u16 voltage_mV);
 195 };
 196
 197 struct sh_pfc_soc_info {
 198         const char *name;
 199         const struct sh_pfc_soc_operations *ops;
 200
 201         struct pinmux_range input;
 202         struct pinmux_range output;
 203         struct pinmux_range function;
 204
 205         const struct sh_pfc_pin *pins;
 206         unsigned int nr_pins;
 207         const struct sh_pfc_pin_group *groups;
 208         unsigned int nr_groups;
 209         const struct sh_pfc_function *functions;
 210         unsigned int nr_functions;
 211
 212 #ifdef CONFIG_SUPERH
 213         const struct pinmux_func *func_gpios;
 214         unsigned int nr_func_gpios;
 215 #endif
 216
 217         const struct pinmux_cfg_reg *cfg_regs;
 218         const struct pinmux_drive_reg *drive_regs;
 219         const struct pinmux_data_reg *data_regs;
 220
 221         const u16 *pinmux_data;
 222         unsigned int pinmux_data_size;
 223
 224         const struct pinmux_irq *gpio_irq;
 225         unsigned int gpio_irq_size;
 226
 227         u32 unlock_reg;
 228 };
 229
 230 /* -----------------------------------------------------------------------------
 231  * Helper macros to create pin and port lists
 232  */
 233
 234 /*
 235  * sh_pfc_soc_info pinmux_data array macros
 236  */
 237
 238 /*
 239  * Describe generic pinmux data
 240  *   - data_or_mark: *_DATA or *_MARK enum ID
 241  *   - ids...: List of enum IDs to associate with data_or_mark
 242  */
 243 #define PINMUX_DATA(data_or_mark, ids...)       data_or_mark, ids, 0
 244
 245 /*
 246  * Describe a pinmux configuration without GPIO function that needs
 247  * configuration in a Peripheral Function Select Register (IPSR)
 248  *   - ipsr: IPSR field (unused, for documentation purposes only)
 249  *   - fn: Function name, referring to a field in the IPSR
 250  */
 251 #define PINMUX_IPSR_NOGP(ipsr, fn)                                      \
 252         PINMUX_DATA(fn##_MARK, FN_##fn)
 253
 254 /*
 255  * Describe a pinmux configuration with GPIO function that needs configuration
 256  * in both a Peripheral Function Select Register (IPSR) and in a
 257  * GPIO/Peripheral Function Select Register (GPSR)
 258  *   - ipsr: IPSR field
 259  *   - fn: Function name, also referring to the IPSR field
 260  */
 261 #define PINMUX_IPSR_GPSR(ipsr, fn)                                      \
 262         PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
 263
 264 /*
 265  * Describe a pinmux configuration without GPIO function that needs
 266  * configuration in a Peripheral Function Select Register (IPSR), and where the
 267  * pinmux function has a representation in a Module Select Register (MOD_SEL).
 268  *   - ipsr: IPSR field (unused, for documentation purposes only)
 269  *   - fn: Function name, also referring to the IPSR field
 270  *   - msel: Module selector
 271  */
 272 #define PINMUX_IPSR_NOGM(ipsr, fn, msel)                                \
 273         PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
 274
 275 /*
 276  * Describe a pinmux configuration with GPIO function where the pinmux function
 277  * has no representation in a Peripheral Function Select Register (IPSR), but
 278  * instead solely depends on a group selection.
 279  *   - gpsr: GPSR field
 280  *   - fn: Function name, also referring to the GPSR field
 281  *   - gsel: Group selector
 282  */
 283 #define PINMUX_IPSR_NOFN(gpsr, fn, gsel)                                \
 284         PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
 285
 286 /*
 287  * Describe a pinmux configuration with GPIO function that needs configuration
 288  * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
 289  * Function Select Register (GPSR), and where the pinmux function has a
 290  * representation in a Module Select Register (MOD_SEL).
 291  *   - ipsr: IPSR field
 292  *   - fn: Function name, also referring to the IPSR field
 293  *   - msel: Module selector
 294  */
 295 #define PINMUX_IPSR_MSEL(ipsr, fn, msel)                                \
 296         PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
 297
 298 /*
 299  * Describe a pinmux configuration for a single-function pin with GPIO
 300  * capability.
 301  *   - fn: Function name
 302  */
 303 #define PINMUX_SINGLE(fn)                                               \
 304         PINMUX_DATA(fn##_MARK, FN_##fn)
 305
 306 /*
 307  * GP port style (32 ports banks)
 308  */
 309
 310 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
 311 #define PORT_GP_1(bank, pin, fn, sfx)   PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
 312
 313 #define PORT_GP_CFG_4(bank, fn, sfx, cfg)                                               \
 314         PORT_GP_CFG_1(bank, 0,  fn, sfx, cfg), PORT_GP_CFG_1(bank, 1,  fn, sfx, cfg),   \
 315         PORT_GP_CFG_1(bank, 2,  fn, sfx, cfg), PORT_GP_CFG_1(bank, 3,  fn, sfx, cfg)
 316 #define PORT_GP_4(bank, fn, sfx)        PORT_GP_CFG_4(bank, fn, sfx, 0)
 317
 318 #define PORT_GP_CFG_8(bank, fn, sfx, cfg)                                               \
 319         PORT_GP_CFG_4(bank, fn, sfx, cfg),                                              \
 320         PORT_GP_CFG_1(bank, 4,  fn, sfx, cfg), PORT_GP_CFG_1(bank, 5,  fn, sfx, cfg),   \
 321         PORT_GP_CFG_1(bank, 6,  fn, sfx, cfg), PORT_GP_CFG_1(bank, 7,  fn, sfx, cfg)
 322 #define PORT_GP_8(bank, fn, sfx)        PORT_GP_CFG_8(bank, fn, sfx, 0)
 323
 324 #define PORT_GP_CFG_9(bank, fn, sfx, cfg)                                               \
 325         PORT_GP_CFG_8(bank, fn, sfx, cfg),                                              \
 326         PORT_GP_CFG_1(bank, 8,  fn, sfx, cfg)
 327 #define PORT_GP_9(bank, fn, sfx)        PORT_GP_CFG_9(bank, fn, sfx, 0)
 328
 329 #define PORT_GP_CFG_12(bank, fn, sfx, cfg)                                              \
 330         PORT_GP_CFG_8(bank, fn, sfx, cfg),                                              \
 331         PORT_GP_CFG_1(bank, 8,  fn, sfx, cfg), PORT_GP_CFG_1(bank, 9,  fn, sfx, cfg),   \
 332         PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
 333 #define PORT_GP_12(bank, fn, sfx)       PORT_GP_CFG_12(bank, fn, sfx, 0)
 334
 335 #define PORT_GP_CFG_14(bank, fn, sfx, cfg)                                              \
 336         PORT_GP_CFG_12(bank, fn, sfx, cfg),                                             \
 337         PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
 338 #define PORT_GP_14(bank, fn, sfx)       PORT_GP_CFG_14(bank, fn, sfx, 0)
 339
 340 #define PORT_GP_CFG_15(bank, fn, sfx, cfg)                                              \
 341         PORT_GP_CFG_14(bank, fn, sfx, cfg),                                             \
 342         PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
 343 #define PORT_GP_15(bank, fn, sfx)       PORT_GP_CFG_15(bank, fn, sfx, 0)
 344
 345 #define PORT_GP_CFG_16(bank, fn, sfx, cfg)                                              \
 346         PORT_GP_CFG_14(bank, fn, sfx, cfg),                                             \
 347         PORT_GP_CFG_1(bank, 14, fn, sfx, cfg), PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
 348 #define PORT_GP_16(bank, fn, sfx)       PORT_GP_CFG_16(bank, fn, sfx, 0)
 349
 350 #define PORT_GP_CFG_18(bank, fn, sfx, cfg)                                              \
 351         PORT_GP_CFG_16(bank, fn, sfx, cfg),                                             \
 352         PORT_GP_CFG_1(bank, 16, fn, sfx, cfg), PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
 353 #define PORT_GP_18(bank, fn, sfx)       PORT_GP_CFG_18(bank, fn, sfx, 0)
 354
 355 #define PORT_GP_CFG_26(bank, fn, sfx, cfg)                                              \
 356         PORT_GP_CFG_18(bank, fn, sfx, cfg),                                             \
 357         PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), PORT_GP_CFG_1(bank, 19, fn, sfx, cfg),   \
 358         PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), PORT_GP_CFG_1(bank, 21, fn, sfx, cfg),   \
 359         PORT_GP_CFG_1(bank, 22, fn, sfx, cfg), PORT_GP_CFG_1(bank, 23, fn, sfx, cfg),   \
 360         PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
 361 #define PORT_GP_26(bank, fn, sfx)       PORT_GP_CFG_26(bank, fn, sfx, 0)
 362
 363 #define PORT_GP_CFG_28(bank, fn, sfx, cfg)                                              \
 364         PORT_GP_CFG_26(bank, fn, sfx, cfg),                                             \
 365         PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
 366 #define PORT_GP_28(bank, fn, sfx)       PORT_GP_CFG_28(bank, fn, sfx, 0)
 367
 368 #define PORT_GP_CFG_30(bank, fn, sfx, cfg)                                              \
 369         PORT_GP_CFG_28(bank, fn, sfx, cfg),                                             \
 370         PORT_GP_CFG_1(bank, 28, fn, sfx, cfg), PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
 371 #define PORT_GP_30(bank, fn, sfx)       PORT_GP_CFG_30(bank, fn, sfx, 0)
 372
 373 #define PORT_GP_CFG_32(bank, fn, sfx, cfg)                                              \
 374         PORT_GP_CFG_30(bank, fn, sfx, cfg),                                             \
 375         PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
 376 #define PORT_GP_32(bank, fn, sfx)       PORT_GP_CFG_32(bank, fn, sfx, 0)
 377
 378 #define PORT_GP_32_REV(bank, fn, sfx)                                   \
 379         PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx),     \
 380         PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx),     \
 381         PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx),     \
 382         PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx),     \
 383         PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx),     \
 384         PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx),     \
 385         PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx),     \
 386         PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx),     \
 387         PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx),     \
 388         PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx),     \
 389         PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx),     \
 390         PORT_GP_1(bank, 9,  fn, sfx), PORT_GP_1(bank, 8,  fn, sfx),     \
 391         PORT_GP_1(bank, 7,  fn, sfx), PORT_GP_1(bank, 6,  fn, sfx),     \
 392         PORT_GP_1(bank, 5,  fn, sfx), PORT_GP_1(bank, 4,  fn, sfx),     \
 393         PORT_GP_1(bank, 3,  fn, sfx), PORT_GP_1(bank, 2,  fn, sfx),     \
 394         PORT_GP_1(bank, 1,  fn, sfx), PORT_GP_1(bank, 0,  fn, sfx)
 395
 396 /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
 397 #define _GP_ALL(bank, pin, name, sfx, cfg)      name##_##sfx
 398 #define GP_ALL(str)                     CPU_ALL_PORT(_GP_ALL, str)
 399
 400 /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
 401 #define _GP_GPIO(bank, _pin, _name, sfx, cfg)                           \
 402         {                                                               \
 403                 .pin = (bank * 32) + _pin,                              \
 404                 .name = __stringify(_name),                             \
 405                 .enum_id = _name##_DATA,                                \
 406                 .configs = cfg,                                         \
 407         }
 408 #define PINMUX_GPIO_GP_ALL()            CPU_ALL_PORT(_GP_GPIO, unused)
 409
 410 /* PINMUX_DATA_GP_ALL -  Expand to a list of name_DATA, name_FN marks */
 411 #define _GP_DATA(bank, pin, name, sfx, cfg)     PINMUX_DATA(name##_DATA, name##_FN)
 412 #define PINMUX_DATA_GP_ALL()            CPU_ALL_PORT(_GP_DATA, unused)
 413
 414 /*
 415  * PORT style (linear pin space)
 416  */
 417
 418 #define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
 419
 420 #define PORT_10(pn, fn, pfx, sfx)                                         \
 421         PORT_1(pn,   fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx),     \
 422         PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx),     \
 423         PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx),     \
 424         PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx),     \
 425         PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
 426
 427 #define PORT_90(pn, fn, pfx, sfx)                                         \
 428         PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
 429         PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
 430         PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
 431         PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
 432         PORT_10(pn+90, fn, pfx##9, sfx)
 433
 434 /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
 435 #define _PORT_ALL(pn, pfx, sfx)         pfx##_##sfx
 436 #define PORT_ALL(str)                   CPU_ALL_PORT(_PORT_ALL, PORT, str)
 437
 438 /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
 439 #define PINMUX_GPIO(_pin)                                               \
 440         [GPIO_##_pin] = {                                               \
 441                 .pin = (u16)-1,                                         \
 442                 .name = __stringify(GPIO_##_pin),                       \
 443                 .enum_id = _pin##_DATA,                                 \
 444         }
 445
 446 /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
 447 #define SH_PFC_PIN_CFG(_pin, cfgs)                                      \
 448         {                                                               \
 449                 .pin = _pin,                                            \
 450                 .name = __stringify(PORT##_pin),                        \
 451                 .enum_id = PORT##_pin##_DATA,                           \
 452                 .configs = cfgs,                                        \
 453         }
 454
 455 /* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */
 456 #define SH_PFC_PIN_NAMED(row, col, _name)                               \
 457         {                                                               \
 458                 .pin = PIN_NUMBER(row, col),                            \
 459                 .name = __stringify(PIN_##_name),                       \
 460                 .configs = SH_PFC_PIN_CFG_NO_GPIO,                      \
 461         }
 462
 463 /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
 464  *                   PORT_name_OUT, PORT_name_IN marks
 465  */
 466 #define _PORT_DATA(pn, pfx, sfx)                                        \
 467         PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0,                  \
 468                     PORT##pfx##_OUT, PORT##pfx##_IN)
 469 #define PINMUX_DATA_ALL()               CPU_ALL_PORT(_PORT_DATA, , unused)
 470
 471 /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
 472 #define PINMUX_GPIO_FN(gpio, base, data_or_mark)                        \
 473         [gpio - (base)] = {                                             \
 474                 .name = __stringify(gpio),                              \
 475                 .enum_id = data_or_mark,                                \
 476         }
 477 #define GPIO_FN(str)                                                    \
 478         PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
 479
 480 /*
 481  * PORTnCR helper macro for SH-Mobile/R-Mobile
 482  */
 483 #define PORTCR(nr, reg)                                                 \
 484         {                                                               \
 485                 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
 486                         /* PULMD[1:0], handled by .set_bias() */        \
 487                         0, 0, 0, 0,                                     \
 488                         /* IE and OE */                                 \
 489                         0, PORT##nr##_OUT, PORT##nr##_IN, 0,            \
 490                         /* SEC, not supported */                        \
 491                         0, 0,                                           \
 492                         /* PTMD[2:0] */                                 \
 493                         PORT##nr##_FN0, PORT##nr##_FN1,                 \
 494                         PORT##nr##_FN2, PORT##nr##_FN3,                 \
 495                         PORT##nr##_FN4, PORT##nr##_FN5,                 \
 496                         PORT##nr##_FN6, PORT##nr##_FN7                  \
 497                 }                                                       \
 498         }
 499
 500 /*
 501  * GPIO number helper macro for R-Car
 502  */
 503 #define RCAR_GP_PIN(bank, pin)          (((bank) * 32) + (pin))
 504
 505 #endif /* __SH_PFC_H */