2 * pinmux driver for CSR SiRFprimaII
4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
7 * Licensed under GPLv2 or later.
10 #include <linux/init.h>
11 #include <linux/module.h>
12 #include <linux/irq.h>
13 #include <linux/platform_device.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/pinctrl/pinctrl.h>
18 #include <linux/pinctrl/pinmux.h>
19 #include <linux/pinctrl/consumer.h>
20 #include <linux/pinctrl/machine.h>
22 #include <linux/of_address.h>
23 #include <linux/of_device.h>
24 #include <linux/of_platform.h>
25 #include <linux/bitops.h>
26 #include <linux/gpio.h>
27 #include <linux/of_gpio.h>
29 #include "pinctrl-sirf.h"
31 #define DRIVER_NAME "pinmux-sirf"
33 struct sirfsoc_gpio_bank
{
39 struct sirfsoc_gpio_chip
{
40 struct of_mm_gpio_chip chip
;
41 bool is_marco
; /* for marco, some registers are different with prima2 */
42 struct sirfsoc_gpio_bank sgpio_bank
[SIRFSOC_GPIO_NO_OF_BANKS
];
45 static DEFINE_SPINLOCK(sgpio_lock
);
47 static struct sirfsoc_pin_group
*sirfsoc_pin_groups
;
48 static int sirfsoc_pingrp_cnt
;
50 static int sirfsoc_get_groups_count(struct pinctrl_dev
*pctldev
)
52 return sirfsoc_pingrp_cnt
;
55 static const char *sirfsoc_get_group_name(struct pinctrl_dev
*pctldev
,
58 return sirfsoc_pin_groups
[selector
].name
;
61 static int sirfsoc_get_group_pins(struct pinctrl_dev
*pctldev
, unsigned selector
,
62 const unsigned **pins
,
65 *pins
= sirfsoc_pin_groups
[selector
].pins
;
66 *num_pins
= sirfsoc_pin_groups
[selector
].num_pins
;
70 static void sirfsoc_pin_dbg_show(struct pinctrl_dev
*pctldev
, struct seq_file
*s
,
73 seq_printf(s
, " " DRIVER_NAME
);
76 static int sirfsoc_dt_node_to_map(struct pinctrl_dev
*pctldev
,
77 struct device_node
*np_config
,
78 struct pinctrl_map
**map
, unsigned *num_maps
)
80 struct sirfsoc_pmx
*spmx
= pinctrl_dev_get_drvdata(pctldev
);
81 struct device_node
*np
;
82 struct property
*prop
;
83 const char *function
, *group
;
84 int ret
, index
= 0, count
= 0;
86 /* calculate number of maps required */
87 for_each_child_of_node(np_config
, np
) {
88 ret
= of_property_read_string(np
, "sirf,function", &function
);
92 ret
= of_property_count_strings(np
, "sirf,pins");
100 dev_err(spmx
->dev
, "No child nodes passed via DT\n");
104 *map
= kzalloc(sizeof(**map
) * count
, GFP_KERNEL
);
108 for_each_child_of_node(np_config
, np
) {
109 of_property_read_string(np
, "sirf,function", &function
);
110 of_property_for_each_string(np
, "sirf,pins", prop
, group
) {
111 (*map
)[index
].type
= PIN_MAP_TYPE_MUX_GROUP
;
112 (*map
)[index
].data
.mux
.group
= group
;
113 (*map
)[index
].data
.mux
.function
= function
;
123 static void sirfsoc_dt_free_map(struct pinctrl_dev
*pctldev
,
124 struct pinctrl_map
*map
, unsigned num_maps
)
129 static struct pinctrl_ops sirfsoc_pctrl_ops
= {
130 .get_groups_count
= sirfsoc_get_groups_count
,
131 .get_group_name
= sirfsoc_get_group_name
,
132 .get_group_pins
= sirfsoc_get_group_pins
,
133 .pin_dbg_show
= sirfsoc_pin_dbg_show
,
134 .dt_node_to_map
= sirfsoc_dt_node_to_map
,
135 .dt_free_map
= sirfsoc_dt_free_map
,
138 static struct sirfsoc_pmx_func
*sirfsoc_pmx_functions
;
139 static int sirfsoc_pmxfunc_cnt
;
141 static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx
*spmx
, unsigned selector
,
145 const struct sirfsoc_padmux
*mux
= sirfsoc_pmx_functions
[selector
].padmux
;
146 const struct sirfsoc_muxmask
*mask
= mux
->muxmask
;
148 for (i
= 0; i
< mux
->muxmask_counts
; i
++) {
150 if (!spmx
->is_marco
) {
151 muxval
= readl(spmx
->gpio_virtbase
+ SIRFSOC_GPIO_PAD_EN(mask
[i
].group
));
153 muxval
= muxval
& ~mask
[i
].mask
;
155 muxval
= muxval
| mask
[i
].mask
;
156 writel(muxval
, spmx
->gpio_virtbase
+ SIRFSOC_GPIO_PAD_EN(mask
[i
].group
));
159 writel(mask
[i
].mask
, spmx
->gpio_virtbase
+
160 SIRFSOC_GPIO_PAD_EN_CLR(mask
[i
].group
));
162 writel(mask
[i
].mask
, spmx
->gpio_virtbase
+
163 SIRFSOC_GPIO_PAD_EN(mask
[i
].group
));
167 if (mux
->funcmask
&& enable
) {
171 readl(spmx
->rsc_virtbase
+ mux
->ctrlreg
);
173 (func_en_val
& ~mux
->funcmask
) | (mux
->funcval
);
174 writel(func_en_val
, spmx
->rsc_virtbase
+ mux
->ctrlreg
);
178 static int sirfsoc_pinmux_enable(struct pinctrl_dev
*pmxdev
, unsigned selector
,
181 struct sirfsoc_pmx
*spmx
;
183 spmx
= pinctrl_dev_get_drvdata(pmxdev
);
184 sirfsoc_pinmux_endisable(spmx
, selector
, true);
189 static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev
*pmxdev
)
191 return sirfsoc_pmxfunc_cnt
;
194 static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev
*pctldev
,
197 return sirfsoc_pmx_functions
[selector
].name
;
200 static int sirfsoc_pinmux_get_groups(struct pinctrl_dev
*pctldev
, unsigned selector
,
201 const char * const **groups
,
202 unsigned * const num_groups
)
204 *groups
= sirfsoc_pmx_functions
[selector
].groups
;
205 *num_groups
= sirfsoc_pmx_functions
[selector
].num_groups
;
209 static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev
*pmxdev
,
210 struct pinctrl_gpio_range
*range
, unsigned offset
)
212 struct sirfsoc_pmx
*spmx
;
214 int group
= range
->id
;
218 spmx
= pinctrl_dev_get_drvdata(pmxdev
);
220 if (!spmx
->is_marco
) {
221 muxval
= readl(spmx
->gpio_virtbase
+ SIRFSOC_GPIO_PAD_EN(group
));
222 muxval
= muxval
| (1 << (offset
- range
->pin_base
));
223 writel(muxval
, spmx
->gpio_virtbase
+ SIRFSOC_GPIO_PAD_EN(group
));
225 writel(1 << (offset
- range
->pin_base
), spmx
->gpio_virtbase
+
226 SIRFSOC_GPIO_PAD_EN(group
));
232 static struct pinmux_ops sirfsoc_pinmux_ops
= {
233 .enable
= sirfsoc_pinmux_enable
,
234 .get_functions_count
= sirfsoc_pinmux_get_funcs_count
,
235 .get_function_name
= sirfsoc_pinmux_get_func_name
,
236 .get_function_groups
= sirfsoc_pinmux_get_groups
,
237 .gpio_request_enable
= sirfsoc_pinmux_request_gpio
,
240 static struct pinctrl_desc sirfsoc_pinmux_desc
= {
242 .pctlops
= &sirfsoc_pctrl_ops
,
243 .pmxops
= &sirfsoc_pinmux_ops
,
244 .owner
= THIS_MODULE
,
247 static void __iomem
*sirfsoc_rsc_of_iomap(void)
249 const struct of_device_id rsc_ids
[] = {
250 { .compatible
= "sirf,prima2-rsc" },
251 { .compatible
= "sirf,marco-rsc" },
254 struct device_node
*np
;
256 np
= of_find_matching_node(NULL
, rsc_ids
);
258 panic("unable to find compatible rsc node in dtb\n");
260 return of_iomap(np
, 0);
263 static int sirfsoc_gpio_of_xlate(struct gpio_chip
*gc
,
264 const struct of_phandle_args
*gpiospec
,
267 if (gpiospec
->args
[0] > SIRFSOC_GPIO_NO_OF_BANKS
* SIRFSOC_GPIO_BANK_SIZE
)
271 *flags
= gpiospec
->args
[1];
273 return gpiospec
->args
[0];
276 static const struct of_device_id pinmux_ids
[] = {
277 { .compatible
= "sirf,prima2-pinctrl", .data
= &prima2_pinctrl_data
, },
278 { .compatible
= "sirf,atlas6-pinctrl", .data
= &atlas6_pinctrl_data
, },
279 { .compatible
= "sirf,marco-pinctrl", .data
= &prima2_pinctrl_data
, },
283 static int sirfsoc_pinmux_probe(struct platform_device
*pdev
)
286 struct sirfsoc_pmx
*spmx
;
287 struct device_node
*np
= pdev
->dev
.of_node
;
288 const struct sirfsoc_pinctrl_data
*pdata
;
290 /* Create state holders etc for this driver */
291 spmx
= devm_kzalloc(&pdev
->dev
, sizeof(*spmx
), GFP_KERNEL
);
295 spmx
->dev
= &pdev
->dev
;
297 platform_set_drvdata(pdev
, spmx
);
299 spmx
->gpio_virtbase
= of_iomap(np
, 0);
300 if (!spmx
->gpio_virtbase
) {
301 dev_err(&pdev
->dev
, "can't map gpio registers\n");
305 spmx
->rsc_virtbase
= sirfsoc_rsc_of_iomap();
306 if (!spmx
->rsc_virtbase
) {
308 dev_err(&pdev
->dev
, "can't map rsc registers\n");
309 goto out_no_rsc_remap
;
312 if (of_device_is_compatible(np
, "sirf,marco-pinctrl"))
315 pdata
= of_match_node(pinmux_ids
, np
)->data
;
316 sirfsoc_pin_groups
= pdata
->grps
;
317 sirfsoc_pingrp_cnt
= pdata
->grps_cnt
;
318 sirfsoc_pmx_functions
= pdata
->funcs
;
319 sirfsoc_pmxfunc_cnt
= pdata
->funcs_cnt
;
320 sirfsoc_pinmux_desc
.pins
= pdata
->pads
;
321 sirfsoc_pinmux_desc
.npins
= pdata
->pads_cnt
;
324 /* Now register the pin controller and all pins it handles */
325 spmx
->pmx
= pinctrl_register(&sirfsoc_pinmux_desc
, &pdev
->dev
, spmx
);
327 dev_err(&pdev
->dev
, "could not register SIRFSOC pinmux driver\n");
332 dev_info(&pdev
->dev
, "initialized SIRFSOC pinmux driver\n");
337 iounmap(spmx
->rsc_virtbase
);
339 iounmap(spmx
->gpio_virtbase
);
343 #ifdef CONFIG_PM_SLEEP
344 static int sirfsoc_pinmux_suspend_noirq(struct device
*dev
)
347 struct sirfsoc_pmx
*spmx
= dev_get_drvdata(dev
);
349 for (i
= 0; i
< SIRFSOC_GPIO_NO_OF_BANKS
; i
++) {
350 for (j
= 0; j
< SIRFSOC_GPIO_BANK_SIZE
; j
++) {
351 spmx
->gpio_regs
[i
][j
] = readl(spmx
->gpio_virtbase
+
352 SIRFSOC_GPIO_CTRL(i
, j
));
354 spmx
->ints_regs
[i
] = readl(spmx
->gpio_virtbase
+
355 SIRFSOC_GPIO_INT_STATUS(i
));
356 spmx
->paden_regs
[i
] = readl(spmx
->gpio_virtbase
+
357 SIRFSOC_GPIO_PAD_EN(i
));
359 spmx
->dspen_regs
= readl(spmx
->gpio_virtbase
+ SIRFSOC_GPIO_DSP_EN0
);
361 for (i
= 0; i
< 3; i
++)
362 spmx
->rsc_regs
[i
] = readl(spmx
->rsc_virtbase
+ 4 * i
);
367 static int sirfsoc_pinmux_resume_noirq(struct device
*dev
)
370 struct sirfsoc_pmx
*spmx
= dev_get_drvdata(dev
);
372 for (i
= 0; i
< SIRFSOC_GPIO_NO_OF_BANKS
; i
++) {
373 for (j
= 0; j
< SIRFSOC_GPIO_BANK_SIZE
; j
++) {
374 writel(spmx
->gpio_regs
[i
][j
], spmx
->gpio_virtbase
+
375 SIRFSOC_GPIO_CTRL(i
, j
));
377 writel(spmx
->ints_regs
[i
], spmx
->gpio_virtbase
+
378 SIRFSOC_GPIO_INT_STATUS(i
));
379 writel(spmx
->paden_regs
[i
], spmx
->gpio_virtbase
+
380 SIRFSOC_GPIO_PAD_EN(i
));
382 writel(spmx
->dspen_regs
, spmx
->gpio_virtbase
+ SIRFSOC_GPIO_DSP_EN0
);
384 for (i
= 0; i
< 3; i
++)
385 writel(spmx
->rsc_regs
[i
], spmx
->rsc_virtbase
+ 4 * i
);
390 static const struct dev_pm_ops sirfsoc_pinmux_pm_ops
= {
391 .suspend_noirq
= sirfsoc_pinmux_suspend_noirq
,
392 .resume_noirq
= sirfsoc_pinmux_resume_noirq
,
393 .freeze_noirq
= sirfsoc_pinmux_suspend_noirq
,
394 .restore_noirq
= sirfsoc_pinmux_resume_noirq
,
398 static struct platform_driver sirfsoc_pinmux_driver
= {
401 .owner
= THIS_MODULE
,
402 .of_match_table
= pinmux_ids
,
403 #ifdef CONFIG_PM_SLEEP
404 .pm
= &sirfsoc_pinmux_pm_ops
,
407 .probe
= sirfsoc_pinmux_probe
,
410 static int __init
sirfsoc_pinmux_init(void)
412 return platform_driver_register(&sirfsoc_pinmux_driver
);
414 arch_initcall(sirfsoc_pinmux_init
);
416 static inline struct sirfsoc_gpio_chip
*to_sirfsoc_gpio(struct gpio_chip
*gc
)
418 return container_of(gc
, struct sirfsoc_gpio_chip
, chip
.gc
);
421 static inline struct sirfsoc_gpio_bank
*
422 sirfsoc_gpio_to_bank(struct sirfsoc_gpio_chip
*sgpio
, unsigned int offset
)
424 return &sgpio
->sgpio_bank
[offset
/ SIRFSOC_GPIO_BANK_SIZE
];
427 static inline int sirfsoc_gpio_to_bankoff(unsigned int offset
)
429 return offset
% SIRFSOC_GPIO_BANK_SIZE
;
432 static void sirfsoc_gpio_irq_ack(struct irq_data
*d
)
434 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
435 struct sirfsoc_gpio_chip
*sgpio
= to_sirfsoc_gpio(gc
);
436 struct sirfsoc_gpio_bank
*bank
= sirfsoc_gpio_to_bank(sgpio
, d
->hwirq
);
437 int idx
= sirfsoc_gpio_to_bankoff(d
->hwirq
);
441 offset
= SIRFSOC_GPIO_CTRL(bank
->id
, idx
);
443 spin_lock_irqsave(&sgpio_lock
, flags
);
445 val
= readl(sgpio
->chip
.regs
+ offset
);
447 writel(val
, sgpio
->chip
.regs
+ offset
);
449 spin_unlock_irqrestore(&sgpio_lock
, flags
);
452 static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip
*sgpio
,
453 struct sirfsoc_gpio_bank
*bank
,
459 offset
= SIRFSOC_GPIO_CTRL(bank
->id
, idx
);
461 spin_lock_irqsave(&sgpio_lock
, flags
);
463 val
= readl(sgpio
->chip
.regs
+ offset
);
464 val
&= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK
;
465 val
&= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK
;
466 writel(val
, sgpio
->chip
.regs
+ offset
);
468 spin_unlock_irqrestore(&sgpio_lock
, flags
);
471 static void sirfsoc_gpio_irq_mask(struct irq_data
*d
)
473 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
474 struct sirfsoc_gpio_chip
*sgpio
= to_sirfsoc_gpio(gc
);
475 struct sirfsoc_gpio_bank
*bank
= sirfsoc_gpio_to_bank(sgpio
, d
->hwirq
);
477 __sirfsoc_gpio_irq_mask(sgpio
, bank
, d
->hwirq
% SIRFSOC_GPIO_BANK_SIZE
);
480 static void sirfsoc_gpio_irq_unmask(struct irq_data
*d
)
482 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
483 struct sirfsoc_gpio_chip
*sgpio
= to_sirfsoc_gpio(gc
);
484 struct sirfsoc_gpio_bank
*bank
= sirfsoc_gpio_to_bank(sgpio
, d
->hwirq
);
485 int idx
= sirfsoc_gpio_to_bankoff(d
->hwirq
);
489 offset
= SIRFSOC_GPIO_CTRL(bank
->id
, idx
);
491 spin_lock_irqsave(&sgpio_lock
, flags
);
493 val
= readl(sgpio
->chip
.regs
+ offset
);
494 val
&= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK
;
495 val
|= SIRFSOC_GPIO_CTL_INTR_EN_MASK
;
496 writel(val
, sgpio
->chip
.regs
+ offset
);
498 spin_unlock_irqrestore(&sgpio_lock
, flags
);
501 static int sirfsoc_gpio_irq_type(struct irq_data
*d
, unsigned type
)
503 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
504 struct sirfsoc_gpio_chip
*sgpio
= to_sirfsoc_gpio(gc
);
505 struct sirfsoc_gpio_bank
*bank
= sirfsoc_gpio_to_bank(sgpio
, d
->hwirq
);
506 int idx
= sirfsoc_gpio_to_bankoff(d
->hwirq
);
510 offset
= SIRFSOC_GPIO_CTRL(bank
->id
, idx
);
512 spin_lock_irqsave(&sgpio_lock
, flags
);
514 val
= readl(sgpio
->chip
.regs
+ offset
);
515 val
&= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK
| SIRFSOC_GPIO_CTL_OUT_EN_MASK
);
520 case IRQ_TYPE_EDGE_RISING
:
521 val
|= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK
| SIRFSOC_GPIO_CTL_INTR_TYPE_MASK
;
522 val
&= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK
;
524 case IRQ_TYPE_EDGE_FALLING
:
525 val
&= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK
;
526 val
|= SIRFSOC_GPIO_CTL_INTR_LOW_MASK
| SIRFSOC_GPIO_CTL_INTR_TYPE_MASK
;
528 case IRQ_TYPE_EDGE_BOTH
:
529 val
|= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK
| SIRFSOC_GPIO_CTL_INTR_LOW_MASK
|
530 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK
;
532 case IRQ_TYPE_LEVEL_LOW
:
533 val
&= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK
| SIRFSOC_GPIO_CTL_INTR_TYPE_MASK
);
534 val
|= SIRFSOC_GPIO_CTL_INTR_LOW_MASK
;
536 case IRQ_TYPE_LEVEL_HIGH
:
537 val
|= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK
;
538 val
&= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK
| SIRFSOC_GPIO_CTL_INTR_TYPE_MASK
);
542 writel(val
, sgpio
->chip
.regs
+ offset
);
544 spin_unlock_irqrestore(&sgpio_lock
, flags
);
549 static struct irq_chip sirfsoc_irq_chip
= {
550 .name
= "sirf-gpio-irq",
551 .irq_ack
= sirfsoc_gpio_irq_ack
,
552 .irq_mask
= sirfsoc_gpio_irq_mask
,
553 .irq_unmask
= sirfsoc_gpio_irq_unmask
,
554 .irq_set_type
= sirfsoc_gpio_irq_type
,
557 static void sirfsoc_gpio_handle_irq(unsigned int irq
, struct irq_desc
*desc
)
559 struct gpio_chip
*gc
= irq_desc_get_handler_data(desc
);
560 struct sirfsoc_gpio_chip
*sgpio
= to_sirfsoc_gpio(gc
);
561 struct sirfsoc_gpio_bank
*bank
;
564 struct irq_chip
*chip
= irq_get_chip(irq
);
567 for (i
= 0; i
< SIRFSOC_GPIO_NO_OF_BANKS
; i
++) {
568 bank
= &sgpio
->sgpio_bank
[i
];
569 if (bank
->parent_irq
== irq
)
572 BUG_ON(i
== SIRFSOC_GPIO_NO_OF_BANKS
);
574 chained_irq_enter(chip
, desc
);
576 status
= readl(sgpio
->chip
.regs
+ SIRFSOC_GPIO_INT_STATUS(bank
->id
));
579 "%s: gpio id %d status %#x no interrupt is flaged\n",
580 __func__
, bank
->id
, status
);
581 handle_bad_irq(irq
, desc
);
586 ctrl
= readl(sgpio
->chip
.regs
+ SIRFSOC_GPIO_CTRL(bank
->id
, idx
));
589 * Here we must check whether the corresponding GPIO's interrupt
590 * has been enabled, otherwise just skip it
592 if ((status
& 0x1) && (ctrl
& SIRFSOC_GPIO_CTL_INTR_EN_MASK
)) {
593 pr_debug("%s: gpio id %d idx %d happens\n",
594 __func__
, bank
->id
, idx
);
595 generic_handle_irq(irq_find_mapping(gc
->irqdomain
, idx
+
596 bank
->id
* SIRFSOC_GPIO_BANK_SIZE
));
600 status
= status
>> 1;
603 chained_irq_exit(chip
, desc
);
606 static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_chip
*sgpio
,
607 unsigned ctrl_offset
)
611 val
= readl(sgpio
->chip
.regs
+ ctrl_offset
);
612 val
&= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK
;
613 writel(val
, sgpio
->chip
.regs
+ ctrl_offset
);
616 static int sirfsoc_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
618 struct sirfsoc_gpio_chip
*sgpio
= to_sirfsoc_gpio(chip
);
619 struct sirfsoc_gpio_bank
*bank
= sirfsoc_gpio_to_bank(sgpio
, offset
);
622 if (pinctrl_request_gpio(chip
->base
+ offset
))
625 spin_lock_irqsave(&bank
->lock
, flags
);
629 * set direction as input and mask irq
631 sirfsoc_gpio_set_input(sgpio
, SIRFSOC_GPIO_CTRL(bank
->id
, offset
));
632 __sirfsoc_gpio_irq_mask(sgpio
, bank
, offset
);
634 spin_unlock_irqrestore(&bank
->lock
, flags
);
639 static void sirfsoc_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
641 struct sirfsoc_gpio_chip
*sgpio
= to_sirfsoc_gpio(chip
);
642 struct sirfsoc_gpio_bank
*bank
= sirfsoc_gpio_to_bank(sgpio
, offset
);
645 spin_lock_irqsave(&bank
->lock
, flags
);
647 __sirfsoc_gpio_irq_mask(sgpio
, bank
, offset
);
648 sirfsoc_gpio_set_input(sgpio
, SIRFSOC_GPIO_CTRL(bank
->id
, offset
));
650 spin_unlock_irqrestore(&bank
->lock
, flags
);
652 pinctrl_free_gpio(chip
->base
+ offset
);
655 static int sirfsoc_gpio_direction_input(struct gpio_chip
*chip
, unsigned gpio
)
657 struct sirfsoc_gpio_chip
*sgpio
= to_sirfsoc_gpio(chip
);
658 struct sirfsoc_gpio_bank
*bank
= sirfsoc_gpio_to_bank(sgpio
, gpio
);
659 int idx
= sirfsoc_gpio_to_bankoff(gpio
);
663 offset
= SIRFSOC_GPIO_CTRL(bank
->id
, idx
);
665 spin_lock_irqsave(&bank
->lock
, flags
);
667 sirfsoc_gpio_set_input(sgpio
, offset
);
669 spin_unlock_irqrestore(&bank
->lock
, flags
);
674 static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_chip
*sgpio
,
675 struct sirfsoc_gpio_bank
*bank
,
682 spin_lock_irqsave(&bank
->lock
, flags
);
684 out_ctrl
= readl(sgpio
->chip
.regs
+ offset
);
686 out_ctrl
|= SIRFSOC_GPIO_CTL_DATAOUT_MASK
;
688 out_ctrl
&= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK
;
690 out_ctrl
&= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK
;
691 out_ctrl
|= SIRFSOC_GPIO_CTL_OUT_EN_MASK
;
692 writel(out_ctrl
, sgpio
->chip
.regs
+ offset
);
694 spin_unlock_irqrestore(&bank
->lock
, flags
);
697 static int sirfsoc_gpio_direction_output(struct gpio_chip
*chip
, unsigned gpio
, int value
)
699 struct sirfsoc_gpio_chip
*sgpio
= to_sirfsoc_gpio(chip
);
700 struct sirfsoc_gpio_bank
*bank
= sirfsoc_gpio_to_bank(sgpio
, gpio
);
701 int idx
= sirfsoc_gpio_to_bankoff(gpio
);
705 offset
= SIRFSOC_GPIO_CTRL(bank
->id
, idx
);
707 spin_lock_irqsave(&sgpio_lock
, flags
);
709 sirfsoc_gpio_set_output(sgpio
, bank
, offset
, value
);
711 spin_unlock_irqrestore(&sgpio_lock
, flags
);
716 static int sirfsoc_gpio_get_value(struct gpio_chip
*chip
, unsigned offset
)
718 struct sirfsoc_gpio_chip
*sgpio
= to_sirfsoc_gpio(chip
);
719 struct sirfsoc_gpio_bank
*bank
= sirfsoc_gpio_to_bank(sgpio
, offset
);
723 spin_lock_irqsave(&bank
->lock
, flags
);
725 val
= readl(sgpio
->chip
.regs
+ SIRFSOC_GPIO_CTRL(bank
->id
, offset
));
727 spin_unlock_irqrestore(&bank
->lock
, flags
);
729 return !!(val
& SIRFSOC_GPIO_CTL_DATAIN_MASK
);
732 static void sirfsoc_gpio_set_value(struct gpio_chip
*chip
, unsigned offset
,
735 struct sirfsoc_gpio_chip
*sgpio
= to_sirfsoc_gpio(chip
);
736 struct sirfsoc_gpio_bank
*bank
= sirfsoc_gpio_to_bank(sgpio
, offset
);
740 spin_lock_irqsave(&bank
->lock
, flags
);
742 ctrl
= readl(sgpio
->chip
.regs
+ SIRFSOC_GPIO_CTRL(bank
->id
, offset
));
744 ctrl
|= SIRFSOC_GPIO_CTL_DATAOUT_MASK
;
746 ctrl
&= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK
;
747 writel(ctrl
, sgpio
->chip
.regs
+ SIRFSOC_GPIO_CTRL(bank
->id
, offset
));
749 spin_unlock_irqrestore(&bank
->lock
, flags
);
752 static void sirfsoc_gpio_set_pullup(struct sirfsoc_gpio_chip
*sgpio
,
756 const unsigned long *p
= (const unsigned long *)pullups
;
758 for (i
= 0; i
< SIRFSOC_GPIO_NO_OF_BANKS
; i
++) {
759 for_each_set_bit(n
, p
+ i
, BITS_PER_LONG
) {
760 u32 offset
= SIRFSOC_GPIO_CTRL(i
, n
);
761 u32 val
= readl(sgpio
->chip
.regs
+ offset
);
762 val
|= SIRFSOC_GPIO_CTL_PULL_MASK
;
763 val
|= SIRFSOC_GPIO_CTL_PULL_HIGH
;
764 writel(val
, sgpio
->chip
.regs
+ offset
);
769 static void sirfsoc_gpio_set_pulldown(struct sirfsoc_gpio_chip
*sgpio
,
770 const u32
*pulldowns
)
773 const unsigned long *p
= (const unsigned long *)pulldowns
;
775 for (i
= 0; i
< SIRFSOC_GPIO_NO_OF_BANKS
; i
++) {
776 for_each_set_bit(n
, p
+ i
, BITS_PER_LONG
) {
777 u32 offset
= SIRFSOC_GPIO_CTRL(i
, n
);
778 u32 val
= readl(sgpio
->chip
.regs
+ offset
);
779 val
|= SIRFSOC_GPIO_CTL_PULL_MASK
;
780 val
&= ~SIRFSOC_GPIO_CTL_PULL_HIGH
;
781 writel(val
, sgpio
->chip
.regs
+ offset
);
786 static int sirfsoc_gpio_probe(struct device_node
*np
)
789 static struct sirfsoc_gpio_chip
*sgpio
;
790 struct sirfsoc_gpio_bank
*bank
;
792 struct platform_device
*pdev
;
793 bool is_marco
= false;
795 u32 pullups
[SIRFSOC_GPIO_NO_OF_BANKS
], pulldowns
[SIRFSOC_GPIO_NO_OF_BANKS
];
797 pdev
= of_find_device_by_node(np
);
801 sgpio
= devm_kzalloc(&pdev
->dev
, sizeof(*sgpio
), GFP_KERNEL
);
805 regs
= of_iomap(np
, 0);
809 if (of_device_is_compatible(np
, "sirf,marco-pinctrl"))
812 sgpio
->chip
.gc
.request
= sirfsoc_gpio_request
;
813 sgpio
->chip
.gc
.free
= sirfsoc_gpio_free
;
814 sgpio
->chip
.gc
.direction_input
= sirfsoc_gpio_direction_input
;
815 sgpio
->chip
.gc
.get
= sirfsoc_gpio_get_value
;
816 sgpio
->chip
.gc
.direction_output
= sirfsoc_gpio_direction_output
;
817 sgpio
->chip
.gc
.set
= sirfsoc_gpio_set_value
;
818 sgpio
->chip
.gc
.base
= 0;
819 sgpio
->chip
.gc
.ngpio
= SIRFSOC_GPIO_BANK_SIZE
* SIRFSOC_GPIO_NO_OF_BANKS
;
820 sgpio
->chip
.gc
.label
= kstrdup(np
->full_name
, GFP_KERNEL
);
821 sgpio
->chip
.gc
.of_node
= np
;
822 sgpio
->chip
.gc
.of_xlate
= sirfsoc_gpio_of_xlate
;
823 sgpio
->chip
.gc
.of_gpio_n_cells
= 2;
824 sgpio
->chip
.gc
.dev
= &pdev
->dev
;
825 sgpio
->chip
.regs
= regs
;
826 sgpio
->is_marco
= is_marco
;
828 err
= gpiochip_add(&sgpio
->chip
.gc
);
830 dev_err(&pdev
->dev
, "%s: error in probe function with status %d\n",
835 err
= gpiochip_irqchip_add(&sgpio
->chip
.gc
,
841 "could not connect irqchip to gpiochip\n");
845 for (i
= 0; i
< SIRFSOC_GPIO_NO_OF_BANKS
; i
++) {
846 bank
= &sgpio
->sgpio_bank
[i
];
847 spin_lock_init(&bank
->lock
);
848 bank
->parent_irq
= platform_get_irq(pdev
, i
);
849 if (bank
->parent_irq
< 0) {
850 err
= bank
->parent_irq
;
854 gpiochip_set_chained_irqchip(&sgpio
->chip
.gc
,
857 sirfsoc_gpio_handle_irq
);
860 err
= gpiochip_add_pin_range(&sgpio
->chip
.gc
, dev_name(&pdev
->dev
),
861 0, 0, SIRFSOC_GPIO_BANK_SIZE
* SIRFSOC_GPIO_NO_OF_BANKS
);
864 "could not add gpiochip pin range\n");
868 if (!of_property_read_u32_array(np
, "sirf,pullups", pullups
,
869 SIRFSOC_GPIO_NO_OF_BANKS
))
870 sirfsoc_gpio_set_pullup(sgpio
, pullups
);
872 if (!of_property_read_u32_array(np
, "sirf,pulldowns", pulldowns
,
873 SIRFSOC_GPIO_NO_OF_BANKS
))
874 sirfsoc_gpio_set_pulldown(sgpio
, pulldowns
);
880 if (gpiochip_remove(&sgpio
->chip
.gc
))
881 dev_err(&pdev
->dev
, "could not remove gpio chip\n");
887 static int __init
sirfsoc_gpio_init(void)
890 struct device_node
*np
;
892 np
= of_find_matching_node(NULL
, pinmux_ids
);
897 return sirfsoc_gpio_probe(np
);
899 subsys_initcall(sirfsoc_gpio_init
);
901 MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, "
902 "Yuping Luo <yuping.luo@csr.com>, "
903 "Barry Song <baohua.song@csr.com>");
904 MODULE_DESCRIPTION("SIRFSOC pin control driver");
905 MODULE_LICENSE("GPL");