drivers/pinctrl/sirf/pinctrl-sirf.c

   1 /*
   2  * pinmux driver for CSR SiRFprimaII
   3  *
   4  * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
   5  * company.
   6  *
   7  * Licensed under GPLv2 or later.
   8  */
   9
  10 #include <linux/init.h>
  11 #include <linux/module.h>
  12 #include <linux/irq.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/io.h>
  15 #include <linux/slab.h>
  16 #include <linux/err.h>
  17 #include <linux/pinctrl/pinctrl.h>
  18 #include <linux/pinctrl/pinmux.h>
  19 #include <linux/pinctrl/consumer.h>
  20 #include <linux/pinctrl/machine.h>
  21 #include <linux/of.h>
  22 #include <linux/of_address.h>
  23 #include <linux/of_device.h>
  24 #include <linux/of_platform.h>
  25 #include <linux/bitops.h>
  26 #include <linux/gpio.h>
  27 #include <linux/of_gpio.h>
  28
  29 #include "pinctrl-sirf.h"
  30
  31 #define DRIVER_NAME "pinmux-sirf"
  32
  33 struct sirfsoc_gpio_bank {
  34         int id;
  35         int parent_irq;
  36         spinlock_t lock;
  37 };
  38
  39 struct sirfsoc_gpio_chip {
  40         struct of_mm_gpio_chip chip;
  41         bool is_marco; /* for marco, some registers are different with prima2 */
  42         struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
  43 };
  44
  45 static DEFINE_SPINLOCK(sgpio_lock);
  46
  47 static struct sirfsoc_pin_group *sirfsoc_pin_groups;
  48 static int sirfsoc_pingrp_cnt;
  49
  50 static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
  51 {
  52         return sirfsoc_pingrp_cnt;
  53 }
  54
  55 static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
  56                                        unsigned selector)
  57 {
  58         return sirfsoc_pin_groups[selector].name;
  59 }
  60
  61 static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
  62                                const unsigned **pins,
  63                                unsigned *num_pins)
  64 {
  65         *pins = sirfsoc_pin_groups[selector].pins;
  66         *num_pins = sirfsoc_pin_groups[selector].num_pins;
  67         return 0;
  68 }
  69
  70 static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
  71                    unsigned offset)
  72 {
  73         seq_printf(s, " " DRIVER_NAME);
  74 }
  75
  76 static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev,
  77                                  struct device_node *np_config,
  78                                  struct pinctrl_map **map, unsigned *num_maps)
  79 {
  80         struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev);
  81         struct device_node *np;
  82         struct property *prop;
  83         const char *function, *group;
  84         int ret, index = 0, count = 0;
  85
  86         /* calculate number of maps required */
  87         for_each_child_of_node(np_config, np) {
  88                 ret = of_property_read_string(np, "sirf,function", &function);
  89                 if (ret < 0)
  90                         return ret;
  91
  92                 ret = of_property_count_strings(np, "sirf,pins");
  93                 if (ret < 0)
  94                         return ret;
  95
  96                 count += ret;
  97         }
  98
  99         if (!count) {
 100                 dev_err(spmx->dev, "No child nodes passed via DT\n");
 101                 return -ENODEV;
 102         }
 103
 104         *map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
 105         if (!*map)
 106                 return -ENOMEM;
 107
 108         for_each_child_of_node(np_config, np) {
 109                 of_property_read_string(np, "sirf,function", &function);
 110                 of_property_for_each_string(np, "sirf,pins", prop, group) {
 111                         (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
 112                         (*map)[index].data.mux.group = group;
 113                         (*map)[index].data.mux.function = function;
 114                         index++;
 115                 }
 116         }
 117
 118         *num_maps = count;
 119
 120         return 0;
 121 }
 122
 123 static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
 124                 struct pinctrl_map *map, unsigned num_maps)
 125 {
 126         kfree(map);
 127 }
 128
 129 static struct pinctrl_ops sirfsoc_pctrl_ops = {
 130         .get_groups_count = sirfsoc_get_groups_count,
 131         .get_group_name = sirfsoc_get_group_name,
 132         .get_group_pins = sirfsoc_get_group_pins,
 133         .pin_dbg_show = sirfsoc_pin_dbg_show,
 134         .dt_node_to_map = sirfsoc_dt_node_to_map,
 135         .dt_free_map = sirfsoc_dt_free_map,
 136 };
 137
 138 static struct sirfsoc_pmx_func *sirfsoc_pmx_functions;
 139 static int sirfsoc_pmxfunc_cnt;
 140
 141 static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector,
 142         bool enable)
 143 {
 144         int i;
 145         const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux;
 146         const struct sirfsoc_muxmask *mask = mux->muxmask;
 147
 148         for (i = 0; i < mux->muxmask_counts; i++) {
 149                 u32 muxval;
 150                 if (!spmx->is_marco) {
 151                         muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
 152                         if (enable)
 153                                 muxval = muxval & ~mask[i].mask;
 154                         else
 155                                 muxval = muxval | mask[i].mask;
 156                         writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
 157                 } else {
 158                         if (enable)
 159                                 writel(mask[i].mask, spmx->gpio_virtbase +
 160                                         SIRFSOC_GPIO_PAD_EN_CLR(mask[i].group));
 161                         else
 162                                 writel(mask[i].mask, spmx->gpio_virtbase +
 163                                         SIRFSOC_GPIO_PAD_EN(mask[i].group));
 164                 }
 165         }
 166
 167         if (mux->funcmask && enable) {
 168                 u32 func_en_val;
 169
 170                 func_en_val =
 171                         readl(spmx->rsc_virtbase + mux->ctrlreg);
 172                 func_en_val =
 173                         (func_en_val & ~mux->funcmask) | (mux->funcval);
 174                 writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg);
 175         }
 176 }
 177
 178 static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector,
 179         unsigned group)
 180 {
 181         struct sirfsoc_pmx *spmx;
 182
 183         spmx = pinctrl_dev_get_drvdata(pmxdev);
 184         sirfsoc_pinmux_endisable(spmx, selector, true);
 185
 186         return 0;
 187 }
 188
 189 static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector,
 190         unsigned group)
 191 {
 192         struct sirfsoc_pmx *spmx;
 193
 194         spmx = pinctrl_dev_get_drvdata(pmxdev);
 195         sirfsoc_pinmux_endisable(spmx, selector, false);
 196 }
 197
 198 static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
 199 {
 200         return sirfsoc_pmxfunc_cnt;
 201 }
 202
 203 static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
 204                                           unsigned selector)
 205 {
 206         return sirfsoc_pmx_functions[selector].name;
 207 }
 208
 209 static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
 210                                const char * const **groups,
 211                                unsigned * const num_groups)
 212 {
 213         *groups = sirfsoc_pmx_functions[selector].groups;
 214         *num_groups = sirfsoc_pmx_functions[selector].num_groups;
 215         return 0;
 216 }
 217
 218 static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
 219         struct pinctrl_gpio_range *range, unsigned offset)
 220 {
 221         struct sirfsoc_pmx *spmx;
 222
 223         int group = range->id;
 224
 225         u32 muxval;
 226
 227         spmx = pinctrl_dev_get_drvdata(pmxdev);
 228
 229         if (!spmx->is_marco) {
 230                 muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
 231                 muxval = muxval | (1 << (offset - range->pin_base));
 232                 writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
 233         } else {
 234                 writel(1 << (offset - range->pin_base), spmx->gpio_virtbase +
 235                         SIRFSOC_GPIO_PAD_EN(group));
 236         }
 237
 238         return 0;
 239 }
 240
 241 static struct pinmux_ops sirfsoc_pinmux_ops = {
 242         .enable = sirfsoc_pinmux_enable,
 243         .disable = sirfsoc_pinmux_disable,
 244         .get_functions_count = sirfsoc_pinmux_get_funcs_count,
 245         .get_function_name = sirfsoc_pinmux_get_func_name,
 246         .get_function_groups = sirfsoc_pinmux_get_groups,
 247         .gpio_request_enable = sirfsoc_pinmux_request_gpio,
 248 };
 249
 250 static struct pinctrl_desc sirfsoc_pinmux_desc = {
 251         .name = DRIVER_NAME,
 252         .pctlops = &sirfsoc_pctrl_ops,
 253         .pmxops = &sirfsoc_pinmux_ops,
 254         .owner = THIS_MODULE,
 255 };
 256
 257 static void __iomem *sirfsoc_rsc_of_iomap(void)
 258 {
 259         const struct of_device_id rsc_ids[]  = {
 260                 { .compatible = "sirf,prima2-rsc" },
 261                 { .compatible = "sirf,marco-rsc" },
 262                 {}
 263         };
 264         struct device_node *np;
 265
 266         np = of_find_matching_node(NULL, rsc_ids);
 267         if (!np)
 268                 panic("unable to find compatible rsc node in dtb\n");
 269
 270         return of_iomap(np, 0);
 271 }
 272
 273 static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc,
 274         const struct of_phandle_args *gpiospec,
 275         u32 *flags)
 276 {
 277         if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE)
 278                 return -EINVAL;
 279
 280         if (flags)
 281                 *flags = gpiospec->args[1];
 282
 283         return gpiospec->args[0];
 284 }
 285
 286 static const struct of_device_id pinmux_ids[] = {
 287         { .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, },
 288         { .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, },
 289         { .compatible = "sirf,marco-pinctrl", .data = &prima2_pinctrl_data, },
 290         {}
 291 };
 292
 293 static int sirfsoc_pinmux_probe(struct platform_device *pdev)
 294 {
 295         int ret;
 296         struct sirfsoc_pmx *spmx;
 297         struct device_node *np = pdev->dev.of_node;
 298         const struct sirfsoc_pinctrl_data *pdata;
 299
 300         /* Create state holders etc for this driver */
 301         spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL);
 302         if (!spmx)
 303                 return -ENOMEM;
 304
 305         spmx->dev = &pdev->dev;
 306
 307         platform_set_drvdata(pdev, spmx);
 308
 309         spmx->gpio_virtbase = of_iomap(np, 0);
 310         if (!spmx->gpio_virtbase) {
 311                 dev_err(&pdev->dev, "can't map gpio registers\n");
 312                 return -ENOMEM;
 313         }
 314
 315         spmx->rsc_virtbase = sirfsoc_rsc_of_iomap();
 316         if (!spmx->rsc_virtbase) {
 317                 ret = -ENOMEM;
 318                 dev_err(&pdev->dev, "can't map rsc registers\n");
 319                 goto out_no_rsc_remap;
 320         }
 321
 322         if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
 323                 spmx->is_marco = 1;
 324
 325         pdata = of_match_node(pinmux_ids, np)->data;
 326         sirfsoc_pin_groups = pdata->grps;
 327         sirfsoc_pingrp_cnt = pdata->grps_cnt;
 328         sirfsoc_pmx_functions = pdata->funcs;
 329         sirfsoc_pmxfunc_cnt = pdata->funcs_cnt;
 330         sirfsoc_pinmux_desc.pins = pdata->pads;
 331         sirfsoc_pinmux_desc.npins = pdata->pads_cnt;
 332
 333
 334         /* Now register the pin controller and all pins it handles */
 335         spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx);
 336         if (!spmx->pmx) {
 337                 dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n");
 338                 ret = -EINVAL;
 339                 goto out_no_pmx;
 340         }
 341
 342         dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
 343
 344         return 0;
 345
 346 out_no_pmx:
 347         iounmap(spmx->rsc_virtbase);
 348 out_no_rsc_remap:
 349         iounmap(spmx->gpio_virtbase);
 350         return ret;
 351 }
 352
 353 #ifdef CONFIG_PM_SLEEP
 354 static int sirfsoc_pinmux_suspend_noirq(struct device *dev)
 355 {
 356         int i, j;
 357         struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
 358
 359         for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
 360                 for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
 361                         spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase +
 362                                 SIRFSOC_GPIO_CTRL(i, j));
 363                 }
 364                 spmx->ints_regs[i] = readl(spmx->gpio_virtbase +
 365                         SIRFSOC_GPIO_INT_STATUS(i));
 366                 spmx->paden_regs[i] = readl(spmx->gpio_virtbase +
 367                         SIRFSOC_GPIO_PAD_EN(i));
 368         }
 369         spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
 370
 371         for (i = 0; i < 3; i++)
 372                 spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i);
 373
 374         return 0;
 375 }
 376
 377 static int sirfsoc_pinmux_resume_noirq(struct device *dev)
 378 {
 379         int i, j;
 380         struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
 381
 382         for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
 383                 for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
 384                         writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase +
 385                                 SIRFSOC_GPIO_CTRL(i, j));
 386                 }
 387                 writel(spmx->ints_regs[i], spmx->gpio_virtbase +
 388                         SIRFSOC_GPIO_INT_STATUS(i));
 389                 writel(spmx->paden_regs[i], spmx->gpio_virtbase +
 390                         SIRFSOC_GPIO_PAD_EN(i));
 391         }
 392         writel(spmx->dspen_regs, spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
 393
 394         for (i = 0; i < 3; i++)
 395                 writel(spmx->rsc_regs[i], spmx->rsc_virtbase + 4 * i);
 396
 397         return 0;
 398 }
 399
 400 static const struct dev_pm_ops sirfsoc_pinmux_pm_ops = {
 401         .suspend_noirq = sirfsoc_pinmux_suspend_noirq,
 402         .resume_noirq = sirfsoc_pinmux_resume_noirq,
 403         .freeze_noirq = sirfsoc_pinmux_suspend_noirq,
 404         .restore_noirq = sirfsoc_pinmux_resume_noirq,
 405 };
 406 #endif
 407
 408 static struct platform_driver sirfsoc_pinmux_driver = {
 409         .driver = {
 410                 .name = DRIVER_NAME,
 411                 .owner = THIS_MODULE,
 412                 .of_match_table = pinmux_ids,
 413 #ifdef CONFIG_PM_SLEEP
 414                 .pm = &sirfsoc_pinmux_pm_ops,
 415 #endif
 416         },
 417         .probe = sirfsoc_pinmux_probe,
 418 };
 419
 420 static int __init sirfsoc_pinmux_init(void)
 421 {
 422         return platform_driver_register(&sirfsoc_pinmux_driver);
 423 }
 424 arch_initcall(sirfsoc_pinmux_init);
 425
 426 static inline struct sirfsoc_gpio_chip *to_sirfsoc_gpio(struct gpio_chip *gc)
 427 {
 428         return container_of(gc, struct sirfsoc_gpio_chip, chip.gc);
 429 }
 430
 431 static inline struct sirfsoc_gpio_bank *
 432 sirfsoc_gpio_to_bank(struct sirfsoc_gpio_chip *sgpio, unsigned int offset)
 433 {
 434         return &sgpio->sgpio_bank[offset / SIRFSOC_GPIO_BANK_SIZE];
 435 }
 436
 437 static inline int sirfsoc_gpio_to_bankoff(unsigned int offset)
 438 {
 439         return offset % SIRFSOC_GPIO_BANK_SIZE;
 440 }
 441
 442 static void sirfsoc_gpio_irq_ack(struct irq_data *d)
 443 {
 444         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 445         struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
 446         struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
 447         int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
 448         u32 val, offset;
 449         unsigned long flags;
 450
 451         offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
 452
 453         spin_lock_irqsave(&sgpio_lock, flags);
 454
 455         val = readl(sgpio->chip.regs + offset);
 456
 457         writel(val, sgpio->chip.regs + offset);
 458
 459         spin_unlock_irqrestore(&sgpio_lock, flags);
 460 }
 461
 462 static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio,
 463                                     struct sirfsoc_gpio_bank *bank,
 464                                     int idx)
 465 {
 466         u32 val, offset;
 467         unsigned long flags;
 468
 469         offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
 470
 471         spin_lock_irqsave(&sgpio_lock, flags);
 472
 473         val = readl(sgpio->chip.regs + offset);
 474         val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
 475         val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
 476         writel(val, sgpio->chip.regs + offset);
 477
 478         spin_unlock_irqrestore(&sgpio_lock, flags);
 479 }
 480
 481 static void sirfsoc_gpio_irq_mask(struct irq_data *d)
 482 {
 483         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 484         struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
 485         struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
 486
 487         __sirfsoc_gpio_irq_mask(sgpio, bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
 488 }
 489
 490 static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
 491 {
 492         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 493         struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
 494         struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
 495         int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
 496         u32 val, offset;
 497         unsigned long flags;
 498
 499         offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
 500
 501         spin_lock_irqsave(&sgpio_lock, flags);
 502
 503         val = readl(sgpio->chip.regs + offset);
 504         val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
 505         val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
 506         writel(val, sgpio->chip.regs + offset);
 507
 508         spin_unlock_irqrestore(&sgpio_lock, flags);
 509 }
 510
 511 static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
 512 {
 513         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 514         struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
 515         struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
 516         int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
 517         u32 val, offset;
 518         unsigned long flags;
 519
 520         offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
 521
 522         spin_lock_irqsave(&sgpio_lock, flags);
 523
 524         val = readl(sgpio->chip.regs + offset);
 525         val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK);
 526
 527         switch (type) {
 528         case IRQ_TYPE_NONE:
 529                 break;
 530         case IRQ_TYPE_EDGE_RISING:
 531                 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
 532                 val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
 533                 break;
 534         case IRQ_TYPE_EDGE_FALLING:
 535                 val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
 536                 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
 537                 break;
 538         case IRQ_TYPE_EDGE_BOTH:
 539                 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
 540                          SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
 541                 break;
 542         case IRQ_TYPE_LEVEL_LOW:
 543                 val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
 544                 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
 545                 break;
 546         case IRQ_TYPE_LEVEL_HIGH:
 547                 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
 548                 val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
 549                 break;
 550         }
 551
 552         writel(val, sgpio->chip.regs + offset);
 553
 554         spin_unlock_irqrestore(&sgpio_lock, flags);
 555
 556         return 0;
 557 }
 558
 559 static struct irq_chip sirfsoc_irq_chip = {
 560         .name = "sirf-gpio-irq",
 561         .irq_ack = sirfsoc_gpio_irq_ack,
 562         .irq_mask = sirfsoc_gpio_irq_mask,
 563         .irq_unmask = sirfsoc_gpio_irq_unmask,
 564         .irq_set_type = sirfsoc_gpio_irq_type,
 565 };
 566
 567 static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
 568 {
 569         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 570         struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
 571         struct sirfsoc_gpio_bank *bank;
 572         u32 status, ctrl;
 573         int idx = 0;
 574         struct irq_chip *chip = irq_get_chip(irq);
 575         int i;
 576
 577         for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
 578                 bank = &sgpio->sgpio_bank[i];
 579                 if (bank->parent_irq == irq)
 580                         break;
 581         }
 582         BUG_ON(i == SIRFSOC_GPIO_NO_OF_BANKS);
 583
 584         chained_irq_enter(chip, desc);
 585
 586         status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
 587         if (!status) {
 588                 printk(KERN_WARNING
 589                         "%s: gpio id %d status %#x no interrupt is flaged\n",
 590                         __func__, bank->id, status);
 591                 handle_bad_irq(irq, desc);
 592                 return;
 593         }
 594
 595         while (status) {
 596                 ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
 597
 598                 /*
 599                  * Here we must check whether the corresponding GPIO's interrupt
 600                  * has been enabled, otherwise just skip it
 601                  */
 602                 if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
 603                         pr_debug("%s: gpio id %d idx %d happens\n",
 604                                 __func__, bank->id, idx);
 605                         generic_handle_irq(irq_find_mapping(gc->irqdomain, idx +
 606                                         bank->id * SIRFSOC_GPIO_BANK_SIZE));
 607                 }
 608
 609                 idx++;
 610                 status = status >> 1;
 611         }
 612
 613         chained_irq_exit(chip, desc);
 614 }
 615
 616 static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_chip *sgpio,
 617                                           unsigned ctrl_offset)
 618 {
 619         u32 val;
 620
 621         val = readl(sgpio->chip.regs + ctrl_offset);
 622         val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
 623         writel(val, sgpio->chip.regs + ctrl_offset);
 624 }
 625
 626 static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
 627 {
 628         struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
 629         struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
 630         unsigned long flags;
 631
 632         if (pinctrl_request_gpio(chip->base + offset))
 633                 return -ENODEV;
 634
 635         spin_lock_irqsave(&bank->lock, flags);
 636
 637         /*
 638          * default status:
 639          * set direction as input and mask irq
 640          */
 641         sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
 642         __sirfsoc_gpio_irq_mask(sgpio, bank, offset);
 643
 644         spin_unlock_irqrestore(&bank->lock, flags);
 645
 646         return 0;
 647 }
 648
 649 static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
 650 {
 651         struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
 652         struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
 653         unsigned long flags;
 654
 655         spin_lock_irqsave(&bank->lock, flags);
 656
 657         __sirfsoc_gpio_irq_mask(sgpio, bank, offset);
 658         sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
 659
 660         spin_unlock_irqrestore(&bank->lock, flags);
 661
 662         pinctrl_free_gpio(chip->base + offset);
 663 }
 664
 665 static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
 666 {
 667         struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
 668         struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
 669         int idx = sirfsoc_gpio_to_bankoff(gpio);
 670         unsigned long flags;
 671         unsigned offset;
 672
 673         offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
 674
 675         spin_lock_irqsave(&bank->lock, flags);
 676
 677         sirfsoc_gpio_set_input(sgpio, offset);
 678
 679         spin_unlock_irqrestore(&bank->lock, flags);
 680
 681         return 0;
 682 }
 683
 684 static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_chip *sgpio,
 685                                            struct sirfsoc_gpio_bank *bank,
 686                                            unsigned offset,
 687                                            int value)
 688 {
 689         u32 out_ctrl;
 690         unsigned long flags;
 691
 692         spin_lock_irqsave(&bank->lock, flags);
 693
 694         out_ctrl = readl(sgpio->chip.regs + offset);
 695         if (value)
 696                 out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
 697         else
 698                 out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
 699
 700         out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
 701         out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK;
 702         writel(out_ctrl, sgpio->chip.regs + offset);
 703
 704         spin_unlock_irqrestore(&bank->lock, flags);
 705 }
 706
 707 static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
 708 {
 709         struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
 710         struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
 711         int idx = sirfsoc_gpio_to_bankoff(gpio);
 712         u32 offset;
 713         unsigned long flags;
 714
 715         offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
 716
 717         spin_lock_irqsave(&sgpio_lock, flags);
 718
 719         sirfsoc_gpio_set_output(sgpio, bank, offset, value);
 720
 721         spin_unlock_irqrestore(&sgpio_lock, flags);
 722
 723         return 0;
 724 }
 725
 726 static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
 727 {
 728         struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
 729         struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
 730         u32 val;
 731         unsigned long flags;
 732
 733         spin_lock_irqsave(&bank->lock, flags);
 734
 735         val = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
 736
 737         spin_unlock_irqrestore(&bank->lock, flags);
 738
 739         return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK);
 740 }
 741
 742 static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
 743         int value)
 744 {
 745         struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
 746         struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
 747         u32 ctrl;
 748         unsigned long flags;
 749
 750         spin_lock_irqsave(&bank->lock, flags);
 751
 752         ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
 753         if (value)
 754                 ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
 755         else
 756                 ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
 757         writel(ctrl, sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
 758
 759         spin_unlock_irqrestore(&bank->lock, flags);
 760 }
 761
 762 static void sirfsoc_gpio_set_pullup(struct sirfsoc_gpio_chip *sgpio,
 763                                     const u32 *pullups)
 764 {
 765         int i, n;
 766         const unsigned long *p = (const unsigned long *)pullups;
 767
 768         for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
 769                 for_each_set_bit(n, p + i, BITS_PER_LONG) {
 770                         u32 offset = SIRFSOC_GPIO_CTRL(i, n);
 771                         u32 val = readl(sgpio->chip.regs + offset);
 772                         val |= SIRFSOC_GPIO_CTL_PULL_MASK;
 773                         val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
 774                         writel(val, sgpio->chip.regs + offset);
 775                 }
 776         }
 777 }
 778
 779 static void sirfsoc_gpio_set_pulldown(struct sirfsoc_gpio_chip *sgpio,
 780                                       const u32 *pulldowns)
 781 {
 782         int i, n;
 783         const unsigned long *p = (const unsigned long *)pulldowns;
 784
 785         for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
 786                 for_each_set_bit(n, p + i, BITS_PER_LONG) {
 787                         u32 offset = SIRFSOC_GPIO_CTRL(i, n);
 788                         u32 val = readl(sgpio->chip.regs + offset);
 789                         val |= SIRFSOC_GPIO_CTL_PULL_MASK;
 790                         val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
 791                         writel(val, sgpio->chip.regs + offset);
 792                 }
 793         }
 794 }
 795
 796 static int sirfsoc_gpio_probe(struct device_node *np)
 797 {
 798         int i, err = 0;
 799         static struct sirfsoc_gpio_chip *sgpio;
 800         struct sirfsoc_gpio_bank *bank;
 801         void __iomem *regs;
 802         struct platform_device *pdev;
 803         bool is_marco = false;
 804
 805         u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS];
 806
 807         pdev = of_find_device_by_node(np);
 808         if (!pdev)
 809                 return -ENODEV;
 810
 811         sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL);
 812         if (!sgpio)
 813                 return -ENOMEM;
 814
 815         regs = of_iomap(np, 0);
 816         if (!regs)
 817                 return -ENOMEM;
 818
 819         if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
 820                 is_marco = 1;
 821
 822         sgpio->chip.gc.request = sirfsoc_gpio_request;
 823         sgpio->chip.gc.free = sirfsoc_gpio_free;
 824         sgpio->chip.gc.direction_input = sirfsoc_gpio_direction_input;
 825         sgpio->chip.gc.get = sirfsoc_gpio_get_value;
 826         sgpio->chip.gc.direction_output = sirfsoc_gpio_direction_output;
 827         sgpio->chip.gc.set = sirfsoc_gpio_set_value;
 828         sgpio->chip.gc.base = 0;
 829         sgpio->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS;
 830         sgpio->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
 831         sgpio->chip.gc.of_node = np;
 832         sgpio->chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
 833         sgpio->chip.gc.of_gpio_n_cells = 2;
 834         sgpio->chip.gc.dev = &pdev->dev;
 835         sgpio->chip.regs = regs;
 836         sgpio->is_marco = is_marco;
 837
 838         err = gpiochip_add(&sgpio->chip.gc);
 839         if (err) {
 840                 dev_err(&pdev->dev, "%s: error in probe function with status %d\n",
 841                         np->full_name, err);
 842                 goto out;
 843         }
 844
 845         err =  gpiochip_irqchip_add(&sgpio->chip.gc,
 846                 &sirfsoc_irq_chip,
 847                 0, handle_level_irq,
 848                 IRQ_TYPE_NONE);
 849         if (err) {
 850                 dev_err(&pdev->dev,
 851                         "could not connect irqchip to gpiochip\n");
 852                 goto out;
 853         }
 854
 855         for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
 856                 bank = &sgpio->sgpio_bank[i];
 857                 spin_lock_init(&bank->lock);
 858                 bank->parent_irq = platform_get_irq(pdev, i);
 859                 if (bank->parent_irq < 0) {
 860                         err = bank->parent_irq;
 861                         goto out_banks;
 862                 }
 863
 864                 gpiochip_set_chained_irqchip(&sgpio->chip.gc,
 865                         &sirfsoc_irq_chip,
 866                         bank->parent_irq,
 867                         sirfsoc_gpio_handle_irq);
 868         }
 869
 870         err = gpiochip_add_pin_range(&sgpio->chip.gc, dev_name(&pdev->dev),
 871                 0, 0, SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS);
 872         if (err) {
 873                 dev_err(&pdev->dev,
 874                         "could not add gpiochip pin range\n");
 875                 goto out_no_range;
 876         }
 877
 878         if (!of_property_read_u32_array(np, "sirf,pullups", pullups,
 879                 SIRFSOC_GPIO_NO_OF_BANKS))
 880                 sirfsoc_gpio_set_pullup(sgpio, pullups);
 881
 882         if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns,
 883                 SIRFSOC_GPIO_NO_OF_BANKS))
 884                 sirfsoc_gpio_set_pulldown(sgpio, pulldowns);
 885
 886         return 0;
 887
 888 out_no_range:
 889 out_banks:
 890         if (gpiochip_remove(&sgpio->chip.gc))
 891                 dev_err(&pdev->dev, "could not remove gpio chip\n");
 892 out:
 893         iounmap(regs);
 894         return err;
 895 }
 896
 897 static int __init sirfsoc_gpio_init(void)
 898 {
 899
 900         struct device_node *np;
 901
 902         np = of_find_matching_node(NULL, pinmux_ids);
 903
 904         if (!np)
 905                 return -ENODEV;
 906
 907         return sirfsoc_gpio_probe(np);
 908 }
 909 subsys_initcall(sirfsoc_gpio_init);
 910
 911 MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, "
 912         "Yuping Luo <yuping.luo@csr.com>, "
 913         "Barry Song <baohua.song@csr.com>");
 914 MODULE_DESCRIPTION("SIRFSOC pin control driver");
 915 MODULE_LICENSE("GPL");