2 * pinmux driver for CSR SiRFprimaII
4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
7 * Licensed under GPLv2 or later.
10 #include <linux/init.h>
11 #include <linux/module.h>
12 #include <linux/irq.h>
13 #include <linux/platform_device.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/pinctrl/pinctrl.h>
18 #include <linux/pinctrl/pinmux.h>
19 #include <linux/pinctrl/consumer.h>
20 #include <linux/pinctrl/machine.h>
22 #include <linux/of_address.h>
23 #include <linux/of_device.h>
24 #include <linux/of_platform.h>
25 #include <linux/bitops.h>
26 #include <linux/gpio.h>
27 #include <linux/of_gpio.h>
29 #include "pinctrl-sirf.h"
31 #define DRIVER_NAME "pinmux-sirf"
33 struct sirfsoc_gpio_bank
{
39 struct sirfsoc_gpio_chip
{
40 struct of_mm_gpio_chip chip
;
41 struct sirfsoc_gpio_bank sgpio_bank
[SIRFSOC_GPIO_NO_OF_BANKS
];
44 static DEFINE_SPINLOCK(sgpio_lock
);
46 static struct sirfsoc_pin_group
*sirfsoc_pin_groups
;
47 static int sirfsoc_pingrp_cnt
;
49 static int sirfsoc_get_groups_count(struct pinctrl_dev
*pctldev
)
51 return sirfsoc_pingrp_cnt
;
54 static const char *sirfsoc_get_group_name(struct pinctrl_dev
*pctldev
,
57 return sirfsoc_pin_groups
[selector
].name
;
60 static int sirfsoc_get_group_pins(struct pinctrl_dev
*pctldev
,
62 const unsigned **pins
,
65 *pins
= sirfsoc_pin_groups
[selector
].pins
;
66 *num_pins
= sirfsoc_pin_groups
[selector
].num_pins
;
70 static void sirfsoc_pin_dbg_show(struct pinctrl_dev
*pctldev
,
71 struct seq_file
*s
, unsigned offset
)
73 seq_printf(s
, " " DRIVER_NAME
);
76 static int sirfsoc_dt_node_to_map(struct pinctrl_dev
*pctldev
,
77 struct device_node
*np_config
,
78 struct pinctrl_map
**map
, unsigned *num_maps
)
80 struct sirfsoc_pmx
*spmx
= pinctrl_dev_get_drvdata(pctldev
);
81 struct device_node
*np
;
82 struct property
*prop
;
83 const char *function
, *group
;
84 int ret
, index
= 0, count
= 0;
86 /* calculate number of maps required */
87 for_each_child_of_node(np_config
, np
) {
88 ret
= of_property_read_string(np
, "sirf,function", &function
);
92 ret
= of_property_count_strings(np
, "sirf,pins");
100 dev_err(spmx
->dev
, "No child nodes passed via DT\n");
104 *map
= kzalloc(sizeof(**map
) * count
, GFP_KERNEL
);
108 for_each_child_of_node(np_config
, np
) {
109 of_property_read_string(np
, "sirf,function", &function
);
110 of_property_for_each_string(np
, "sirf,pins", prop
, group
) {
111 (*map
)[index
].type
= PIN_MAP_TYPE_MUX_GROUP
;
112 (*map
)[index
].data
.mux
.group
= group
;
113 (*map
)[index
].data
.mux
.function
= function
;
123 static void sirfsoc_dt_free_map(struct pinctrl_dev
*pctldev
,
124 struct pinctrl_map
*map
, unsigned num_maps
)
129 static struct pinctrl_ops sirfsoc_pctrl_ops
= {
130 .get_groups_count
= sirfsoc_get_groups_count
,
131 .get_group_name
= sirfsoc_get_group_name
,
132 .get_group_pins
= sirfsoc_get_group_pins
,
133 .pin_dbg_show
= sirfsoc_pin_dbg_show
,
134 .dt_node_to_map
= sirfsoc_dt_node_to_map
,
135 .dt_free_map
= sirfsoc_dt_free_map
,
138 static struct sirfsoc_pmx_func
*sirfsoc_pmx_functions
;
139 static int sirfsoc_pmxfunc_cnt
;
141 static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx
*spmx
,
142 unsigned selector
, bool enable
)
145 const struct sirfsoc_padmux
*mux
=
146 sirfsoc_pmx_functions
[selector
].padmux
;
147 const struct sirfsoc_muxmask
*mask
= mux
->muxmask
;
149 for (i
= 0; i
< mux
->muxmask_counts
; i
++) {
151 muxval
= readl(spmx
->gpio_virtbase
+
152 SIRFSOC_GPIO_PAD_EN(mask
[i
].group
));
154 muxval
= muxval
& ~mask
[i
].mask
;
156 muxval
= muxval
| mask
[i
].mask
;
157 writel(muxval
, spmx
->gpio_virtbase
+
158 SIRFSOC_GPIO_PAD_EN(mask
[i
].group
));
161 if (mux
->funcmask
&& enable
) {
165 readl(spmx
->rsc_virtbase
+ mux
->ctrlreg
);
167 (func_en_val
& ~mux
->funcmask
) | (mux
->funcval
);
168 writel(func_en_val
, spmx
->rsc_virtbase
+ mux
->ctrlreg
);
172 static int sirfsoc_pinmux_set_mux(struct pinctrl_dev
*pmxdev
,
176 struct sirfsoc_pmx
*spmx
;
178 spmx
= pinctrl_dev_get_drvdata(pmxdev
);
179 sirfsoc_pinmux_endisable(spmx
, selector
, true);
184 static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev
*pmxdev
)
186 return sirfsoc_pmxfunc_cnt
;
189 static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev
*pctldev
,
192 return sirfsoc_pmx_functions
[selector
].name
;
195 static int sirfsoc_pinmux_get_groups(struct pinctrl_dev
*pctldev
,
197 const char * const **groups
,
198 unsigned * const num_groups
)
200 *groups
= sirfsoc_pmx_functions
[selector
].groups
;
201 *num_groups
= sirfsoc_pmx_functions
[selector
].num_groups
;
205 static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev
*pmxdev
,
206 struct pinctrl_gpio_range
*range
, unsigned offset
)
208 struct sirfsoc_pmx
*spmx
;
210 int group
= range
->id
;
214 spmx
= pinctrl_dev_get_drvdata(pmxdev
);
216 muxval
= readl(spmx
->gpio_virtbase
+
217 SIRFSOC_GPIO_PAD_EN(group
));
218 muxval
= muxval
| (1 << (offset
- range
->pin_base
));
219 writel(muxval
, spmx
->gpio_virtbase
+
220 SIRFSOC_GPIO_PAD_EN(group
));
225 static struct pinmux_ops sirfsoc_pinmux_ops
= {
226 .set_mux
= sirfsoc_pinmux_set_mux
,
227 .get_functions_count
= sirfsoc_pinmux_get_funcs_count
,
228 .get_function_name
= sirfsoc_pinmux_get_func_name
,
229 .get_function_groups
= sirfsoc_pinmux_get_groups
,
230 .gpio_request_enable
= sirfsoc_pinmux_request_gpio
,
233 static struct pinctrl_desc sirfsoc_pinmux_desc
= {
235 .pctlops
= &sirfsoc_pctrl_ops
,
236 .pmxops
= &sirfsoc_pinmux_ops
,
237 .owner
= THIS_MODULE
,
240 static void __iomem
*sirfsoc_rsc_of_iomap(void)
242 const struct of_device_id rsc_ids
[] = {
243 { .compatible
= "sirf,prima2-rsc" },
246 struct device_node
*np
;
248 np
= of_find_matching_node(NULL
, rsc_ids
);
250 panic("unable to find compatible rsc node in dtb\n");
252 return of_iomap(np
, 0);
255 static int sirfsoc_gpio_of_xlate(struct gpio_chip
*gc
,
256 const struct of_phandle_args
*gpiospec
,
259 if (gpiospec
->args
[0] > SIRFSOC_GPIO_NO_OF_BANKS
* SIRFSOC_GPIO_BANK_SIZE
)
263 *flags
= gpiospec
->args
[1];
265 return gpiospec
->args
[0];
268 static const struct of_device_id pinmux_ids
[] = {
269 { .compatible
= "sirf,prima2-pinctrl", .data
= &prima2_pinctrl_data
, },
270 { .compatible
= "sirf,atlas6-pinctrl", .data
= &atlas6_pinctrl_data
, },
274 static int sirfsoc_pinmux_probe(struct platform_device
*pdev
)
277 struct sirfsoc_pmx
*spmx
;
278 struct device_node
*np
= pdev
->dev
.of_node
;
279 const struct sirfsoc_pinctrl_data
*pdata
;
281 /* Create state holders etc for this driver */
282 spmx
= devm_kzalloc(&pdev
->dev
, sizeof(*spmx
), GFP_KERNEL
);
286 spmx
->dev
= &pdev
->dev
;
288 platform_set_drvdata(pdev
, spmx
);
290 spmx
->gpio_virtbase
= of_iomap(np
, 0);
291 if (!spmx
->gpio_virtbase
) {
292 dev_err(&pdev
->dev
, "can't map gpio registers\n");
296 spmx
->rsc_virtbase
= sirfsoc_rsc_of_iomap();
297 if (!spmx
->rsc_virtbase
) {
299 dev_err(&pdev
->dev
, "can't map rsc registers\n");
300 goto out_no_rsc_remap
;
303 pdata
= of_match_node(pinmux_ids
, np
)->data
;
304 sirfsoc_pin_groups
= pdata
->grps
;
305 sirfsoc_pingrp_cnt
= pdata
->grps_cnt
;
306 sirfsoc_pmx_functions
= pdata
->funcs
;
307 sirfsoc_pmxfunc_cnt
= pdata
->funcs_cnt
;
308 sirfsoc_pinmux_desc
.pins
= pdata
->pads
;
309 sirfsoc_pinmux_desc
.npins
= pdata
->pads_cnt
;
312 /* Now register the pin controller and all pins it handles */
313 spmx
->pmx
= pinctrl_register(&sirfsoc_pinmux_desc
, &pdev
->dev
, spmx
);
315 dev_err(&pdev
->dev
, "could not register SIRFSOC pinmux driver\n");
320 dev_info(&pdev
->dev
, "initialized SIRFSOC pinmux driver\n");
325 iounmap(spmx
->rsc_virtbase
);
327 iounmap(spmx
->gpio_virtbase
);
331 #ifdef CONFIG_PM_SLEEP
332 static int sirfsoc_pinmux_suspend_noirq(struct device
*dev
)
335 struct sirfsoc_pmx
*spmx
= dev_get_drvdata(dev
);
337 for (i
= 0; i
< SIRFSOC_GPIO_NO_OF_BANKS
; i
++) {
338 for (j
= 0; j
< SIRFSOC_GPIO_BANK_SIZE
; j
++) {
339 spmx
->gpio_regs
[i
][j
] = readl(spmx
->gpio_virtbase
+
340 SIRFSOC_GPIO_CTRL(i
, j
));
342 spmx
->ints_regs
[i
] = readl(spmx
->gpio_virtbase
+
343 SIRFSOC_GPIO_INT_STATUS(i
));
344 spmx
->paden_regs
[i
] = readl(spmx
->gpio_virtbase
+
345 SIRFSOC_GPIO_PAD_EN(i
));
347 spmx
->dspen_regs
= readl(spmx
->gpio_virtbase
+ SIRFSOC_GPIO_DSP_EN0
);
349 for (i
= 0; i
< 3; i
++)
350 spmx
->rsc_regs
[i
] = readl(spmx
->rsc_virtbase
+ 4 * i
);
355 static int sirfsoc_pinmux_resume_noirq(struct device
*dev
)
358 struct sirfsoc_pmx
*spmx
= dev_get_drvdata(dev
);
360 for (i
= 0; i
< SIRFSOC_GPIO_NO_OF_BANKS
; i
++) {
361 for (j
= 0; j
< SIRFSOC_GPIO_BANK_SIZE
; j
++) {
362 writel(spmx
->gpio_regs
[i
][j
], spmx
->gpio_virtbase
+
363 SIRFSOC_GPIO_CTRL(i
, j
));
365 writel(spmx
->ints_regs
[i
], spmx
->gpio_virtbase
+
366 SIRFSOC_GPIO_INT_STATUS(i
));
367 writel(spmx
->paden_regs
[i
], spmx
->gpio_virtbase
+
368 SIRFSOC_GPIO_PAD_EN(i
));
370 writel(spmx
->dspen_regs
, spmx
->gpio_virtbase
+ SIRFSOC_GPIO_DSP_EN0
);
372 for (i
= 0; i
< 3; i
++)
373 writel(spmx
->rsc_regs
[i
], spmx
->rsc_virtbase
+ 4 * i
);
378 static const struct dev_pm_ops sirfsoc_pinmux_pm_ops
= {
379 .suspend_noirq
= sirfsoc_pinmux_suspend_noirq
,
380 .resume_noirq
= sirfsoc_pinmux_resume_noirq
,
381 .freeze_noirq
= sirfsoc_pinmux_suspend_noirq
,
382 .restore_noirq
= sirfsoc_pinmux_resume_noirq
,
386 static struct platform_driver sirfsoc_pinmux_driver
= {
389 .of_match_table
= pinmux_ids
,
390 #ifdef CONFIG_PM_SLEEP
391 .pm
= &sirfsoc_pinmux_pm_ops
,
394 .probe
= sirfsoc_pinmux_probe
,
397 static int __init
sirfsoc_pinmux_init(void)
399 return platform_driver_register(&sirfsoc_pinmux_driver
);
401 arch_initcall(sirfsoc_pinmux_init
);
403 static inline struct sirfsoc_gpio_chip
*to_sirfsoc_gpio(struct gpio_chip
*gc
)
405 return container_of(gc
, struct sirfsoc_gpio_chip
, chip
.gc
);
408 static inline struct sirfsoc_gpio_bank
*
409 sirfsoc_gpio_to_bank(struct sirfsoc_gpio_chip
*sgpio
, unsigned int offset
)
411 return &sgpio
->sgpio_bank
[offset
/ SIRFSOC_GPIO_BANK_SIZE
];
414 static inline int sirfsoc_gpio_to_bankoff(unsigned int offset
)
416 return offset
% SIRFSOC_GPIO_BANK_SIZE
;
419 static void sirfsoc_gpio_irq_ack(struct irq_data
*d
)
421 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
422 struct sirfsoc_gpio_chip
*sgpio
= to_sirfsoc_gpio(gc
);
423 struct sirfsoc_gpio_bank
*bank
= sirfsoc_gpio_to_bank(sgpio
, d
->hwirq
);
424 int idx
= sirfsoc_gpio_to_bankoff(d
->hwirq
);
428 offset
= SIRFSOC_GPIO_CTRL(bank
->id
, idx
);
430 spin_lock_irqsave(&sgpio_lock
, flags
);
432 val
= readl(sgpio
->chip
.regs
+ offset
);
434 writel(val
, sgpio
->chip
.regs
+ offset
);
436 spin_unlock_irqrestore(&sgpio_lock
, flags
);
439 static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip
*sgpio
,
440 struct sirfsoc_gpio_bank
*bank
,
446 offset
= SIRFSOC_GPIO_CTRL(bank
->id
, idx
);
448 spin_lock_irqsave(&sgpio_lock
, flags
);
450 val
= readl(sgpio
->chip
.regs
+ offset
);
451 val
&= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK
;
452 val
&= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK
;
453 writel(val
, sgpio
->chip
.regs
+ offset
);
455 spin_unlock_irqrestore(&sgpio_lock
, flags
);
458 static void sirfsoc_gpio_irq_mask(struct irq_data
*d
)
460 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
461 struct sirfsoc_gpio_chip
*sgpio
= to_sirfsoc_gpio(gc
);
462 struct sirfsoc_gpio_bank
*bank
= sirfsoc_gpio_to_bank(sgpio
, d
->hwirq
);
464 __sirfsoc_gpio_irq_mask(sgpio
, bank
, d
->hwirq
% SIRFSOC_GPIO_BANK_SIZE
);
467 static void sirfsoc_gpio_irq_unmask(struct irq_data
*d
)
469 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
470 struct sirfsoc_gpio_chip
*sgpio
= to_sirfsoc_gpio(gc
);
471 struct sirfsoc_gpio_bank
*bank
= sirfsoc_gpio_to_bank(sgpio
, d
->hwirq
);
472 int idx
= sirfsoc_gpio_to_bankoff(d
->hwirq
);
476 offset
= SIRFSOC_GPIO_CTRL(bank
->id
, idx
);
478 spin_lock_irqsave(&sgpio_lock
, flags
);
480 val
= readl(sgpio
->chip
.regs
+ offset
);
481 val
&= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK
;
482 val
|= SIRFSOC_GPIO_CTL_INTR_EN_MASK
;
483 writel(val
, sgpio
->chip
.regs
+ offset
);
485 spin_unlock_irqrestore(&sgpio_lock
, flags
);
488 static int sirfsoc_gpio_irq_type(struct irq_data
*d
, unsigned type
)
490 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
491 struct sirfsoc_gpio_chip
*sgpio
= to_sirfsoc_gpio(gc
);
492 struct sirfsoc_gpio_bank
*bank
= sirfsoc_gpio_to_bank(sgpio
, d
->hwirq
);
493 int idx
= sirfsoc_gpio_to_bankoff(d
->hwirq
);
497 offset
= SIRFSOC_GPIO_CTRL(bank
->id
, idx
);
499 spin_lock_irqsave(&sgpio_lock
, flags
);
501 val
= readl(sgpio
->chip
.regs
+ offset
);
502 val
&= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK
| SIRFSOC_GPIO_CTL_OUT_EN_MASK
);
507 case IRQ_TYPE_EDGE_RISING
:
508 val
|= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK
|
509 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK
;
510 val
&= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK
;
512 case IRQ_TYPE_EDGE_FALLING
:
513 val
&= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK
;
514 val
|= SIRFSOC_GPIO_CTL_INTR_LOW_MASK
|
515 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK
;
517 case IRQ_TYPE_EDGE_BOTH
:
518 val
|= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK
|
519 SIRFSOC_GPIO_CTL_INTR_LOW_MASK
|
520 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK
;
522 case IRQ_TYPE_LEVEL_LOW
:
523 val
&= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK
|
524 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK
);
525 val
|= SIRFSOC_GPIO_CTL_INTR_LOW_MASK
;
527 case IRQ_TYPE_LEVEL_HIGH
:
528 val
|= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK
;
529 val
&= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK
|
530 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK
);
534 writel(val
, sgpio
->chip
.regs
+ offset
);
536 spin_unlock_irqrestore(&sgpio_lock
, flags
);
541 static struct irq_chip sirfsoc_irq_chip
= {
542 .name
= "sirf-gpio-irq",
543 .irq_ack
= sirfsoc_gpio_irq_ack
,
544 .irq_mask
= sirfsoc_gpio_irq_mask
,
545 .irq_unmask
= sirfsoc_gpio_irq_unmask
,
546 .irq_set_type
= sirfsoc_gpio_irq_type
,
549 static void sirfsoc_gpio_handle_irq(unsigned int irq
, struct irq_desc
*desc
)
551 struct gpio_chip
*gc
= irq_desc_get_handler_data(desc
);
552 struct sirfsoc_gpio_chip
*sgpio
= to_sirfsoc_gpio(gc
);
553 struct sirfsoc_gpio_bank
*bank
;
556 struct irq_chip
*chip
= irq_get_chip(irq
);
559 for (i
= 0; i
< SIRFSOC_GPIO_NO_OF_BANKS
; i
++) {
560 bank
= &sgpio
->sgpio_bank
[i
];
561 if (bank
->parent_irq
== irq
)
564 BUG_ON(i
== SIRFSOC_GPIO_NO_OF_BANKS
);
566 chained_irq_enter(chip
, desc
);
568 status
= readl(sgpio
->chip
.regs
+ SIRFSOC_GPIO_INT_STATUS(bank
->id
));
571 "%s: gpio id %d status %#x no interrupt is flaged\n",
572 __func__
, bank
->id
, status
);
573 handle_bad_irq(irq
, desc
);
578 ctrl
= readl(sgpio
->chip
.regs
+ SIRFSOC_GPIO_CTRL(bank
->id
, idx
));
581 * Here we must check whether the corresponding GPIO's interrupt
582 * has been enabled, otherwise just skip it
584 if ((status
& 0x1) && (ctrl
& SIRFSOC_GPIO_CTL_INTR_EN_MASK
)) {
585 pr_debug("%s: gpio id %d idx %d happens\n",
586 __func__
, bank
->id
, idx
);
587 generic_handle_irq(irq_find_mapping(gc
->irqdomain
, idx
+
588 bank
->id
* SIRFSOC_GPIO_BANK_SIZE
));
592 status
= status
>> 1;
595 chained_irq_exit(chip
, desc
);
598 static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_chip
*sgpio
,
599 unsigned ctrl_offset
)
603 val
= readl(sgpio
->chip
.regs
+ ctrl_offset
);
604 val
&= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK
;
605 writel(val
, sgpio
->chip
.regs
+ ctrl_offset
);
608 static int sirfsoc_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
610 struct sirfsoc_gpio_chip
*sgpio
= to_sirfsoc_gpio(chip
);
611 struct sirfsoc_gpio_bank
*bank
= sirfsoc_gpio_to_bank(sgpio
, offset
);
614 if (pinctrl_request_gpio(chip
->base
+ offset
))
617 spin_lock_irqsave(&bank
->lock
, flags
);
621 * set direction as input and mask irq
623 sirfsoc_gpio_set_input(sgpio
, SIRFSOC_GPIO_CTRL(bank
->id
, offset
));
624 __sirfsoc_gpio_irq_mask(sgpio
, bank
, offset
);
626 spin_unlock_irqrestore(&bank
->lock
, flags
);
631 static void sirfsoc_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
633 struct sirfsoc_gpio_chip
*sgpio
= to_sirfsoc_gpio(chip
);
634 struct sirfsoc_gpio_bank
*bank
= sirfsoc_gpio_to_bank(sgpio
, offset
);
637 spin_lock_irqsave(&bank
->lock
, flags
);
639 __sirfsoc_gpio_irq_mask(sgpio
, bank
, offset
);
640 sirfsoc_gpio_set_input(sgpio
, SIRFSOC_GPIO_CTRL(bank
->id
, offset
));
642 spin_unlock_irqrestore(&bank
->lock
, flags
);
644 pinctrl_free_gpio(chip
->base
+ offset
);
647 static int sirfsoc_gpio_direction_input(struct gpio_chip
*chip
, unsigned gpio
)
649 struct sirfsoc_gpio_chip
*sgpio
= to_sirfsoc_gpio(chip
);
650 struct sirfsoc_gpio_bank
*bank
= sirfsoc_gpio_to_bank(sgpio
, gpio
);
651 int idx
= sirfsoc_gpio_to_bankoff(gpio
);
655 offset
= SIRFSOC_GPIO_CTRL(bank
->id
, idx
);
657 spin_lock_irqsave(&bank
->lock
, flags
);
659 sirfsoc_gpio_set_input(sgpio
, offset
);
661 spin_unlock_irqrestore(&bank
->lock
, flags
);
666 static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_chip
*sgpio
,
667 struct sirfsoc_gpio_bank
*bank
,
674 spin_lock_irqsave(&bank
->lock
, flags
);
676 out_ctrl
= readl(sgpio
->chip
.regs
+ offset
);
678 out_ctrl
|= SIRFSOC_GPIO_CTL_DATAOUT_MASK
;
680 out_ctrl
&= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK
;
682 out_ctrl
&= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK
;
683 out_ctrl
|= SIRFSOC_GPIO_CTL_OUT_EN_MASK
;
684 writel(out_ctrl
, sgpio
->chip
.regs
+ offset
);
686 spin_unlock_irqrestore(&bank
->lock
, flags
);
689 static int sirfsoc_gpio_direction_output(struct gpio_chip
*chip
,
690 unsigned gpio
, int value
)
692 struct sirfsoc_gpio_chip
*sgpio
= to_sirfsoc_gpio(chip
);
693 struct sirfsoc_gpio_bank
*bank
= sirfsoc_gpio_to_bank(sgpio
, gpio
);
694 int idx
= sirfsoc_gpio_to_bankoff(gpio
);
698 offset
= SIRFSOC_GPIO_CTRL(bank
->id
, idx
);
700 spin_lock_irqsave(&sgpio_lock
, flags
);
702 sirfsoc_gpio_set_output(sgpio
, bank
, offset
, value
);
704 spin_unlock_irqrestore(&sgpio_lock
, flags
);
709 static int sirfsoc_gpio_get_value(struct gpio_chip
*chip
, unsigned offset
)
711 struct sirfsoc_gpio_chip
*sgpio
= to_sirfsoc_gpio(chip
);
712 struct sirfsoc_gpio_bank
*bank
= sirfsoc_gpio_to_bank(sgpio
, offset
);
716 spin_lock_irqsave(&bank
->lock
, flags
);
718 val
= readl(sgpio
->chip
.regs
+ SIRFSOC_GPIO_CTRL(bank
->id
, offset
));
720 spin_unlock_irqrestore(&bank
->lock
, flags
);
722 return !!(val
& SIRFSOC_GPIO_CTL_DATAIN_MASK
);
725 static void sirfsoc_gpio_set_value(struct gpio_chip
*chip
, unsigned offset
,
728 struct sirfsoc_gpio_chip
*sgpio
= to_sirfsoc_gpio(chip
);
729 struct sirfsoc_gpio_bank
*bank
= sirfsoc_gpio_to_bank(sgpio
, offset
);
733 spin_lock_irqsave(&bank
->lock
, flags
);
735 ctrl
= readl(sgpio
->chip
.regs
+ SIRFSOC_GPIO_CTRL(bank
->id
, offset
));
737 ctrl
|= SIRFSOC_GPIO_CTL_DATAOUT_MASK
;
739 ctrl
&= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK
;
740 writel(ctrl
, sgpio
->chip
.regs
+ SIRFSOC_GPIO_CTRL(bank
->id
, offset
));
742 spin_unlock_irqrestore(&bank
->lock
, flags
);
745 static void sirfsoc_gpio_set_pullup(struct sirfsoc_gpio_chip
*sgpio
,
749 const unsigned long *p
= (const unsigned long *)pullups
;
751 for (i
= 0; i
< SIRFSOC_GPIO_NO_OF_BANKS
; i
++) {
752 for_each_set_bit(n
, p
+ i
, BITS_PER_LONG
) {
753 u32 offset
= SIRFSOC_GPIO_CTRL(i
, n
);
754 u32 val
= readl(sgpio
->chip
.regs
+ offset
);
755 val
|= SIRFSOC_GPIO_CTL_PULL_MASK
;
756 val
|= SIRFSOC_GPIO_CTL_PULL_HIGH
;
757 writel(val
, sgpio
->chip
.regs
+ offset
);
762 static void sirfsoc_gpio_set_pulldown(struct sirfsoc_gpio_chip
*sgpio
,
763 const u32
*pulldowns
)
766 const unsigned long *p
= (const unsigned long *)pulldowns
;
768 for (i
= 0; i
< SIRFSOC_GPIO_NO_OF_BANKS
; i
++) {
769 for_each_set_bit(n
, p
+ i
, BITS_PER_LONG
) {
770 u32 offset
= SIRFSOC_GPIO_CTRL(i
, n
);
771 u32 val
= readl(sgpio
->chip
.regs
+ offset
);
772 val
|= SIRFSOC_GPIO_CTL_PULL_MASK
;
773 val
&= ~SIRFSOC_GPIO_CTL_PULL_HIGH
;
774 writel(val
, sgpio
->chip
.regs
+ offset
);
779 static int sirfsoc_gpio_probe(struct device_node
*np
)
782 static struct sirfsoc_gpio_chip
*sgpio
;
783 struct sirfsoc_gpio_bank
*bank
;
785 struct platform_device
*pdev
;
787 u32 pullups
[SIRFSOC_GPIO_NO_OF_BANKS
], pulldowns
[SIRFSOC_GPIO_NO_OF_BANKS
];
789 pdev
= of_find_device_by_node(np
);
793 sgpio
= devm_kzalloc(&pdev
->dev
, sizeof(*sgpio
), GFP_KERNEL
);
797 regs
= of_iomap(np
, 0);
801 sgpio
->chip
.gc
.request
= sirfsoc_gpio_request
;
802 sgpio
->chip
.gc
.free
= sirfsoc_gpio_free
;
803 sgpio
->chip
.gc
.direction_input
= sirfsoc_gpio_direction_input
;
804 sgpio
->chip
.gc
.get
= sirfsoc_gpio_get_value
;
805 sgpio
->chip
.gc
.direction_output
= sirfsoc_gpio_direction_output
;
806 sgpio
->chip
.gc
.set
= sirfsoc_gpio_set_value
;
807 sgpio
->chip
.gc
.base
= 0;
808 sgpio
->chip
.gc
.ngpio
= SIRFSOC_GPIO_BANK_SIZE
* SIRFSOC_GPIO_NO_OF_BANKS
;
809 sgpio
->chip
.gc
.label
= kstrdup(np
->full_name
, GFP_KERNEL
);
810 sgpio
->chip
.gc
.of_node
= np
;
811 sgpio
->chip
.gc
.of_xlate
= sirfsoc_gpio_of_xlate
;
812 sgpio
->chip
.gc
.of_gpio_n_cells
= 2;
813 sgpio
->chip
.gc
.dev
= &pdev
->dev
;
814 sgpio
->chip
.regs
= regs
;
816 err
= gpiochip_add(&sgpio
->chip
.gc
);
818 dev_err(&pdev
->dev
, "%s: error in probe function with status %d\n",
823 err
= gpiochip_irqchip_add(&sgpio
->chip
.gc
,
829 "could not connect irqchip to gpiochip\n");
833 for (i
= 0; i
< SIRFSOC_GPIO_NO_OF_BANKS
; i
++) {
834 bank
= &sgpio
->sgpio_bank
[i
];
835 spin_lock_init(&bank
->lock
);
836 bank
->parent_irq
= platform_get_irq(pdev
, i
);
837 if (bank
->parent_irq
< 0) {
838 err
= bank
->parent_irq
;
842 gpiochip_set_chained_irqchip(&sgpio
->chip
.gc
,
845 sirfsoc_gpio_handle_irq
);
848 err
= gpiochip_add_pin_range(&sgpio
->chip
.gc
, dev_name(&pdev
->dev
),
849 0, 0, SIRFSOC_GPIO_BANK_SIZE
* SIRFSOC_GPIO_NO_OF_BANKS
);
852 "could not add gpiochip pin range\n");
856 if (!of_property_read_u32_array(np
, "sirf,pullups", pullups
,
857 SIRFSOC_GPIO_NO_OF_BANKS
))
858 sirfsoc_gpio_set_pullup(sgpio
, pullups
);
860 if (!of_property_read_u32_array(np
, "sirf,pulldowns", pulldowns
,
861 SIRFSOC_GPIO_NO_OF_BANKS
))
862 sirfsoc_gpio_set_pulldown(sgpio
, pulldowns
);
868 gpiochip_remove(&sgpio
->chip
.gc
);
874 static int __init
sirfsoc_gpio_init(void)
877 struct device_node
*np
;
879 np
= of_find_matching_node(NULL
, pinmux_ids
);
884 return sirfsoc_gpio_probe(np
);
886 subsys_initcall(sirfsoc_gpio_init
);
888 MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>");
889 MODULE_AUTHOR("Yuping Luo <yuping.luo@csr.com>");
890 MODULE_AUTHOR("Barry Song <baohua.song@csr.com>");
891 MODULE_DESCRIPTION("SIRFSOC pin control driver");
892 MODULE_LICENSE("GPL");