2 * Driver header file for the ST Microelectronics SPEAr pinmux
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
12 #ifndef __PINMUX_SPEAR_H__
13 #define __PINMUX_SPEAR_H__
15 #include <linux/pinctrl/pinctrl.h>
16 #include <linux/types.h>
18 struct platform_device
;
22 * struct spear_pmx_mode - SPEAr pmx mode
23 * @name: name of pmx mode
25 * @reg: register for configuring this mode
26 * @mask: mask of this mode in reg
27 * @val: val to be configured at reg after doing (val & mask)
29 struct spear_pmx_mode
{
30 const char *const name
;
38 * struct spear_muxreg - SPEAr mux reg configuration
39 * @reg: register offset
41 * @val: val to be written on mask bits
50 * struct spear_modemux - SPEAr mode mux configuration
51 * @modes: mode ids supported by this group of muxregs
52 * @nmuxregs: number of muxreg configurations to be done for modes
53 * @muxregs: array of muxreg configurations to be done for modes
55 struct spear_modemux
{
58 struct spear_muxreg
*muxregs
;
62 * struct spear_pingroup - SPEAr pin group configurations
63 * @name: name of pin group
64 * @pins: array containing pin numbers
65 * @npins: size of pins array
66 * @modemuxs: array of modemux configurations for this pin group
67 * @nmodemuxs: size of array modemuxs
69 * A representation of a group of pins in the SPEAr pin controller. Each group
70 * allows some parameter or parameters to be configured.
72 struct spear_pingroup
{
76 struct spear_modemux
*modemuxs
;
81 * struct spear_function - SPEAr pinctrl mux function
82 * @name: The name of the function, exported to pinctrl core.
83 * @groups: An array of pin groups that may select this function.
84 * @ngroups: The number of entries in @groups.
86 struct spear_function
{
88 const char *const *groups
;
93 * struct spear_pinctrl_machdata - SPEAr pin controller machine driver
95 * @pins: An array describing all pins the pin controller affects.
96 * All pins which are also GPIOs must be listed first within the *array,
97 * and be numbered identically to the GPIO controller's *numbering.
98 * @npins: The numbmer of entries in @pins.
99 * @functions: An array describing all mux functions the SoC supports.
100 * @nfunctions: The numbmer of entries in @functions.
101 * @groups: An array describing all pin groups the pin SoC supports.
102 * @ngroups: The numbmer of entries in @groups.
104 * @modes_supported: Does SoC support modes
105 * @mode: mode configured from probe
106 * @pmx_modes: array of modes supported by SoC
107 * @npmx_modes: number of entries in pmx_modes.
109 struct spear_pinctrl_machdata
{
110 const struct pinctrl_pin_desc
*pins
;
112 struct spear_function
**functions
;
114 struct spear_pingroup
**groups
;
117 bool modes_supported
;
119 struct spear_pmx_mode
**pmx_modes
;
124 * struct spear_pmx - SPEAr pinctrl mux
125 * @dev: pointer to struct dev of platform_device registered
126 * @pctl: pointer to struct pinctrl_dev
127 * @machdata: pointer to SoC or machine specific structure
128 * @vbase: virtual base address of pinmux controller
132 struct pinctrl_dev
*pctl
;
133 struct spear_pinctrl_machdata
*machdata
;
137 /* exported routines */
138 void __devinit
pmx_init_addr(struct spear_pinctrl_machdata
*machdata
, u16 reg
);
139 int __devinit
spear_pinctrl_probe(struct platform_device
*pdev
,
140 struct spear_pinctrl_machdata
*machdata
);
141 int __devexit
spear_pinctrl_remove(struct platform_device
*pdev
);
143 #define SPEAR_PIN_0_TO_101 \
144 PINCTRL_PIN(0, "PLGPIO0"), \
145 PINCTRL_PIN(1, "PLGPIO1"), \
146 PINCTRL_PIN(2, "PLGPIO2"), \
147 PINCTRL_PIN(3, "PLGPIO3"), \
148 PINCTRL_PIN(4, "PLGPIO4"), \
149 PINCTRL_PIN(5, "PLGPIO5"), \
150 PINCTRL_PIN(6, "PLGPIO6"), \
151 PINCTRL_PIN(7, "PLGPIO7"), \
152 PINCTRL_PIN(8, "PLGPIO8"), \
153 PINCTRL_PIN(9, "PLGPIO9"), \
154 PINCTRL_PIN(10, "PLGPIO10"), \
155 PINCTRL_PIN(11, "PLGPIO11"), \
156 PINCTRL_PIN(12, "PLGPIO12"), \
157 PINCTRL_PIN(13, "PLGPIO13"), \
158 PINCTRL_PIN(14, "PLGPIO14"), \
159 PINCTRL_PIN(15, "PLGPIO15"), \
160 PINCTRL_PIN(16, "PLGPIO16"), \
161 PINCTRL_PIN(17, "PLGPIO17"), \
162 PINCTRL_PIN(18, "PLGPIO18"), \
163 PINCTRL_PIN(19, "PLGPIO19"), \
164 PINCTRL_PIN(20, "PLGPIO20"), \
165 PINCTRL_PIN(21, "PLGPIO21"), \
166 PINCTRL_PIN(22, "PLGPIO22"), \
167 PINCTRL_PIN(23, "PLGPIO23"), \
168 PINCTRL_PIN(24, "PLGPIO24"), \
169 PINCTRL_PIN(25, "PLGPIO25"), \
170 PINCTRL_PIN(26, "PLGPIO26"), \
171 PINCTRL_PIN(27, "PLGPIO27"), \
172 PINCTRL_PIN(28, "PLGPIO28"), \
173 PINCTRL_PIN(29, "PLGPIO29"), \
174 PINCTRL_PIN(30, "PLGPIO30"), \
175 PINCTRL_PIN(31, "PLGPIO31"), \
176 PINCTRL_PIN(32, "PLGPIO32"), \
177 PINCTRL_PIN(33, "PLGPIO33"), \
178 PINCTRL_PIN(34, "PLGPIO34"), \
179 PINCTRL_PIN(35, "PLGPIO35"), \
180 PINCTRL_PIN(36, "PLGPIO36"), \
181 PINCTRL_PIN(37, "PLGPIO37"), \
182 PINCTRL_PIN(38, "PLGPIO38"), \
183 PINCTRL_PIN(39, "PLGPIO39"), \
184 PINCTRL_PIN(40, "PLGPIO40"), \
185 PINCTRL_PIN(41, "PLGPIO41"), \
186 PINCTRL_PIN(42, "PLGPIO42"), \
187 PINCTRL_PIN(43, "PLGPIO43"), \
188 PINCTRL_PIN(44, "PLGPIO44"), \
189 PINCTRL_PIN(45, "PLGPIO45"), \
190 PINCTRL_PIN(46, "PLGPIO46"), \
191 PINCTRL_PIN(47, "PLGPIO47"), \
192 PINCTRL_PIN(48, "PLGPIO48"), \
193 PINCTRL_PIN(49, "PLGPIO49"), \
194 PINCTRL_PIN(50, "PLGPIO50"), \
195 PINCTRL_PIN(51, "PLGPIO51"), \
196 PINCTRL_PIN(52, "PLGPIO52"), \
197 PINCTRL_PIN(53, "PLGPIO53"), \
198 PINCTRL_PIN(54, "PLGPIO54"), \
199 PINCTRL_PIN(55, "PLGPIO55"), \
200 PINCTRL_PIN(56, "PLGPIO56"), \
201 PINCTRL_PIN(57, "PLGPIO57"), \
202 PINCTRL_PIN(58, "PLGPIO58"), \
203 PINCTRL_PIN(59, "PLGPIO59"), \
204 PINCTRL_PIN(60, "PLGPIO60"), \
205 PINCTRL_PIN(61, "PLGPIO61"), \
206 PINCTRL_PIN(62, "PLGPIO62"), \
207 PINCTRL_PIN(63, "PLGPIO63"), \
208 PINCTRL_PIN(64, "PLGPIO64"), \
209 PINCTRL_PIN(65, "PLGPIO65"), \
210 PINCTRL_PIN(66, "PLGPIO66"), \
211 PINCTRL_PIN(67, "PLGPIO67"), \
212 PINCTRL_PIN(68, "PLGPIO68"), \
213 PINCTRL_PIN(69, "PLGPIO69"), \
214 PINCTRL_PIN(70, "PLGPIO70"), \
215 PINCTRL_PIN(71, "PLGPIO71"), \
216 PINCTRL_PIN(72, "PLGPIO72"), \
217 PINCTRL_PIN(73, "PLGPIO73"), \
218 PINCTRL_PIN(74, "PLGPIO74"), \
219 PINCTRL_PIN(75, "PLGPIO75"), \
220 PINCTRL_PIN(76, "PLGPIO76"), \
221 PINCTRL_PIN(77, "PLGPIO77"), \
222 PINCTRL_PIN(78, "PLGPIO78"), \
223 PINCTRL_PIN(79, "PLGPIO79"), \
224 PINCTRL_PIN(80, "PLGPIO80"), \
225 PINCTRL_PIN(81, "PLGPIO81"), \
226 PINCTRL_PIN(82, "PLGPIO82"), \
227 PINCTRL_PIN(83, "PLGPIO83"), \
228 PINCTRL_PIN(84, "PLGPIO84"), \
229 PINCTRL_PIN(85, "PLGPIO85"), \
230 PINCTRL_PIN(86, "PLGPIO86"), \
231 PINCTRL_PIN(87, "PLGPIO87"), \
232 PINCTRL_PIN(88, "PLGPIO88"), \
233 PINCTRL_PIN(89, "PLGPIO89"), \
234 PINCTRL_PIN(90, "PLGPIO90"), \
235 PINCTRL_PIN(91, "PLGPIO91"), \
236 PINCTRL_PIN(92, "PLGPIO92"), \
237 PINCTRL_PIN(93, "PLGPIO93"), \
238 PINCTRL_PIN(94, "PLGPIO94"), \
239 PINCTRL_PIN(95, "PLGPIO95"), \
240 PINCTRL_PIN(96, "PLGPIO96"), \
241 PINCTRL_PIN(97, "PLGPIO97"), \
242 PINCTRL_PIN(98, "PLGPIO98"), \
243 PINCTRL_PIN(99, "PLGPIO99"), \
244 PINCTRL_PIN(100, "PLGPIO100"), \
245 PINCTRL_PIN(101, "PLGPIO101")
247 #endif /* __PINMUX_SPEAR_H__ */
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