2 * Allwinner A1X SoCs pinctrl driver.
4 * Copyright (C) 2012 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
14 #include <linux/clk.h>
15 #include <linux/gpio.h>
16 #include <linux/irqdomain.h>
17 #include <linux/irqchip/chained_irq.h>
18 #include <linux/module.h>
20 #include <linux/of_address.h>
21 #include <linux/of_device.h>
22 #include <linux/of_irq.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pinctrl/machine.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinconf-generic.h>
27 #include <linux/pinctrl/pinmux.h>
28 #include <linux/platform_device.h>
29 #include <linux/reset.h>
30 #include <linux/slab.h>
33 #include "pinctrl-sunxi.h"
34 #include "pinctrl-sunxi-pins.h"
36 static struct sunxi_pinctrl_group
*
37 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl
*pctl
, const char *group
)
41 for (i
= 0; i
< pctl
->ngroups
; i
++) {
42 struct sunxi_pinctrl_group
*grp
= pctl
->groups
+ i
;
44 if (!strcmp(grp
->name
, group
))
51 static struct sunxi_pinctrl_function
*
52 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl
*pctl
,
55 struct sunxi_pinctrl_function
*func
= pctl
->functions
;
58 for (i
= 0; i
< pctl
->nfunctions
; i
++) {
62 if (!strcmp(func
[i
].name
, name
))
69 static struct sunxi_desc_function
*
70 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl
*pctl
,
72 const char *func_name
)
76 for (i
= 0; i
< pctl
->desc
->npins
; i
++) {
77 const struct sunxi_desc_pin
*pin
= pctl
->desc
->pins
+ i
;
79 if (!strcmp(pin
->pin
.name
, pin_name
)) {
80 struct sunxi_desc_function
*func
= pin
->functions
;
83 if (!strcmp(func
->name
, func_name
))
94 static struct sunxi_desc_function
*
95 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl
*pctl
,
97 const char *func_name
)
101 for (i
= 0; i
< pctl
->desc
->npins
; i
++) {
102 const struct sunxi_desc_pin
*pin
= pctl
->desc
->pins
+ i
;
104 if (pin
->pin
.number
== pin_num
) {
105 struct sunxi_desc_function
*func
= pin
->functions
;
108 if (!strcmp(func
->name
, func_name
))
119 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev
*pctldev
)
121 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
123 return pctl
->ngroups
;
126 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev
*pctldev
,
129 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
131 return pctl
->groups
[group
].name
;
134 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev
*pctldev
,
136 const unsigned **pins
,
139 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
141 *pins
= (unsigned *)&pctl
->groups
[group
].pin
;
147 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev
*pctldev
,
148 struct device_node
*node
,
149 struct pinctrl_map
**map
,
152 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
153 unsigned long *pinconfig
;
154 struct property
*prop
;
155 const char *function
;
157 int ret
, nmaps
, i
= 0;
163 ret
= of_property_read_string(node
, "allwinner,function", &function
);
166 "missing allwinner,function property in node %s\n",
171 nmaps
= of_property_count_strings(node
, "allwinner,pins") * 2;
174 "missing allwinner,pins property in node %s\n",
179 *map
= kmalloc(nmaps
* sizeof(struct pinctrl_map
), GFP_KERNEL
);
183 of_property_for_each_string(node
, "allwinner,pins", prop
, group
) {
184 struct sunxi_pinctrl_group
*grp
=
185 sunxi_pinctrl_find_group_by_name(pctl
, group
);
186 int j
= 0, configlen
= 0;
189 dev_err(pctl
->dev
, "unknown pin %s", group
);
193 if (!sunxi_pinctrl_desc_find_function_by_name(pctl
,
196 dev_err(pctl
->dev
, "unsupported function %s on pin %s",
201 (*map
)[i
].type
= PIN_MAP_TYPE_MUX_GROUP
;
202 (*map
)[i
].data
.mux
.group
= group
;
203 (*map
)[i
].data
.mux
.function
= function
;
207 (*map
)[i
].type
= PIN_MAP_TYPE_CONFIGS_GROUP
;
208 (*map
)[i
].data
.configs
.group_or_pin
= group
;
210 if (of_find_property(node
, "allwinner,drive", NULL
))
212 if (of_find_property(node
, "allwinner,pull", NULL
))
215 pinconfig
= kzalloc(configlen
* sizeof(*pinconfig
), GFP_KERNEL
);
217 if (!of_property_read_u32(node
, "allwinner,drive", &val
)) {
218 u16 strength
= (val
+ 1) * 10;
220 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH
,
224 if (!of_property_read_u32(node
, "allwinner,pull", &val
)) {
225 enum pin_config_param pull
= PIN_CONFIG_END
;
227 pull
= PIN_CONFIG_BIAS_PULL_UP
;
229 pull
= PIN_CONFIG_BIAS_PULL_DOWN
;
230 pinconfig
[j
++] = pinconf_to_config_packed(pull
, 0);
233 (*map
)[i
].data
.configs
.configs
= pinconfig
;
234 (*map
)[i
].data
.configs
.num_configs
= configlen
;
244 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev
*pctldev
,
245 struct pinctrl_map
*map
,
250 for (i
= 0; i
< num_maps
; i
++) {
251 if (map
[i
].type
== PIN_MAP_TYPE_CONFIGS_GROUP
)
252 kfree(map
[i
].data
.configs
.configs
);
258 static const struct pinctrl_ops sunxi_pctrl_ops
= {
259 .dt_node_to_map
= sunxi_pctrl_dt_node_to_map
,
260 .dt_free_map
= sunxi_pctrl_dt_free_map
,
261 .get_groups_count
= sunxi_pctrl_get_groups_count
,
262 .get_group_name
= sunxi_pctrl_get_group_name
,
263 .get_group_pins
= sunxi_pctrl_get_group_pins
,
266 static int sunxi_pconf_group_get(struct pinctrl_dev
*pctldev
,
268 unsigned long *config
)
270 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
272 *config
= pctl
->groups
[group
].config
;
277 static int sunxi_pconf_group_set(struct pinctrl_dev
*pctldev
,
279 unsigned long *configs
,
280 unsigned num_configs
)
282 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
283 struct sunxi_pinctrl_group
*g
= &pctl
->groups
[group
];
290 spin_lock_irqsave(&pctl
->lock
, flags
);
292 for (i
= 0; i
< num_configs
; i
++) {
293 switch (pinconf_to_config_param(configs
[i
])) {
294 case PIN_CONFIG_DRIVE_STRENGTH
:
295 strength
= pinconf_to_config_argument(configs
[i
]);
297 spin_unlock_irqrestore(&pctl
->lock
, flags
);
301 * We convert from mA to what the register expects:
307 dlevel
= strength
/ 10 - 1;
308 val
= readl(pctl
->membase
+ sunxi_dlevel_reg(g
->pin
));
309 mask
= DLEVEL_PINS_MASK
<< sunxi_dlevel_offset(g
->pin
);
311 | dlevel
<< sunxi_dlevel_offset(g
->pin
),
312 pctl
->membase
+ sunxi_dlevel_reg(g
->pin
));
314 case PIN_CONFIG_BIAS_PULL_UP
:
315 val
= readl(pctl
->membase
+ sunxi_pull_reg(g
->pin
));
316 mask
= PULL_PINS_MASK
<< sunxi_pull_offset(g
->pin
);
317 writel((val
& ~mask
) | 1 << sunxi_pull_offset(g
->pin
),
318 pctl
->membase
+ sunxi_pull_reg(g
->pin
));
320 case PIN_CONFIG_BIAS_PULL_DOWN
:
321 val
= readl(pctl
->membase
+ sunxi_pull_reg(g
->pin
));
322 mask
= PULL_PINS_MASK
<< sunxi_pull_offset(g
->pin
);
323 writel((val
& ~mask
) | 2 << sunxi_pull_offset(g
->pin
),
324 pctl
->membase
+ sunxi_pull_reg(g
->pin
));
329 /* cache the config value */
330 g
->config
= configs
[i
];
331 } /* for each config */
333 spin_unlock_irqrestore(&pctl
->lock
, flags
);
338 static const struct pinconf_ops sunxi_pconf_ops
= {
339 .pin_config_group_get
= sunxi_pconf_group_get
,
340 .pin_config_group_set
= sunxi_pconf_group_set
,
343 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev
*pctldev
)
345 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
347 return pctl
->nfunctions
;
350 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev
*pctldev
,
353 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
355 return pctl
->functions
[function
].name
;
358 static int sunxi_pmx_get_func_groups(struct pinctrl_dev
*pctldev
,
360 const char * const **groups
,
361 unsigned * const num_groups
)
363 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
365 *groups
= pctl
->functions
[function
].groups
;
366 *num_groups
= pctl
->functions
[function
].ngroups
;
371 static void sunxi_pmx_set(struct pinctrl_dev
*pctldev
,
375 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
379 spin_lock_irqsave(&pctl
->lock
, flags
);
381 val
= readl(pctl
->membase
+ sunxi_mux_reg(pin
));
382 mask
= MUX_PINS_MASK
<< sunxi_mux_offset(pin
);
383 writel((val
& ~mask
) | config
<< sunxi_mux_offset(pin
),
384 pctl
->membase
+ sunxi_mux_reg(pin
));
386 spin_unlock_irqrestore(&pctl
->lock
, flags
);
389 static int sunxi_pmx_enable(struct pinctrl_dev
*pctldev
,
393 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
394 struct sunxi_pinctrl_group
*g
= pctl
->groups
+ group
;
395 struct sunxi_pinctrl_function
*func
= pctl
->functions
+ function
;
396 struct sunxi_desc_function
*desc
=
397 sunxi_pinctrl_desc_find_function_by_name(pctl
,
404 sunxi_pmx_set(pctldev
, g
->pin
, desc
->muxval
);
410 sunxi_pmx_gpio_set_direction(struct pinctrl_dev
*pctldev
,
411 struct pinctrl_gpio_range
*range
,
415 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
416 struct sunxi_desc_function
*desc
;
424 desc
= sunxi_pinctrl_desc_find_function_by_pin(pctl
, offset
, func
);
428 sunxi_pmx_set(pctldev
, offset
, desc
->muxval
);
433 static const struct pinmux_ops sunxi_pmx_ops
= {
434 .get_functions_count
= sunxi_pmx_get_funcs_cnt
,
435 .get_function_name
= sunxi_pmx_get_func_name
,
436 .get_function_groups
= sunxi_pmx_get_func_groups
,
437 .enable
= sunxi_pmx_enable
,
438 .gpio_set_direction
= sunxi_pmx_gpio_set_direction
,
441 static struct pinctrl_desc sunxi_pctrl_desc
= {
442 .confops
= &sunxi_pconf_ops
,
443 .pctlops
= &sunxi_pctrl_ops
,
444 .pmxops
= &sunxi_pmx_ops
,
447 static int sunxi_pinctrl_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
449 return pinctrl_request_gpio(chip
->base
+ offset
);
452 static void sunxi_pinctrl_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
454 pinctrl_free_gpio(chip
->base
+ offset
);
457 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip
*chip
,
460 return pinctrl_gpio_direction_input(chip
->base
+ offset
);
463 static int sunxi_pinctrl_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
465 struct sunxi_pinctrl
*pctl
= dev_get_drvdata(chip
->dev
);
467 u32 reg
= sunxi_data_reg(offset
);
468 u8 index
= sunxi_data_offset(offset
);
469 u32 val
= (readl(pctl
->membase
+ reg
) >> index
) & DATA_PINS_MASK
;
474 static void sunxi_pinctrl_gpio_set(struct gpio_chip
*chip
,
475 unsigned offset
, int value
)
477 struct sunxi_pinctrl
*pctl
= dev_get_drvdata(chip
->dev
);
478 u32 reg
= sunxi_data_reg(offset
);
479 u8 index
= sunxi_data_offset(offset
);
483 spin_lock_irqsave(&pctl
->lock
, flags
);
485 regval
= readl(pctl
->membase
+ reg
);
488 regval
|= BIT(index
);
490 regval
&= ~(BIT(index
));
492 writel(regval
, pctl
->membase
+ reg
);
494 spin_unlock_irqrestore(&pctl
->lock
, flags
);
497 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip
*chip
,
498 unsigned offset
, int value
)
500 sunxi_pinctrl_gpio_set(chip
, offset
, value
);
501 return pinctrl_gpio_direction_output(chip
->base
+ offset
);
504 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip
*gc
,
505 const struct of_phandle_args
*gpiospec
,
510 base
= PINS_PER_BANK
* gpiospec
->args
[0];
511 pin
= base
+ gpiospec
->args
[1];
513 if (pin
> (gc
->base
+ gc
->ngpio
))
517 *flags
= gpiospec
->args
[2];
522 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip
*chip
, unsigned offset
)
524 struct sunxi_pinctrl
*pctl
= dev_get_drvdata(chip
->dev
);
525 struct sunxi_desc_function
*desc
;
527 if (offset
>= chip
->ngpio
)
530 desc
= sunxi_pinctrl_desc_find_function_by_pin(pctl
, offset
, "irq");
534 pctl
->irq_array
[desc
->irqnum
] = offset
;
536 dev_dbg(chip
->dev
, "%s: request IRQ for GPIO %d, return %d\n",
537 chip
->label
, offset
+ chip
->base
, desc
->irqnum
);
539 return irq_find_mapping(pctl
->domain
, desc
->irqnum
);
543 static int sunxi_pinctrl_irq_set_type(struct irq_data
*d
,
546 struct sunxi_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
547 u32 reg
= sunxi_irq_cfg_reg(d
->hwirq
);
548 u8 index
= sunxi_irq_cfg_offset(d
->hwirq
);
554 case IRQ_TYPE_EDGE_RISING
:
555 mode
= IRQ_EDGE_RISING
;
557 case IRQ_TYPE_EDGE_FALLING
:
558 mode
= IRQ_EDGE_FALLING
;
560 case IRQ_TYPE_EDGE_BOTH
:
561 mode
= IRQ_EDGE_BOTH
;
563 case IRQ_TYPE_LEVEL_HIGH
:
564 mode
= IRQ_LEVEL_HIGH
;
566 case IRQ_TYPE_LEVEL_LOW
:
567 mode
= IRQ_LEVEL_LOW
;
573 spin_lock_irqsave(&pctl
->lock
, flags
);
575 regval
= readl(pctl
->membase
+ reg
);
576 regval
&= ~(IRQ_CFG_IRQ_MASK
<< index
);
577 writel(regval
| (mode
<< index
), pctl
->membase
+ reg
);
579 spin_unlock_irqrestore(&pctl
->lock
, flags
);
584 static void sunxi_pinctrl_irq_mask_ack(struct irq_data
*d
)
586 struct sunxi_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
587 u32 ctrl_reg
= sunxi_irq_ctrl_reg(d
->hwirq
);
588 u8 ctrl_idx
= sunxi_irq_ctrl_offset(d
->hwirq
);
589 u32 status_reg
= sunxi_irq_status_reg(d
->hwirq
);
590 u8 status_idx
= sunxi_irq_status_offset(d
->hwirq
);
594 spin_lock_irqsave(&pctl
->lock
, flags
);
597 val
= readl(pctl
->membase
+ ctrl_reg
);
598 writel(val
& ~(1 << ctrl_idx
), pctl
->membase
+ ctrl_reg
);
601 writel(1 << status_idx
, pctl
->membase
+ status_reg
);
603 spin_unlock_irqrestore(&pctl
->lock
, flags
);
606 static void sunxi_pinctrl_irq_mask(struct irq_data
*d
)
608 struct sunxi_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
609 u32 reg
= sunxi_irq_ctrl_reg(d
->hwirq
);
610 u8 idx
= sunxi_irq_ctrl_offset(d
->hwirq
);
614 spin_lock_irqsave(&pctl
->lock
, flags
);
617 val
= readl(pctl
->membase
+ reg
);
618 writel(val
& ~(1 << idx
), pctl
->membase
+ reg
);
620 spin_unlock_irqrestore(&pctl
->lock
, flags
);
623 static void sunxi_pinctrl_irq_unmask(struct irq_data
*d
)
625 struct sunxi_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
626 struct sunxi_desc_function
*func
;
627 u32 reg
= sunxi_irq_ctrl_reg(d
->hwirq
);
628 u8 idx
= sunxi_irq_ctrl_offset(d
->hwirq
);
632 func
= sunxi_pinctrl_desc_find_function_by_pin(pctl
,
633 pctl
->irq_array
[d
->hwirq
],
636 /* Change muxing to INT mode */
637 sunxi_pmx_set(pctl
->pctl_dev
, pctl
->irq_array
[d
->hwirq
], func
->muxval
);
639 spin_lock_irqsave(&pctl
->lock
, flags
);
642 val
= readl(pctl
->membase
+ reg
);
643 writel(val
| (1 << idx
), pctl
->membase
+ reg
);
645 spin_unlock_irqrestore(&pctl
->lock
, flags
);
648 static struct irq_chip sunxi_pinctrl_irq_chip
= {
649 .irq_mask
= sunxi_pinctrl_irq_mask
,
650 .irq_mask_ack
= sunxi_pinctrl_irq_mask_ack
,
651 .irq_unmask
= sunxi_pinctrl_irq_unmask
,
652 .irq_set_type
= sunxi_pinctrl_irq_set_type
,
655 static void sunxi_pinctrl_irq_handler(unsigned irq
, struct irq_desc
*desc
)
657 struct irq_chip
*chip
= irq_get_chip(irq
);
658 struct sunxi_pinctrl
*pctl
= irq_get_handler_data(irq
);
659 const unsigned long reg
= readl(pctl
->membase
+ IRQ_STATUS_REG
);
661 /* Clear all interrupts */
662 writel(reg
, pctl
->membase
+ IRQ_STATUS_REG
);
667 chained_irq_enter(chip
, desc
);
668 for_each_set_bit(irqoffset
, ®
, SUNXI_IRQ_NUMBER
) {
669 int pin_irq
= irq_find_mapping(pctl
->domain
, irqoffset
);
670 generic_handle_irq(pin_irq
);
672 chained_irq_exit(chip
, desc
);
676 static struct of_device_id sunxi_pinctrl_match
[] = {
677 { .compatible
= "allwinner,sun4i-a10-pinctrl", .data
= (void *)&sun4i_a10_pinctrl_data
},
678 { .compatible
= "allwinner,sun5i-a10s-pinctrl", .data
= (void *)&sun5i_a10s_pinctrl_data
},
679 { .compatible
= "allwinner,sun5i-a13-pinctrl", .data
= (void *)&sun5i_a13_pinctrl_data
},
680 { .compatible
= "allwinner,sun6i-a31-pinctrl", .data
= (void *)&sun6i_a31_pinctrl_data
},
681 { .compatible
= "allwinner,sun6i-a31-r-pinctrl", .data
= (void *)&sun6i_a31_r_pinctrl_data
},
682 { .compatible
= "allwinner,sun7i-a20-pinctrl", .data
= (void *)&sun7i_a20_pinctrl_data
},
685 MODULE_DEVICE_TABLE(of
, sunxi_pinctrl_match
);
687 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl
*pctl
,
690 struct sunxi_pinctrl_function
*func
= pctl
->functions
;
693 /* function already there */
694 if (strcmp(func
->name
, name
) == 0) {
709 static int sunxi_pinctrl_build_state(struct platform_device
*pdev
)
711 struct sunxi_pinctrl
*pctl
= platform_get_drvdata(pdev
);
714 pctl
->ngroups
= pctl
->desc
->npins
;
716 /* Allocate groups */
717 pctl
->groups
= devm_kzalloc(&pdev
->dev
,
718 pctl
->ngroups
* sizeof(*pctl
->groups
),
723 for (i
= 0; i
< pctl
->desc
->npins
; i
++) {
724 const struct sunxi_desc_pin
*pin
= pctl
->desc
->pins
+ i
;
725 struct sunxi_pinctrl_group
*group
= pctl
->groups
+ i
;
727 group
->name
= pin
->pin
.name
;
728 group
->pin
= pin
->pin
.number
;
732 * We suppose that we won't have any more functions than pins,
733 * we'll reallocate that later anyway
735 pctl
->functions
= devm_kzalloc(&pdev
->dev
,
736 pctl
->desc
->npins
* sizeof(*pctl
->functions
),
738 if (!pctl
->functions
)
741 /* Count functions and their associated groups */
742 for (i
= 0; i
< pctl
->desc
->npins
; i
++) {
743 const struct sunxi_desc_pin
*pin
= pctl
->desc
->pins
+ i
;
744 struct sunxi_desc_function
*func
= pin
->functions
;
747 sunxi_pinctrl_add_function(pctl
, func
->name
);
752 pctl
->functions
= krealloc(pctl
->functions
,
753 pctl
->nfunctions
* sizeof(*pctl
->functions
),
756 for (i
= 0; i
< pctl
->desc
->npins
; i
++) {
757 const struct sunxi_desc_pin
*pin
= pctl
->desc
->pins
+ i
;
758 struct sunxi_desc_function
*func
= pin
->functions
;
761 struct sunxi_pinctrl_function
*func_item
;
762 const char **func_grp
;
764 func_item
= sunxi_pinctrl_find_function_by_name(pctl
,
769 if (!func_item
->groups
) {
771 devm_kzalloc(&pdev
->dev
,
772 func_item
->ngroups
* sizeof(*func_item
->groups
),
774 if (!func_item
->groups
)
778 func_grp
= func_item
->groups
;
782 *func_grp
= pin
->pin
.name
;
790 static int sunxi_pinctrl_probe(struct platform_device
*pdev
)
792 struct device_node
*node
= pdev
->dev
.of_node
;
793 const struct of_device_id
*device
;
794 struct pinctrl_pin_desc
*pins
;
795 struct sunxi_pinctrl
*pctl
;
796 struct reset_control
*rstc
;
797 int i
, ret
, last_pin
;
800 pctl
= devm_kzalloc(&pdev
->dev
, sizeof(*pctl
), GFP_KERNEL
);
803 platform_set_drvdata(pdev
, pctl
);
805 spin_lock_init(&pctl
->lock
);
807 pctl
->membase
= of_iomap(node
, 0);
811 device
= of_match_device(sunxi_pinctrl_match
, &pdev
->dev
);
815 pctl
->desc
= device
->data
;
817 ret
= sunxi_pinctrl_build_state(pdev
);
819 dev_err(&pdev
->dev
, "dt probe failed: %d\n", ret
);
823 pins
= devm_kzalloc(&pdev
->dev
,
824 pctl
->desc
->npins
* sizeof(*pins
),
829 for (i
= 0; i
< pctl
->desc
->npins
; i
++)
830 pins
[i
] = pctl
->desc
->pins
[i
].pin
;
832 sunxi_pctrl_desc
.name
= dev_name(&pdev
->dev
);
833 sunxi_pctrl_desc
.owner
= THIS_MODULE
;
834 sunxi_pctrl_desc
.pins
= pins
;
835 sunxi_pctrl_desc
.npins
= pctl
->desc
->npins
;
836 pctl
->dev
= &pdev
->dev
;
837 pctl
->pctl_dev
= pinctrl_register(&sunxi_pctrl_desc
,
839 if (!pctl
->pctl_dev
) {
840 dev_err(&pdev
->dev
, "couldn't register pinctrl driver\n");
844 pctl
->chip
= devm_kzalloc(&pdev
->dev
, sizeof(*pctl
->chip
), GFP_KERNEL
);
850 last_pin
= pctl
->desc
->pins
[pctl
->desc
->npins
- 1].pin
.number
;
851 pctl
->chip
->owner
= THIS_MODULE
;
852 pctl
->chip
->request
= sunxi_pinctrl_gpio_request
,
853 pctl
->chip
->free
= sunxi_pinctrl_gpio_free
,
854 pctl
->chip
->direction_input
= sunxi_pinctrl_gpio_direction_input
,
855 pctl
->chip
->direction_output
= sunxi_pinctrl_gpio_direction_output
,
856 pctl
->chip
->get
= sunxi_pinctrl_gpio_get
,
857 pctl
->chip
->set
= sunxi_pinctrl_gpio_set
,
858 pctl
->chip
->of_xlate
= sunxi_pinctrl_gpio_of_xlate
,
859 pctl
->chip
->to_irq
= sunxi_pinctrl_gpio_to_irq
,
860 pctl
->chip
->of_gpio_n_cells
= 3,
861 pctl
->chip
->can_sleep
= false,
862 pctl
->chip
->ngpio
= round_up(last_pin
, PINS_PER_BANK
) -
863 pctl
->desc
->pin_base
;
864 pctl
->chip
->label
= dev_name(&pdev
->dev
);
865 pctl
->chip
->dev
= &pdev
->dev
;
866 pctl
->chip
->base
= pctl
->desc
->pin_base
;
868 ret
= gpiochip_add(pctl
->chip
);
872 for (i
= 0; i
< pctl
->desc
->npins
; i
++) {
873 const struct sunxi_desc_pin
*pin
= pctl
->desc
->pins
+ i
;
875 ret
= gpiochip_add_pin_range(pctl
->chip
, dev_name(&pdev
->dev
),
882 clk
= devm_clk_get(&pdev
->dev
, NULL
);
888 ret
= clk_prepare_enable(clk
);
892 rstc
= devm_reset_control_get_optional(&pdev
->dev
, NULL
);
894 ret
= reset_control_deassert(rstc
);
899 pctl
->irq
= irq_of_parse_and_map(node
, 0);
905 pctl
->domain
= irq_domain_add_linear(node
, SUNXI_IRQ_NUMBER
,
906 &irq_domain_simple_ops
, NULL
);
908 dev_err(&pdev
->dev
, "Couldn't register IRQ domain\n");
913 for (i
= 0; i
< SUNXI_IRQ_NUMBER
; i
++) {
914 int irqno
= irq_create_mapping(pctl
->domain
, i
);
916 irq_set_chip_and_handler(irqno
, &sunxi_pinctrl_irq_chip
,
918 irq_set_chip_data(irqno
, pctl
);
921 irq_set_chained_handler(pctl
->irq
, sunxi_pinctrl_irq_handler
);
922 irq_set_handler_data(pctl
->irq
, pctl
);
924 dev_info(&pdev
->dev
, "initialized sunXi PIO driver\n");
930 reset_control_assert(rstc
);
932 clk_disable_unprepare(clk
);
934 if (gpiochip_remove(pctl
->chip
))
935 dev_err(&pdev
->dev
, "failed to remove gpio chip\n");
937 pinctrl_unregister(pctl
->pctl_dev
);
941 static struct platform_driver sunxi_pinctrl_driver
= {
942 .probe
= sunxi_pinctrl_probe
,
944 .name
= "sunxi-pinctrl",
945 .owner
= THIS_MODULE
,
946 .of_match_table
= sunxi_pinctrl_match
,
949 module_platform_driver(sunxi_pinctrl_driver
);
951 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
952 MODULE_DESCRIPTION("Allwinner A1X pinctrl driver");
953 MODULE_LICENSE("GPL");