2 * Allwinner A1X SoCs pinctrl driver.
4 * Copyright (C) 2012 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
14 #include <linux/clk.h>
15 #include <linux/gpio.h>
16 #include <linux/irqdomain.h>
17 #include <linux/irqchip/chained_irq.h>
18 #include <linux/module.h>
20 #include <linux/of_address.h>
21 #include <linux/of_device.h>
22 #include <linux/of_irq.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pinctrl/machine.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinconf-generic.h>
27 #include <linux/pinctrl/pinmux.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
32 #include "pinctrl-sunxi.h"
34 static struct sunxi_pinctrl_group
*
35 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl
*pctl
, const char *group
)
39 for (i
= 0; i
< pctl
->ngroups
; i
++) {
40 struct sunxi_pinctrl_group
*grp
= pctl
->groups
+ i
;
42 if (!strcmp(grp
->name
, group
))
49 static struct sunxi_pinctrl_function
*
50 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl
*pctl
,
53 struct sunxi_pinctrl_function
*func
= pctl
->functions
;
56 for (i
= 0; i
< pctl
->nfunctions
; i
++) {
60 if (!strcmp(func
[i
].name
, name
))
67 static struct sunxi_desc_function
*
68 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl
*pctl
,
70 const char *func_name
)
74 for (i
= 0; i
< pctl
->desc
->npins
; i
++) {
75 const struct sunxi_desc_pin
*pin
= pctl
->desc
->pins
+ i
;
77 if (!strcmp(pin
->pin
.name
, pin_name
)) {
78 struct sunxi_desc_function
*func
= pin
->functions
;
81 if (!strcmp(func
->name
, func_name
))
92 static struct sunxi_desc_function
*
93 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl
*pctl
,
95 const char *func_name
)
99 for (i
= 0; i
< pctl
->desc
->npins
; i
++) {
100 const struct sunxi_desc_pin
*pin
= pctl
->desc
->pins
+ i
;
102 if (pin
->pin
.number
== pin_num
) {
103 struct sunxi_desc_function
*func
= pin
->functions
;
106 if (!strcmp(func
->name
, func_name
))
117 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev
*pctldev
)
119 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
121 return pctl
->ngroups
;
124 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev
*pctldev
,
127 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
129 return pctl
->groups
[group
].name
;
132 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev
*pctldev
,
134 const unsigned **pins
,
137 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
139 *pins
= (unsigned *)&pctl
->groups
[group
].pin
;
145 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev
*pctldev
,
146 struct device_node
*node
,
147 struct pinctrl_map
**map
,
150 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
151 unsigned long *pinconfig
;
152 struct property
*prop
;
153 const char *function
;
155 int ret
, nmaps
, i
= 0;
161 ret
= of_property_read_string(node
, "allwinner,function", &function
);
164 "missing allwinner,function property in node %s\n",
169 nmaps
= of_property_count_strings(node
, "allwinner,pins") * 2;
172 "missing allwinner,pins property in node %s\n",
177 *map
= kmalloc(nmaps
* sizeof(struct pinctrl_map
), GFP_KERNEL
);
181 of_property_for_each_string(node
, "allwinner,pins", prop
, group
) {
182 struct sunxi_pinctrl_group
*grp
=
183 sunxi_pinctrl_find_group_by_name(pctl
, group
);
184 int j
= 0, configlen
= 0;
187 dev_err(pctl
->dev
, "unknown pin %s", group
);
191 if (!sunxi_pinctrl_desc_find_function_by_name(pctl
,
194 dev_err(pctl
->dev
, "unsupported function %s on pin %s",
199 (*map
)[i
].type
= PIN_MAP_TYPE_MUX_GROUP
;
200 (*map
)[i
].data
.mux
.group
= group
;
201 (*map
)[i
].data
.mux
.function
= function
;
205 (*map
)[i
].type
= PIN_MAP_TYPE_CONFIGS_GROUP
;
206 (*map
)[i
].data
.configs
.group_or_pin
= group
;
208 if (of_find_property(node
, "allwinner,drive", NULL
))
210 if (of_find_property(node
, "allwinner,pull", NULL
))
213 pinconfig
= kzalloc(configlen
* sizeof(*pinconfig
), GFP_KERNEL
);
215 if (!of_property_read_u32(node
, "allwinner,drive", &val
)) {
216 u16 strength
= (val
+ 1) * 10;
218 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH
,
222 if (!of_property_read_u32(node
, "allwinner,pull", &val
)) {
223 enum pin_config_param pull
= PIN_CONFIG_END
;
225 pull
= PIN_CONFIG_BIAS_PULL_UP
;
227 pull
= PIN_CONFIG_BIAS_PULL_DOWN
;
228 pinconfig
[j
++] = pinconf_to_config_packed(pull
, 0);
231 (*map
)[i
].data
.configs
.configs
= pinconfig
;
232 (*map
)[i
].data
.configs
.num_configs
= configlen
;
242 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev
*pctldev
,
243 struct pinctrl_map
*map
,
248 for (i
= 0; i
< num_maps
; i
++) {
249 if (map
[i
].type
== PIN_MAP_TYPE_CONFIGS_GROUP
)
250 kfree(map
[i
].data
.configs
.configs
);
256 static const struct pinctrl_ops sunxi_pctrl_ops
= {
257 .dt_node_to_map
= sunxi_pctrl_dt_node_to_map
,
258 .dt_free_map
= sunxi_pctrl_dt_free_map
,
259 .get_groups_count
= sunxi_pctrl_get_groups_count
,
260 .get_group_name
= sunxi_pctrl_get_group_name
,
261 .get_group_pins
= sunxi_pctrl_get_group_pins
,
264 static int sunxi_pconf_group_get(struct pinctrl_dev
*pctldev
,
266 unsigned long *config
)
268 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
270 *config
= pctl
->groups
[group
].config
;
275 static int sunxi_pconf_group_set(struct pinctrl_dev
*pctldev
,
277 unsigned long *configs
,
278 unsigned num_configs
)
280 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
281 struct sunxi_pinctrl_group
*g
= &pctl
->groups
[group
];
283 unsigned pin
= g
->pin
- pctl
->desc
->pin_base
;
289 spin_lock_irqsave(&pctl
->lock
, flags
);
291 for (i
= 0; i
< num_configs
; i
++) {
292 switch (pinconf_to_config_param(configs
[i
])) {
293 case PIN_CONFIG_DRIVE_STRENGTH
:
294 strength
= pinconf_to_config_argument(configs
[i
]);
296 spin_unlock_irqrestore(&pctl
->lock
, flags
);
300 * We convert from mA to what the register expects:
306 dlevel
= strength
/ 10 - 1;
307 val
= readl(pctl
->membase
+ sunxi_dlevel_reg(pin
));
308 mask
= DLEVEL_PINS_MASK
<< sunxi_dlevel_offset(pin
);
310 | dlevel
<< sunxi_dlevel_offset(pin
),
311 pctl
->membase
+ sunxi_dlevel_reg(pin
));
313 case PIN_CONFIG_BIAS_PULL_UP
:
314 val
= readl(pctl
->membase
+ sunxi_pull_reg(pin
));
315 mask
= PULL_PINS_MASK
<< sunxi_pull_offset(pin
);
316 writel((val
& ~mask
) | 1 << sunxi_pull_offset(pin
),
317 pctl
->membase
+ sunxi_pull_reg(pin
));
319 case PIN_CONFIG_BIAS_PULL_DOWN
:
320 val
= readl(pctl
->membase
+ sunxi_pull_reg(pin
));
321 mask
= PULL_PINS_MASK
<< sunxi_pull_offset(pin
);
322 writel((val
& ~mask
) | 2 << sunxi_pull_offset(pin
),
323 pctl
->membase
+ sunxi_pull_reg(pin
));
328 /* cache the config value */
329 g
->config
= configs
[i
];
330 } /* for each config */
332 spin_unlock_irqrestore(&pctl
->lock
, flags
);
337 static const struct pinconf_ops sunxi_pconf_ops
= {
338 .pin_config_group_get
= sunxi_pconf_group_get
,
339 .pin_config_group_set
= sunxi_pconf_group_set
,
342 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev
*pctldev
)
344 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
346 return pctl
->nfunctions
;
349 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev
*pctldev
,
352 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
354 return pctl
->functions
[function
].name
;
357 static int sunxi_pmx_get_func_groups(struct pinctrl_dev
*pctldev
,
359 const char * const **groups
,
360 unsigned * const num_groups
)
362 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
364 *groups
= pctl
->functions
[function
].groups
;
365 *num_groups
= pctl
->functions
[function
].ngroups
;
370 static void sunxi_pmx_set(struct pinctrl_dev
*pctldev
,
374 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
378 spin_lock_irqsave(&pctl
->lock
, flags
);
380 pin
-= pctl
->desc
->pin_base
;
381 val
= readl(pctl
->membase
+ sunxi_mux_reg(pin
));
382 mask
= MUX_PINS_MASK
<< sunxi_mux_offset(pin
);
383 writel((val
& ~mask
) | config
<< sunxi_mux_offset(pin
),
384 pctl
->membase
+ sunxi_mux_reg(pin
));
386 spin_unlock_irqrestore(&pctl
->lock
, flags
);
389 static int sunxi_pmx_enable(struct pinctrl_dev
*pctldev
,
393 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
394 struct sunxi_pinctrl_group
*g
= pctl
->groups
+ group
;
395 struct sunxi_pinctrl_function
*func
= pctl
->functions
+ function
;
396 struct sunxi_desc_function
*desc
=
397 sunxi_pinctrl_desc_find_function_by_name(pctl
,
404 sunxi_pmx_set(pctldev
, g
->pin
, desc
->muxval
);
410 sunxi_pmx_gpio_set_direction(struct pinctrl_dev
*pctldev
,
411 struct pinctrl_gpio_range
*range
,
415 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
416 struct sunxi_desc_function
*desc
;
424 desc
= sunxi_pinctrl_desc_find_function_by_pin(pctl
, offset
, func
);
428 sunxi_pmx_set(pctldev
, offset
, desc
->muxval
);
433 static const struct pinmux_ops sunxi_pmx_ops
= {
434 .get_functions_count
= sunxi_pmx_get_funcs_cnt
,
435 .get_function_name
= sunxi_pmx_get_func_name
,
436 .get_function_groups
= sunxi_pmx_get_func_groups
,
437 .enable
= sunxi_pmx_enable
,
438 .gpio_set_direction
= sunxi_pmx_gpio_set_direction
,
441 static int sunxi_pinctrl_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
443 return pinctrl_request_gpio(chip
->base
+ offset
);
446 static void sunxi_pinctrl_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
448 pinctrl_free_gpio(chip
->base
+ offset
);
451 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip
*chip
,
454 return pinctrl_gpio_direction_input(chip
->base
+ offset
);
457 static int sunxi_pinctrl_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
459 struct sunxi_pinctrl
*pctl
= dev_get_drvdata(chip
->dev
);
461 u32 reg
= sunxi_data_reg(offset
);
462 u8 index
= sunxi_data_offset(offset
);
463 u32 val
= (readl(pctl
->membase
+ reg
) >> index
) & DATA_PINS_MASK
;
468 static void sunxi_pinctrl_gpio_set(struct gpio_chip
*chip
,
469 unsigned offset
, int value
)
471 struct sunxi_pinctrl
*pctl
= dev_get_drvdata(chip
->dev
);
472 u32 reg
= sunxi_data_reg(offset
);
473 u8 index
= sunxi_data_offset(offset
);
477 spin_lock_irqsave(&pctl
->lock
, flags
);
479 regval
= readl(pctl
->membase
+ reg
);
482 regval
|= BIT(index
);
484 regval
&= ~(BIT(index
));
486 writel(regval
, pctl
->membase
+ reg
);
488 spin_unlock_irqrestore(&pctl
->lock
, flags
);
491 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip
*chip
,
492 unsigned offset
, int value
)
494 sunxi_pinctrl_gpio_set(chip
, offset
, value
);
495 return pinctrl_gpio_direction_output(chip
->base
+ offset
);
498 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip
*gc
,
499 const struct of_phandle_args
*gpiospec
,
504 base
= PINS_PER_BANK
* gpiospec
->args
[0];
505 pin
= base
+ gpiospec
->args
[1];
507 if (pin
> (gc
->base
+ gc
->ngpio
))
511 *flags
= gpiospec
->args
[2];
516 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip
*chip
, unsigned offset
)
518 struct sunxi_pinctrl
*pctl
= dev_get_drvdata(chip
->dev
);
519 struct sunxi_desc_function
*desc
;
521 if (offset
>= chip
->ngpio
)
524 desc
= sunxi_pinctrl_desc_find_function_by_pin(pctl
, offset
, "irq");
528 dev_dbg(chip
->dev
, "%s: request IRQ for GPIO %d, return %d\n",
529 chip
->label
, offset
+ chip
->base
, desc
->irqnum
);
531 return irq_find_mapping(pctl
->domain
, desc
->irqnum
);
535 static int sunxi_pinctrl_irq_set_type(struct irq_data
*d
,
538 struct sunxi_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
539 u32 reg
= sunxi_irq_cfg_reg(d
->hwirq
);
540 u8 index
= sunxi_irq_cfg_offset(d
->hwirq
);
546 case IRQ_TYPE_EDGE_RISING
:
547 mode
= IRQ_EDGE_RISING
;
549 case IRQ_TYPE_EDGE_FALLING
:
550 mode
= IRQ_EDGE_FALLING
;
552 case IRQ_TYPE_EDGE_BOTH
:
553 mode
= IRQ_EDGE_BOTH
;
555 case IRQ_TYPE_LEVEL_HIGH
:
556 mode
= IRQ_LEVEL_HIGH
;
558 case IRQ_TYPE_LEVEL_LOW
:
559 mode
= IRQ_LEVEL_LOW
;
565 spin_lock_irqsave(&pctl
->lock
, flags
);
567 regval
= readl(pctl
->membase
+ reg
);
568 regval
&= ~(IRQ_CFG_IRQ_MASK
<< index
);
569 writel(regval
| (mode
<< index
), pctl
->membase
+ reg
);
571 spin_unlock_irqrestore(&pctl
->lock
, flags
);
576 static void sunxi_pinctrl_irq_mask_ack(struct irq_data
*d
)
578 struct sunxi_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
579 u32 ctrl_reg
= sunxi_irq_ctrl_reg(d
->hwirq
);
580 u8 ctrl_idx
= sunxi_irq_ctrl_offset(d
->hwirq
);
581 u32 status_reg
= sunxi_irq_status_reg(d
->hwirq
);
582 u8 status_idx
= sunxi_irq_status_offset(d
->hwirq
);
586 spin_lock_irqsave(&pctl
->lock
, flags
);
589 val
= readl(pctl
->membase
+ ctrl_reg
);
590 writel(val
& ~(1 << ctrl_idx
), pctl
->membase
+ ctrl_reg
);
593 writel(1 << status_idx
, pctl
->membase
+ status_reg
);
595 spin_unlock_irqrestore(&pctl
->lock
, flags
);
598 static void sunxi_pinctrl_irq_mask(struct irq_data
*d
)
600 struct sunxi_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
601 u32 reg
= sunxi_irq_ctrl_reg(d
->hwirq
);
602 u8 idx
= sunxi_irq_ctrl_offset(d
->hwirq
);
606 spin_lock_irqsave(&pctl
->lock
, flags
);
609 val
= readl(pctl
->membase
+ reg
);
610 writel(val
& ~(1 << idx
), pctl
->membase
+ reg
);
612 spin_unlock_irqrestore(&pctl
->lock
, flags
);
615 static void sunxi_pinctrl_irq_unmask(struct irq_data
*d
)
617 struct sunxi_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
618 struct sunxi_desc_function
*func
;
619 u32 reg
= sunxi_irq_ctrl_reg(d
->hwirq
);
620 u8 idx
= sunxi_irq_ctrl_offset(d
->hwirq
);
624 func
= sunxi_pinctrl_desc_find_function_by_pin(pctl
,
625 pctl
->irq_array
[d
->hwirq
],
628 /* Change muxing to INT mode */
629 sunxi_pmx_set(pctl
->pctl_dev
, pctl
->irq_array
[d
->hwirq
], func
->muxval
);
631 spin_lock_irqsave(&pctl
->lock
, flags
);
634 val
= readl(pctl
->membase
+ reg
);
635 writel(val
| (1 << idx
), pctl
->membase
+ reg
);
637 spin_unlock_irqrestore(&pctl
->lock
, flags
);
640 static struct irq_chip sunxi_pinctrl_irq_chip
= {
641 .irq_mask
= sunxi_pinctrl_irq_mask
,
642 .irq_mask_ack
= sunxi_pinctrl_irq_mask_ack
,
643 .irq_unmask
= sunxi_pinctrl_irq_unmask
,
644 .irq_set_type
= sunxi_pinctrl_irq_set_type
,
647 static void sunxi_pinctrl_irq_handler(unsigned irq
, struct irq_desc
*desc
)
649 struct irq_chip
*chip
= irq_get_chip(irq
);
650 struct sunxi_pinctrl
*pctl
= irq_get_handler_data(irq
);
651 const unsigned long reg
= readl(pctl
->membase
+ IRQ_STATUS_REG
);
653 /* Clear all interrupts */
654 writel(reg
, pctl
->membase
+ IRQ_STATUS_REG
);
659 chained_irq_enter(chip
, desc
);
660 for_each_set_bit(irqoffset
, ®
, SUNXI_IRQ_NUMBER
) {
661 int pin_irq
= irq_find_mapping(pctl
->domain
, irqoffset
);
662 generic_handle_irq(pin_irq
);
664 chained_irq_exit(chip
, desc
);
668 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl
*pctl
,
671 struct sunxi_pinctrl_function
*func
= pctl
->functions
;
674 /* function already there */
675 if (strcmp(func
->name
, name
) == 0) {
690 static int sunxi_pinctrl_build_state(struct platform_device
*pdev
)
692 struct sunxi_pinctrl
*pctl
= platform_get_drvdata(pdev
);
695 pctl
->ngroups
= pctl
->desc
->npins
;
697 /* Allocate groups */
698 pctl
->groups
= devm_kzalloc(&pdev
->dev
,
699 pctl
->ngroups
* sizeof(*pctl
->groups
),
704 for (i
= 0; i
< pctl
->desc
->npins
; i
++) {
705 const struct sunxi_desc_pin
*pin
= pctl
->desc
->pins
+ i
;
706 struct sunxi_pinctrl_group
*group
= pctl
->groups
+ i
;
708 group
->name
= pin
->pin
.name
;
709 group
->pin
= pin
->pin
.number
;
713 * We suppose that we won't have any more functions than pins,
714 * we'll reallocate that later anyway
716 pctl
->functions
= devm_kzalloc(&pdev
->dev
,
717 pctl
->desc
->npins
* sizeof(*pctl
->functions
),
719 if (!pctl
->functions
)
722 /* Count functions and their associated groups */
723 for (i
= 0; i
< pctl
->desc
->npins
; i
++) {
724 const struct sunxi_desc_pin
*pin
= pctl
->desc
->pins
+ i
;
725 struct sunxi_desc_function
*func
= pin
->functions
;
728 /* Create interrupt mapping while we're at it */
729 if (!strcmp(func
->name
, "irq"))
730 pctl
->irq_array
[func
->irqnum
] = pin
->pin
.number
;
731 sunxi_pinctrl_add_function(pctl
, func
->name
);
736 pctl
->functions
= krealloc(pctl
->functions
,
737 pctl
->nfunctions
* sizeof(*pctl
->functions
),
740 for (i
= 0; i
< pctl
->desc
->npins
; i
++) {
741 const struct sunxi_desc_pin
*pin
= pctl
->desc
->pins
+ i
;
742 struct sunxi_desc_function
*func
= pin
->functions
;
745 struct sunxi_pinctrl_function
*func_item
;
746 const char **func_grp
;
748 func_item
= sunxi_pinctrl_find_function_by_name(pctl
,
753 if (!func_item
->groups
) {
755 devm_kzalloc(&pdev
->dev
,
756 func_item
->ngroups
* sizeof(*func_item
->groups
),
758 if (!func_item
->groups
)
762 func_grp
= func_item
->groups
;
766 *func_grp
= pin
->pin
.name
;
774 int sunxi_pinctrl_init(struct platform_device
*pdev
,
775 const struct sunxi_pinctrl_desc
*desc
)
777 struct device_node
*node
= pdev
->dev
.of_node
;
778 struct pinctrl_desc
*pctrl_desc
;
779 struct pinctrl_pin_desc
*pins
;
780 struct sunxi_pinctrl
*pctl
;
781 struct resource
*res
;
782 int i
, ret
, last_pin
;
785 pctl
= devm_kzalloc(&pdev
->dev
, sizeof(*pctl
), GFP_KERNEL
);
788 platform_set_drvdata(pdev
, pctl
);
790 spin_lock_init(&pctl
->lock
);
792 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
793 pctl
->membase
= devm_ioremap_resource(&pdev
->dev
, res
);
794 if (IS_ERR(pctl
->membase
))
795 return PTR_ERR(pctl
->membase
);
797 pctl
->dev
= &pdev
->dev
;
800 ret
= sunxi_pinctrl_build_state(pdev
);
802 dev_err(&pdev
->dev
, "dt probe failed: %d\n", ret
);
806 pins
= devm_kzalloc(&pdev
->dev
,
807 pctl
->desc
->npins
* sizeof(*pins
),
812 for (i
= 0; i
< pctl
->desc
->npins
; i
++)
813 pins
[i
] = pctl
->desc
->pins
[i
].pin
;
815 pctrl_desc
= devm_kzalloc(&pdev
->dev
,
821 pctrl_desc
->name
= dev_name(&pdev
->dev
);
822 pctrl_desc
->owner
= THIS_MODULE
;
823 pctrl_desc
->pins
= pins
;
824 pctrl_desc
->npins
= pctl
->desc
->npins
;
825 pctrl_desc
->confops
= &sunxi_pconf_ops
;
826 pctrl_desc
->pctlops
= &sunxi_pctrl_ops
;
827 pctrl_desc
->pmxops
= &sunxi_pmx_ops
;
829 pctl
->pctl_dev
= pinctrl_register(pctrl_desc
,
831 if (!pctl
->pctl_dev
) {
832 dev_err(&pdev
->dev
, "couldn't register pinctrl driver\n");
836 pctl
->chip
= devm_kzalloc(&pdev
->dev
, sizeof(*pctl
->chip
), GFP_KERNEL
);
842 last_pin
= pctl
->desc
->pins
[pctl
->desc
->npins
- 1].pin
.number
;
843 pctl
->chip
->owner
= THIS_MODULE
;
844 pctl
->chip
->request
= sunxi_pinctrl_gpio_request
,
845 pctl
->chip
->free
= sunxi_pinctrl_gpio_free
,
846 pctl
->chip
->direction_input
= sunxi_pinctrl_gpio_direction_input
,
847 pctl
->chip
->direction_output
= sunxi_pinctrl_gpio_direction_output
,
848 pctl
->chip
->get
= sunxi_pinctrl_gpio_get
,
849 pctl
->chip
->set
= sunxi_pinctrl_gpio_set
,
850 pctl
->chip
->of_xlate
= sunxi_pinctrl_gpio_of_xlate
,
851 pctl
->chip
->to_irq
= sunxi_pinctrl_gpio_to_irq
,
852 pctl
->chip
->of_gpio_n_cells
= 3,
853 pctl
->chip
->can_sleep
= false,
854 pctl
->chip
->ngpio
= round_up(last_pin
, PINS_PER_BANK
) -
855 pctl
->desc
->pin_base
;
856 pctl
->chip
->label
= dev_name(&pdev
->dev
);
857 pctl
->chip
->dev
= &pdev
->dev
;
858 pctl
->chip
->base
= pctl
->desc
->pin_base
;
860 ret
= gpiochip_add(pctl
->chip
);
864 for (i
= 0; i
< pctl
->desc
->npins
; i
++) {
865 const struct sunxi_desc_pin
*pin
= pctl
->desc
->pins
+ i
;
867 ret
= gpiochip_add_pin_range(pctl
->chip
, dev_name(&pdev
->dev
),
874 clk
= devm_clk_get(&pdev
->dev
, NULL
);
880 ret
= clk_prepare_enable(clk
);
884 pctl
->irq
= irq_of_parse_and_map(node
, 0);
890 pctl
->domain
= irq_domain_add_linear(node
, SUNXI_IRQ_NUMBER
,
891 &irq_domain_simple_ops
, NULL
);
893 dev_err(&pdev
->dev
, "Couldn't register IRQ domain\n");
898 for (i
= 0; i
< SUNXI_IRQ_NUMBER
; i
++) {
899 int irqno
= irq_create_mapping(pctl
->domain
, i
);
901 irq_set_chip_and_handler(irqno
, &sunxi_pinctrl_irq_chip
,
903 irq_set_chip_data(irqno
, pctl
);
906 irq_set_chained_handler(pctl
->irq
, sunxi_pinctrl_irq_handler
);
907 irq_set_handler_data(pctl
->irq
, pctl
);
909 dev_info(&pdev
->dev
, "initialized sunXi PIO driver\n");
914 clk_disable_unprepare(clk
);
916 if (gpiochip_remove(pctl
->chip
))
917 dev_err(&pdev
->dev
, "failed to remove gpio chip\n");
919 pinctrl_unregister(pctl
->pctl_dev
);