2 * Allwinner A1X SoCs pinctrl driver.
4 * Copyright (C) 2012 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
14 #include <linux/clk.h>
15 #include <linux/gpio.h>
16 #include <linux/irqdomain.h>
17 #include <linux/irqchip/chained_irq.h>
18 #include <linux/module.h>
20 #include <linux/of_address.h>
21 #include <linux/of_device.h>
22 #include <linux/of_irq.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pinctrl/machine.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinconf-generic.h>
27 #include <linux/pinctrl/pinmux.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
32 #include "pinctrl-sunxi.h"
34 static struct irq_chip sunxi_pinctrl_edge_irq_chip
;
35 static struct irq_chip sunxi_pinctrl_level_irq_chip
;
37 static struct sunxi_pinctrl_group
*
38 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl
*pctl
, const char *group
)
42 for (i
= 0; i
< pctl
->ngroups
; i
++) {
43 struct sunxi_pinctrl_group
*grp
= pctl
->groups
+ i
;
45 if (!strcmp(grp
->name
, group
))
52 static struct sunxi_pinctrl_function
*
53 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl
*pctl
,
56 struct sunxi_pinctrl_function
*func
= pctl
->functions
;
59 for (i
= 0; i
< pctl
->nfunctions
; i
++) {
63 if (!strcmp(func
[i
].name
, name
))
70 static struct sunxi_desc_function
*
71 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl
*pctl
,
73 const char *func_name
)
77 for (i
= 0; i
< pctl
->desc
->npins
; i
++) {
78 const struct sunxi_desc_pin
*pin
= pctl
->desc
->pins
+ i
;
80 if (!strcmp(pin
->pin
.name
, pin_name
)) {
81 struct sunxi_desc_function
*func
= pin
->functions
;
84 if (!strcmp(func
->name
, func_name
))
95 static struct sunxi_desc_function
*
96 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl
*pctl
,
98 const char *func_name
)
102 for (i
= 0; i
< pctl
->desc
->npins
; i
++) {
103 const struct sunxi_desc_pin
*pin
= pctl
->desc
->pins
+ i
;
105 if (pin
->pin
.number
== pin_num
) {
106 struct sunxi_desc_function
*func
= pin
->functions
;
109 if (!strcmp(func
->name
, func_name
))
120 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev
*pctldev
)
122 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
124 return pctl
->ngroups
;
127 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev
*pctldev
,
130 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
132 return pctl
->groups
[group
].name
;
135 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev
*pctldev
,
137 const unsigned **pins
,
140 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
142 *pins
= (unsigned *)&pctl
->groups
[group
].pin
;
148 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev
*pctldev
,
149 struct device_node
*node
,
150 struct pinctrl_map
**map
,
153 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
154 unsigned long *pinconfig
;
155 struct property
*prop
;
156 const char *function
;
158 int ret
, nmaps
, i
= 0;
164 ret
= of_property_read_string(node
, "allwinner,function", &function
);
167 "missing allwinner,function property in node %s\n",
172 nmaps
= of_property_count_strings(node
, "allwinner,pins") * 2;
175 "missing allwinner,pins property in node %s\n",
180 *map
= kmalloc(nmaps
* sizeof(struct pinctrl_map
), GFP_KERNEL
);
184 of_property_for_each_string(node
, "allwinner,pins", prop
, group
) {
185 struct sunxi_pinctrl_group
*grp
=
186 sunxi_pinctrl_find_group_by_name(pctl
, group
);
187 int j
= 0, configlen
= 0;
190 dev_err(pctl
->dev
, "unknown pin %s", group
);
194 if (!sunxi_pinctrl_desc_find_function_by_name(pctl
,
197 dev_err(pctl
->dev
, "unsupported function %s on pin %s",
202 (*map
)[i
].type
= PIN_MAP_TYPE_MUX_GROUP
;
203 (*map
)[i
].data
.mux
.group
= group
;
204 (*map
)[i
].data
.mux
.function
= function
;
208 (*map
)[i
].type
= PIN_MAP_TYPE_CONFIGS_GROUP
;
209 (*map
)[i
].data
.configs
.group_or_pin
= group
;
211 if (of_find_property(node
, "allwinner,drive", NULL
))
213 if (of_find_property(node
, "allwinner,pull", NULL
))
216 pinconfig
= kzalloc(configlen
* sizeof(*pinconfig
), GFP_KERNEL
);
218 if (!of_property_read_u32(node
, "allwinner,drive", &val
)) {
219 u16 strength
= (val
+ 1) * 10;
221 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH
,
225 if (!of_property_read_u32(node
, "allwinner,pull", &val
)) {
226 enum pin_config_param pull
= PIN_CONFIG_END
;
228 pull
= PIN_CONFIG_BIAS_PULL_UP
;
230 pull
= PIN_CONFIG_BIAS_PULL_DOWN
;
231 pinconfig
[j
++] = pinconf_to_config_packed(pull
, 0);
234 (*map
)[i
].data
.configs
.configs
= pinconfig
;
235 (*map
)[i
].data
.configs
.num_configs
= configlen
;
245 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev
*pctldev
,
246 struct pinctrl_map
*map
,
251 for (i
= 0; i
< num_maps
; i
++) {
252 if (map
[i
].type
== PIN_MAP_TYPE_CONFIGS_GROUP
)
253 kfree(map
[i
].data
.configs
.configs
);
259 static const struct pinctrl_ops sunxi_pctrl_ops
= {
260 .dt_node_to_map
= sunxi_pctrl_dt_node_to_map
,
261 .dt_free_map
= sunxi_pctrl_dt_free_map
,
262 .get_groups_count
= sunxi_pctrl_get_groups_count
,
263 .get_group_name
= sunxi_pctrl_get_group_name
,
264 .get_group_pins
= sunxi_pctrl_get_group_pins
,
267 static int sunxi_pconf_group_get(struct pinctrl_dev
*pctldev
,
269 unsigned long *config
)
271 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
273 *config
= pctl
->groups
[group
].config
;
278 static int sunxi_pconf_group_set(struct pinctrl_dev
*pctldev
,
280 unsigned long *configs
,
281 unsigned num_configs
)
283 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
284 struct sunxi_pinctrl_group
*g
= &pctl
->groups
[group
];
286 unsigned pin
= g
->pin
- pctl
->desc
->pin_base
;
292 spin_lock_irqsave(&pctl
->lock
, flags
);
294 for (i
= 0; i
< num_configs
; i
++) {
295 switch (pinconf_to_config_param(configs
[i
])) {
296 case PIN_CONFIG_DRIVE_STRENGTH
:
297 strength
= pinconf_to_config_argument(configs
[i
]);
299 spin_unlock_irqrestore(&pctl
->lock
, flags
);
303 * We convert from mA to what the register expects:
309 dlevel
= strength
/ 10 - 1;
310 val
= readl(pctl
->membase
+ sunxi_dlevel_reg(pin
));
311 mask
= DLEVEL_PINS_MASK
<< sunxi_dlevel_offset(pin
);
313 | dlevel
<< sunxi_dlevel_offset(pin
),
314 pctl
->membase
+ sunxi_dlevel_reg(pin
));
316 case PIN_CONFIG_BIAS_PULL_UP
:
317 val
= readl(pctl
->membase
+ sunxi_pull_reg(pin
));
318 mask
= PULL_PINS_MASK
<< sunxi_pull_offset(pin
);
319 writel((val
& ~mask
) | 1 << sunxi_pull_offset(pin
),
320 pctl
->membase
+ sunxi_pull_reg(pin
));
322 case PIN_CONFIG_BIAS_PULL_DOWN
:
323 val
= readl(pctl
->membase
+ sunxi_pull_reg(pin
));
324 mask
= PULL_PINS_MASK
<< sunxi_pull_offset(pin
);
325 writel((val
& ~mask
) | 2 << sunxi_pull_offset(pin
),
326 pctl
->membase
+ sunxi_pull_reg(pin
));
331 /* cache the config value */
332 g
->config
= configs
[i
];
333 } /* for each config */
335 spin_unlock_irqrestore(&pctl
->lock
, flags
);
340 static const struct pinconf_ops sunxi_pconf_ops
= {
341 .pin_config_group_get
= sunxi_pconf_group_get
,
342 .pin_config_group_set
= sunxi_pconf_group_set
,
345 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev
*pctldev
)
347 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
349 return pctl
->nfunctions
;
352 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev
*pctldev
,
355 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
357 return pctl
->functions
[function
].name
;
360 static int sunxi_pmx_get_func_groups(struct pinctrl_dev
*pctldev
,
362 const char * const **groups
,
363 unsigned * const num_groups
)
365 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
367 *groups
= pctl
->functions
[function
].groups
;
368 *num_groups
= pctl
->functions
[function
].ngroups
;
373 static void sunxi_pmx_set(struct pinctrl_dev
*pctldev
,
377 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
381 spin_lock_irqsave(&pctl
->lock
, flags
);
383 pin
-= pctl
->desc
->pin_base
;
384 val
= readl(pctl
->membase
+ sunxi_mux_reg(pin
));
385 mask
= MUX_PINS_MASK
<< sunxi_mux_offset(pin
);
386 writel((val
& ~mask
) | config
<< sunxi_mux_offset(pin
),
387 pctl
->membase
+ sunxi_mux_reg(pin
));
389 spin_unlock_irqrestore(&pctl
->lock
, flags
);
392 static int sunxi_pmx_enable(struct pinctrl_dev
*pctldev
,
396 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
397 struct sunxi_pinctrl_group
*g
= pctl
->groups
+ group
;
398 struct sunxi_pinctrl_function
*func
= pctl
->functions
+ function
;
399 struct sunxi_desc_function
*desc
=
400 sunxi_pinctrl_desc_find_function_by_name(pctl
,
407 sunxi_pmx_set(pctldev
, g
->pin
, desc
->muxval
);
413 sunxi_pmx_gpio_set_direction(struct pinctrl_dev
*pctldev
,
414 struct pinctrl_gpio_range
*range
,
418 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
419 struct sunxi_desc_function
*desc
;
427 desc
= sunxi_pinctrl_desc_find_function_by_pin(pctl
, offset
, func
);
431 sunxi_pmx_set(pctldev
, offset
, desc
->muxval
);
436 static const struct pinmux_ops sunxi_pmx_ops
= {
437 .get_functions_count
= sunxi_pmx_get_funcs_cnt
,
438 .get_function_name
= sunxi_pmx_get_func_name
,
439 .get_function_groups
= sunxi_pmx_get_func_groups
,
440 .enable
= sunxi_pmx_enable
,
441 .gpio_set_direction
= sunxi_pmx_gpio_set_direction
,
444 static int sunxi_pinctrl_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
446 return pinctrl_request_gpio(chip
->base
+ offset
);
449 static void sunxi_pinctrl_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
451 pinctrl_free_gpio(chip
->base
+ offset
);
454 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip
*chip
,
457 return pinctrl_gpio_direction_input(chip
->base
+ offset
);
460 static int sunxi_pinctrl_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
462 struct sunxi_pinctrl
*pctl
= dev_get_drvdata(chip
->dev
);
464 u32 reg
= sunxi_data_reg(offset
);
465 u8 index
= sunxi_data_offset(offset
);
466 u32 val
= (readl(pctl
->membase
+ reg
) >> index
) & DATA_PINS_MASK
;
471 static void sunxi_pinctrl_gpio_set(struct gpio_chip
*chip
,
472 unsigned offset
, int value
)
474 struct sunxi_pinctrl
*pctl
= dev_get_drvdata(chip
->dev
);
475 u32 reg
= sunxi_data_reg(offset
);
476 u8 index
= sunxi_data_offset(offset
);
480 spin_lock_irqsave(&pctl
->lock
, flags
);
482 regval
= readl(pctl
->membase
+ reg
);
485 regval
|= BIT(index
);
487 regval
&= ~(BIT(index
));
489 writel(regval
, pctl
->membase
+ reg
);
491 spin_unlock_irqrestore(&pctl
->lock
, flags
);
494 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip
*chip
,
495 unsigned offset
, int value
)
497 sunxi_pinctrl_gpio_set(chip
, offset
, value
);
498 return pinctrl_gpio_direction_output(chip
->base
+ offset
);
501 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip
*gc
,
502 const struct of_phandle_args
*gpiospec
,
507 base
= PINS_PER_BANK
* gpiospec
->args
[0];
508 pin
= base
+ gpiospec
->args
[1];
510 if (pin
> (gc
->base
+ gc
->ngpio
))
514 *flags
= gpiospec
->args
[2];
519 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip
*chip
, unsigned offset
)
521 struct sunxi_pinctrl
*pctl
= dev_get_drvdata(chip
->dev
);
522 struct sunxi_desc_function
*desc
;
524 if (offset
>= chip
->ngpio
)
527 desc
= sunxi_pinctrl_desc_find_function_by_pin(pctl
, offset
, "irq");
531 dev_dbg(chip
->dev
, "%s: request IRQ for GPIO %d, return %d\n",
532 chip
->label
, offset
+ chip
->base
, desc
->irqnum
);
534 return irq_find_mapping(pctl
->domain
, desc
->irqnum
);
537 static int sunxi_pinctrl_irq_request_resources(struct irq_data
*d
)
539 struct sunxi_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
540 struct sunxi_desc_function
*func
;
542 func
= sunxi_pinctrl_desc_find_function_by_pin(pctl
,
543 pctl
->irq_array
[d
->hwirq
], "irq");
547 /* Change muxing to INT mode */
548 sunxi_pmx_set(pctl
->pctl_dev
, pctl
->irq_array
[d
->hwirq
], func
->muxval
);
553 static int sunxi_pinctrl_irq_set_type(struct irq_data
*d
, unsigned int type
)
555 struct sunxi_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
556 struct irq_desc
*desc
= container_of(d
, struct irq_desc
, irq_data
);
557 u32 reg
= sunxi_irq_cfg_reg(d
->hwirq
);
558 u8 index
= sunxi_irq_cfg_offset(d
->hwirq
);
564 case IRQ_TYPE_EDGE_RISING
:
565 mode
= IRQ_EDGE_RISING
;
567 case IRQ_TYPE_EDGE_FALLING
:
568 mode
= IRQ_EDGE_FALLING
;
570 case IRQ_TYPE_EDGE_BOTH
:
571 mode
= IRQ_EDGE_BOTH
;
573 case IRQ_TYPE_LEVEL_HIGH
:
574 mode
= IRQ_LEVEL_HIGH
;
576 case IRQ_TYPE_LEVEL_LOW
:
577 mode
= IRQ_LEVEL_LOW
;
583 if (type
& IRQ_TYPE_LEVEL_MASK
) {
584 d
->chip
= &sunxi_pinctrl_level_irq_chip
;
585 desc
->handle_irq
= handle_fasteoi_irq
;
587 d
->chip
= &sunxi_pinctrl_edge_irq_chip
;
588 desc
->handle_irq
= handle_edge_irq
;
591 spin_lock_irqsave(&pctl
->lock
, flags
);
593 regval
= readl(pctl
->membase
+ reg
);
594 regval
&= ~(IRQ_CFG_IRQ_MASK
<< index
);
595 writel(regval
| (mode
<< index
), pctl
->membase
+ reg
);
597 spin_unlock_irqrestore(&pctl
->lock
, flags
);
602 static void sunxi_pinctrl_irq_ack(struct irq_data
*d
)
604 struct sunxi_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
605 u32 status_reg
= sunxi_irq_status_reg(d
->hwirq
);
606 u8 status_idx
= sunxi_irq_status_offset(d
->hwirq
);
609 writel(1 << status_idx
, pctl
->membase
+ status_reg
);
612 static void sunxi_pinctrl_irq_mask(struct irq_data
*d
)
614 struct sunxi_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
615 u32 reg
= sunxi_irq_ctrl_reg(d
->hwirq
);
616 u8 idx
= sunxi_irq_ctrl_offset(d
->hwirq
);
620 spin_lock_irqsave(&pctl
->lock
, flags
);
623 val
= readl(pctl
->membase
+ reg
);
624 writel(val
& ~(1 << idx
), pctl
->membase
+ reg
);
626 spin_unlock_irqrestore(&pctl
->lock
, flags
);
629 static void sunxi_pinctrl_irq_unmask(struct irq_data
*d
)
631 struct sunxi_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
632 u32 reg
= sunxi_irq_ctrl_reg(d
->hwirq
);
633 u8 idx
= sunxi_irq_ctrl_offset(d
->hwirq
);
637 spin_lock_irqsave(&pctl
->lock
, flags
);
640 val
= readl(pctl
->membase
+ reg
);
641 writel(val
| (1 << idx
), pctl
->membase
+ reg
);
643 spin_unlock_irqrestore(&pctl
->lock
, flags
);
646 static void sunxi_pinctrl_irq_ack_unmask(struct irq_data
*d
)
648 sunxi_pinctrl_irq_ack(d
);
649 sunxi_pinctrl_irq_unmask(d
);
652 static struct irq_chip sunxi_pinctrl_edge_irq_chip
= {
653 .irq_ack
= sunxi_pinctrl_irq_ack
,
654 .irq_mask
= sunxi_pinctrl_irq_mask
,
655 .irq_unmask
= sunxi_pinctrl_irq_unmask
,
656 .irq_request_resources
= sunxi_pinctrl_irq_request_resources
,
657 .irq_set_type
= sunxi_pinctrl_irq_set_type
,
658 .flags
= IRQCHIP_SKIP_SET_WAKE
,
661 static struct irq_chip sunxi_pinctrl_level_irq_chip
= {
662 .irq_eoi
= sunxi_pinctrl_irq_ack
,
663 .irq_mask
= sunxi_pinctrl_irq_mask
,
664 .irq_unmask
= sunxi_pinctrl_irq_unmask
,
665 /* Define irq_enable / disable to avoid spurious irqs for drivers
666 * using these to suppress irqs while they clear the irq source */
667 .irq_enable
= sunxi_pinctrl_irq_ack_unmask
,
668 .irq_disable
= sunxi_pinctrl_irq_mask
,
669 .irq_request_resources
= sunxi_pinctrl_irq_request_resources
,
670 .irq_set_type
= sunxi_pinctrl_irq_set_type
,
671 .flags
= IRQCHIP_SKIP_SET_WAKE
| IRQCHIP_EOI_THREADED
|
672 IRQCHIP_EOI_IF_HANDLED
,
675 static void sunxi_pinctrl_irq_handler(unsigned irq
, struct irq_desc
*desc
)
677 struct irq_chip
*chip
= irq_get_chip(irq
);
678 struct sunxi_pinctrl
*pctl
= irq_get_handler_data(irq
);
679 unsigned long bank
, reg
, val
;
681 for (bank
= 0; bank
< pctl
->desc
->irq_banks
; bank
++)
682 if (irq
== pctl
->irq
[bank
])
685 if (bank
== pctl
->desc
->irq_banks
)
688 reg
= sunxi_irq_status_reg_from_bank(bank
);
689 val
= readl(pctl
->membase
+ reg
);
694 chained_irq_enter(chip
, desc
);
695 for_each_set_bit(irqoffset
, &val
, IRQ_PER_BANK
) {
696 int pin_irq
= irq_find_mapping(pctl
->domain
,
697 bank
* IRQ_PER_BANK
+ irqoffset
);
698 generic_handle_irq(pin_irq
);
700 chained_irq_exit(chip
, desc
);
704 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl
*pctl
,
707 struct sunxi_pinctrl_function
*func
= pctl
->functions
;
710 /* function already there */
711 if (strcmp(func
->name
, name
) == 0) {
726 static int sunxi_pinctrl_build_state(struct platform_device
*pdev
)
728 struct sunxi_pinctrl
*pctl
= platform_get_drvdata(pdev
);
731 pctl
->ngroups
= pctl
->desc
->npins
;
733 /* Allocate groups */
734 pctl
->groups
= devm_kzalloc(&pdev
->dev
,
735 pctl
->ngroups
* sizeof(*pctl
->groups
),
740 for (i
= 0; i
< pctl
->desc
->npins
; i
++) {
741 const struct sunxi_desc_pin
*pin
= pctl
->desc
->pins
+ i
;
742 struct sunxi_pinctrl_group
*group
= pctl
->groups
+ i
;
744 group
->name
= pin
->pin
.name
;
745 group
->pin
= pin
->pin
.number
;
749 * We suppose that we won't have any more functions than pins,
750 * we'll reallocate that later anyway
752 pctl
->functions
= devm_kzalloc(&pdev
->dev
,
753 pctl
->desc
->npins
* sizeof(*pctl
->functions
),
755 if (!pctl
->functions
)
758 /* Count functions and their associated groups */
759 for (i
= 0; i
< pctl
->desc
->npins
; i
++) {
760 const struct sunxi_desc_pin
*pin
= pctl
->desc
->pins
+ i
;
761 struct sunxi_desc_function
*func
= pin
->functions
;
764 /* Create interrupt mapping while we're at it */
765 if (!strcmp(func
->name
, "irq")) {
766 int irqnum
= func
->irqnum
+ func
->irqbank
* IRQ_PER_BANK
;
767 pctl
->irq_array
[irqnum
] = pin
->pin
.number
;
770 sunxi_pinctrl_add_function(pctl
, func
->name
);
775 pctl
->functions
= krealloc(pctl
->functions
,
776 pctl
->nfunctions
* sizeof(*pctl
->functions
),
779 for (i
= 0; i
< pctl
->desc
->npins
; i
++) {
780 const struct sunxi_desc_pin
*pin
= pctl
->desc
->pins
+ i
;
781 struct sunxi_desc_function
*func
= pin
->functions
;
784 struct sunxi_pinctrl_function
*func_item
;
785 const char **func_grp
;
787 func_item
= sunxi_pinctrl_find_function_by_name(pctl
,
792 if (!func_item
->groups
) {
794 devm_kzalloc(&pdev
->dev
,
795 func_item
->ngroups
* sizeof(*func_item
->groups
),
797 if (!func_item
->groups
)
801 func_grp
= func_item
->groups
;
805 *func_grp
= pin
->pin
.name
;
813 int sunxi_pinctrl_init(struct platform_device
*pdev
,
814 const struct sunxi_pinctrl_desc
*desc
)
816 struct device_node
*node
= pdev
->dev
.of_node
;
817 struct pinctrl_desc
*pctrl_desc
;
818 struct pinctrl_pin_desc
*pins
;
819 struct sunxi_pinctrl
*pctl
;
820 struct resource
*res
;
821 int i
, ret
, last_pin
;
824 pctl
= devm_kzalloc(&pdev
->dev
, sizeof(*pctl
), GFP_KERNEL
);
827 platform_set_drvdata(pdev
, pctl
);
829 spin_lock_init(&pctl
->lock
);
831 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
832 pctl
->membase
= devm_ioremap_resource(&pdev
->dev
, res
);
833 if (IS_ERR(pctl
->membase
))
834 return PTR_ERR(pctl
->membase
);
836 pctl
->dev
= &pdev
->dev
;
839 pctl
->irq_array
= devm_kcalloc(&pdev
->dev
,
840 IRQ_PER_BANK
* pctl
->desc
->irq_banks
,
841 sizeof(*pctl
->irq_array
),
843 if (!pctl
->irq_array
)
846 ret
= sunxi_pinctrl_build_state(pdev
);
848 dev_err(&pdev
->dev
, "dt probe failed: %d\n", ret
);
852 pins
= devm_kzalloc(&pdev
->dev
,
853 pctl
->desc
->npins
* sizeof(*pins
),
858 for (i
= 0; i
< pctl
->desc
->npins
; i
++)
859 pins
[i
] = pctl
->desc
->pins
[i
].pin
;
861 pctrl_desc
= devm_kzalloc(&pdev
->dev
,
867 pctrl_desc
->name
= dev_name(&pdev
->dev
);
868 pctrl_desc
->owner
= THIS_MODULE
;
869 pctrl_desc
->pins
= pins
;
870 pctrl_desc
->npins
= pctl
->desc
->npins
;
871 pctrl_desc
->confops
= &sunxi_pconf_ops
;
872 pctrl_desc
->pctlops
= &sunxi_pctrl_ops
;
873 pctrl_desc
->pmxops
= &sunxi_pmx_ops
;
875 pctl
->pctl_dev
= pinctrl_register(pctrl_desc
,
877 if (!pctl
->pctl_dev
) {
878 dev_err(&pdev
->dev
, "couldn't register pinctrl driver\n");
882 pctl
->chip
= devm_kzalloc(&pdev
->dev
, sizeof(*pctl
->chip
), GFP_KERNEL
);
888 last_pin
= pctl
->desc
->pins
[pctl
->desc
->npins
- 1].pin
.number
;
889 pctl
->chip
->owner
= THIS_MODULE
;
890 pctl
->chip
->request
= sunxi_pinctrl_gpio_request
,
891 pctl
->chip
->free
= sunxi_pinctrl_gpio_free
,
892 pctl
->chip
->direction_input
= sunxi_pinctrl_gpio_direction_input
,
893 pctl
->chip
->direction_output
= sunxi_pinctrl_gpio_direction_output
,
894 pctl
->chip
->get
= sunxi_pinctrl_gpio_get
,
895 pctl
->chip
->set
= sunxi_pinctrl_gpio_set
,
896 pctl
->chip
->of_xlate
= sunxi_pinctrl_gpio_of_xlate
,
897 pctl
->chip
->to_irq
= sunxi_pinctrl_gpio_to_irq
,
898 pctl
->chip
->of_gpio_n_cells
= 3,
899 pctl
->chip
->can_sleep
= false,
900 pctl
->chip
->ngpio
= round_up(last_pin
, PINS_PER_BANK
) -
901 pctl
->desc
->pin_base
;
902 pctl
->chip
->label
= dev_name(&pdev
->dev
);
903 pctl
->chip
->dev
= &pdev
->dev
;
904 pctl
->chip
->base
= pctl
->desc
->pin_base
;
906 ret
= gpiochip_add(pctl
->chip
);
910 for (i
= 0; i
< pctl
->desc
->npins
; i
++) {
911 const struct sunxi_desc_pin
*pin
= pctl
->desc
->pins
+ i
;
913 ret
= gpiochip_add_pin_range(pctl
->chip
, dev_name(&pdev
->dev
),
920 clk
= devm_clk_get(&pdev
->dev
, NULL
);
926 ret
= clk_prepare_enable(clk
);
930 pctl
->irq
= devm_kcalloc(&pdev
->dev
,
931 pctl
->desc
->irq_banks
,
939 for (i
= 0; i
< pctl
->desc
->irq_banks
; i
++) {
940 pctl
->irq
[i
] = platform_get_irq(pdev
, i
);
941 if (pctl
->irq
[i
] < 0) {
947 pctl
->domain
= irq_domain_add_linear(node
,
948 pctl
->desc
->irq_banks
* IRQ_PER_BANK
,
949 &irq_domain_simple_ops
,
952 dev_err(&pdev
->dev
, "Couldn't register IRQ domain\n");
957 for (i
= 0; i
< (pctl
->desc
->irq_banks
* IRQ_PER_BANK
); i
++) {
958 int irqno
= irq_create_mapping(pctl
->domain
, i
);
960 irq_set_chip_and_handler(irqno
, &sunxi_pinctrl_edge_irq_chip
,
962 irq_set_chip_data(irqno
, pctl
);
965 for (i
= 0; i
< pctl
->desc
->irq_banks
; i
++) {
966 /* Mask and clear all IRQs before registering a handler */
967 writel(0, pctl
->membase
+ sunxi_irq_ctrl_reg_from_bank(i
));
969 pctl
->membase
+ sunxi_irq_status_reg_from_bank(i
));
971 irq_set_chained_handler(pctl
->irq
[i
],
972 sunxi_pinctrl_irq_handler
);
973 irq_set_handler_data(pctl
->irq
[i
], pctl
);
976 dev_info(&pdev
->dev
, "initialized sunXi PIO driver\n");
981 clk_disable_unprepare(clk
);
983 if (gpiochip_remove(pctl
->chip
))
984 dev_err(&pdev
->dev
, "failed to remove gpio chip\n");
986 pinctrl_unregister(pctl
->pctl_dev
);